Semiconductor manufacturing apparatus and method of manufacturing semiconductor device

Abstract

Embodiments provide a semiconductor manufacturing apparatus and a semiconductor device manufacturing method capable of performing processing with high precision when processing a layer to be processed using dry etching. The semiconductor device manufacturing apparatus of the embodiments includes: a chamber; a holder disposed in the chamber, capable of adsorbing a substrate, and including a recess provided on a surface, a first hole provided in the recess, and a second hole provided in the recess; a first gas passage connected to the first hole; a second gas passage connected to the second hole; a first valve provided on the first gas passage; a second valve provided on the second gas passage; a first gas supply pipe that supplies a first gas to the recess; and a gas discharge pipe that discharges a gas from the recess; and the first gas passage and the second gas passage are connected to the first gas supply pipe, or the first gas passage and the second gas passage are connected to the gas discharge pipe.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-99777 (filed June 15, 2021) and Japanese Patent Application No. 2021-205698 (filed December 20, 2021). This application incorporates the entire contents of the aforementioned basic applications by reference. Technical Field

[0003] The embodiments of the present invention relate to a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor apparatus. Background Technology

[0004] As semiconductor devices become increasingly miniaturized, there is a demand for high-precision processing when using dry etching to fabricate layers. For example, in the fabrication of three-dimensional semiconductor memories, it is desirable to form memory holes with high aspect ratios with high processing accuracy. Summary of the Invention

[0005] One embodiment of the present invention provides a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device that can perform high-precision processing when processing a layer by dry etching.

[0006] A semiconductor manufacturing apparatus according to an embodiment includes: a chamber; a holder disposed in the chamber, capable of adsorbing a substrate, and comprising a surface recess, a first hole disposed in the recess, and a second hole disposed in the recess; a first gas passage connected to the first hole; a second gas passage connected to the second hole; a first valve disposed on the first gas passage; a second valve disposed on the second gas passage; a first gas supply pipe for supplying a first gas to the recess; and a gas discharge pipe for discharging gas from the recess; the first gas passage and the second gas passage are connected to the first gas supply pipe, or the first gas passage and the second gas passage are connected to the gas discharge pipe. Attached Figure Description

[0007] Figure 1 This is a schematic cross-sectional view of a semiconductor device manufactured using the semiconductor device manufacturing method of the first embodiment.

[0008] Figure 2 This is a schematic diagram of an example of a reactive ion etching apparatus used in the semiconductor device manufacturing method of the first embodiment.

[0009] Figure 3 This is an explanatory diagram of the manufacturing method of the semiconductor device according to the first embodiment.

[0010] Figure 4(a)~(d) Figure 5 (a)~(d) Figure 6 (a)~(c) Figure 7 (a) to (c) are schematic diagrams illustrating the manufacturing method of the semiconductor device according to the first embodiment.

[0011] Figure 8 This is an explanatory diagram of the manufacturing method of the semiconductor device according to the second embodiment.

[0012] Figure 9 This is an explanatory diagram of the manufacturing method of the semiconductor device according to the third embodiment.

[0013] Figure 10 This is an explanatory diagram of the manufacturing method of the semiconductor device according to the fourth embodiment.

[0014] Figure 11 This is an explanatory diagram of the manufacturing method of the semiconductor device according to the fifth embodiment.

[0015] Figure 12 (a)~(d) Figure 13 (a)~(d) Figure 14 (a)~(d) Figure 15 (a) to (c) are schematic diagrams illustrating the manufacturing method of the semiconductor device according to the fifth embodiment.

[0016] Figure 16 This is a schematic diagram of the semiconductor manufacturing apparatus according to the sixth embodiment.

[0017] Figure 17 (a) and (b) are schematic diagrams of the main parts of the semiconductor manufacturing apparatus according to the sixth embodiment.

[0018] Figure 18 (a) to (d) are explanatory diagrams of the operation of the semiconductor manufacturing apparatus according to the sixth embodiment.

[0019] Figure 19 (a) and (b) are schematic diagrams of the main parts of the semiconductor manufacturing apparatus of the comparative example.

[0020] Figure 20 This is a schematic diagram of the main parts of the semiconductor manufacturing apparatus according to the seventh embodiment.

[0021] Figure 21 This is a schematic diagram of the main parts of a semiconductor manufacturing apparatus according to a variation of the seventh embodiment.

[0022] Figure 22 This is a schematic diagram of the main parts of the semiconductor manufacturing apparatus according to the eighth embodiment.

[0023] Figure 23This is a schematic diagram of the main parts of the semiconductor manufacturing apparatus according to the ninth embodiment. Detailed Implementation

[0024] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same symbols, and descriptions of components that have already been described once may be appropriately omitted.

[0025] Additionally, for ease of explanation, the terms "upper" or "lower" are sometimes used in this specification. "Upper" or "lower" is, for example, a term indicating a relative positional relationship within the accompanying drawings. The terms "upper" or "lower" do not necessarily specify a positional relationship relative to gravity.

[0026] Qualitative and quantitative analyses of the chemical composition of the components constituting the semiconductor device described in this specification can be performed, for example, by secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX). Furthermore, measurements of the thickness of the components constituting the semiconductor device, the distance between components, etc., can be performed, for example, by transmission electron microscopy (TEM) or scanning electron microscopy (SEM).

[0027] Hereinafter, the manufacturing method of the semiconductor device according to the embodiments will be described with reference to the accompanying drawings.

[0028] (First Embodiment)

[0029] The semiconductor device manufacturing method of the first embodiment involves placing a substrate having a processed layer on a holder disposed in a chamber, supplying a first gas in contact with the substrate between the holder and the substrate, controlling the pressure of the first gas to a first pressure, performing a first etching process to etch the processed layer using a reactive ion etching method after controlling the pressure of the first gas to the first pressure, controlling the pressure of the first gas to a second pressure lower than the first pressure after controlling the pressure of the first gas to the second pressure, performing a first reaction product removal process to remove reaction products on the processed layer, controlling the pressure of the first gas to a third pressure higher than the second pressure after the first reaction product removal process, and performing a second etching process to etch the processed layer using a reactive ion etching method after controlling the pressure of the first gas to the third pressure.

[0030] Furthermore, in the semiconductor device manufacturing method of the first embodiment, a substrate having a processed layer is placed on a holder provided in a chamber, a first gas in contact with the substrate is supplied between the holder and the substrate, the pressure of the first gas is controlled to a first pressure, and after the pressure of the first gas is controlled to the first pressure, a first etching process is performed to etch the processed layer using a reactive ion etching method in a first state where the substrate temperature is below 60°C, after the first etching process, the pressure of the first gas is controlled to a second pressure lower than the first pressure, after the pressure of the first gas is controlled to the second pressure, a second state where the substrate temperature is above 100°C is achieved, after the second state is achieved, the pressure of the first gas is controlled to a third pressure higher than the second pressure, and after the pressure of the first gas is controlled to the third pressure, a second etching process is performed to etch the processed layer using a reactive ion etching method in a third state where the substrate temperature is below 60°C.

[0031] Figure 1 This is a schematic cross-sectional view of a semiconductor device manufactured using the semiconductor device manufacturing method of the first embodiment. The semiconductor device manufactured using the semiconductor device manufacturing method of the first embodiment is a non-volatile memory 100 with memory cells arranged in three dimensions. Figure 1 This is a cross-sectional view of the memory cell array of the non-volatile memory 100.

[0032] The non-volatile memory 100 includes a silicon substrate 10, a channel layer 11, multiple interlayer insulating layers 12, a gate insulating layer 13, multiple word lines WL, and multiple bit lines BL. The non-volatile memory 100 has multiple memory cells MC arranged in a three-dimensional configuration. Figure 1 The area enclosed by the dashed line in the diagram is equivalent to a storage unit MC.

[0033] Channel layer 11 extends in the normal direction to the surface of silicon substrate 10. Channel layer 11 is electrically connected to silicon substrate 10. Channel layer 11 functions as a channel region of the transistor in memory cell MC. Channel layer 11 is a semiconductor. Channel layer 11 is, for example, polycrystalline silicon.

[0034] Word lines WL are deposited on the surface of silicon substrate 10 in the normal direction. Word lines WL function as the gate electrodes of transistors in memory cells MC. Word lines WL are, for example, plate-shaped conductors. Word lines WL are, for example, tungsten (W). Channel layer 11 extends through multiple word lines WL.

[0035] An interlayer insulation layer 12 is disposed between word lines WL. The interlayer insulation layer 12 electrically separates the word lines WL from each other.

[0036] Bit line BL extends in a direction parallel to the surface of silicon substrate 10. Bit line BL is electrically connected to channel layer 11.

[0037] A gate insulating layer 13 is disposed between the channel layer 11 and the word line WL. The gate insulating layer 13 may include, for example, a tunnel insulating film, a charge storage film, and a barrier insulating film (not shown). The tunnel insulating film may be, for example, a silicon oxide film. The charge storage film may be, for example, a silicon nitride film. The barrier insulating film may be, for example, an aluminum oxide film.

[0038] The memory cell MC stores data using the charge stored in the charge storage film of the gate insulating layer 13. The threshold voltage of the transistor in the memory cell MC varies according to the amount of charge stored in the charge storage film. The data stored in the memory cell MC is read out by monitoring the current flowing between the word line WL and the bit line BL, which varies according to the threshold voltage of the transistor.

[0039] Figure 2 This is a schematic diagram of an example of a reactive ion etching apparatus used in the semiconductor device manufacturing method of the first embodiment. Figure 2 The reactive ion etching apparatus (RIE apparatus) is a dual-frequency capacitively coupled plasma apparatus (CCP apparatus).

[0040] The RIE device includes, for example, a chamber 20, a retainer 22, a first high-frequency power supply 24, a second high-frequency power supply 26, a processing gas supply pipe 30, a spray plate 32, a processing gas discharge pipe 34, an exhaust device 36, a refrigerant assembly 38, a refrigerant supply pipe 40, a refrigerant discharge pipe 42, a heat transfer gas supply section 44, a first heat transfer gas supply pipe 46, a heat transfer gas discharge pipe 48, a first main valve 50, a second main valve 52, and a control circuit 54.

[0041] Holder 22 is disposed in chamber 20. Holder 22, for example, holds a semiconductor wafer W.

[0042] The retainer 22 has a support 22a, an electrostatic chuck 22b and an outer ring 22c.

[0043] The support portion 22a functions as a lower electrode. High-frequency power is applied to the support portion 22a. The support portion 22a is, for example, metal.

[0044] A refrigerant flow path 22ax is provided inside the support section 22a. The refrigerant flow path 22ax is an open space. Refrigerant used to cool the support section 22a is supplied to the refrigerant flow path 22ax. The refrigerant is, for example, a fluorine-based inert liquid.

[0045] An electrostatic chuck 22b is disposed on the support portion 22a. The electrostatic chuck 22b has the function of adsorbing and fixing the semiconductor wafer W. The electrostatic chuck 22b is formed, for example, of a dielectric material having internal electrodes. The dielectric material is, for example, ceramic.

[0046] A thermally conductive gas region 76 is formed on the upper surface of the electrostatic chuck 22b. Thermally conductive gas is supplied between the electrostatic chuck 22b and the semiconductor wafer W to cool the semiconductor wafer W. By fixing the semiconductor wafer W to the electrostatic chuck 22b, the thermally conductive gas region 76 becomes a closed space.

[0047] Thermally conductive gases include, for example, helium (He), hydrogen (H), nitrogen (N), neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe).

[0048] An outer ring 22c is disposed on the support portion 22a. The outer ring 22c is disposed around the electrostatic chuck 22b. The outer ring 22c functions to support the outer periphery of the semiconductor wafer W. The upper surface of the outer ring 22c is formed, for example, from silicon.

[0049] The first high-frequency power supply 24 has the function of applying a first high-frequency power to the interior of the chamber 20. The first high-frequency power supply 24 applies high-frequency power between the support portion 22a of the holder 22 and the cluster plate 32. By using the first high-frequency power applied to the chamber 20 by the first high-frequency power supply 24, plasma is generated in the chamber 20.

[0050] The first high-frequency power applied by the first high-frequency power supply 24 is, for example, 50W or more and 20,000W or less. The first frequency applied by the first high-frequency power supply 24 is, for example, 20MHz or more and 200MHz or less.

[0051] The second high-frequency power supply 26 has the function of applying a second high-frequency power to the interior of the chamber 20. The second high-frequency power supply 26 applies the second high-frequency power to the support portion 22a of the holder 22. By applying the second high-frequency power to the holder 22, the energy of the ions colliding with the semiconductor wafer W is controlled.

[0052] The second high-frequency power applied to the retainer 22 is, for example, 50W or more and 20,000W or less. The second frequency applied to the retainer 22 is lower than the first frequency applied to the chamber 20 using the first high-frequency power supply 24. The second frequency applied to the retainer 22 is, for example, 0.1MHz or more and 20MHz or less.

[0053] The processing gas supply piping 30 is located at the top of the chamber 20. Etching gas is supplied from the processing gas supply piping 30 to the cluster plate 32.

[0054] The cluster plate 32 is disposed in the chamber 20. The cluster plate 32 is disposed above the retainer 22.

[0055] Etching gas is supplied from the processing gas supply pipe 30 to the cluster plate 32. Etching gas is supplied into the chamber 20 from multiple gas supply ports provided on the cluster plate 32.

[0056] The cluster plate 32 also functions as the upper electrode of the first high-frequency power.

[0057] The process gas exhaust pipe 34 is located at the bottom of the chamber 20. Unconsumed etching gases and reaction products from the etching reaction are discharged from the process gas exhaust pipe 34 to the outside of the chamber 20.

[0058] The exhaust device 36 is connected to the processed gas exhaust pipe 34 and the heat-conducting gas exhaust pipe 48. The exhaust device 36 is, for example, a vacuum pump.

[0059] Refrigerant assembly 38 is connected to refrigerant supply piping 40. Refrigerant supply piping 40 is connected to refrigerant flow path 22ax. Refrigerant flow path 22ax is connected to refrigerant discharge piping 42. Refrigerant circulates in refrigerant supply piping 40, refrigerant flow path 22ax, and refrigerant discharge piping 42 through refrigerant assembly 38.

[0060] A heat transfer gas supply unit 44 is connected to a first heat transfer gas supply pipe 46. The first heat transfer gas supply pipe 46 is connected to a heat transfer gas region 76. A first main valve 50 is installed in the first heat transfer gas supply pipe 46. Heat transfer gas is supplied to the heat transfer gas region 76 through the heat transfer gas supply unit 44.

[0061] The first main valve 50 is, for example, a flow control valve. By controlling the first main valve 50, the pressure of the heat-conducting gas in the heat-conducting gas region 76 can be controlled. Alternatively, the first main valve 50 can be used to block the supply of heat-conducting gas to the heat-conducting gas region 76.

[0062] The heat-conducting gas zone 76 is connected to the heat-conducting gas exhaust pipe 48. The heat-conducting gas exhaust pipe 48 is connected to the exhaust device 36. The heat-conducting gas in the heat-conducting gas zone 76 is exhausted using the heat-conducting gas exhaust pipe 48.

[0063] The second main valve 52 is installed in the heat transfer gas discharge pipe 48. The second main valve 52 is used to control the discharge of heat transfer gas.

[0064] The control circuit 54 has the function of controlling the operation of the first high-frequency power supply 24, the second high-frequency power supply 26, the exhaust device 36, the refrigerant assembly 38, the heat transfer gas supply unit 44, the first main valve 50, and the second main valve 52.

[0065] Anisotropic etching is performed on the semiconductor wafer W placed in the holder 22 using plasma generated between the cluster plate 32 and the holder 22 in the chamber 20.

[0066] Next, an example of the manufacturing method of the semiconductor device according to the first embodiment will be described.

[0067] Figure 3This is an explanatory diagram of the manufacturing method of the semiconductor device according to the first embodiment. Figures 4-7 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to the first embodiment. Figures 4-7 Corresponding to Figure 1 It contains a section of channel layer 11.

[0068] First, a multilayer 60 is formed on the silicon substrate 10. Figure 4 (a) The silicon substrate 10 is a semiconductor wafer. The laminate 60 is an insulating layer. The silicon substrate 10 is an example of a substrate. The laminate 60 is an example of a layer to be processed. The silicon substrate 10 is... Figure 2 An example of a semiconductor wafer W.

[0069] The stack 60 comprises a structure formed by alternating layers of silicon oxide film 60a and silicon nitride film 60b. The silicon oxide film 60a and silicon nitride film 60b are formed, for example, by chemical vapor deposition (CVD).

[0070] A portion of the silicon oxide film 60a will eventually become the interlayer insulating layer 12.

[0071] Next, a carbon layer 62 with a pore pattern 62a is formed on the laminate 60. Figure 4 (b) The carbon layer 62 is a mask layer. The carbon layer 62 is formed, for example, by sputtering. The hole pattern 62a is formed, for example, by photolithography and RIE.

[0072] Mask layers can also be, for example, resist layers, insulating layers, or metal layers.

[0073] Next, the silicon substrate 10 is moved into the chamber 20 of the RIE device. The silicon substrate 10 is placed on the holder 22 provided in the chamber 20. The silicon substrate 10 is an example of a substrate.

[0074] In chamber 20 of the RIE device, a memory aperture MH is formed using reactive ion etching with carbon layer 62 as a mask. Figure 4 (c)~ Figure 5 (d) The memory hole MH is etched while the pressure of the heat-conducting gas cooling the silicon substrate 10 is periodically varied. The memory hole MH is an example of a recess.

[0075] Figure 3 This indicates the relationship between the heat-conducting gas pressure, total high frequency power, wafer temperature, and etching time during the formation of memory vias (MH).

[0076] At time t1, a thermally conductive gas is supplied to the thermally conductive gas region 76 between the holder 22 and the silicon substrate 10. The thermally conductive gas is, for example, helium. The helium gas contacts the back side of the silicon substrate 10. Helium is an example of a first gas.

[0077] At time t1, the pressure of the helium gas is controlled to a first pressure P1. The pressure of the helium gas is controlled, for example, by using the flow control of the first main valve 50. By adjusting the opening of the first main valve 50, the pressure of the helium gas is controlled to the first pressure P1.

[0078] The first pressure P1 is, for example, above 133 Pa (1 Torr) and below 133-32 Pa (100 Torr).

[0079] Additionally, at time t1, high-frequency power is applied to the interior of chamber 20. For example, using a first high-frequency power source 24, a first high-frequency power source is applied between the support portion 22a of the retainer 22 and the cluster plate 32. For example, using a second high-frequency power source 26, a second high-frequency power source is applied to the support portion 22a of the retainer 22. The sum of the first high-frequency power and the second high-frequency power is called the total high-frequency power.

[0080] Additionally, at time t1, etching gas is supplied to chamber 20. The etching gas is supplied to chamber 20 from the processing gas supply pipe 30 through the spray plate 32.

[0081] Etching gases may contain, for example, carbon (C) and fluorine (F). Etching gases may also contain, for example, CxHyFz (where x is an integer greater than or equal to 1, y is an integer greater than or equal to 0, and z is an integer greater than or equal to 1). Etching gases may also contain, for example, C4F6, C4F8, and CH2F2.

[0082] Etching gases may include, for example, oxygen. Etching gases may also include, for example, hydrogen bromide gas (HBr).

[0083] Additionally, at time t1, refrigerant is supplied to the refrigerant flow path 22ax. The refrigerant is, for example, a fluorine-based inert liquid. By supplying refrigerant to the refrigerant flow path 22ax, the temperature of the support portion 22a and the electrostatic chuck 22b of the retainer 22 decreases. The temperature of the support portion 22a and the electrostatic chuck 22b of the retainer 22 is, for example, between -196°C and 60°C.

[0084] After controlling the helium gas pressure to the first pressure P1, a first etching process is performed to etch the laminate 60 using reactive ion etching. Figure 4 (c)). Between time t1 and time t2, a first etching process is performed to etch the stacked layer 60. During the first etching process, the memory via MH does not penetrate the stacked layer 60.

[0085] During the first etching process, the temperature of the silicon substrate 10 is, for example, between -150°C and 60°C. During the first etching process, for example, a first state in which the temperature of the silicon substrate 10 is between -150°C and 60°C is achieved.

[0086] During the first etching process, reaction product 63 is formed on the stack 60. During the first etching process, reaction product 63 is formed on the bottom and side surfaces of the memory hole MH. The reaction product 63 formed during the first etching process is an example of the first reaction product.

[0087] Reaction product 63 may contain, for example, silicon (Si), nitrogen (N), and fluorine (F). Reaction product 63 may contain, for example, ammonium fluorosilicate. Reaction product 63 may contain, for example, (NH4)2SiF6.

[0088] After the first etching process, at time t2, the helium pressure is controlled to the second pressure P2. After the first etching process, at time t2, the helium pressure is changed from the first pressure P1 to the second pressure P2. The second pressure P2 is lower than the first pressure P1.

[0089] The pressure of helium is controlled, for example, by using flow control of the first main valve 50. For example, by closing the first main valve 50, the inflow of helium into the heat-conducting gas region 76 is blocked. For example, by closing the first main valve 50, the second pressure P2 is brought close to a vacuum.

[0090] The second pressure P2 is, for example, above 0 Pa and below 13.3 Pa (0.1 Torr). The second pressure P2 is, for example, less than one percent of the first pressure P1.

[0091] After controlling the helium pressure to the second pressure P2, the first reaction product removal (removal of reaction product 63 from the laminate 60) is performed. Figure 4 (d)). Between time t2 and time t3, the reaction product 63 on the stack 60 is removed. The reaction product 63 on the bottom and sides of the memory hole MH is removed by performing the first reaction product removal.

[0092] During the removal of the first reaction product, the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower. During the removal of the first reaction product, a second state in which the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower is achieved.

[0093] At time t2, after the helium pressure is controlled from the first pressure P1 to the second pressure P2, the temperature of the silicon substrate 10 rises, achieving a second state where the temperature of the silicon substrate 10 is above 100°C. Heat transfer in the helium is controlled by decreasing the helium pressure. This suppresses heat dissipation from the silicon substrate 10 to the holder 22 via the helium, causing the temperature of the silicon substrate 10 to rise.

[0094] For example, higher temperatures promote the decomposition of reaction product 63, thereby facilitating its removal from the memory aperture MH. For instance, the decomposition of reaction product 63 is promoted by raising the temperature of the silicon substrate 10 to 100°C or higher. This is especially true when reaction product 63 is ammonium fluorosilicate; raising the temperature of the silicon substrate 10 to 100°C or higher further promotes the decomposition reaction.

[0095] Furthermore, for example, during the removal of the first reaction product, etching gas continues to be supplied to chamber 20.

[0096] After the first reaction product is removed, at time t3, the helium pressure is controlled to the third pressure P3. After the first reaction product is removed, at time t3, the helium pressure is changed from the second pressure P2 to the third pressure P3. After achieving the second state, the helium pressure is controlled to the third pressure P3.

[0097] The third pressure P3 is higher than the second pressure P2. The pressure of helium is controlled, for example, by using the flow control of the first main valve 50. For example, by opening the first main valve 50, helium begins to flow into the heat-conducting gas region 76. By adjusting the opening degree of the first main valve 50, the pressure of the helium is controlled to the third pressure P3.

[0098] The third pressure P3 is, for example, above 133 Pa (1 Torr) and below 13332 Pa (100 Torr). The third pressure P3 is, for example, equal to the first pressure P1.

[0099] After controlling the helium pressure to the third pressure P3, a second etching process is performed to etch the laminate 60 using reactive ion etching. Figure 5 (a)). During the second etching process, etching gas continues to be supplied to chamber 20.

[0100] Between time t3 and time t4, a second etching process is performed on the stacked layer 60. During the second etching process, the bottom surface of the memory hole MH is etched. During the second etching process, the memory hole MH becomes deeper. During the second etching process, the memory hole MH does not penetrate the stacked layer 60.

[0101] By increasing the pressure of the helium gas from the second pressure P2 to the third pressure P3, heat transfer in the helium gas is promoted. This promotes heat dissipation from the silicon substrate 1 to the holder 22 via the helium gas 0, thereby reducing the temperature of the silicon substrate 10.

[0102] During the second etching process, the temperature of the silicon substrate 10 is, for example, between -150°C and 60°C. During the second etching process, a third state in which the temperature of the silicon substrate 10 is between -150°C and 60°C is achieved, for example.

[0103] During the second etching process, reaction product 63 is formed on the stack 60. During the second etching process, reaction product 63 is formed on the bottom and side surfaces of the memory hole MH. The reaction product 63 formed during the second etching process is an example of the second reaction product.

[0104] After the second etching process, at time t4, the helium pressure is controlled to the fourth pressure P4. After the second etching process, at time t4, the helium pressure is changed from the third pressure P3 to the fourth pressure P4. The fourth pressure P4 is lower than the third pressure P3. The fourth pressure P4 is, for example, equal to the second pressure P2.

[0105] The fourth pressure P4 is, for example, above 0 Pa and below 13.3 Pa (0.1 Torr). The fourth pressure P4 is, for example, less than one percent of the third pressure P3.

[0106] After controlling the helium pressure to the fourth pressure P4, the second reaction product removal process is carried out to remove reaction product 63 from the laminate 60. Figure 5 (b)). Between time t4 and time t5, the reaction product 63 on the stack 60 is removed. The reaction product 63 on the bottom and sides of the memory hole MH is removed by performing a second reaction product removal.

[0107] During the removal of the second reaction product, the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower. During the removal of the second reaction product, a fourth state in which the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower is achieved.

[0108] At time t4, after the pressure of the helium gas changes from the third pressure P3 to the fourth pressure P4, the temperature of the silicon substrate 10 rises, achieving the fourth state where the temperature of the silicon substrate 10 is above 100°C and below 300°C.

[0109] Furthermore, for example, during the removal of the second reaction product, etching gas is continuously supplied to chamber 20.

[0110] After the removal of the second reaction product, at time t5, the helium pressure is controlled to the fifth pressure P5. After the removal of the second reaction product, at time t5, the helium pressure is changed from the fourth pressure P4 to the fifth pressure P5. After achieving the fourth state, the helium pressure is controlled to the fifth pressure P5.

[0111] The fifth pressure P5 is higher than the fourth pressure P4. The fifth pressure P5 is, for example, between 133 Pa (1 Torr) and 13332 Pa (100 Torr). The fifth pressure P5 is, for example, equal to the first pressure P1 and the third pressure P3.

[0112] After controlling the helium pressure to the fifth pressure P5, a third etching process is performed to etch the laminate 60 using reactive ion etching. Figure 5 (c)). During the fifth etching, etching gas continues to be supplied to chamber 20.

[0113] Between time t5 and time t6, a third etching process is performed to etch the stacked layer 60. During the third etching process, the bottom surface of the memory hole MH is etched. During the third etching process, the memory hole MH becomes deeper. During the third etching process, the memory hole MH penetrates the stacked layer 60 and reaches the silicon substrate 10. The aspect ratio of the memory hole MH penetrating the stacked layer 60 is, for example, 30 or more.

[0114] By increasing the pressure of helium gas from pressure 4 P4 to pressure 5 P5, the temperature of silicon substrate 10 is reduced.

[0115] During the third etching process, the temperature of the silicon substrate 10 is, for example, between -150°C and 60°C. During the third etching process, for example, a fifth state is achieved where the temperature of the silicon substrate 10 is between -150°C and 60°C.

[0116] During the third etching process, reaction product 63 is formed on the stack 60. During the third etching process, reaction product 63 is formed on the bottom and side surfaces of the memory hole MH.

[0117] After the third etching process, at time t6, the helium pressure is controlled to the sixth pressure P6. After the third etching process, at time t6, the helium pressure is changed from the fifth pressure P5 to the sixth pressure P6. The sixth pressure P6 is lower than the fifth pressure P5. The sixth pressure P6 is, for example, equal to the second pressure P2 and the fourth pressure P4.

[0118] The sixth pressure P6 is, for example, above 0 Pa and below 13.3 Pa (0.1 Torr). The sixth pressure P6 is, for example, less than one percent of the fifth pressure P5.

[0119] After controlling the helium pressure to the sixth pressure P6, the third reaction product removal process is carried out to remove reaction product 63 from the laminate 60. Figure 5 (d)). After time t6, the reaction product 63 on the stack 60 is removed. The reaction product 63 on the bottom and sides of the memory hole MH is removed by performing the third reaction product removal.

[0120] During the removal of the third reaction product, the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower. During the removal of the third reaction product, a sixth state is achieved, for example, where the temperature of the silicon substrate 10 is 100°C or higher and 300°C or lower.

[0121] At time t6, after the pressure of the helium gas is changed from the 5th pressure P5 to the 6th pressure P6, the temperature of the silicon substrate 10 rises, achieving the 6th state where the temperature of the silicon substrate 10 is above 100°C.

[0122] Furthermore, for example, during the removal of the third reaction product, etching gas is continuously supplied to chamber 20.

[0123] After the third reaction product is removed, at time t7, the application of high-frequency power to the interior of chamber 20 is stopped. Additionally, at time t7, the supply of etching gas to chamber 20 is also stopped.

[0124] At time t7, the etching of memory hole MH ends.

[0125] Alternatively, after the removal of the third reaction product, the pressure of the helium gas can be increased to a pressure higher than the sixth pressure P6, and the etching of the memory hole MH can be completed while the temperature of the silicon substrate 10 is reduced.

[0126] like Figure 3 As shown, during the etching of the memory hole MH, the helium pressure is controlled to the first pressure P1 for a time td1. During the etching of the memory hole MH, the helium pressure is controlled to the second pressure P2 for a time td2. During the etching of the memory hole MH, the helium pressure is controlled to the third pressure P3 for a time td3. During the etching of the memory hole MH, the helium pressure is controlled to the fourth pressure P4 for a time td4. During the etching of the memory hole MH, the helium pressure is controlled to the fifth pressure P5 for a time td5.

[0127] For example, times td1, td3, and td5 are equal. Also, for example, times td2 and td4 are equal.

[0128] Additionally, for example, time td1 is equal to time td2. Additionally, for example, time td3 is equal to time td4.

[0129] Additionally, for example, time td2 is shorter than time td1. Additionally, for example, time td4 is shorter than time td3.

[0130] Additionally, for example, time td2 is longer than time td1. Additionally, for example, time td4 is longer than time td3.

[0131] When the time for controlling the helium pressure to the second pressure P2 is set to td2 (sec), the temperature of the holder 22 during the first etching process is set to T (°C), the ratio of the surface area of ​​the silicon substrate 10 to the sum of the area of ​​the silicon substrate 10 and the area of ​​the inner wall of the chamber 20 is set to k, the high-frequency power applied to the inside of the chamber 20 during the period when the helium pressure is controlled to the second pressure P2 is set to Pw (W), the mass of the silicon substrate 10 is set to m (kg), and the specific heat capacity of the silicon substrate 10 is set to c (J / (kg·°C)), for example, the following inequality (1) holds.

[0132] td2≧(100-T) / {(k×Pw) / (m×c)} (1)

[0133] Furthermore, the temperature T of the holder 22 is the set temperature of the electrostatic chuck 22b. During the etching of the memory hole MH, the set temperature of the electrostatic chuck 22b is maintained at a fixed temperature. The temperature of the electrostatic chuck 22b is, for example, determined by... Figure 2 The thermometer not shown in the image was used for measurement.

[0134] In addition, the ratio k is expressed by the following formula.

[0135] k = Surface area of ​​silicon substrate / (Surface area of ​​silicon substrate + Inner wall area of ​​cavity)

[0136] In addition, the high-frequency power Pw is the sum of the first high-frequency power and the second high-frequency power, which is the total high-frequency power.

[0137] Similarly, regarding the time td4 for controlling the pressure of helium to the fourth pressure P4, for example, the following inequality (2) holds.

[0138] td4≧(100-T) / {(k×Pw) / (m×c)} (2)

[0139] After the etching of the memory hole MH is completed, the silicon substrate 10 is removed from the chamber 20 of the RIE device.

[0140] Next, remove carbon layer 62 ( Figure 6 (a)). Carbon layer 62 is formed, for example, by ashing using oxygen plasma.

[0141] Next, a multilayer insulating layer 66 is formed in the memory hole MH. Figure 6 (b)). The stacked insulating layer 66 has, for example, a stacked structure of a silicon oxide film, a silicon nitride film, and an aluminum oxide film. The stacked insulating layer 66 ultimately becomes the gate insulating layer 13.

[0142] Next, a polysilicon layer 68 is formed in the memory hole MH. Figure 6 (c)). The polysilicon layer 68 will eventually become the channel layer 11.

[0143] Next, the silicon nitride film 60b was selectively removed. Figure 7 (a)).

[0144] Next, a first tungsten layer 70 is formed in the region where the silicon nitride film 60b has been removed. Figure 7 (b)). The first tungsten layer 70 will eventually become the word line WL.

[0145] Next, a second tungsten layer 69 is formed on the polycrystalline silicon layer 68. Figure 7 (c)). The second tungsten layer 69 will eventually become the bit line BL.

[0146] Using the manufacturing methods described above, the following products were manufactured: Figure 1 The non-volatile memory 100 shown.

[0147] Next, the operation and effects of the semiconductor device manufacturing method of the first embodiment will be explained.

[0148] In a non-volatile memory 100 composed of three-dimensionally arranged memory cells, in order to achieve a large memory capacity, for example, the aperture of the memory hole is reduced and the number of word lines WL is increased. If the aperture of the memory hole is reduced and the number of word lines WL is increased, then a memory hole with a high aspect ratio (depth of memory hole / aperture of memory hole) must be formed.

[0149] If the aspect ratio of the memory hole increases, it will be impossible to process the memory hole into the required shape. In other words, there will be a problem with the reduced processing accuracy of the memory hole shape.

[0150] For example, the shape of the cross-section perpendicular to the depth direction of the memory hole may be deformed compared to the desired shape. Additionally, for example, the etching in the depth direction of the memory hole may not be perpendicular, resulting in a curved shape in the depth direction of the memory hole.

[0151] One reason, as described above, for the reduced machining accuracy of the memory hole shape is believed to be the reaction products formed on the bottom and sides of the memory hole during etching. In other words, it is believed that the reaction products formed on the bottom and sides of the memory hole hinder etching, thereby reducing the machining accuracy of the memory hole shape.

[0152] For example, the lower the temperature of the substrate with the processed layer, the faster the etching rate of the memory holes. From the viewpoint of increasing the etching throughput of the memory holes, it is ideal to reduce the temperature of the substrate with the processed layer. From the viewpoint of increasing the etching throughput of the memory holes, the temperature of the substrate with the processed layer is preferably 60°C or lower, more preferably 20°C or lower, and even more preferably 0°C or lower.

[0153] On the other hand, if the decomposition temperature of the reaction products formed during the etching of memory holes is high, the reaction products may become difficult to decompose due to the decrease in substrate temperature. Therefore, there are concerns that the etching process will be further hindered by the reaction products due to the decrease in substrate temperature. As etching becomes more difficult, there are concerns that the processing accuracy of the memory hole shape may be further reduced.

[0154] In the semiconductor device manufacturing method of the first embodiment, when forming the memory hole MH, the temperature of the silicon substrate 10 having the laminate 60 as the processed layer is varied. That is, the low temperature state of the silicon substrate 10 and the high temperature state of the silicon substrate 10 are alternated repeatedly.

[0155] The first, third, and fifth states correspond to low-temperature states. Conversely, the second, fourth, and sixth states correspond to high-temperature states.

[0156] When the silicon substrate 10 is at a low temperature, the etching rate of the memory hole MH increases, and the etching of the stack 60 is mainly carried out. On the other hand, when the silicon substrate 10 is at a high temperature, the decomposition reaction of the reaction product 63 formed on the bottom and side surfaces of the memory hole MH is promoted, and the decomposition of the reaction product 63 is mainly carried out.

[0157] When the silicon substrate 10 transitions from a high-temperature state to a low-temperature state, the reaction product 63 is removed, thus reducing the likelihood of the reaction product 63 hindering etching. Consequently, the processing precision of the memory hole shape is improved.

[0158] In the semiconductor device manufacturing method of the first embodiment, the memory hole MH is formed by alternating between a low-temperature state and a high-temperature state of the silicon substrate 10, thereby improving the processing accuracy of the memory hole shape. Furthermore, the etching throughput of the memory hole MH is increased.

[0159] In the semiconductor device manufacturing method of the first embodiment, the transition between a high-temperature state and a low-temperature state of the silicon substrate 10 is achieved by changing the pressure of a gas. The heat-conducting gas is, for example, helium.

[0160] The heat transfer between the silicon substrate 10 and the holder 22 is altered by changing the pressure of the heat-conducting gas. If the pressure of the heat-conducting gas increases, heat transfer accelerates; if the pressure decreases, heat transfer is suppressed. For example, by decreasing the pressure of the heat-conducting gas, the silicon substrate 10 can be changed from a low-temperature state to a high-temperature state. Conversely, by increasing the pressure of the heat-conducting gas, the silicon substrate 10 can be changed from a high-temperature state to a low-temperature state.

[0161] In the semiconductor device manufacturing method of the first embodiment, the temperature of the silicon substrate 10 can be changed simply by altering the pressure of the heat-conducting gas used to cool the silicon substrate 10. Therefore, there is no need to add new structures to the RIE device to change the temperature of the silicon substrate 10. This allows for easy improvement in the processing accuracy of the memory hole shape.

[0162] During the etching process of the laminate 60, the surface of the silicon substrate 10 is exposed to a high-energy plasma formed by the application of high-frequency electricity. The temperature of the silicon substrate 10 rises due to heat absorption from the high-energy plasma. On the other hand, the temperature of the silicon substrate 10 decreases due to heat output to the holder 22, which is cooled by the supply of a refrigerant. The temperature of the silicon substrate 10 is determined by the balance between heat absorption from the plasma and heat output to the holder 22.

[0163] When the time for controlling the helium pressure to a low pressure is set to td (sec), the temperature of the holder 22 before the helium pressure is controlled to a low pressure is set to T (°C), the ratio of the surface area of ​​the silicon substrate 10 to the sum of the surface area of ​​the silicon substrate 10 and the inner wall area of ​​the chamber 20 is set to k, the high-frequency power applied to the interior of the chamber 20 during the period when the helium pressure is controlled to a low pressure is set to Pw (W), the mass of the silicon substrate 10 is set to m (kg), and the specific heat capacity of the silicon substrate 10 is set to c (J / (kg·°C)), the following inequality (3) is preferably true.

[0164] td≧(100-T) / {(k×PW) / (m×c)} (3)

[0165] Furthermore, the temperature T of the holder 22 is the set temperature of the electrostatic chuck 22b. During the etching of the memory hole MH, the set temperature of the electrostatic chuck 22b is maintained at a fixed temperature. The temperature of the electrostatic chuck 22b is, for example, determined by... Figure 2 The temperature T of the holder 22 can be measured by a thermometer not shown in the figure. Alternatively, for example, when switching control from high pressure to low pressure, the temperature T of the holder 22 can also be the temperature of the electrostatic chuck 22b measured by a thermometer.

[0166] In addition, the ratio k is expressed by the following formula.

[0167] k = Surface area of ​​silicon substrate / (Surface area of ​​silicon substrate + Inner wall area of ​​cavity)

[0168] In addition, the high-frequency power PW is the sum of the first high-frequency power and the second high-frequency power, which is the total high-frequency power.

[0169] By making time td satisfy the aforementioned inequality (3), the temperature of the silicon substrate 10 can be raised to above 100°C during the time td. By making the temperature of the silicon substrate 10 above 100°C, the decomposition of the reaction product 63 is promoted.

[0170] Therefore, the inequality (1) is preferably true for the time td2 when the pressure of helium is controlled to the second pressure P2.

[0171] Similarly, regarding the time td4 for controlling the pressure of helium to the fourth pressure P4, it is preferable that the inequality (2) holds.

[0172] From the viewpoint of promoting the decomposition reaction of reaction product 63 on silicon substrate 10, a higher temperature for silicon substrate 10 is preferable. Therefore, it is preferable to control the helium pressure at a low pressure for a longer period of time. Consequently, the time td2 for controlling the helium pressure to the second pressure P2 is preferably longer than 10 seconds, more preferably longer than 15 seconds. Furthermore, the time td4 for controlling the helium pressure to the fourth pressure P4 is preferably longer than 10 seconds, more preferably longer than 15 seconds.

[0173] From the viewpoint of increasing the etching throughput of memory holes, it is preferable that the time of the high-temperature state, where the main reactant generation and removal occur, is shorter than the time of the low-temperature state, where the main etching occurs. Therefore, the time for controlling the helium pressure to a low pressure is preferably shorter than the time for controlling the helium pressure to a high pressure. Consequently, time td2 is preferably shorter than times td1, td3, and td5. Time td4 is preferably shorter than times td1, td3, and td5. Time td6 is preferably shorter than times td1, td3, and td5.

[0174] From the viewpoint of increasing the temperature change rate of the silicon substrate 10, the heat-conducting gas is preferably helium or hydrogen, which have high thermal conductivity.

[0175] (Example of variation)

[0176] The variation of the semiconductor device manufacturing method of the first embodiment differs from that of the semiconductor device manufacturing method of the first embodiment in that the temperature of the substrate is measured, and the pressure of the first gas is controlled to a third pressure based on the measured temperature of the substrate.

[0177] In a variation of the semiconductor device manufacturing method, the RIE device for etching the memory hole MH includes Figure 2 A thermometer, not shown, is used to measure the temperature of the silicon substrate 10. The thermometer measures the temperature of the silicon substrate 10 directly or indirectly.

[0178] The thermometer is, for example, a phosphor thermometer or thermocouple that directly measures the temperature of the silicon substrate 10. The thermometer is, for example, a phosphor thermometer or thermocouple that directly measures the temperature of the outer ring 22c. The temperature of the silicon substrate 10 can be indirectly derived from the temperature of the outer ring 22c.

[0179] In a variation of the semiconductor device manufacturing method, the helium pressure is controlled based on the temperature of the substrate measured by a thermometer. The control of the helium pressure based on the temperature of the silicon substrate 10 is performed, for example, using a control circuit 54.

[0180] For example, the temperature of the silicon substrate 10 is measured while the helium pressure is controlled at a second pressure P2. For example, when the temperature of the silicon substrate 10 reaches a predetermined temperature, the helium pressure is switched from the second pressure P2 to a third pressure P3, which is higher than the second pressure P2. The predetermined temperature is, for example, 120°C. Based on the temperature of the silicon substrate 10, the helium pressure is controlled at the third pressure P3.

[0181] By switching the pressure of helium gas from the second pressure P2 to the third pressure P3 based on the temperature of the silicon substrate 10, it is possible to reliably prevent the temperature of the silicon substrate 10 from becoming too high.

[0182] Additionally, for example, the temperature of the silicon substrate 10 is measured while the helium pressure is controlled at a third pressure P3. For example, after the temperature of the silicon substrate 10 decreases to a predetermined temperature, and after a predetermined time, the helium pressure is switched from the third pressure P3 to a fourth pressure P4, which is lower than the third pressure P3. The predetermined temperature is, for example, 20°C. The predetermined time is, for example, 10 seconds. Based on the temperature of the silicon substrate 10, the helium pressure is controlled to the fourth pressure P4.

[0183] By switching the pressure of helium gas from the third pressure P3 to the fourth pressure P4 based on the temperature of the silicon substrate 10, the etching amount of the stack 60 can be controlled with high precision, for example.

[0184] According to the semiconductor device manufacturing method of the first embodiment and its variations, when processing the layer to be processed using dry etching, high-precision processing can be performed.

[0185] (Second Implementation)

[0186] The difference between the semiconductor device manufacturing method of the second embodiment and the manufacturing method of the first embodiment is that the control of the change in the pressure of the first gas is synchronized with the control of the change in the high-frequency power applied to the cavity. Furthermore, in the semiconductor device manufacturing method of the second embodiment, the high-frequency power applied to the cavity during the removal of the first reaction product is higher than the high-frequency power applied to the cavity during the first etching process. Hereinafter, some details that are repeated in the first embodiment will be omitted.

[0187] Figure 8 This is an explanatory diagram of the manufacturing method of the semiconductor device according to the second embodiment. Figure 8 This indicates the relationship between the heat-conducting gas pressure, total high-frequency power, wafer temperature, and etching time during the formation of memory aperture MH.

[0188] At time t1, a thermally conductive gas is supplied to the thermally conductive gas region 76 between the holder 22 and the silicon substrate 10. The thermally conductive gas is, for example, helium.

[0189] At time t1, the pressure of the helium gas is controlled to the first pressure P1. At time t1, the first electrical current Pw1 is applied to the interior of chamber 20.

[0190] Additionally, at time t1, etching gas is supplied to chamber 20. Also at time t1, coolant is supplied to coolant flow path 22ax.

[0191] After controlling the helium gas pressure to a first pressure P1, a first etching process is performed to etch the multilayer 60 using a reactive ion etching method. During the first etching process, the temperature of the silicon substrate 10 is, for example, between -150°C and 60°C. During the first etching process, a first state is achieved, for example, where the temperature of the silicon substrate 10 is between -150°C and 60°C. During the first etching process, a reaction product 63 is formed on the multilayer 60.

[0192] After the first etching process, at time t2, the helium pressure is controlled to the second pressure P2. After the first etching process, at time t2, the helium pressure is changed from the first pressure P1 to the second pressure P2. The second pressure P2 is lower than the first pressure P1.

[0193] Additionally, at time t2, a second electrical power Pw2 is applied to the interior of chamber 20. At time t2, the high-frequency electrical power applied to the interior of chamber 20 is changed from the first electrical power Pw1 to the second electrical power Pw2. The second electrical power Pw2 is higher than the first electrical power Pw1.

[0194] After controlling the pressure of helium gas to the second pressure P2 and applying the second electric current Pw2, the first reaction product removal is carried out to remove the reaction product 63 on the laminate 60.

[0195] During the removal of the first reaction product, the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower. During the removal of the first reaction product, a second state in which the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower is achieved.

[0196] After the first reaction product is removed, at time t3, the helium pressure is controlled to the third pressure P3. After the first reaction product is removed, at time t3, the helium pressure is changed from the second pressure P2 to the third pressure P3. The third pressure P3 is higher than the second pressure P2.

[0197] Additionally, at time t3, a third electrical power Pw3 is applied to the interior of chamber 20. At time t3, the high-frequency electrical power applied to the interior of chamber 20 is changed from the second electrical power Pw2 to the third electrical power Pw3. The third electrical power Pw3 is lower than the second electrical power Pw2.

[0198] After controlling the pressure of helium gas to the third pressure P3 and applying the third electric current Pw3, a second etching process is performed to etch the laminate 60 using reactive ion etching.

[0199] Between time t3 and time t4, a second etching process is performed to etch the stack 60.

[0200] By increasing the helium pressure from the second pressure P2 to the third pressure P3, the temperature of the silicon substrate 10 is reduced. During the second etching process, for example, a third state is achieved where the temperature of the silicon substrate 10 is between -150°C and 60°C. During the second etching process, reaction products 63 are formed on the laminate 60.

[0201] After the second etching process, at time t4, the helium pressure is controlled to the fourth pressure P4. After the second etching process, at time t4, the helium pressure is changed from the third pressure P3 to the fourth pressure P4. The fourth pressure P4 is lower than the third pressure P3.

[0202] Additionally, at time t4, a fourth electrical power Pw4 is applied to the interior of chamber 20. At time t4, the high-frequency electrical power applied to the interior of chamber 20 is changed from the third electrical power Pw3 to the fourth electrical power Pw4. The fourth electrical power Pw4 is higher than the third electrical power Pw3.

[0203] After the helium pressure is controlled to the fourth pressure P4 and the fourth electric current Pw4 is applied, the second reaction product removal is carried out to remove the reaction product 63 on the laminate 60.

[0204] During the removal of the second reaction product, the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower. During the removal of the second reaction product, a fourth state in which the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower is achieved.

[0205] After the removal of the second reaction product, at time t5, the helium pressure is controlled to the fifth pressure P5. After the removal of the first reaction product, at time t5, the helium pressure is changed from the fourth pressure P4 to the fifth pressure P5. The fifth pressure P5 is higher than the fourth pressure P4.

[0206] Additionally, at time t5, a fifth electrical power Pw5 is applied to the interior of chamber 20. At time t5, the high-frequency electrical power applied to the interior of chamber 20 is changed from the fourth electrical power Pw4 to the fifth electrical power Pw5. The fifth electrical power Pw5 is lower than the fourth electrical power Pw4.

[0207] After controlling the pressure of helium gas to the fifth pressure P5 and applying the fifth electric current Pw5, a third etching process is performed to etch the laminate 60 using reactive ion etching.

[0208] Between time t5 and time t6, a third etching process is performed to etch the stack 60.

[0209] By increasing the helium pressure from pressure P4 to pressure P5, the temperature of the silicon substrate 10 is reduced. During the third etching process, for example, a fifth state is achieved where the temperature of the silicon substrate 10 is between -150°C and 60°C. During the third etching process, reaction product 63 is formed on the laminate 60.

[0210] After the third etching process, at time t6, the helium pressure is controlled to the sixth pressure P6. After the third etching process, at time t6, the helium pressure is changed from the fifth pressure P5 to the sixth pressure P6. The sixth pressure P6 is lower than the fifth pressure P5.

[0211] Additionally, at time t6, a sixth electrical power Pw6 is applied to the interior of chamber 20. At time t6, the high-frequency electrical power applied to the interior of chamber 20 is changed from the fifth electrical power Pw5 to the sixth electrical power Pw6. The sixth electrical power Pw6 is higher than the fifth electrical power Pw5.

[0212] After the helium pressure is controlled to the sixth pressure P6 and the sixth electric current Pw6 is applied, the third reaction product removal is carried out to remove the reaction product 63 on the laminate 60.

[0213] During the removal of the third reaction product, the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower. During the removal of the third reaction product, a sixth state is achieved, for example, where the temperature of the silicon substrate 10 is 100°C or higher and 300°C or lower.

[0214] After the third reaction product is removed, at time t7, the application of high-frequency power to the interior of chamber 20 is stopped. Additionally, at time t7, the supply of etching gas to chamber 20 is also stopped.

[0215] At time t7, the etching of memory hole MH ends.

[0216] Next, the operation and effects of the semiconductor device manufacturing method of the second embodiment will be explained.

[0217] In the semiconductor device manufacturing method of the second embodiment, the pressure change control of the conductive gas is synchronized with the change control of the high-frequency power applied inside the chamber. The high-frequency power is increased in sync with decreasing the pressure of the conductive gas. Conversely, the high-frequency power is decreased in sync with increasing the pressure of the conductive gas.

[0218] Specifically, for example, as described above, after the first etching process, at time t2, the helium pressure is reduced from the first pressure P1 to the second pressure P2, while the high-frequency power applied to the interior of chamber 20 is increased from the first power Pw1 to the second power Pw2. Furthermore, at time t3, the helium pressure is increased from the second pressure P2 to the third pressure P3, while the high-frequency power applied to the interior of chamber 20 is reduced from the second power Pw2 to the third power Pw3.

[0219] In the removal of the first reaction product after the first etching process, it is desirable to have a higher temperature for the silicon substrate 10 in order to improve the removal efficiency of the reaction product 63. Furthermore, from the viewpoint of increasing the etching throughput of the memory hole MH, it is preferable to have a faster temperature rise rate for the silicon substrate 10.

[0220] Furthermore, from the viewpoint of increasing the etching throughput of the memory hole MH, it is preferable that the temperature of the silicon substrate 10 decreases rapidly after the removal of the first reaction product.

[0221] At time t2, by increasing the high-frequency power from the first power Pw1 to the second power Pw2, more heat is input from the plasma to the silicon substrate 10. Therefore, the temperature of the silicon substrate 10 can be increased during the removal of the first reaction product. In addition, the rate of temperature rise of the silicon substrate 10 can be accelerated.

[0222] Furthermore, at time t3, by reducing the high-frequency power from the second power Pw2 to the third power Pw3, less heat is input from the plasma to the silicon substrate 10. Therefore, after the removal of the first reaction product, the rate of temperature decrease of the silicon substrate 10 can be suppressed.

[0223] Furthermore, the pressure change of the conductive gas and the change of the high-frequency power do not necessarily have to occur simultaneously. For example, the change of the high-frequency power can be made before the pressure change of the conductive gas by a predetermined time, or the change of the high-frequency power can be made after the pressure change of the conductive gas by a predetermined time.

[0224] According to the semiconductor device manufacturing method of the second embodiment, when processing the workpiece layer using dry etching, high-precision processing can be performed.

[0225] (Third Implementation)

[0226] The manufacturing method of the semiconductor device in the third embodiment differs from that in the first embodiment in that the control of the change in the first gas pressure is synchronized with the control of the change in the high-frequency power applied to the cavity. Furthermore, the manufacturing method of the semiconductor device in the third embodiment differs from that in the second embodiment in that the high-frequency power applied to the cavity during the removal of the first reaction product is lower than the high-frequency power applied to the cavity during the first etching process. Hereinafter, details that are repeated in the first or second embodiment will sometimes be omitted.

[0227] Figure 9 This is an explanatory diagram of the manufacturing method of the semiconductor device according to the third embodiment. Figure 9 This indicates the relationship between the heat-conducting gas pressure, total high-frequency power, wafer temperature, and etching time during the formation of memory aperture MH.

[0228] like Figure 9 As shown, at time t2, a second power Pw2 is applied to the interior of chamber 20. At time t2, the high-frequency power applied to the interior of chamber 20 is changed from the first power Pw1 to the second power Pw2. The second power Pw2 is lower than the first power Pw1.

[0229] Additionally, at time t3, a third electrical power Pw3 is applied to the interior of chamber 20. At time t3, the high-frequency electrical power applied to the interior of chamber 20 is changed from the second electrical power Pw2 to the third electrical power Pw3. The third electrical power Pw3 is higher than the second electrical power Pw2.

[0230] Additionally, at time t4, a fourth electrical power Pw4 is applied to the interior of chamber 20. At time t4, the high-frequency electrical power applied to the interior of chamber 20 is changed from the third electrical power Pw3 to the fourth electrical power Pw4. The fourth electrical power Pw4 is lower than the third electrical power Pw3.

[0231] Additionally, at time t5, a fifth electrical power Pw5 is applied to the interior of chamber 20. At time t5, the high-frequency electrical power applied to the interior of chamber 20 is changed from the fourth electrical power Pw4 to the fifth electrical power Pw5. The fifth electrical power Pw5 is higher than the fourth electrical power Pw4.

[0232] Additionally, at time t6, a sixth electrical power Pw6 is applied to the interior of chamber 20. At time t6, the high-frequency electrical power applied to the interior of chamber 20 is changed from the fifth electrical power Pw5 to the sixth electrical power Pw6. The sixth electrical power Pw6 is lower than the fifth electrical power Pw5.

[0233] Additionally, at time t7, the application of high-frequency power to the interior of chamber 20 is stopped. Also, at time t7, the supply of etching gas to chamber 20 is blocked.

[0234] At time t7, the etching of memory hole MH ends.

[0235] Furthermore, the pressure change of the conductive gas and the change of the high-frequency power do not necessarily have to occur simultaneously. For example, the change of the high-frequency power can be made before the pressure change of the conductive gas by a predetermined time, or the change of the high-frequency power can be made after the pressure change of the conductive gas by a predetermined time.

[0236] Next, the operation and effects of the semiconductor device manufacturing method of the third embodiment will be explained.

[0237] In the semiconductor device manufacturing method of the third embodiment, the pressure change control of the conductive gas is synchronized with the change control of the high-frequency power applied inside the chamber. The high-frequency power is reduced in sync with the decrease in the pressure of the conductive gas. Conversely, the high-frequency power is increased in sync with the increase in the pressure of the conductive gas.

[0238] Specifically, for example, as described above, after the first etching process, at time t2, the helium pressure is reduced from the first pressure P1 to the second pressure P2, while the high-frequency power applied to the interior of chamber 20 is reduced from the first power Pw1 to the second power Pw2. Furthermore, at time t3, the helium pressure is increased from the second pressure P2 to the third pressure P3, while the high-frequency power applied to the interior of chamber 20 is increased from the second power Pw2 to the third power Pw3.

[0239] During the removal of the first reaction product after the first etching process, the helium pressure decreases from the first pressure P1 to the second pressure P2, and the pressure in the thermally conductive gas region 76 decreases. If the pressure in the thermally conductive gas region 76 decreases, discharge is more likely to occur in the thermally conductive gas region 76. If discharge occurs in the thermally conductive gas region 76, there is a concern about damage to, for example, the silicon substrate 10 or the electrostatic chuck 22b.

[0240] In the semiconductor device manufacturing method of the third embodiment, for example, at time t2, discharge in the heat-conducting gas region 76 is suppressed by reducing the high-frequency power from the first power Pw1 to the second power Pw2. Therefore, damage to the silicon substrate 10 or the electrostatic chuck 22b caused by discharge can be suppressed.

[0241] According to the semiconductor device manufacturing method of the third embodiment, when processing the workpiece layer using dry etching, high-precision processing can be performed.

[0242] (Fourth implementation)

[0243] The method for manufacturing the semiconductor device in the fourth embodiment differs from the method in the first embodiment in that, after controlling the pressure of the first gas to a second pressure, a third gas with a lower thermal conductivity than the first gas is supplied between the holder and the substrate in a contact manner, instead of the first gas. After removing the first reaction product, the first gas is supplied between the holder and the substrate in a contact manner, instead of the third gas, and the pressure of the first gas is controlled to a third pressure higher than the second pressure. Hereinafter, some details that are repeated in the first embodiment will be omitted.

[0244] Figure 10 This is an explanatory diagram of the manufacturing method of the semiconductor device according to the fourth embodiment. Figure 10 This indicates the relationship between the heat-conducting gas pressure, total high-frequency power, wafer temperature, and etching time during the formation of memory aperture MH.

[0245] At time t1, a thermally conductive gas is supplied to the thermally conductive gas region 76 between the holder 22 and the silicon substrate 10. The thermally conductive gas is, for example, helium. Helium is an example of the first gas.

[0246] At time t1, the pressure of the helium gas is controlled to the first pressure P1. At time t1, the first electrical current Pw1 is applied to the interior of chamber 20.

[0247] Additionally, at time t1, etching gas is supplied to chamber 20. This etching gas is an example of the second gas. Also at time t1, refrigerant is supplied to refrigerant flow path 22ax.

[0248] After the pressure of helium gas is controlled to the first pressure P1, the first etching process is carried out to etch the laminate 60 using reactive ion etching.

[0249] After the first etching process, at time t2, the helium pressure is controlled to the second pressure P2. After the first etching process, at time t2, the helium pressure is changed from the first pressure P1 to the second pressure P2. The second pressure P2 is lower than the first pressure P1.

[0250] After the helium pressure is controlled to the second pressure P2, at time ta, argon gas is supplied to the thermally conductive gas region 76 between the holder 22 and the silicon substrate 10 to replace the helium gas. The argon gas contacts the back side of the silicon substrate 10. Argon gas is an example of a third gas. The thermal conductivity of argon gas is lower than that of helium gas.

[0251] Switching from helium supply to argon supply is achieved, for example, by controlling the heat transfer gas supply unit 44 via control circuit 54.

[0252] The pressure of the argon gas is controlled, for example, at pressure Pa. Pressure Pa is higher than the second pressure P2. Pressure Pa is, for example, equal to the first pressure P1.

[0253] In addition, Figure 10 In the diagram, the pressure of helium is represented by a solid line, and the pressure of argon is represented by a dashed line.

[0254] After the pressure of helium is controlled to the second pressure P2, the first reaction product removal is carried out to remove the reaction product 63 on the laminate 60.

[0255] After the first reaction product is removed, at time t3, helium is supplied to the thermally conductive gas region 76 between the holder 22 and the silicon substrate 10 to replace argon. The helium contacts the back side of the silicon substrate 10. The pressure of the helium is controlled at a third pressure P3. The third pressure P3 is higher than the second pressure P2.

[0256] After the helium pressure is controlled to the third pressure P3, a second etching process is performed to etch the stack 60 using reactive ion etching.

[0257] Between time t3 and time t4, a second etching process is performed to etch the stack 60.

[0258] After the second etching process, at time t4, the helium pressure is controlled to the fourth pressure P4. After the second etching process, at time t4, the helium pressure is changed from the third pressure P3 to the fourth pressure P4. The fourth pressure P4 is lower than the third pressure P3.

[0259] After the pressure of helium is controlled to the fourth pressure P4, at time tb, argon is supplied to the thermally conductive gas region 76 between the holder 22 and the silicon substrate 10 to replace helium.

[0260] The pressure of the argon gas is controlled, for example, to a pressure Pb. Pressure Pb is higher than a fourth pressure P4. Pressure Pb is, for example, equal to a third pressure P3.

[0261] After the helium pressure is controlled to the fourth pressure P4, the second reaction product removal is carried out to remove the reaction product 63 on the laminate 60.

[0262] After the removal of the second reaction product, at time t5, helium is supplied to the thermally conductive gas region 76 between the holder 22 and the silicon substrate 10 to replace argon. The helium contacts the back side of the silicon substrate 10. The pressure of the helium is controlled at a fifth pressure P5. The fifth pressure P5 is higher than the fourth pressure P4.

[0263] After controlling the helium pressure to the fifth pressure P5, a third etching process is performed to etch the stack 60 using reactive ion etching.

[0264] Between time t5 and time t6, a third etching process is performed to etch the stack 60.

[0265] After the third etching process, at time t6, the helium pressure is controlled to the sixth pressure P6. After the third etching process, at time t6, the helium pressure is changed from the fifth pressure P5 to the sixth pressure P6. The sixth pressure P6 is lower than the fifth pressure P5.

[0266] After the helium pressure is controlled to the sixth pressure P6, the third reaction product removal is carried out to remove the reaction product 63 on the laminate 60.

[0267] After the third reaction product is removed, at time t7, the application of high-frequency power to the interior of chamber 20 is stopped. Additionally, at time t7, the supply of etching gas to chamber 20 is also stopped.

[0268] At time t7, the etching of memory hole MH ends.

[0269] Next, the operation and effects of the semiconductor device manufacturing method of the fourth embodiment will be explained.

[0270] In the semiconductor device manufacturing method of the fourth embodiment, for example, at time ta, argon gas, which has a lower thermal conductivity than helium, is supplied to the heat-conducting gas region 76. Since argon gas has a lower thermal conductivity than helium, the rate of temperature change of the silicon substrate 10 is slower compared to the case with helium.

[0271] Therefore, for example, the silicon substrate 10 can be stably maintained at a temperature of 100°C or higher. Furthermore, it is easy to extend the time the silicon substrate 10 is maintained at a temperature of 100°C or higher. This, in turn, promotes the removal of reaction products.

[0272] Furthermore, hydrogen can be used instead of helium as the first gas. Additionally, nitrogen, neon, krypton, or xenon can be used instead of argon as the third gas, which has a lower thermal conductivity than the first gas.

[0273] Furthermore, the pressure Pa can be different from the first pressure P1. Additionally, the pressure Pb can be different from the third pressure P3. Furthermore, the pressure Pc can be different from the fifth pressure P5.

[0274] According to the semiconductor device manufacturing method of the fourth embodiment, when processing the workpiece layer using dry etching, high-precision processing can be performed.

[0275] (Fifth Embodiment)

[0276] The semiconductor device manufacturing method of the fifth embodiment involves placing a substrate having a processed layer on a holder disposed in a chamber, supplying a first gas in contact with the substrate between the holder and the substrate, controlling the pressure of the first gas to a first pressure, performing a first etching process to form a recess by using a reactive ion etching method with the first processing gas on the processed layer, after the first etching process, controlling the pressure of the first gas to a second pressure lower than the first pressure, performing a first process to supply hydrogen radicals to the recess using a hydrogen-containing second processing gas while the substrate temperature is above 200°C and below 350°C, and after the first process, controlling the pressure of the first gas to a third pressure higher than the second pressure, and performing a second etching process to etch the bottom surface of the recess by using a reactive ion etching method with a third processing gas.

[0277] The semiconductor device manufactured by the semiconductor device manufacturing method of the fifth embodiment is the same as the semiconductor device manufactured by the semiconductor device of the first embodiment. The semiconductor device manufactured by the semiconductor device manufacturing method of the fifth embodiment is a non-volatile memory 100 with storage cells arranged in three dimensions. Figure 1 This is a cross-sectional view of the memory cell array of the non-volatile memory 100. In the following description of the non-volatile memory 100, some details that are repeated in the first embodiment are omitted.

[0278] Furthermore, the reactive ion etching apparatus used in the semiconductor device manufacturing method of the fifth embodiment is the same as the reactive ion etching apparatus used in the semiconductor device manufacturing method of the first embodiment. Figure 2 This is a schematic diagram of an example of a reactive ion etching apparatus used in the semiconductor device manufacturing method of the fifth embodiment. Figure 2 The reactive ion etching apparatus (RIE apparatus) is a dual-frequency capacitively coupled plasma apparatus (CCP apparatus). Hereinafter, the description of the RIE apparatus will omit some details that are repeated in the first embodiment.

[0279] Next, an example of the manufacturing method of the semiconductor device according to the fifth embodiment will be described.

[0280] Figure 11 This is an explanatory diagram of the manufacturing method of the semiconductor device according to the fifth embodiment. Figures 12-15 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to the fifth embodiment. Figures 12-15 Corresponding to Figure 1 It contains a section of channel layer 11.

[0281] First, a multilayer 60 is formed on the silicon substrate 10. Figure 12(a) The silicon substrate 10 is a semiconductor wafer. The laminate 60 is an insulating layer. The silicon substrate 10 is an example of a substrate. The laminate 60 is an example of a layer to be processed. The silicon substrate 10 is... Figure 2 An example of a semiconductor wafer W.

[0282] The laminate 60 comprises alternating layers of silicon oxide film 60a and silicon nitride film 60b. The silicon oxide film 60a and silicon nitride film 60b are formed, for example, by Chemical Vapor Deposition (CVD). Silicon oxide film 60a is an example of the first layer. Silicon nitride film 60b is an example of the second layer.

[0283] A portion of the silicon oxide film 60a will eventually become the interlayer insulating layer 12.

[0284] Next, a carbon layer 62 with a pore pattern 62a is formed on the laminate 60. Figure 12 (b) The carbon layer 62 is an example of a mask layer. The carbon layer 62 is formed, for example, by sputtering. The hole pattern 62a is formed, for example, using photolithography and RIE.

[0285] As a mask layer, for example, a resist layer, an insulating layer, or a metal layer can also be used.

[0286] Next, the silicon substrate 10 is moved into the chamber 20 of the RIE device. The silicon substrate 10 is then placed on the holder 22 provided in the chamber 20. The silicon substrate 10 is an example of a substrate.

[0287] In chamber 20 of the RIE device, a memory hole MH is formed using reactive ion etching with carbon layer 62 as a mask. Figure 12 (c)~ Figure 14 (a)). The memory hole MH is etched while the pressure of the heat-conducting gas cooling the silicon substrate 10 is periodically varied. The memory hole MH is an example of a recess.

[0288] Figure 11 This indicates the relationship between the heat-conducting gas pressure, total high-frequency power, wafer temperature, and etching time during the formation of the memory aperture MH. Figure 11 The timing of supplying hydrogen plasma to the silicon substrate 10 is also shown.

[0289] At time t1, a thermally conductive gas is supplied to the thermally conductive gas region 76 between the holder 22 and the silicon substrate 10. The thermally conductive gas is, for example, helium. The helium gas contacts the back side of the silicon substrate 10. Helium is an example of a first gas.

[0290] At time t1, the pressure of the helium gas is controlled to a first pressure P1. The pressure of the helium gas is controlled, for example, by using the flow control of the first main valve 50. By adjusting the opening of the first main valve 50, the pressure of the helium gas is controlled to the first pressure P1.

[0291] The first pressure P1 is, for example, above 133 Pa (1 Torr) and below 133-32 Pa (100 Torr).

[0292] Additionally, at time t1, high-frequency power is applied to the interior of chamber 20. For example, using a first high-frequency power source 24, a first high-frequency power is applied between the support portion 22a of retainer 22 and the cluster plate 32. For example, using a second high-frequency power source 26, a second high-frequency power is applied to the support portion 22a of retainer 22. The sum of the first high-frequency power and the second high-frequency power is called the total high-frequency power. At time t1, a first power source Pw1 is applied to the interior of chamber 20.

[0293] Additionally, at time t1, a first etching gas is supplied to chamber 20. The first etching gas is an example of a first processing gas. The etching gas is supplied to chamber 20 from processing gas supply piping 30 via cluster plate 32.

[0294] The first etching gas contains, for example, carbon (C) and fluorine (F).

[0295] Additionally, at time t1, refrigerant is supplied to the refrigerant flow path 22ax. The refrigerant is, for example, a fluorine-based inert liquid. By supplying refrigerant to the refrigerant flow path 22ax, the temperature of the support portion 22a of the retainer 22 and the electrostatic chuck 22b decreases. The temperature of the support portion 22a of the retainer 22 and the electrostatic chuck 22b is, for example, between -150°C and 20°C.

[0296] After controlling the helium gas pressure to the first pressure P1, a first etching process is performed to etch the laminate 60 using reactive ion etching. Figure 12 (c)). Between time t1 and time t2, a first etching process is performed to etch the stacked layer 60. During the first etching process, the memory via MH does not penetrate the stacked layer 60.

[0297] During the first etching process, the temperature of the silicon substrate 10 is, for example, between -150°C and 20°C. During the first etching process, for example, a first state in which the temperature of the silicon substrate 10 is between -150°C and 20°C is achieved.

[0298] During the first etching process, a first protective film 64a is formed on the surface of the memory hole MH. The first protective film 64a is formed, for example, on the sidewall of the memory hole MH. The first protective film 64a is formed simultaneously with the formation of the memory hole MH. The first protective film 64a is an example of a first film.

[0299] The first protective film 64a is a reaction product derived from the first etching gas. The first protective film 64a may contain, for example, carbon (C) and fluorine (F). The first protective film 64a may be, for example, a fluorocarbon film.

[0300] After the first etching process, at time t2, the helium pressure is controlled to the second pressure P2. After the first etching process, at time t2, the helium pressure is changed from the first pressure P1 to the second pressure P2. The second pressure P2 is lower than the first pressure P1.

[0301] The pressure of helium is controlled, for example, by using flow control of the first main valve 50. For example, by closing the first main valve 50, the inflow of helium into the heat-conducting gas region 76 is blocked. For example, by closing the first main valve 50, the second pressure P2 is brought close to a vacuum.

[0302] The second pressure P2 is, for example, above 0 Pa and below 13.3 Pa (0.1 Torr). The second pressure P2 is, for example, less than one percent of the first pressure P1.

[0303] After the first etching process, for example, at time t3, a second electric current Pw2 is applied to the interior of chamber 20. At time t3, the high-frequency electric current applied to the interior of chamber 20 is changed from the first electric current Pw1 to the second electric current Pw2. The second electric current Pw2 is lower than the first electric current Pw1.

[0304] After controlling the helium pressure to a second pressure P2 and changing the high-frequency power applied to the interior of chamber 20 to a second power Pw2, the first modification process is performed. Figure 12 (d)). In the first modification process, hydrogen radicals are supplied to the memory hole MH in chamber 20. The first modification process is an example of the first process.

[0305] During the first refining process, for example, at time t3, a first refining gas is supplied to the interior of chamber 20. The first refining gas is a hydrogen (H)-containing gas. The first refining gas, for example, contains hydrogen gas. The first refining gas is an example of the second processing gas.

[0306] During the first modification process, the gas supplied to the interior of chamber 20 is switched from the first etching gas to the first modification gas. For example, at time t3, the gas supplied to the interior of chamber 20 is switched from the first etching gas to the first modification gas.

[0307] During the first modification process, a plasma containing hydrogen radicals is generated by applying high-frequency electricity to hydrogen gas.

[0308] Plasma containing hydrogen radicals is supplied to the surface of silicon substrate 10. The hydrogen radicals are then supplied to memory aperture MH. The surface of the first protective film 64a is exposed to the hydrogen radicals.

[0309] The first modification treatment was performed when the temperature of the silicon substrate 10 was above 200°C and below 350°C. During the first modification treatment, a second state was achieved where the temperature of the silicon substrate 10 was above 200°C and below 350°C.

[0310] At time t2, after the helium pressure is controlled from the first pressure P1 to the second pressure P2, the temperature of the silicon substrate 10 rises, achieving a second state where the temperature of the silicon substrate 10 is above 200°C. Heat propagation in the helium is suppressed by reducing the helium pressure. This suppression of heat dissipation from the silicon substrate 10 to the holder 22 via the helium causes the temperature of the silicon substrate 10 to rise.

[0311] During the first modification treatment, the first protective film 64a is modified into a first modified protective film 65a. The chemical composition of the first modified protective film 65a is different from that of the first protective film 64a, for example.

[0312] During the first modification treatment, the first protective film 64a is reduced, for example. During the first modification treatment, for example, the fluorine concentration of the first protective film 64a decreases.

[0313] During the first modification treatment, for example, no film is formed on the first protective film 64a. After the first modification treatment, for example, the inner diameter of the memory hole MH does not decrease. After the first modification treatment, for example, the volume of the cavity portion of the memory hole MH does not decrease.

[0314] After the first refining process, at time t4, the helium pressure is controlled to the third pressure P3. After the first refining process, at time t4, the helium pressure is changed from the second pressure P2 to the third pressure P3. After achieving the second state, the helium pressure is controlled to the third pressure P3.

[0315] The third pressure P3 is higher than the second pressure P2. The pressure of helium is controlled, for example, by using the flow control of the first main valve 50. For example, by opening the first main valve 50, helium begins to flow into the heated gas region 76. By adjusting the opening degree of the first main valve 50, the pressure of the helium is controlled to the third pressure P3.

[0316] The third pressure P3 is, for example, above 133 Pa (1 Torr) and below 13332 Pa (100 Torr). The third pressure P3 is, for example, equal to the first pressure P1.

[0317] After the first modification treatment, for example, at time t4, a third electric current Pw3 is applied to the interior of chamber 20. At time t4, the high-frequency electric current applied to the interior of chamber 20 is changed from the second electric current Pw2 to the third electric current Pw3. The third electric current Pw3 is higher than the second electric current Pw2.

[0318] Additionally, at time t4, a second etching gas is supplied to chamber 20. This second etching gas is an example of a third processing gas. The second etching gas is supplied to chamber 20 from the processing gas supply pipe 30 via the spray plate 32. For example, the gas supplied to the interior of chamber 20 at time t4 may be switched from the first modified gas to the second etching gas.

[0319] The second etching gas contains, for example, carbon (C) and fluorine (F).

[0320] After controlling the helium pressure to a third pressure P3, changing the high-frequency power applied to the interior of chamber 20 to a third power Pw3, and supplying the interior of chamber 20 with the second etching gas, a second etching process is performed to etch the laminate 60 using reactive ion etching. Figure 13 (a)).

[0321] The carbon layer 62 was used as a mask for the second etching process.

[0322] The memory hole MH is etched at least on its bottom surface using a second etching process. This second etching process is performed between time t4 and time t5. During the second etching process, the memory hole MH does not penetrate the stacked layer 60.

[0323] By increasing the pressure of the helium gas from the second pressure P2 to the third pressure P3, heat transfer in the helium gas is promoted. This promotes heat dissipation from the silicon substrate 10 to the holder 22 via the helium gas, thereby reducing the temperature of the silicon substrate 10.

[0324] During the second etching process, the temperature of the silicon substrate 10 is, for example, between -150°C and 20°C. During the second etching process, for example, a third state is achieved where the temperature of the silicon substrate 10 is between -150°C and 20°C.

[0325] During the second etching process, a second protective film 64b is formed on the surface of the memory hole MH. The second protective film 64b is formed, for example, on the sidewall of the memory hole MH in the portion that has become darker due to the second etching process. The second protective film 64b is an example of a second film.

[0326] The second protective film 64b is a reaction product derived from the second etching gas. The second protective film 64b may contain, for example, carbon (C) and fluorine (F). The second protective film 64b may be, for example, a fluorocarbon film.

[0327] After the second etching process, at time t5, the helium pressure is controlled to the fourth pressure P4. After the second etching process, at time t5, the helium pressure is changed from the third pressure P3 to the fourth pressure P4. The fourth pressure P4 is lower than the third pressure P3.

[0328] The pressure of helium is controlled, for example, by using flow control of the first main valve 50. For example, by closing the first main valve 50, the inflow of helium into the heat-conducting gas region 76 is blocked. For example, by closing the first main valve 50, the fourth pressure P4 is brought close to a vacuum.

[0329] The fourth pressure P4 is, for example, above 0 Pa and below 13.3 Pa (0.1 Torr). The fourth pressure P4 is, for example, less than one percent of the third pressure P3.

[0330] After the second etching process, for example, at time t6, a fourth power Pw4 is applied to the interior of chamber 20. At time t6, the high-frequency power applied to the interior of chamber 20 is changed from the third power Pw3 to the fourth power Pw4. The fourth power Pw4 is lower than the third power Pw3.

[0331] After controlling the helium pressure to the third pressure P3 and changing the high-frequency power applied to the interior of chamber 20 to the fourth power Pw4, the second modification process is performed. Figure 13 (b)). In the second modification process, hydrogen radicals are supplied to the memory hole MH in chamber 20. The second modification process is an example of the second process.

[0332] During the second refining process, for example, at time t6, a second refining gas is supplied to the interior of chamber 20. The second refining gas is a gas containing hydrogen (H). For example, the second refining gas contains hydrogen gas. The second refining gas is an example of the fourth processing gas.

[0333] During the second modification process, the gas supplied to the interior of chamber 20 is switched from the second etching gas to the second modification gas. For example, at time t6, the gas supplied to the interior of chamber 20 is switched from the second etching gas to the second modification gas.

[0334] During the second modification process, a plasma containing hydrogen radicals is generated by applying high-frequency electricity to hydrogen gas.

[0335] A plasma containing hydrogen radicals is supplied to the surface of the silicon substrate 10. The hydrogen radicals are then supplied to the memory aperture MH. The surface of the second protective film 64b is exposed to the hydrogen radicals.

[0336] The second modification treatment was performed when the temperature of the silicon substrate 10 was between 200°C and 350°C. During the second modification treatment, a fourth state was achieved where the temperature of the silicon substrate 10 was between 200°C and 350°C.

[0337] At time t5, after the helium pressure is controlled from the third pressure P3 to the fourth pressure P4, the temperature of the silicon substrate 10 rises, achieving the fourth state where the temperature of the silicon substrate 10 is above 200°C. The heat transfer in the helium gas is suppressed by reducing the helium pressure. This suppression of heat dissipation from the silicon substrate 10 to the holder 22 via the helium gas causes the temperature of the silicon substrate 10 to rise.

[0338] During the second modification treatment, the second protective film 64b is modified into a second modified protective film 65b. The chemical composition of the second modified protective film 65b is different from that of the second protective film 64b, for example.

[0339] During the second modification treatment, the second protective film 64b is reduced, for example. During the second modification treatment, for example, the fluorine concentration of the second protective film 64b decreases.

[0340] During the second modification treatment, for example, no film is formed on the second protective film 64b. After the second modification treatment, for example, the inner diameter of the memory hole MH does not decrease. After the second modification treatment, for example, the volume of the cavity portion of the memory hole MH does not decrease.

[0341] After the second refining process, at time t7, the helium pressure is controlled to pressure 5, P5. After the second refining process, at time t7, the helium pressure is changed from pressure 4, P4, to pressure 5, P5. After achieving the fourth state, the helium pressure is controlled to pressure 5, P5.

[0342] The fifth pressure, P5, is higher than the fourth pressure, P4. The pressure of the helium gas is controlled, for example, by using the flow control of the first main valve 50. For example, by opening the first main valve 50, helium gas begins to flow into the heated gas region 76. By adjusting the opening degree of the first main valve 50, the pressure of the helium gas is controlled to the fifth pressure, P5.

[0343] The fifth pressure P5 is, for example, between 133 Pa (1 Torr) and 13332 Pa (100 Torr). The fifth pressure P5 is, for example, equal to the first pressure P1.

[0344] Following the second modification treatment, for example, at time t7, a fifth electrical current Pw5 is applied to the interior of chamber 20. At time t7, the high-frequency electrical current applied to the interior of chamber 20 is changed from the fourth electrical current Pw4 to the fifth electrical current Pw5. The fifth electrical current Pw5 is higher than the fourth electrical current Pw4.

[0345] Additionally, at time t7, a third etching gas is supplied to chamber 20. This third etching gas is an example of the fifth processing gas. The third etching gas is supplied to chamber 20 from the processing gas supply pipe 30 via the spray plate 32. For example, the gas supplied to the interior of chamber 20 at time t7 may be switched from the second modified gas to the third etching gas.

[0346] The third etching gas contains, for example, carbon (C) and fluorine (F).

[0347] The pressure of the helium gas is controlled to the fifth pressure P5, the high-frequency power applied to the inside of the chamber 20 is changed to the fifth power Pw5, and after the third etching gas is supplied to the inside of the chamber 20, the third etching process is performed to etch the laminate 60 using reactive ion etching. Figure 13 (c) The carbon layer 62 is used as a mask for the third etching process.

[0348] The memory hole MH is etched at least on its bottom surface using the third etching process. This third etching process is performed between time t7 and time t8. During the third etching process, the memory hole MH does not penetrate the stacked layer 60.

[0349] By increasing the pressure of the helium gas from pressure 4 P4 to pressure 5 P5, heat transfer in the helium gas is facilitated. This promotes heat dissipation from the silicon substrate 10 to the holder 22 via the helium gas, thereby reducing the temperature of the silicon substrate 10.

[0350] During the third etching process, the temperature of the silicon substrate 10 is, for example, between -150°C and 20°C. During the third etching process, for example, a fifth state is achieved where the temperature of the silicon substrate 10 is between -150°C and 20°C.

[0351] During the third etching process, a third protective film 64c is formed on the surface of the memory hole MH. The third protective film 64c is formed, for example, on the sidewall of the memory hole MH in the portion that has become darker through the third etching process. The third protective film 64c is an example of a third film.

[0352] The third protective film 64c is a reaction product derived from the third etching gas. The third protective film 64c contains, for example, carbon (C) and fluorine (F). The third protective film 64c is, for example, a fluorocarbon film.

[0353] After the third etching process, at time t8, the helium pressure is controlled to the sixth pressure P6. After the third etching process, at time t8, the helium pressure is changed from the fifth pressure P5 to the sixth pressure P6. The sixth pressure P6 is lower than the fifth pressure P5.

[0354] The pressure of helium is controlled, for example, by using flow control of the first main valve 50. For example, by closing the first main valve 50, the inflow of helium into the heat-conducting gas region 76 is blocked. For example, by closing the first main valve 50, the sixth pressure P6 is brought close to a vacuum.

[0355] The sixth pressure P6 is, for example, above 0 Pa and below 13.3 Pa (0.1 Torr). The sixth pressure P6 is, for example, less than one percent of the fifth pressure P5.

[0356] After the third etching process, for example, at time t9, a sixth power Pw6 is applied to the interior of chamber 20. At time t9, the high-frequency power applied to the interior of chamber 20 is changed from the fifth power Pw5 to the sixth power Pw6. The sixth power Pw6 is lower than the fifth power Pw5.

[0357] After controlling the helium pressure to the sixth pressure P6 and changing the high-frequency power applied to the interior of chamber 20 to the sixth power Pw6, the third modification process is performed. Figure 13 (d)). In the third modification process, hydrogen radicals are supplied to the memory hole MH in chamber 20. The third modification process is an example of the third process.

[0358] During the third refining process, for example, at time t9, a third refining gas is supplied to the interior of chamber 20. The third refining gas is a gas containing hydrogen (H). For example, the third refining gas contains hydrogen gas.

[0359] During the third modification process, the gas supplied to the interior of chamber 20 is switched from the third etching gas to the third modification gas. For example, at time t9, the gas supplied to the interior of chamber 20 is switched from the third etching gas to the third modification gas.

[0360] During the third modification process, a plasma containing hydrogen radicals is generated by applying high-frequency electricity to hydrogen gas.

[0361] Plasma containing hydrogen radicals is supplied to the surface of silicon substrate 10. The hydrogen radicals are then supplied to memory vias MH. The surface of the third protective film 64c is exposed to the hydrogen radicals.

[0362] The third modification treatment was performed when the temperature of the silicon substrate 10 was between 200°C and 350°C. During the third modification treatment, the sixth state, where the temperature of the silicon substrate 10 was between 200°C and 350°C, was achieved.

[0363] At time t8, after the helium pressure is controlled from pressure P5 (5th pressure) to pressure P6 (6th pressure), the temperature of the silicon substrate 10 rises, achieving a sixth state where the temperature of the silicon substrate 10 is above 200°C. The heat transfer within the helium gas is suppressed by decreasing the helium pressure. This suppression of heat dissipation from the silicon substrate 10 to the holder 22 via the helium gas causes the temperature of the silicon substrate 10 to rise.

[0364] During the third modification treatment, the third protective film 64c is modified into a third modified protective film 65c. The chemical composition of the third modified protective film 65c is different from that of the third protective film 64c, for example.

[0365] During the third modification treatment, the third protective film 64c is reduced, for example. During the third modification treatment, for example, the fluorine concentration of the third protective film 64c decreases.

[0366] During the third modification treatment, for example, no film is formed on the third protective film 64c. After the third modification treatment, for example, the inner diameter of the memory hole MH does not decrease. After the third modification treatment, for example, the volume of the cavity portion of the memory hole MH does not decrease.

[0367] After the third refining process, at time t10, the helium pressure is controlled to the 7th pressure P7. After the third refining process, at time t10, the helium pressure is changed from the 6th pressure P6 to the 7th pressure P7. After achieving the 6th state, the helium pressure is controlled to the 7th pressure P7.

[0368] The seventh pressure, P7, is higher than the sixth pressure, P6. The pressure of the helium gas is controlled, for example, by using the flow control of the first main valve 50. For example, by opening the first main valve 50, helium gas begins to flow into the heated gas region 76. By adjusting the opening degree of the first main valve 50, the pressure of the helium gas is controlled to the seventh pressure, P7.

[0369] The seventh pressure P7 is, for example, between 133 Pa (1 Torr) and 13332 Pa (100 Torr). The seventh pressure P7 is, for example, equal to the first pressure P1.

[0370] After the third modification treatment, for example, at time t10, a seventh power Pw7 is applied to the interior of chamber 20. At time t10, the high-frequency power applied to the interior of chamber 20 is changed from the sixth power Pw6 to the seventh power Pw7. The seventh power Pw7 is higher than the sixth power Pw6.

[0371] Additionally, at time t10, a fourth etching gas is supplied to chamber 20. The fourth etching gas is supplied to chamber 20 from the process gas supply pipe 30 via the cluster plate 32. For example, the gas supplied to the interior of chamber 20 at time t10 may be switched from the third modified gas to the fourth etching gas.

[0372] The fourth etching gas contains, for example, carbon (C) and fluorine (F).

[0373] After controlling the helium pressure to the 7th pressure P7, changing the high-frequency power applied to the interior of chamber 20 to the 7th power Pw7, and supplying the 4th etching gas into the interior of chamber 20, a 4th etching process is performed to etch the laminate 60 using reactive ion etching. Figure 14 (a)). The carbon layer 62 is used as a mask for the fourth etching process.

[0374] The memory hole MH is etched at least on its bottom surface through the fourth etching process. The fourth etching process is performed between time t10 and time t11. During the fourth etching process, the memory hole MH penetrates the stacked layer 60.

[0375] By increasing the pressure of the helium gas from pressure 6 P6 to pressure 7 P7, heat transfer in the helium gas is facilitated. This promotes heat dissipation from the silicon substrate 10 to the holder 22 via the helium gas, thereby reducing the temperature of the silicon substrate 10.

[0376] During the fourth etching process, the temperature of the silicon substrate 10 is, for example, between -150°C and 20°C. During the fourth etching process, for example, a seventh state is achieved where the temperature of the silicon substrate 10 is between -150°C and 20°C.

[0377] During the fourth etching process, a fourth protective film 64d is formed on the surface of the memory hole MH. The fourth protective film 64d is formed, for example, on the sidewall of the memory hole MH in the portion that has become darker by the fourth etching process.

[0378] The fourth protective film 64d is a reaction product derived from the fourth etching gas. The fourth protective film 64d may contain, for example, carbon (C) and fluorine (F). The fourth protective film 64d may be, for example, a fluorocarbon film.

[0379] After the fourth etching process, at time t11, the application of high-frequency power to the interior of chamber 20 is stopped. Additionally, at time t11, the supply of etching gas for the fourth etching process to chamber 20 is also stopped.

[0380] At time t11, the etching of memory hole MH ends.

[0381] The aspect ratio of the memory via MH through the stacked layer 60 is, for example, 30 or higher. After the fourth etching process, the silicon substrate 10 is removed from the chamber 20 of the RIE device.

[0382] Furthermore, the first, second, third, and fourth etching gases may contain, for example, carbon (C) and fluorine (F). Additionally, the first, second, third, and fourth etching gases may contain, for example, oxygen (O). Furthermore, the first, second, third, and fourth etching gases may contain, for example, hydrogen (H).

[0383] The first, second, third, and fourth etching gases may contain, for example, CxHyFz (where x is an integer greater than or equal to 1, y is an integer greater than or equal to 0, and z is an integer greater than or equal to 1). The first, second, third, and fourth etching gases may contain, for example, C4F6, C4F8, and CH2F2.

[0384] The first etching gas, the second etching gas, the third etching gas, and the fourth etching gas contain, for example, oxygen.

[0385] The first, second, third, and fourth etching gases are, for example, a mixture of C4F6, C4F8, CH2F2, and oxygen.

[0386] The first etching gas, the second etching gas, the third etching gas, and the fourth etching gas are, for example, the same gas. Alternatively, for example, at least one of the first etching gas, the second etching gas, the third etching gas, and the fourth etching gas is different from the other gases.

[0387] Furthermore, the first, second, and third modified gases contain hydrogen (H). For example, the first, second, and third modified gases contain hydrogen gas.

[0388] Next, the carbon layer 62, the first modified protective film 65a, the second modified protective film 65b, the third modified protective film 65c, and the fourth protective film 64d are removed. Figure 14 (b) The removal of carbon layer 62, first modified protective film 65a, second modified protective film 65b, third modified protective film 65c and fourth protective film 64d is carried out, for example, by ashing treatment using oxygen plasma.

[0389] Next, a multilayer insulating layer 66 is formed in the memory hole MH. Figure 14 (c)). The stacked insulating layer 66 has, for example, a stacked structure of a silicon oxide film, a silicon nitride film, and an aluminum oxide film. The stacked insulating layer 66 ultimately becomes the gate insulating layer 13.

[0390] Next, a polysilicon layer 68 is formed in the memory hole MH. Figure 14 (d)). The polysilicon layer 68 will eventually become the channel layer 11.

[0391] Next, the silicon nitride film 60b was selectively removed. Figure 15 (a)).

[0392] Next, a first tungsten layer 70 is formed in the region where the silicon nitride film 60b has been removed. Figure 15 (b)). The first tungsten layer 70 will eventually become the word line WL.

[0393] Next, a second tungsten layer 69 is formed on the polycrystalline silicon layer 68. Figure 15 (c)). The second tungsten layer 69 will eventually become the bit line BL.

[0394] Manufactured using the above manufacturing methods Figure 1 The non-volatile memory 100 shown.

[0395] Next, the operation and effects of the semiconductor device manufacturing method of the fifth embodiment will be explained.

[0396] For ease of explanation, the first etching process, the second etching process, the third etching process, and the fourth etching process will sometimes be referred to simply as etching process. Additionally, the first modification process, the second modification process, and the third modification process will sometimes be referred to simply as modification process. Furthermore, the first protective film 64a, the second protective film 64b, and the third protective film 64c will sometimes be referred to simply as protective film 64. Additionally, the first modified protective film 65a, the second modified protective film 65b, and the third modified protective film 65c will sometimes be referred to simply as modified protective film 65.

[0397] In non-volatile memory where storage cells are arranged in three dimensions, to achieve higher memory capacity, for example, the aperture of the memory hole is reduced, increasing the number of word lines (WL). If the aperture of the memory hole is reduced to increase the number of word lines (WL), then the memory hole with a high aspect ratio (depth of memory hole / aperture of memory hole) must be formed.

[0398] If the aspect ratio of the memory via becomes high, it can cause the memory via to become curved. The curved shape of the memory via is caused by the expansion of the aperture during the etching process that forms the memory via.

[0399] During the etching of memory vias, substances derived from the plasma-generated etching gas adhere to the sidewalls, forming a protective film. By forming this protective film on the sidewalls of the memory vias, etching of the sidewalls is prevented, thereby inhibiting via enlargement.

[0400] The reason for the aperture enlargement during the etching process of memory vias is believed to be that the protective film formed on the sidewalls of the memory via reacts with the material exposed on the sidewalls during etching, causing the etching of the sidewalls of the memory via to progress. The reaction between the protective film and the exposed material on the sidewalls occurs, for example, due to the kinetic energy of ions incident on the protective film during etching. The progress of etching on the sidewalls of the memory via leads to the enlargement of the aperture size.

[0401] The sidewalls of the memory hole are formed, for example, of a silicon-containing (Si) material such as silicon oxide or silicon nitride. The protective film formed on the sidewalls of the memory hole is, for example, a fluorocarbon film containing carbon and fluorine.

[0402] For example, silicon in the material forming the sidewalls reacts with fluorine in the protective film to form silicon fluoride. After formation, the silicon fluoride escapes in gaseous form, thus allowing etching of the memory hole's sidewalls to progress. This etching progress enlarges the memory hole's diameter.

[0403] In the semiconductor device manufacturing method of the fifth embodiment, during the etching of the memory hole MH, the protective film 64 formed on the sidewall is modified to form a modified protective film 65. By modifying the protective film 64 into the modified protective film 65, the reaction between the modified protective film 65 and the material forming the sidewall of the memory hole MH is suppressed.

[0404] Specifically, for example, the protective film 64 is reduced to form a modified protective film 65. Specifically, for example, the fluorine concentration of the protective film 64 is reduced to form a modified protective film 65.

[0405] Specifically, for example, hydrogen radicals are supplied to the surface of the protective film 64, causing the hydrogen radicals to react with the fluorine in the protective film 64 to produce hydrogen fluoride. The produced hydrogen fluoride is released in gaseous form, forming a modified protective film 65 with a lower fluorine concentration compared to the protective film 64.

[0406] Because the fluorine concentration of the modified protective film 65 is reduced, the reaction between the modified protective film 65 and the material forming the sidewalls of the memory hole MH is suppressed. Therefore, the etching of the sidewalls of the memory hole MH is suppressed, and the aperture enlargement of the memory hole MH is suppressed.

[0407] Furthermore, because the fluorine concentration in the modified protective film 65 is reduced, the ratio of carbon-carbon bonds (CC bonds), which have a higher bonding energy than carbon-fluorine bonds (CF bonds), increases in the modified protective film 65. Therefore, the etch resistance of the protective film during memory hole MH formation also increases.

[0408] Therefore, according to the semiconductor device manufacturing method of the fifth embodiment, etching of the sidewalls of the memory hole MH can be suppressed, and the shape of the memory hole can be suppressed from becoming a curved shape.

[0409] When modifying the protective film 64 through a modification process, it can sometimes be difficult to modify the protective film 64 at the bottom of deep trenches with a high aspect ratio. If the modification of the protective film 64 at the bottom of the trench is insufficient, the shape of the bottom of the trench will become curved.

[0410] In the semiconductor device manufacturing method of the fifth embodiment, hydrogen radicals are used during the modification process. Hydrogen radicals are less prone to deactivation than hydrogen ions. Therefore, it is believed that hydrogen radicals can easily reach the bottom of deep trenches with a large aspect ratio without deactivation.

[0411] In order to use hydrogen radicals to modify the protective film 64, energy must be provided to cause the hydrogen radicals to react with the fluorine in the protective film 64. In the semiconductor device manufacturing method of the fifth embodiment, the temperature of the silicon substrate 10 is increased. In the semiconductor device manufacturing method of the fifth embodiment, thermal energy is used as the energy to cause the hydrogen radicals to react with the fluorine in the protective film 64.

[0412] According to the inventors' research, a temperature above 200°C is required for hydrogen free radicals to react with fluorine in the fluorocarbon film and to abstract fluorine from the fluorocarbon film. Furthermore, it is clear that the fluorocarbon film in contact with the silicon oxide film reacts at temperatures exceeding 350°C, leading to etching of the silicon oxide film. Additionally, it is evident that the decomposition of the fluorocarbon film is more pronounced at temperatures exceeding 300°C.

[0413] In the semiconductor device manufacturing method of the fifth embodiment, the temperature of the silicon substrate 10 on which the laminate 60 is formed is controlled to be 200°C or higher. Therefore, hydrogen free radicals can react with fluorine in the protective film 64 to modify the protective film 64.

[0414] Furthermore, in the semiconductor device manufacturing method of the fifth embodiment, the temperature of the silicon substrate 10 on which the stacked body 60 is formed is controlled to be 350°C or below. Therefore, the reaction between the material of the sidewalls of the memory hole MH and the protective film 64 is suppressed, and the etching of the sidewall material is suppressed. Thus, the aperture expansion of the memory hole MH can be suppressed, and the shape of the memory hole MH can be prevented from becoming curved.

[0415] From the viewpoint of promoting the modification of the protective film 64, the temperature of the silicon substrate 10 during the modification treatment is preferably 225°C or higher, more preferably 250°C or higher. Furthermore, from the viewpoint of suppressing the etching of the sidewall material and suppressing the decomposition of the protective film 64, the temperature of the silicon substrate 10 during the modification treatment is preferably 325°C or lower, more preferably 300°C or lower. Moreover, by controlling the temperature of the silicon substrate within the aforementioned range, the reaction product 63 of the first embodiment can also be removed.

[0416] In the semiconductor device manufacturing method of the fifth embodiment, from the viewpoint of increasing the etching rate of the stacked body 60 and increasing the throughput of the etching process, the temperature of the silicon substrate 10 on which the stacked body 60 is formed is preferably low. In the semiconductor device manufacturing method of the fifth embodiment, the temperature of the silicon substrate 10 during the etching process is preferably 20°C or lower, more preferably 0°C or lower. The temperature of the silicon substrate 10 during the modification process is preferably higher than the temperature of the silicon substrate 10 during the etching process.

[0417] In the semiconductor device manufacturing method of the fifth embodiment, when forming the memory hole MH, the temperature of the silicon substrate 10 having the laminate 60 as the processed layer is varied. That is, the low temperature state of the silicon substrate 10 and the high temperature state of the silicon substrate 10 are alternated repeatedly.

[0418] The first, third, and fifth states correspond to low-temperature states. Conversely, the second, fourth, and sixth states correspond to high-temperature states.

[0419] When the silicon substrate 10 is at a low temperature, the memory hole MH is etched. On the other hand, when the silicon substrate 10 is at a high temperature, the protective film 64 is modified.

[0420] In the semiconductor device manufacturing method of the fifth embodiment, by forming memory holes MH within the same RIE device while alternating between a low-temperature state and a high-temperature state of the silicon substrate 10, the processing accuracy of the memory hole shape is improved. Furthermore, the etching throughput of the memory holes MH is increased.

[0421] In the semiconductor device manufacturing method of the fifth embodiment, the transition between a high-temperature state and a low-temperature state of the silicon substrate 10 is achieved by changing the pressure of a heat-conducting gas. The heat-conducting gas is, for example, helium.

[0422] The heat transfer between the silicon substrate 10 and the holder 22 is altered by changing the pressure of the heat-conducting gas. If the pressure of the heat-conducting gas increases, heat transfer accelerates; if the pressure decreases, heat transfer is suppressed. For example, by decreasing the pressure of the heat-conducting gas, the silicon substrate 10 can be changed from a low-temperature state to a high-temperature state. Conversely, by increasing the pressure of the heat-conducting gas, the silicon substrate 10 can be changed from a high-temperature state to a low-temperature state.

[0423] In the semiconductor device manufacturing method of the fifth embodiment, the temperature of the silicon substrate 10 is changed by varying the pressure of the heat-conducting gas used to cool the silicon substrate 10. Therefore, it is unnecessary to add a new structure to the RIE device to change the temperature of the silicon substrate 10. This allows for easy improvement in the processing accuracy of the memory hole shape.

[0424] In the semiconductor device manufacturing method of the fifth embodiment, when a modification process is performed, ions in the plasma collide with the carbon layer 62. From the viewpoint of suppressing the etching of the carbon layer 62, the high-frequency power applied to the silicon substrate 10 during the modification process is preferably lower than the high-frequency power applied to the silicon substrate 10 during the etching process.

[0425] According to the semiconductor device manufacturing method of the fifth embodiment, the shape of the memory hole can be suppressed from becoming a curved shape, and the memory hole can be formed with high processing accuracy.

[0426] (Sixth Embodiment)

[0427] The semiconductor manufacturing apparatus of the sixth embodiment includes: a chamber; a holder disposed in the chamber, capable of adsorbing a substrate, and including a recess disposed on a surface, a first hole disposed in the recess, and a second hole disposed in the recess; a first gas passage connected to the first hole; a second gas passage connected to the second hole; a first valve connected to the first gas passage; a second valve disposed in the second gas passage; a first gas supply pipe for supplying a first gas to the recess; and a gas discharge pipe for discharging gas from the recess; the first gas passage and the second gas passage are connected to the first gas supply pipe, or the first gas passage and the second gas passage are connected to the gas discharge pipe.

[0428] The semiconductor manufacturing apparatus of the sixth embodiment is used, for example, for implementing the manufacturing methods of the semiconductor apparatus of the first to fifth embodiments.

[0429] The semiconductor device manufacturing method of the sixth embodiment involves placing a substrate having a processed layer on a holder, the holder being disposed in a chamber and having a recess on its surface, a first hole in the recess, and a second hole in the recess; opening a first valve disposed in a first gas passage connected to the first hole and a second valve disposed in a second gas passage connected to the second hole; supplying a first gas in contact with the substrate to the space between the holder and the substrate via the first gas passage and the second gas passage; controlling the pressure of the first gas to a first pressure; performing a first etching process to etch the processed layer using a reactive ion etching method; closing the first valve and the second valve during or after the first etching process; opening the first valve and the second valve after closing the first valve and the second valve; discharging the first gas from between the holder and the substrate via the first gas passage and the second gas passage; controlling the pressure of the first gas to a second pressure lower than the first pressure; and performing a first reaction product removal process to remove reaction products from the processed layer. Furthermore, when supplying the first gas, either the first valve or the second valve is opened first; or, when discharging the first gas, either the first valve or the second valve is opened first. The difference between the semiconductor device manufacturing method of the sixth embodiment and the semiconductor device manufacturing method of the first embodiment is that the semiconductor manufacturing apparatus of the sixth embodiment is used. Hereinafter, some details that are repeated in the semiconductor device manufacturing method of the first embodiment will be omitted.

[0430] Figure 16 This is a schematic diagram of a semiconductor manufacturing apparatus according to the sixth embodiment. The semiconductor manufacturing apparatus of the sixth embodiment is a reactive ion etching apparatus (RIE apparatus). The reactive ion etching apparatus of the sixth embodiment is a dual-frequency capacitively coupled plasma apparatus (CCP apparatus).

[0431] The RIE device includes, for example, a chamber 20, a retainer 22, a first high-frequency power supply 24, a second high-frequency power supply 26, a processing gas supply pipe 30, a spray plate 32, a processing gas discharge pipe 34, an exhaust device 36, a refrigerant assembly 38, a refrigerant supply pipe 40, a refrigerant discharge pipe 42, a heat transfer gas supply section 44, a first heat transfer gas supply pipe 46, a heat transfer gas discharge pipe 48, a first main valve 50, a second main valve 52, a control circuit 54, a heat transfer gas passage 56, and a heat transfer gas valve 58.

[0432] The heat-conducting gas passage 56 includes a first heat-conducting gas passage 56a, a second heat-conducting gas passage 56b, a third heat-conducting gas passage 56c, a fourth heat-conducting gas passage 56d, and a fifth heat-conducting gas passage 56e. Additionally, the heat-conducting gas valve 58 includes a first heat-conducting gas valve 58a, a second heat-conducting gas valve 58b, a third heat-conducting gas valve 58c, a fourth heat-conducting gas valve 58d, and a fifth heat-conducting gas valve 58e.

[0433] The first heat-conducting gas supply pipe 46 is an example of a first gas supply pipe. The heat-conducting gas exhaust pipe 48 is an example of a gas exhaust pipe. The first heat-conducting gas passage 56a is an example of a first gas passage. The second heat-conducting gas passage 56b is an example of a second gas passage. The third heat-conducting gas passage 56c is an example of a third gas passage. The fourth heat-conducting gas passage 56d is an example of a fourth gas passage. The fifth heat-conducting gas passage 56e is an example of a fifth gas passage.

[0434] The first thermally conductive gas valve 58a is an example of the first valve. The second thermally conductive gas valve 58b is an example of the second valve. The third thermally conductive gas valve 58c is an example of the third valve. The fourth thermally conductive gas valve 58d is an example of the fourth valve. The fifth thermally conductive gas valve 58e is an example of the fifth valve.

[0435] Figure 17 This is a schematic diagram of the main parts of the semiconductor manufacturing apparatus according to the sixth embodiment. Figure 17 (a) is a top view of retainer 22. Figure 17 (a) is a top view of the electrostatic chuck 22b. Figure 17 (b) is a diagram showing the relationship between the electrostatic chuck 22b, the thermal gas passage 56, the thermal gas valve 58, the first thermal gas supply pipe 46, the thermal gas discharge pipe 48, the first main valve 50, and the second main valve 52. Figure 17 (b) is included Figure 17 (a) Schematic diagram of section AA'.

[0436] A holder 22 is disposed in the chamber 20. The holder 22, for example, holds a semiconductor wafer W. The holder 22 is capable of holding the semiconductor wafer W. The semiconductor wafer W is an example of a substrate.

[0437] The retainer 22 has a support 22a, an electrostatic chuck 22b and an outer ring 22c.

[0438] The support portion 22a functions as a lower electrode. High-frequency power is applied to the support portion 22a. The support portion 22a is, for example, metal.

[0439] A refrigerant flow path 22ax is provided inside the support section 22a. The refrigerant flow path 22ax is an open space. Refrigerant for cooling the support section 22a is supplied to the refrigerant flow path 22ax. The refrigerant is, for example, a fluorine-based inert liquid.

[0440] The electrostatic chuck 22b includes a substrate support portion 71, a recess 72, and thermally conductive gas holes 74. The thermally conductive gas holes 74 include a first thermally conductive gas hole 74a, a second thermally conductive gas hole 74b, a third thermally conductive gas hole 74c, a fourth thermally conductive gas hole 74d, and a fifth thermally conductive gas hole 74e. The first thermally conductive gas hole 74a is an example of the first hole. The second thermally conductive gas hole 74b is an example of the second hole. The third thermally conductive gas hole 74c is an example of the third hole. The fourth thermally conductive gas hole 74d is an example of the fourth hole. The fifth thermally conductive gas hole 74e is an example of the fifth hole.

[0441] An electrostatic chuck 22b is disposed on the support portion 22a. The electrostatic chuck 22b has the function of adsorbing and fixing the semiconductor wafer W. The electrostatic chuck 22b is formed, for example, of a dielectric material having internal electrodes. The dielectric material is, for example, ceramic.

[0442] A substrate support 71 is provided on the surface of the electrostatic chuck 22b. The substrate support 71 has, for example, an annular portion provided on the outer periphery of the electrostatic chuck 22b and a plurality of protrusions provided on the inner side of the annular portion. When a semiconductor wafer W is placed on the holder 22, the back side of the semiconductor wafer W is in contact with the substrate support 71.

[0443] A recess 72 is provided on the surface of the electrostatic chuck 22b. When a semiconductor wafer W is placed on the holder 22, a thermally conductive gas region 76 is formed on the upper surface of the electrostatic chuck 22b, which is surrounded by the back side of the semiconductor wafer W and the recess 72.

[0444] Multiple thermally conductive gas holes 74 are provided on the surface of the electrostatic chuck 22b. The thermally conductive gas holes 74 are located in the recess 72. Thermally conductive gas for cooling the semiconductor wafer W is supplied to the thermally conductive gas region 76 through the thermally conductive gas holes 74.

[0445] Multiple heat-conducting gas holes 74 are arranged at equal intervals on the surface of the electrostatic chuck 22b, for example. The distance between two adjacent heat-conducting gas holes 74 is, for example, more than 10 cm and less than 20 cm.

[0446] Thermally conductive gases include, for example, helium (He), hydrogen (H), nitrogen (N), neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe).

[0447] An outer ring 22c is disposed on the support portion 22a. The outer ring 22c is disposed around the electrostatic chuck 22b. The outer ring 22c functions to support the outer periphery of the semiconductor wafer W. The upper surface of the outer ring 22c is formed, for example, from silicon.

[0448] The first high-frequency power supply 24 has the function of applying a first high-frequency power to the interior of the chamber 20. The first high-frequency power supply 24 applies high-frequency power between the support 22a of the holder 22 and the cluster plate 32. By using the first high-frequency power applied to the chamber 20 by the first high-frequency power supply 24, plasma is generated in the chamber 20.

[0449] The first high-frequency power applied by the first high-frequency power supply 24 is, for example, 50W or more and 20,000W or less. The first frequency applied by the first high-frequency power supply 24 is, for example, 20MHz or more and 200MHz or less.

[0450] The second high-frequency power supply 26 has the function of applying a second high-frequency power to the interior of the chamber 20. The second high-frequency power supply 26 applies the second high-frequency power to the support portion 22a of the holder 22. By applying the second high-frequency power to the holder 22, the energy of the ions colliding with the semiconductor wafer W is controlled.

[0451] The second high-frequency power applied to the retainer 22 is, for example, 50W or more and 20,000W or less. The second frequency applied to the retainer 22 is lower than the first frequency applied to the chamber 20 by the first high-frequency power supply 24. The second frequency applied to the retainer 22 is, for example, 0.1MHz or more and 20MHz or less.

[0452] A processing gas supply pipe 30 is located at the top of the chamber 20. Processing gas is supplied from the processing gas supply pipe 30 to the cluster plate 32. For example, etching gas or modifying gas is supplied from the processing gas supply pipe 30 to the cluster plate 32.

[0453] The cluster plate 32 is disposed in the chamber 20. The cluster plate 32 is disposed above the retainer 22.

[0454] Processing gas is supplied from the processing gas supply pipe 30 to the spray plate 32. Processing gas is supplied into the chamber 20 from multiple gas supply ports provided on the spray plate 32.

[0455] The cluster plate 32 also functions as the upper electrode of the first high-frequency power.

[0456] A process gas exhaust pipe 34 is located at the lower part of the chamber 20. Unconsumed etching gases and reaction products from the etching reaction are discharged from the process gas exhaust pipe 34 to the outside of the chamber 20.

[0457] The exhaust device 36 is connected to the processed gas exhaust pipe 34 and the heat-conducting gas exhaust pipe 48. The exhaust device 36 is, for example, a vacuum pump.

[0458] Refrigerant assembly 38 is connected to refrigerant supply piping 40. Refrigerant supply piping 40 is connected to refrigerant flow path 22ax. Refrigerant flow path 22ax is connected to refrigerant discharge piping 42. Refrigerant circulates in refrigerant supply piping 40, refrigerant flow path 22ax, and refrigerant discharge piping 42 through refrigerant assembly 38.

[0459] The heat transfer gas supply unit 44 is connected to the first heat transfer gas supply pipe 46. The heat transfer gas supply unit 44 is, for example, a gas storage tank for storing heat transfer gas. Heat transfer gas is supplied from the heat transfer gas supply unit 44 to the first heat transfer gas supply pipe 46. The heat transfer gas is an example of a first gas.

[0460] The first heat-conducting gas supply pipe 46 is connected to the recess 72. The first heat-conducting gas supply pipe 46 is connected to the heat-conducting gas passage 56. Heat-conducting gas is supplied from the first heat-conducting gas supply pipe 46 to the heat-conducting gas passage 56.

[0461] A first main valve 50 is installed in the first heat transfer gas supply pipe 46. The first main valve 50 is, for example, a flow control valve. The first main valve 50 is used to control the supply of heat transfer gas to the heat transfer gas passage 56. The first main valve 50 can also be used to block the supply of heat transfer gas to the heat transfer gas passage 56.

[0462] The exhaust device 36 is connected to the chamber 20 and the heat transfer gas exhaust pipe 48. The heat transfer gas is discharged outside the RIE device through the heat transfer gas exhaust pipe 48.

[0463] A heat transfer gas exhaust pipe 48 is connected to the recess 72. The heat transfer gas exhaust pipe 48 is connected to the heat transfer gas passage 56. The heat transfer gas is discharged outside the RIE device through the heat transfer gas passage 56.

[0464] The second main valve 52 is installed in the heat transfer gas discharge pipe 48. The second main valve 52 is used to control the discharge of heat transfer gas from the heat transfer gas passage 56.

[0465] A heat-conducting gas passage 56 is connected to a heat-conducting gas hole 74. For example, a first heat-conducting gas passage 56a is connected to a first heat-conducting gas hole 74a. For example, a second heat-conducting gas passage 56b is connected to a second heat-conducting gas hole 74b. For example, a third heat-conducting gas passage 56c is connected to a third heat-conducting gas hole 74c. For example, a fourth heat-conducting gas passage 56d is connected to a fourth heat-conducting gas hole 74d. For example, a fifth heat-conducting gas passage 56e is connected to a fifth heat-conducting gas hole 74e.

[0466] Heat-conducting gas is supplied to the heat-conducting gas region 76 through the heat-conducting gas passage 56 and the heat-conducting gas hole 74. Heat-conducting gas is also discharged from the heat-conducting gas region 76 through the heat-conducting gas hole 74 into the heat-conducting gas passage 56.

[0467] At least a portion of the heat-conducting gas passage 56 is disposed in the retainer 22.

[0468] The heat-conducting gas passage 56 is connected to the first heat-conducting gas supply pipe 46. For example, the first heat-conducting gas passage 56a, the second heat-conducting gas passage 56b, the third heat-conducting gas passage 56c, the fourth heat-conducting gas passage 56d, and the fifth heat-conducting gas passage 56e are connected to the first heat-conducting gas supply pipe 46.

[0469] Additionally, the heat-conducting gas passage 56 is connected to the heat-conducting gas exhaust pipe 48. For example, the first heat-conducting gas passage 56a, the second heat-conducting gas passage 56b, the third heat-conducting gas passage 56c, the fourth heat-conducting gas passage 56d, and the fifth heat-conducting gas passage 56e are connected to the heat-conducting gas exhaust pipe 48.

[0470] A heat-conducting gas valve 58 is provided in the heat-conducting gas passage 56. For example, a first heat-conducting gas valve 58a is provided in the first heat-conducting gas passage 56a. For example, a second heat-conducting gas valve 58b is provided in the second heat-conducting gas passage 56b. For example, a third heat-conducting gas valve 58c is provided in the third heat-conducting gas passage 56c. For example, a fourth heat-conducting gas valve 58d is provided in the fourth heat-conducting gas passage 56d. For example, a fifth heat-conducting gas valve 58 is provided in the fifth heat-conducting gas passage 56e. For example, heat-conducting gas valves 58 are also provided in heat-conducting gas passages 56 other than the first to fifth heat-conducting gas passages 56a to 56e.

[0471] Alternatively, the multiple heat-conducting gas passages 56 can be made common, with a single heat-conducting gas valve 58 provided. That is, it can also be configured to provide one heat-conducting gas valve 58 relative to the multiple heat-conducting gas holes 74. For example, it can also be configured to provide one heat-conducting gas valve 58 relative to the multiple heat-conducting gas holes 74 arranged in a ring on the surface of the electrostatic chuck 22b. Furthermore, for example, it can also be configured to provide one heat-conducting gas valve 58 relative to the multiple heat-conducting gas holes 74 arranged in a fan shape on the surface of the electrostatic chuck 22b.

[0472] The flow rate of heat-conducting gas supplied from the heat-conducting gas passage 56 to the heat-conducting gas region 76 can be controlled, for example, for each heat-conducting gas passage 56. Additionally, the flow rate of heat-conducting gas discharged from the heat-conducting gas region 76 to the heat-conducting gas passage 56 can be controlled, for example, for each heat-conducting gas passage 56.

[0473] The heat transfer gas valve 58 is, for example, a flow control valve or a pressure control valve.

[0474] A heat-conducting gas valve 58 is provided, for example, in the retainer 22. The heat-conducting gas valve 58 is provided, for example, in the support 22a.

[0475] The control circuit 54 has the function of controlling the operation of the first high-frequency power supply 24, the second high-frequency power supply 26, the exhaust device 36, the refrigerant assembly 38, the heat transfer gas supply unit 44, the first main valve 50, the second main valve 52 and the heat transfer gas valve 58.

[0476] Control circuit 54, for example, controls the opening and closing of heat-conducting gas valve 58. Control circuit 54, for example, independently controls the opening and closing of multiple heat-conducting gas valves 58. Control circuit 54, for example, independently controls the opening and closing of the first heat-conducting gas valve 58a and the second heat-conducting gas valve 58b.

[0477] Additionally, the control circuit 54 controls, for example, the opening degree of the heat transfer gas valve 58. The control circuit 54 can independently control the opening degree of multiple heat transfer gas valves 58. For example, the control circuit 54 can independently control the opening degree of the first heat transfer gas valve 58a and the second heat transfer gas valve 58b.

[0478] The control circuit 54 may be composed of hardware and software. The control circuit 54 may include electronic circuitry.

[0479] Anisotropic etching is performed on the semiconductor wafer W placed in the holder 22 using plasma generated between the cluster plate 32 and the holder 22 in the chamber 20.

[0480] Next, a method for manufacturing a semiconductor device according to a sixth embodiment using the semiconductor manufacturing apparatus of the sixth embodiment will be described. Hereinafter, an example will be given of etching the multilayer 60 using the RIE apparatus of the sixth embodiment and the same method as that used in the semiconductor device manufacturing method of the first embodiment. Referring to the first embodiment... Figure 4 Please provide an explanation.

[0481] Figure 18 This is an explanatory diagram of the operation of the semiconductor manufacturing apparatus according to the sixth embodiment. Figure 18This is a diagram illustrating an example of the control sequence of the first main valve 50, the second main valve 52, and the heat-conducting gas valve 58 when the temperature of the semiconductor wafer W changes.

[0482] For example, such as Figure 4 As shown in (c), during the first etching process, as Figure 18 As shown in (a), the first main valve 50 and the heat transfer gas valve 58 are opened, and helium is supplied to the heat transfer gas region 76 from the first heat transfer gas supply pipe 46. For example, the pressure of the helium in the heat transfer gas region 76 is controlled to a first pressure P1.

[0483] The silicon substrate 10 is at a low temperature. When the silicon substrate 10 is at a low temperature, the etching rate of the memory hole MH increases, and the etching of the stack 60 is mainly performed.

[0484] Then, during or after the first etching process, as... Figure 18 As shown in (b), the first main valve 50 and the heat transfer gas valve 58 are closed. Then, by opening the second main valve 52, helium gas in the heat transfer gas passage 56 between the heat transfer gas valve 58 and the heat transfer gas discharge pipe 48 connected to the heat transfer gas passage 56 is discharged from the heat transfer gas discharge pipe 48. The heat transfer gas passage 56 downstream of the heat transfer gas valve 58 is in a vacuum state.

[0485] Next, in Figure 4 When the first reaction product shown in (d) is removed, the pressure of the helium gas in the heat-conducting gas region 76 is changed from the first pressure P1 to the second pressure P2. The second pressure P2 is lower than the first pressure P1.

[0486] First, initially as Figure 18 As shown in (c), the fourth thermal gas valve 58d and the fifth thermal gas valve 58e are opened first. By pre-emptively vacuuming the thermal gas passage 56 downstream of the thermal gas valve 58, the pressure in the thermal gas region 76 is reduced.

[0487] Next, as Figure 18 As shown in (d), open the first thermal gas valve 58a, the second thermal gas valve 58b, and the third thermal gas valve 58c.

[0488] As the pressure in the heat-conducting gas region 76 decreases, the silicon substrate 10 reaches a high-temperature state. When the silicon substrate 10 is in a high-temperature state, the decomposition reaction of the reaction products 63 formed on the bottom and side surfaces of the memory hole MH is promoted, thereby mainly carrying out the decomposition of the reaction products 63.

[0489] Next, during the second etching and the removal of the second reaction products, the process is repeated. Figure 18 (a)~ Figure 18 (d) The action. Through repeated practice... Figure 18 (a)~ Figure 18 The action of (d) causes a change in the pressure of the conductive gas in the heat-conducting gas region 76, which can cause the low temperature state of the silicon substrate 10 to alternate with the high temperature state of the silicon substrate 10.

[0490] Next, the function and effects of the semiconductor manufacturing apparatus of the sixth embodiment will be explained.

[0491] Figure 19 This is a schematic diagram of the main parts of a comparative example semiconductor manufacturing apparatus. Figure 19 (a) is a top view of retainer 22. Figure 19 (a) is a top view of the electrostatic chuck 22b. Figure 19 (b) is a diagram showing the relationship between the electrostatic chuck 22b, the thermal gas passage 56, the thermal gas valve 58, the first thermal gas supply pipe 46, the thermal gas discharge pipe 48, the first main valve 50, and the second main valve 52. Figure 19 (b) is included Figure 19 (a) Graph of BB' section. Figure 19 It is the same as the sixth embodiment. Figure 17 The corresponding diagram.

[0492] The RIE device in the comparative example differs from the RIE device in the sixth embodiment in that each of the following is provided: a heat-conducting gas passage 56, a heat-conducting gas valve 58, and a heat-conducting gas orifice 74 for supplying heat-conducting gas, and each of the following is provided: a heat-conducting gas passage 56, a heat-conducting gas valve 58, and a heat-conducting gas orifice 74 for discharging heat-conducting gas.

[0493] Specifically, the comparative example RIE device has a heat-conducting gas passage 56x, a heat-conducting gas valve 58x, and a heat-conducting gas orifice 74x for supplying heat-conducting gas. The comparative example RIE device has a heat-conducting gas passage 56y, a heat-conducting gas valve 58y, and a heat-conducting gas orifice 74y for discharging heat-conducting gas.

[0494] In the comparative RIE apparatus, when the pressure of the conductive gas in the heat-conducting gas region 76 is varied, causing the low-temperature state of the semiconductor wafer W to alternate with the high-temperature state of the semiconductor wafer W, there is a problem of increased in-plane temperature non-uniformity of the semiconductor wafer W. If the in-plane temperature non-uniformity of the semiconductor wafer W increases, then the differences during etching processes or removal of reaction products become larger, and the processing accuracy when processing the layer using dry etching decreases.

[0495] One of the reasons for the in-plane temperature non-uniformity of the semiconductor wafer W is that the pressure change of the conductive gas in the heat-conducting gas region 76 is highly location-dependent.

[0496] For example, when the semiconductor wafer W is changed from a high-temperature state to a low-temperature state, that is, when the pressure of the conductive gas in the heat-conducting gas region 76 is increased, if the supply of the heat-conducting gas is slow at the outer periphery of the electrostatic chuck 22b, then the temperature of the outer periphery of the semiconductor wafer W is difficult to decrease. Conversely, if the supply of the heat-conducting gas is slow at the inner periphery of the electrostatic chuck 22b, then the temperature of the inner periphery of the semiconductor wafer W is difficult to decrease.

[0497] Furthermore, for example, when the semiconductor wafer W is changed from a low-temperature state to a high-temperature state, that is, when the pressure of the conductive gas in the heat-conducting gas region 76 is reduced, if the heat-conducting gas is slowly discharged from the outer periphery of the electrostatic chuck 22b, then the temperature of the outer periphery of the semiconductor wafer W is difficult to rise. Conversely, if the heat-conducting gas is slowly discharged from the inner periphery of the electrostatic chuck 22b, then the temperature of the inner periphery of the semiconductor wafer W is difficult to rise.

[0498] The RIE apparatus of the sixth embodiment is provided with multiple heat-conducting gas passages 56 and multiple heat-conducting gas holes 74 for supplying heat-conducting gas. Therefore, compared with the comparative example, the supply of heat-conducting gas to the heat-conducting gas region 76 is promoted. As a result, when the semiconductor wafer W is changed from a high temperature state to a low temperature state, in-plane temperature non-uniformity of the semiconductor wafer W is suppressed.

[0499] Furthermore, the RIE apparatus of the sixth embodiment is provided with multiple heat-conducting gas passages 56 and multiple heat-conducting gas holes 74 for discharging heat-conducting gas. Therefore, compared with the comparative example, it promotes the discharge of heat-conducting gas from the heat-conducting gas region 76. As a result, when the semiconductor wafer W is changed from a low temperature state to a high temperature state, in-plane temperature non-uniformity of the semiconductor wafer W is suppressed.

[0500] Furthermore, in the RIE device of the sixth embodiment, heat-conducting gas valves 58 are respectively provided on multiple heat-conducting gas passages 56. The opening and closing or the opening degree of the heat-conducting gas valves 58 can be controlled independently.

[0501] Therefore, for example, the supply of heat-conducting gas to the heat-conducting gas region 76 can be adjusted at each location of the heat-conducting gas region 76. For example, it is possible to promote the supply of heat-conducting gas to regions where the temperature of the semiconductor wafer W is difficult to decrease. As a result, when the semiconductor wafer W is changed from a high-temperature state to a low-temperature state, in-plane temperature non-uniformity of the semiconductor wafer W can be further suppressed.

[0502] Furthermore, for example, the discharge of heat-conducting gas from the heat-conducting gas region 76 can be adjusted at each location of the heat-conducting gas region 76. For example, it can promote the discharge of heat-conducting gas from regions where the temperature of the semiconductor wafer W is difficult to rise. As a result, when the semiconductor wafer W is transitioned from a low-temperature state to a high-temperature state, in-plane temperature non-uniformity of the semiconductor wafer W can be further suppressed.

[0503] Figure 18 For example, an example of the control sequence of the first main valve 50, the second main valve 52, and the heat-conducting gas valve 58 is shown when the silicon substrate 10 is transitioned from a low-temperature state to a high-temperature state, that is, when the temperature of the outer periphery of the silicon substrate 10 is difficult to rise. Figure 18 As shown in (c), by first opening the fourth thermally conductive gas valve 58d and the fifth thermally conductive gas valve 58e, thermally conductive gas is facilitated to be discharged from the thermally conductive gas region 76 corresponding to the outer periphery of the silicon substrate 10. Therefore, the temperature of the outer periphery of the silicon substrate 10 easily rises. As a result, in-plane temperature non-uniformity of the silicon substrate 10 when the silicon substrate 10 is changed from a low temperature state to a high temperature state can be suppressed.

[0504] also, Figure 18 In (c), the fourth thermal gas valve 58d and the fifth thermal gas valve 58e are opened first, but the order in which they are opened is not limited to these. For example, the first thermal gas valve 58a may be opened before the second thermal gas valve 58b is opened. Alternatively, the second thermal gas valve 58b may be opened before the first thermal gas valve 58a is opened.

[0505] Furthermore, for example, when changing the silicon substrate 10 from a high-temperature state to a low-temperature state, that is, when opening the first main valve 50 and the thermally conductive gas valve 58 to supply helium from the first thermally conductive gas supply pipe 46 to the thermally conductive gas region 76, a portion of the thermally conductive gas valve 58 can be opened first. For example, the first thermally conductive gas valve 58a can be opened before the second thermally conductive gas valve 58b. This allows the temperature of the silicon substrate 10 on the first thermally conductive gas port 74a to drop faster than the temperature of the silicon substrate 10 on the second thermally conductive gas port 74b. Alternatively, for example, the second thermally conductive gas valve 58b can be opened before the first thermally conductive gas valve 58a. This allows the temperature of the silicon substrate 10 on the second thermally conductive gas port 74b to drop faster than the temperature of the silicon substrate 10 on the first thermally conductive gas port 74a.

[0506] According to the semiconductor device manufacturing apparatus and semiconductor device manufacturing method of the sixth embodiment, when processing the workpiece layer using dry etching, high-precision processing can be performed.

[0507] (Seventh Embodiment)

[0508] The semiconductor manufacturing apparatus of the seventh embodiment differs from that of the semiconductor manufacturing apparatus of the sixth embodiment in that the first gas passage and the second gas passage are connected to a gas exhaust pipe, while the first gas passage and the second gas passage are not connected to a first gas supply pipe. Hereinafter, some details that are repeated in the sixth embodiment will be omitted.

[0509] Figure 20 This is a schematic diagram of the main parts of the semiconductor manufacturing apparatus according to the seventh embodiment. Figure 20 This corresponds to the sixth embodiment. Figure 17 (b) is the diagram.

[0510] One of the heat-conducting gas passages 56 is connected to the first heat-conducting gas supply pipe 46. The fourth heat-conducting gas passage 56d is connected to the first heat-conducting gas supply pipe 46.

[0511] Additionally, a portion of the heat-conducting gas passage 56 is connected to the heat-conducting gas exhaust pipe 48. The first heat-conducting gas passage 56a, the second heat-conducting gas passage 56b, the third heat-conducting gas passage 56c, and the fifth heat-conducting gas passage 56e are connected to the heat-conducting gas exhaust pipe 48.

[0512] The RIE device of the seventh embodiment can, for example, adjust the discharge of heat-conducting gas from the heat-conducting gas region 76 at each position of the heat-conducting gas region 76. For example, it can promote the discharge of heat-conducting gas from regions where the temperature of the semiconductor wafer W is difficult to rise. As a result, when the semiconductor wafer W is changed from a low temperature state to a high temperature state, in-plane temperature non-uniformity of the semiconductor wafer W can be suppressed.

[0513] (Example of variation)

[0514] Figure 21 This is a schematic diagram of the main parts of a semiconductor manufacturing apparatus according to a variation of the seventh embodiment. Figure 21 This corresponds to the 7th embodiment. Figure 20 The figure shows that the semiconductor manufacturing apparatus of the seventh embodiment differs from that of the semiconductor manufacturing apparatus of the seventh embodiment in that the first gas passage and the second gas passage are not connected to the gas discharge pipe, but are connected to the first gas supply pipe.

[0515] A portion of the heat-conducting gas passage 56 is connected to the first heat-conducting gas supply pipe 46. The first heat-conducting gas passage 56a, the second heat-conducting gas passage 56b, the third heat-conducting gas passage 56c, and the fourth heat-conducting gas passage 56d are connected to the first heat-conducting gas supply pipe 46.

[0516] Additionally, one of the heat-conducting gas passages 56 is connected to the heat-conducting gas exhaust pipe 48. The fifth heat-conducting gas passage 56e is connected to the heat-conducting gas exhaust pipe 48.

[0517] The RIE apparatus of the seventh embodiment, for example, can adjust the supply of heat-conducting gas to the heat-conducting gas region 76 at each position of the heat-conducting gas region 76. For example, it can promote the supply of heat-conducting gas to regions where the temperature of the semiconductor wafer W is difficult to decrease. As a result, when the semiconductor wafer W is changed from a high temperature state to a low temperature state, in-plane temperature non-uniformity of the semiconductor wafer W can be suppressed.

[0518] According to the semiconductor device manufacturing apparatus of the seventh embodiment and its variations, when processing the workpiece layer using dry etching, high-precision processing can be performed.

[0519] (Eighth Embodiment)

[0520] The semiconductor manufacturing apparatus of the eighth embodiment differs from that of the sixth embodiment in that the first gas passage, the second gas passage, and the third gas passage are connected to the first gas supply pipe but not to the gas exhaust pipe, while the fourth gas passage and the fifth gas passage are not connected to the first gas supply pipe but are connected to the gas exhaust pipe. Hereinafter, some details that are repeated in the sixth embodiment will be omitted.

[0521] Figure 22 This is a schematic diagram of the main parts of the semiconductor manufacturing apparatus according to the eighth embodiment. Figure 22 This corresponds to the sixth embodiment. Figure 17 (b) is the diagram.

[0522] A portion of the heat-conducting gas passage 56 is connected to the first heat-conducting gas supply pipe 46. The first heat-conducting gas passage 56a, the second heat-conducting gas passage 56b, and the third heat-conducting gas passage 56c are connected to the first heat-conducting gas supply pipe 46.

[0523] Additionally, a portion of the heat-conducting gas passage 56 is connected to the heat-conducting gas exhaust pipe 48. The fourth heat-conducting gas passage 56d and the fifth heat-conducting gas passage 56e are connected to the heat-conducting gas exhaust pipe 48.

[0524] The RIE device of the eighth embodiment, for example, can adjust the discharge of heat-conducting gas from the heat-conducting gas region 76 at each position of the heat-conducting gas region 76. For example, it can promote the discharge of heat-conducting gas from regions where the temperature of the semiconductor wafer W is difficult to rise. As a result, when the semiconductor wafer W is changed from a low temperature state to a high temperature state, in-plane temperature non-uniformity of the semiconductor wafer W can be suppressed.

[0525] Furthermore, for example, the supply of heat-conducting gas to the heat-conducting gas region 76 can be adjusted at each location of the heat-conducting gas region 76. For example, it is possible to promote the supply of heat-conducting gas to regions where the temperature of the semiconductor wafer W is difficult to decrease. As a result, when the semiconductor wafer W is changed from a high-temperature state to a low-temperature state, in-plane temperature non-uniformity of the semiconductor wafer W can be suppressed.

[0526] According to the eighth embodiment and the semiconductor device manufacturing apparatus, when processing the workpiece layer using dry etching, high-precision processing can be performed.

[0527] (9th embodiment)

[0528] The semiconductor manufacturing apparatus of the ninth embodiment differs from that of the semiconductor manufacturing apparatus of the sixth embodiment in that it further includes a second gas supply pipe for supplying a second gas different from the first gas to the recess, and the first gas passage and the second gas passage are connected to the first gas supply pipe and the second gas supply pipe. Hereinafter, some descriptions that are repeated in the sixth embodiment will be omitted.

[0529] Figure 23 This is a schematic diagram of the main parts of the semiconductor manufacturing apparatus according to the ninth embodiment. Figure 23 This corresponds to the sixth embodiment. Figure 17 (b) is the diagram.

[0530] The RIE device of the ninth embodiment includes a second heat-conducting gas supply pipe 47 and a third main valve 53.

[0531] The second heat-conducting gas supply pipe 47 is connected to the recess 72. The second heat-conducting gas supply pipe 47 is connected to the heat-conducting gas passage 56. Heat-conducting gas is supplied from the second heat-conducting gas supply pipe 47 to the heat-conducting gas passage 56.

[0532] The second heat-conducting gas supply pipe 47 supplies a different heat-conducting gas than the first heat-conducting gas supply pipe 46. The heat-conducting gas supplied from the second heat-conducting gas supply pipe 47 is an example of the second gas.

[0533] The thermal conductivity of the thermally conductive gas supplied from the second thermally conductive gas supply pipe 47 is, for example, lower than that of the thermally conductive gas supplied from the first thermally conductive gas supply pipe 46.

[0534] For example, the heat-conducting gas supplied from the first heat-conducting gas supply pipe 46 is helium, and the heat-conducting gas supplied from the second heat-conducting gas supply pipe 47 is argon or nitrogen.

[0535] A third main valve 53 is installed in the second heat transfer gas supply piping 47. The third main valve 53 is, for example, a flow control valve. The third main valve 53 is used to control the supply of heat transfer gas to the heat transfer gas passage 56. The third main valve 53 can also be used to block the supply of heat transfer gas to the heat transfer gas passage 56.

[0536] The RIE device of the ninth embodiment is used, for example, to implement the manufacturing method of the semiconductor device of the fourth embodiment using two thermally conductive gases.

[0537] According to the ninth embodiment and the semiconductor device manufacturing apparatus, when processing the workpiece layer using dry etching, high-precision processing can be performed.

[0538] In embodiments 1 to 4, the case of performing three etching operations and removing the reaction products after each etching was described as an example. However, the number of etching operations is not limited to three. Any number of etching operations can be set as long as there are two or more etching operations.

[0539] In the fifth embodiment, the case of performing four etching operations is described as an example. However, the number of etching operations is not limited to four. As long as the number of etching operations is two or more, it can be set to any number.

[0540] In embodiments 1 to 5, the case of a non-volatile memory as the semiconductor device was described as an example, but the semiconductor device is not limited to non-volatile memory.

[0541] In embodiments 1 to 5, an example was described where the processed layer comprises alternating layers of silicon oxide and silicon nitride films, but the processed layer is not particularly limited. For example, the processed layer may also comprise alternating layers of insulating films other than silicon oxide and silicon nitride films. Furthermore, for example, the processed layer may comprise alternating layers of insulating films and semiconductor films. Furthermore, for example, the processed layer may comprise alternating layers of insulating films and metal films. Additionally, the processed layer may also be composed of a single film.

[0542] In embodiments 1 to 5, the case of forming a memory hole MH in the processed layer by etching was described as an example, but the pattern formed in the processed layer is not limited to a hole pattern. The pattern formed in the processed layer may also be a groove pattern, for example. In addition, a method of etching the entire surface of the processed layer may also be adopted.

[0543] In embodiments 1 to 5, the reactive ion etching apparatus (RIE apparatus) was described as a dual-frequency capacitively coupled plasma apparatus (CCP apparatus). However, the type of RIE apparatus is not particularly limited.

[0544] In the first to fourth embodiments, the case in which etching gas is still supplied to chamber 20 during the removal of reaction products is described as an example. However, for example, hydrogen, nitrogen or argon may be supplied to chamber 20 instead of etching gas during the removal of reaction products.

[0545] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. For example, the constituent elements of one embodiment can be replaced or modified with the constituent elements of other embodiments. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0546] (Postscript 1)

[0547] A method for manufacturing a semiconductor device involves placing a substrate having a layer to be processed on a holder disposed in a chamber.

[0548] A first gas in contact with the substrate is supplied between the holder and the substrate.

[0549] The pressure of the first gas is controlled to a first pressure.

[0550] The first etching process, which forms recesses, is performed on the processed layer using a reactive ion etching method with a first processing gas.

[0551] After the first etching process, the pressure of the first gas is controlled to a second pressure that is lower than the first pressure.

[0552] While the substrate temperature is between 200°C and 350°C, a first treatment is performed, in which hydrogen radicals are supplied to the recess using a second treatment gas containing hydrogen.

[0553] After the first treatment, the pressure of the first gas is controlled to a third pressure that is higher than the second pressure.

[0554] A second etching process is performed to etch the bottom surface of the recess using a reactive ion etching method with a third processing gas.

[0555] (Postscript 2)

[0556] According to the semiconductor device manufacturing method described in Appendix 1, the first etching process, the first process and the second etching process are performed in the same chamber.

[0557] (Note 3)

[0558] According to the method for manufacturing a semiconductor device as described in Appendix 1, the first processing gas comprises carbon and fluorine.

[0559] (Note 4)

[0560] According to the semiconductor device manufacturing method described in Appendix 1, a first film is formed on the surface of the recess by using a reactive ion etching method with the first processing gas.

[0561] (Note 5)

[0562] According to the method for manufacturing a semiconductor device as described in Appendix 4, the first film comprises carbon and fluorine.

[0563] (Note 6)

[0564] According to the method for manufacturing a semiconductor device as described in Appendix 4, the first film is reduced in the first process.

[0565] (Note 7)

[0566] According to the method for manufacturing a semiconductor device as described in Appendix 4, in the first process, the fluorine concentration of the first membrane is reduced.

[0567] (Postscript 8)

[0568] According to the method for manufacturing a semiconductor device as described in Appendix 1, the second processing gas comprises hydrogen.

[0569] (Note 9)

[0570] According to the semiconductor device manufacturing method described in Appendix 1, a patterned mask layer is formed on the processed layer before the first etching process is performed, and the recess is formed by using the mask layer as a mask.

[0571] (Postscript 10)

[0572] According to the method for manufacturing a semiconductor device as described in Appendix 9, the mask layer comprises carbon.

[0573] (Postscript 11)

[0574] According to the semiconductor device manufacturing method described in Appendix 1, the temperature of the substrate during the first etching process is below 20°C.

[0575] (Postscript 12)

[0576] According to the method for manufacturing a semiconductor device as described in Appendix 1, the high-frequency power applied to the substrate during the first process is lower than the high-frequency power applied to the substrate during the first etching process.

[0577] (Postscript 13)

[0578] According to the method of manufacturing a semiconductor device as described in Appendix 1, the processed layer comprises silicon.

[0579] (Postscript 14)

[0580] According to the semiconductor device manufacturing method described in Appendix 1, the processed layer comprises a structure consisting of alternating layers of a first layer and a second layer different from the first layer.

[0581] (Postscript 15)

[0582] According to the method for manufacturing a semiconductor device as described in Appendix 14, the first layer is a silicon oxide film and the second layer is a silicon nitride film.

[0583] (Postscript 16)

[0584] According to the semiconductor device manufacturing method described in Appendix 1, after the second etching process, the pressure of the first gas is controlled to a fourth pressure that is lower than the third pressure.

[0585] While the substrate temperature is between 200°C and 350°C, a second treatment is performed, in which hydrogen radicals are supplied to the recess using a fourth treatment gas containing hydrogen.

[0586] After the second treatment, the pressure of the first gas is controlled to a fifth pressure, which is higher than the fourth pressure.

[0587] A third etching process is performed to etch the bottom surface of the recess using a reactive ion etching method with a fifth processing gas.

[0588] (Postscript 17)

[0589] A method for manufacturing a semiconductor device involves placing a substrate having a layer to be processed on a holder disposed in a chamber.

[0590] A first gas in contact with the substrate is supplied between the holder and the substrate.

[0591] The pressure of the first gas is controlled to a first pressure.

[0592] A first etching process is performed to etch the layer to be processed using a reactive ion etching method.

[0593] After the first etching process, the pressure of the first gas is controlled to a second pressure that is lower than the first pressure.

[0594] The first reaction product removal process is performed to remove the reaction products from the processed layer.

[0595] After the removal of the first reaction product, the pressure of the first gas is controlled to a third pressure that is higher than the second pressure.

[0596] A second etching process is performed to etch the processed layer using a reactive ion etching method.

[0597] (Postscript 18)

[0598] According to the semiconductor device manufacturing method described in Appendix 17, a second gas comprising carbon (C) and fluorine (F) is supplied to the chamber during the first etching process and the second etching process.

[0599] (Postscript 19)

[0600] According to the method for manufacturing a semiconductor device as described in Appendix 18, the second gas is supplied to the chamber during the removal of the first reaction product.

[0601] (Postscript 20)

[0602] According to the method for manufacturing a semiconductor device as described in Appendix 17, the processed layer comprises silicon (Si) and nitrogen (N).

[0603] (Postscript 21)

[0604] According to the semiconductor device manufacturing method described in Appendix 17, the processed layer comprises a structure formed by alternating layers of silicon oxide film and silicon nitride film.

[0605] (Postscript 22)

[0606] According to the semiconductor device manufacturing method described in Appendix 17, wherein the time for controlling the pressure of the first gas to the second pressure is set to td (sec), the temperature of the holder during the first etching process is set to T (°C), the ratio of the area of ​​the substrate to the sum of the area of ​​the substrate and the area of ​​the inner wall of the chamber is set to k, the high-frequency power applied to the interior of the chamber is set to Pw (W), the mass of the substrate is set to m (kg), and the specific heat capacity of the substrate is set to c (J / (kg·°C)), the following inequality holds.

[0607] td≧(100-T) / {(k×Pw) / (m×c)}

[0608] (Postscript 23)

[0609] According to the method for manufacturing a semiconductor device as described in Appendix 17, the time for controlling the pressure of the first gas to the second pressure is longer than 10 seconds.

[0610] (Postscript 24)

[0611] According to the semiconductor device manufacturing method described in Appendix 17, the pressure change control of the first gas is synchronized with the high-frequency power applied to the interior of the chamber.

[0612] (Postscript 25)

[0613] According to the method for manufacturing a semiconductor device as described in Appendix 24, the high-frequency power applied to the interior of the cavity during the removal of the first reaction product is higher than the high-frequency power applied to the interior of the cavity during the first etching process.

[0614] (Postscript 26)

[0615] According to the method for manufacturing a semiconductor device as described in Appendix 24, the high-frequency power applied to the interior of the cavity during the removal of the first reaction product is lower than the high-frequency power applied to the interior of the cavity during the first etching process.

[0616] (Postscript 27)

[0617] According to the semiconductor device manufacturing method described in Appendix 17, during the first etching process, a recess is formed in the processed layer.

[0618] During the second etching process, the bottom surface of the recess is etched.

[0619] (Postscript 28)

[0620] According to the method for manufacturing a semiconductor device as described in Appendix 17, the first gas comprises helium (He), hydrogen (H), nitrogen (N), neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe).

[0621] (Postscript 29)

[0622] According to the semiconductor device manufacturing method described in Appendix 17, after the pressure of the first gas is controlled to the second pressure, a third gas with a lower thermal conductivity than the first gas is supplied between the holder and the substrate in contact with the substrate.

[0623] After the removal of the first reaction product, the first gas is supplied between the holder and the substrate in contact with the substrate, replacing the third gas.

[0624] The pressure of the first gas is controlled to a third pressure that is higher than the second pressure.

[0625] (Postscript 30)

[0626] According to the method of manufacturing a semiconductor device as described in Appendix 17, the second pressure is less than one-hundredth of the first pressure.

[0627] (Postscript 31)

[0628] According to the semiconductor device manufacturing method described in Appendix 17, the temperature of the substrate during the first etching process is below 60°C.

[0629] The temperature of the substrate during the removal of the first reaction product is above 100°C.

[0630] (Postscript 32)

[0631] According to the semiconductor device manufacturing method described in Appendix 17, after the second etching process, the pressure of the first gas is controlled to a fourth pressure that is lower than the third pressure.

[0632] A second reaction product removal process is performed to remove the reaction products from the processed layer.

[0633] After the removal of the second reaction product, the pressure of the first gas is controlled to a fifth pressure, which is higher than the fourth pressure.

[0634] A third etching process is performed to etch the processed layer using a reactive ion etching method.

[0635] (Postscript 33)

[0636] According to the semiconductor device manufacturing method described in Appendix 17, the temperature of the substrate is measured, and the pressure of the first gas is controlled to the third pressure based on the measured temperature of the substrate.

[0637] (Postscript 34)

[0638] A method for manufacturing a semiconductor device involves placing a substrate having a layer to be processed on a holder disposed in a chamber.

[0639] A first gas in contact with the substrate is supplied between the holder and the substrate.

[0640] The pressure of the first gas is controlled to a first pressure.

[0641] In a first state where the substrate temperature is below 60°C, a first etching process is performed to etch the layer to be processed using a reactive ion etching method.

[0642] After the first etching process, the pressure of the first gas is controlled to a second pressure that is lower than the first pressure.

[0643] The second state, in which the substrate temperature is above 100°C, was achieved.

[0644] After achieving the second state, the pressure of the first gas is controlled to a third pressure that is higher than the second pressure.

[0645] In the third state, when the temperature of the substrate is below 60°C, a second etching process is performed to etch the processed layer using a reactive ion etching method.

[0646] (Postscript 35)

[0647] According to the semiconductor device manufacturing method described in Appendix 34, wherein the time for controlling the pressure of the first gas to the second pressure is set to td (sec), the temperature of the holder during the first etching process is set to T (°C), the ratio of the area of ​​the substrate to the sum of the area of ​​the substrate and the area of ​​the inner wall of the chamber is set to k, the high-frequency power applied to the interior of the chamber is set to Pw (W), the mass of the substrate is set to m (kg), and the specific heat capacity of the substrate is set to c (J / (kg·°C)), the following inequality holds.

[0648] td≧(100-T) / {(k×Pw) / (m×c)}

[0649] (Postscript 36)

[0650] According to the semiconductor device manufacturing method described in Appendix 34, the pressure change control of the first gas is synchronized with the high-frequency power applied to the interior of the chamber.

[0651] [Explanation of Symbols]

[0652] 10. Silicon substrate (substrate)

[0653] 20 chambers

[0654] 22 Retainer

[0655] 22b electrostatic chuck

[0656] 46 First heat transfer gas supply piping (First gas supply piping)

[0657] 47 Second heat transfer gas supply piping (Second gas supply piping)

[0658] 48. Heat-conducting gas exhaust piping (gas exhaust piping)

[0659] 50 First Main Valve

[0660] 52 Second Main Valve

[0661] 54 Control Circuit

[0662] 56a First heat conduction gas passage (First gas passage)

[0663] 56b Second heat conduction gas passage (Second gas passage)

[0664] 56c Third heat conduction gas passage (Third gas passage)

[0665] 58a First heat transfer gas valve (Valve 1)

[0666] 58b Second thermally conductive gas valve (second valve)

[0667] 58c Third heat-conducting gas valve (third valve)

[0668] 60. Laminated body (processed layer)

[0669] 60a silicon oxide film (layer 1)

[0670] 60b silicon nitride film (second layer)

[0671] 62 Carbon layer (mask layer)

[0672] 64a First protective film (first film)

[0673] 72 recess

[0674] 74a First thermally conductive gas hole (hole 1)

[0675] 74b Second thermally conductive gas port (Second port)

[0676] 74c Third thermally conductive gas pore (Third pore)

[0677] 100 Non-volatile memory (semiconductor device)

[0678] MH memory hole (recess).

Claims

1. A method for manufacturing a semiconductor device, wherein a substrate having a layer to be processed is placed on a holder, the holder being disposed in a chamber and having a recess disposed on a surface, a first hole disposed in the recess, and a second hole disposed in the recess; Open the first valve provided on the first gas passage connected to the first hole and the second valve provided on the second gas passage connected to the second hole, and supply the first gas in contact with the substrate to the space between the holder and the substrate through the first gas passage and the second gas passage; The pressure of the first gas is controlled to the first pressure; A first etching process is performed to etch the layer to be processed using a reactive ion etching method; During or after the first etching process, the first valve and the second valve are closed. After closing the first valve and the second valve, the first valve and the second valve are opened, and the first gas is discharged from between the holder and the substrate through the first gas passage and the second gas passage; The pressure of the first gas is controlled to a second pressure that is lower than the first pressure; and Perform a first reaction product removal process to remove reaction products from the processed layer; When supplying the first gas, first open either the first valve or the second valve, or When venting the first gas, either the first valve or the second valve is opened first.

2. The method of manufacturing a semiconductor device according to claim 1, wherein when the first gas is supplied, either the first valve or the second valve is opened first.

3. The method of manufacturing a semiconductor device according to claim 1, wherein when the first gas is discharged, either the first valve or the second valve is opened first.

4. The method of manufacturing a semiconductor device according to claim 1, wherein after closing the first valve and the second valve and before opening the first valve and the second valve, the first gas in the first gas passage between the first valve and the gas discharge pipe, and the first gas in the second gas passage between the second valve and the gas discharge pipe are discharged from a gas discharge pipe connected to the first gas passage and the second gas passage.

5. The method for manufacturing a semiconductor device according to claim 1, wherein... After the removal of the first reaction product, the pressure of the first gas is controlled to a third pressure that is higher than the second pressure. A second etching process is performed to etch the processed layer using a reactive ion etching method.

6. The method of manufacturing a semiconductor device according to claim 5, wherein during the first etching process and the second etching process, a second gas comprising carbon (C) and fluorine (F) is supplied to the chamber.

7. The method of manufacturing a semiconductor device according to claim 6, wherein the second gas is supplied to the chamber during the removal of the first reaction product.

8. The method of manufacturing a semiconductor device according to claim 1, wherein the pressure change control of the first gas is synchronized with the high-frequency power applied to the interior of the chamber.

9. The method for manufacturing a semiconductor device according to claim 5, wherein During the first etching process, a recess is formed in the layer being processed. During the second etching process, the bottom surface of the recess is etched.

10. The method of manufacturing a semiconductor device according to claim 1, wherein the first gas comprises helium (He), hydrogen (H), nitrogen (N), neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe).

11. The method of manufacturing a semiconductor device according to claim 1, wherein After the pressure of the first gas is controlled to the second pressure, a third gas with a lower thermal conductivity than the first gas is supplied between the holder and the substrate in contact with the substrate. After the removal of the first reaction product, the first gas is supplied between the holder and the substrate in contact with the substrate, replacing the third gas. The pressure of the first gas is controlled to a third pressure that is higher than the second pressure.

12. The method for manufacturing a semiconductor device according to claim 1, wherein... The temperature of the substrate during the first etching process is below 60°C. The temperature of the substrate during the removal of the first reaction product is above 100°C.

13. The method for manufacturing a semiconductor device according to claim 1, wherein the time for controlling the pressure of the first gas to the second pressure is td (sec), the temperature of the holder during the first etching process is T (°C), the ratio of the area of ​​the substrate to the sum of the area of ​​the substrate and the area of ​​the inner wall of the chamber is k, the high-frequency power applied to the interior of the chamber is Pw (W), the mass of the substrate is m (kg), and the specific heat capacity of the substrate is c (J / (kg•°C)), the following inequality holds. td≧(100-T) / {(k×Pw) / (m×c)}.

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