Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a manufacturing method thereof. The method includes: forming an isolation structure on a substrate for partitioning an active region; forming a first gate oxide layer on the substrate and the isolation structure; forming a photoresist on the first gate oxide layer and developing the photoresist; removing the photoresist residue particles formed by development through plasma reaction; removing the first gate oxide layer at positions not protected by the photoresist through etching to form a first gate oxide structure; forming a second gate oxide structure; forming a first gate on the first gate oxide structure and forming a second gate on the second gate oxide structure. By removing the photoresist residue particles formed by development through plasma, the integrity / density of the second gate oxide structure at the junction of the isolation structure and the active region can be improved, thereby solving the problem of second device GOI failure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, in particular to a manufacturing method of semiconductor devices, and also relates to a semiconductor device. Background Art

[0002] In order to obtain better luminance and color mixing effects, liquid crystal panels (TFT-LCDs) usually use Source-Driver chips with small line widths (0.18 μm and below) to drive LCD circuits. In an exemplary Source-Driver chip, there is a low-voltage device as the input terminal and a high-voltage device as the conversion terminal, so low-voltage and high-voltage devices coexist.

[0003] In actual production, it is found that the stability of the Gate Oxide Integrity (GOI) of the low-voltage devices in the Source-Driver chip is poor, and the situation of GOI failure frequently occurs. The leakage and low-yield failure caused thereby have become a problem that frequently occurs and is difficult to solve. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor device and its manufacturing method that can improve GOI.

[0005] A manufacturing method of a semiconductor device includes: obtaining a wafer having an isolation structure formed on a substrate, where the isolation structure is used to divide an active region; forming a first gate oxide layer on the substrate and the isolation structure; forming a photoresist on the first gate oxide layer and developing the photoresist to remove the photoresist at positions where the first gate does not need to be formed; removing the photoresist residue particles formed by development through plasma reaction; removing the first gate oxide layer at positions not protected by the photoresist through etching to form a first gate oxide structure; forming a second gate oxide structure; forming a first gate on the first gate oxide structure and forming a second gate on the second gate oxide structure, where the second gate extends to the upper surface of the isolation structure; wherein, the first gate is the gate of a first device, the second gate is the gate of a second device, the operating voltage of the first device is greater than that of the second device, and the thickness of the first gate oxide layer is greater than that of the second gate oxide layer.

[0006] In the manufacturing method of the above semiconductor device, there is a height difference at the junction between the isolation structure and the active region. Therefore, there is also a height difference in the first gate oxide layer at this junction. Photoresist residue particles (PR residue or PR scum) formed due to unclean development are likely to remain at the height difference position of the first gate oxide layer. If these photoresist residue particles are not removed, they are likely to combine with the components of the unetched first gate oxide layer during the etching of the first gate oxide layer to form impurity particles, which accumulate at the height difference position of the first gate oxide layer and cause the second gate oxide structure at this junction to be incomplete / dense when the second gate oxide structure is formed. Since the second gate extends onto the isolation structure, the incomplete / dense second gate oxide structure at this junction will cause the GOI of the second device (i.e., the low-voltage device) to fail. The manufacturing method of the above semiconductor device can improve the integrity / density of the second gate oxide structure at this junction by removing these photoresist residue particles through plasma, thereby solving the problem of GOI failure of the second device.

[0007] In one embodiment, after the step of etching away the first gate oxide layer at the position not protected by the photoresist and before the step of forming the second gate oxide structure, there is also a step of surface-treating the wafer with dilute hydrofluoric acid.

[0008] In one embodiment, the dilute hydrofluoric acid is a dilute hydrofluoric acid with a volume ratio of HF to water of 1:100.

[0009] In one embodiment, the treatment time of the step of surface-treating the wafer with dilute hydrofluoric acid is 30 to 60 seconds.

[0010] In one embodiment, after the step of surface-treating the wafer with dilute hydrofluoric acid and before the step of forming the second gate oxide structure, there is also a step of cleaning the wafer with the RCA standard cleaning method.

[0011] In one embodiment, in the step of removing the photoresist residue particles formed by development through plasma by reaction, the gas source for forming the plasma includes N2H2 and O2.

[0012] In one embodiment, the step of removing the photoresist residue particles formed by development through plasma by reaction is to form the plasma using an inductively coupled plasma device.

[0013] In one embodiment, the step of removing the photoresist residue particles formed by development through plasma by reaction includes introducing an inert gas as a dilution gas into the device.

[0014] In one embodiment, the dilution gas is helium.

[0015] In one embodiment, the isolation structure is a shallow trench isolation structure.

[0016] In one embodiment, the step of forming the first gate oxide layer on the substrate and the isolation structure includes depositing a high-temperature oxide.

[0017] In one embodiment, the thickness of the first gate oxide structure is

[0018] In one embodiment, the step of forming the second gate oxide structure includes thermally oxidizing to grow the second gate oxide layer.

[0019] In one embodiment, the thickness of the second gate oxide structure is

[0020] In one embodiment, the step of removing the first gate oxide layer at the positions not protected by the photoresist by etching includes etching using a buffered oxide etchant.

[0021] In one embodiment, in the step of forming the photoresist on the first gate oxide layer, the formed photoresist thickness is greater than

[0022] In one embodiment, the thickness of the photoresist is

[0023] In one embodiment, the semiconductor device includes a source driver circuit of a thin film transistor liquid crystal display.

[0024] A semiconductor device is formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, and the currently understood best mode of these inventions.

[0026] Figures 1a to 1d is a schematic diagram showing that defects are likely to exist in the low-voltage gate oxide formed in the exemplary process with both high- and low-voltage devices;

[0027] Figure 2 is a flowchart of a manufacturing method of a semiconductor device in one embodiment;

[0028] Figure 3 is a schematic diagram of a partial structure of a semiconductor device in one embodiment. DETAILED DESCRIPTION

[0029] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present invention is more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which the present invention belongs. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0031] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part.

[0032] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience in description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0034] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown are to be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be limited to the particular shapes of regions shown herein but should include shape deviations due to, for example, manufacturing. For example, an implanted region shown as rectangular will typically have rounded or curved features at its edges and / or an implanted concentration gradient, rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present invention.

[0035] The semiconductor field vocabulary used herein is the common technical vocabulary of those skilled in the art. For example, for P-type and N-type impurities, to distinguish the doping concentration, simply use P+ type to represent the P-type with heavy doping concentration, P type to represent the P-type with medium doping concentration, P- type to represent the P-type with light doping concentration, N+ type to represent the N-type with heavy doping concentration, N type to represent the N-type with medium doping concentration, and N- type to represent the N-type with light doping concentration.

[0036] Taking the Source Driver IC process with a critical dimension (CD) of 0.18 μm, the operating voltage of the low-voltage device of 3.3 V, and the breakdown voltage of the high-voltage device of 18 V as an example, the operating voltage of the low-voltage device is 3.3 V, the gate oxide material is a thermal oxide layer, and the thickness is The operating voltage of the high-voltage device is 18 V, and the gate oxide material is a high-temperature oxide (HTO) material. For example, an oxide layer formed by high-temperature CVD (chemical vapor deposition), and the thickness is

[0037] Comparing the status of the gate oxide integrity (GOI) of 3.3V devices in the Source-Driver process with other standard processes, it can be seen that both the average breakdown voltage characteristics and the distribution of the breakdown voltage levels of the Source-Driver process are significantly worse than those of the standard process, which will greatly affect the yield stability of the product.

[0038] The inventors analyzed this problem and finally confirmed that there are significant process differences between high-voltage and low-voltage devices in Source-Driver products. When forming the gate oxide for low-voltage devices, the edge of the active area is affected by the process of high-voltage devices, resulting in incomplete or non-dense formation of the gate oxide, ultimately leading to the failure of the GOI of low-voltage devices.

[0039] Specifically, the process flow of the above Source-Driver process is as follows: high-voltage gate oxide deposition ( HTO) → ensuring that only the high-voltage device area retains the high-voltage gate oxide through photolithography and etching → growing the low-voltage gate oxide in the remaining low-voltage area See Figure 1a , after depositing HTO (high-temperature oxide) over the entire surface of the wafer (Wafer) as the high-voltage gate oxide (HVGOX), due to the height difference at the junction of STI (shallow trench isolation) and the active area, there is also a height difference on the surface of the relatively thick high-voltage gate oxide. After defining the high-voltage gate region through DG photolithography (the photoresist in other regions is developed and removed), due to the thick photoresist in DG photolithography, there are likely to be photoresist residue particles (PR residue or PRscum) formed due to incomplete development at the height difference on the surface of the high-voltage gate oxide. See the elliptical box in Figure 1b . After cleaning the unprotected HTO with buffered oxide etchant (BOE), under the dual influence of the photoresist residue particles and the relatively thick high-voltage gate oxide at the junction of STI and the active area, it is difficult to completely remove the HTO at the corners / corners of the junction, and finally tiny impurity particles formed by the combination of the remaining HTO and other impurities (the particles contain elements such as C, Si, O, etc.) are left. See Figure 1c . When growing the low-voltage gate oxide, due to the presence of these impurity particles at the junction, the grown low-voltage gate oxide is incomplete / non-dense, ultimately affecting the GOI characteristics of the low-voltage devices.

[0040] To address the above problems, the present application improves the cleaning and surface treatment processes during device manufacturing, which can completely clean the gate oxide at the height difference, avoid the formation of tiny particles that are difficult to remove, and finally form a complete and dense low-voltage gate oxide film layer, effectively solving the problem of frequent failure of the GOI of low-voltage devices.

[0041] Figure 2 is a flowchart of a method for manufacturing a semiconductor device in an embodiment, including the following steps:

[0042] S210, form an isolation structure for partitioning an active region on a substrate.

[0043] In one embodiment of the present application, the isolation structure is a shallow trench isolation (STI) structure.

[0044] In one embodiment of the present application, the substrate is a semiconductor substrate, and its material can be undoped single-crystalline silicon, doped single-crystalline silicon, silicon on insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-germanium-on-insulator stacked (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc., and can also be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. Figure 2 In the corresponding embodiment, the constituent material of the substrate is selected as single-crystalline silicon.

[0045] S220, form a first gate oxide layer on the substrate and the isolation structure.

[0046] In one embodiment of the present application, global planarization of STI and well implantation of the device can also be performed before step S220.

[0047] In one embodiment of the present application, the first gate oxide layer is formed by a deposition process and will be used as the gate oxide of high-voltage devices subsequently.

[0048] S230, form a photoresist on the first gate oxide layer and develop the photoresist.

[0049] In one embodiment of the present application, a photoresist is coated on the first gate oxide layer, and then the photoresist is developed according to the pattern of the gate of the high-voltage device, so as to remove the photoresist at the positions where the gate of the high-voltage device does not need to be formed.

[0050] Specifically, the high-voltage region and the low-voltage region can be defined by DG lithography. As described above, there is a height difference at the junction between the isolation structure and the active region, so there is also a height difference in the first gate oxide layer at this junction. Photoresist residue particles (PR residue or PR scum) formed by unclean development are likely to remain at the height difference positions of the first gate oxide layer. The components of these particles include elements such as C, H, N, O, and are generally organic polymers (Polymer).

[0051] S240, react and remove the photoresist residue particles formed by development through plasma.

[0052] Generate a plasma of the desired ions through a corresponding device, and react the photoresist residue particles with the plasma to remove them. In an embodiment of the present application, an ICP (Inductively Coupled Plasma) device is used to form a plasma, and the photoresist residue particles are removed by a combination of chemical etching and physical bombardment.

[0053] In an embodiment of the present application, the gas source for forming the plasma includes N2H2 and O2. In an embodiment of the present application, an inert gas as a dilution gas can also be introduced into the device to obtain better in-chip uniformity. Specifically, the dilution gas can be helium.

[0054] S250, Remove the first gate oxide layer that is not protected by the photoresist through etching to form a first gate oxide structure.

[0055] Since the photoresist residue particles have been removed in step S240, the etching in step S250 can basically etch clean the first gate oxide layer at the junction of the isolation structure and the active region.

[0056] S260, Form a second gate oxide structure.

[0057] In an embodiment of the present application, the second gate oxide layer can be formed by a thermal oxidation growth process, and then etched to form a second gate oxide structure. As the gate oxide of a low-voltage device, the thickness of the second gate oxide structure is less than that of the first gate oxide structure. Specifically, the second gate oxide layer can be formed by high-temperature furnace tube thermal oxidation.

[0058] S270, Form a first gate on the first gate oxide structure and a second gate on the second gate oxide structure.

[0059] The gate of the low-voltage device (i.e., the second gate) extends to the upper surface of the isolation structure. Therefore, the quality of the second gate oxide layer at the junction of the isolation structure and the active region will have a significant impact on the GOI of the low-voltage device.

[0060] The manufacturing method of the above semiconductor device can improve the integrity / density of the second gate oxide structure at the junction of the isolation structure and the active region by removing the photoresist residue particles formed by developing in step S230 through plasma, thereby solving the problem of the failure of the GOI of the second device.

[0061] In an embodiment of the present application, step S220 deposits HTO through a chemical vapor deposition process.

[0062] In an embodiment of the present application, the thickness of the HTO deposited in step S220 is

[0063] In one embodiment of the present application, the etching solution used in step S250 is BOE.

[0064] In one embodiment of the present application, between step S250 and S260, there is also included step S252: performing a surface treatment on the wafer using dilute hydrofluoric acid. Since the etching rate of the etchant used in step S250 is relatively fast, after the first gate oxide layer at the positions on the wafer surface not protected by the photoresist is substantially removed, over-etching cannot be performed for too long. Adding a step of cleaning with dilute hydrofluoric acid can ensure that the first gate oxide layer at the junction of the isolation structure and the active region is completely removed. In one embodiment of the present application, step S252 uses hydrofluoric acid with a volume ratio of 1:100. In one embodiment of the present application, the time for the surface treatment of the wafer with dilute hydrofluoric acid in step S252 is 30 to 60 seconds.

[0065] The size of the gate of a high-voltage device is generally relatively large. Exemplarily, the width of the gate of a high-voltage device is 0.8 micrometers (the space between the gate and the adjacent structure can also be 0.8 micrometers). Therefore, the photoresist formed in step S230 is correspondingly thicker. In one embodiment of the present application, the thickness of the photoresist is greater than For example, it can be Step S230 is prone to incomplete development and formation of photoresist residue particles. One of the reasons is that the photoresist is thicker.

[0066] In one embodiment of the present application, the thickness of the second gate oxide structure formed in step S260 is

[0067] In one embodiment of the present application, after step S252 and before step S260, there is also included a step of performing a pre-cleaning on the front surface of the second gate oxide. Specifically, the wafer can be cleaned using the RCA standard cleaning method.

[0068] The present application correspondingly provides a semiconductor device, which is manufactured according to the manufacturing method of the semiconductor device described in any of the foregoing embodiments, and this semiconductor device integrates a high-voltage device and a low-voltage device. Figure 3 It is a schematic diagram of a partial structure of a semiconductor device in an embodiment, including a substrate 110, a first well region PT and a second well region PX in the substrate 110, and an N-type doped region NM in the second well region PX as the source region / drain region; an isolation structure 120 is provided on the substrate 110; a gate oxide 132 of a low-voltage device is provided on the first well region PT, a low-voltage device gate 134 is provided on the gate oxide 132, a gate oxide 142 of a high-voltage device is provided on the second well region PX, and a high-voltage device gate 144 is provided on the gate oxide 142. Among them, the low-voltage device is a narrow-channel device, and the low-voltage device gate 134 extends onto the isolation structure 120.

[0069] In one embodiment of the present application, the semiconductor device is a source driver circuit of a thin film transistor liquid crystal display (TFT-LCD).

[0070] In one embodiment of the present application, the substrate 110 is a semiconductor substrate, and its material can be undoped single crystal silicon, doped single crystal silicon, silicon on insulator (SOI), silicon-on-insulator stacked silicon (SSOI), silicon-germanium-on-insulator stacked silicon (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), etc. It can also be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. In Figure 3 In the illustrated embodiment, the constituent material of the substrate 110 is selected as single crystal silicon.

[0071] In one embodiment of the present application, the isolation structure 120 is STI.

[0072] In one embodiment of the present application, the gate oxide 132 is formed by thermal oxidation growth, and the thickness is

[0073] In one embodiment of the present application, the gate oxide 142 is HTO, and the thickness is

[0074] It should be understood that although the steps in the flowcharts of the present application are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts of the present application may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps or stages in other steps.

[0075] In the description of this specification, the description of reference terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials, or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0076] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0077] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent shall be subject to the appended claims.

Claims

1. A manufacturing method of a semiconductor device, comprising: Obtaining a wafer with an isolation structure formed on a substrate, the isolation structure being used to demarcate active regions; Forming a first gate oxide layer on the substrate and the isolation structure; Forming a photoresist on the first gate oxide layer and developing the photoresist to remove the photoresist at positions where the first gate is not required to be formed; Reactively removing the photoresist residue particles formed by development through plasma; Removing the first gate oxide layer at positions not protected by the photoresist through etching to form a first gate oxide structure; Performing surface treatment on the wafer using dilute hydrofluoric acid to ensure that the first gate oxide layer at the junction of the isolation structure and the active region is completely removed; Forming a second gate oxide structure after the surface treatment; Forming a first gate on the first gate oxide structure and a second gate on the second gate oxide structure, the second gate extending to the upper surface of the isolation structure; Wherein, the first gate is the gate of a first device, the second gate is the gate of a second device, the operating voltage of the first device is greater than that of the second device, and the thickness of the first gate oxide structure is greater than that of the second gate oxide structure.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, In the step of reactively removing the photoresist residue particles formed by development through plasma, the gas source for forming the plasma includes N2H2 and O2.

3. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The isolation structure is a shallow trench isolation structure.

4. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The step of forming the first gate oxide layer on the substrate and the isolation structure includes depositing a high-temperature oxide.

5. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The step of forming the second gate oxide structure includes thermally oxidizing and growing a second gate oxide layer.

6. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The step of removing the first gate oxide layer at positions not protected by the photoresist through etching includes etching using a buffered oxide etchant.

7. The manufacturing method of the semiconductor device according to claim 1, characterized in that, In the step of forming the photoresist on the first gate oxide layer, the thickness of the formed photoresist is greater than 14000 Å.

8. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The semiconductor device includes a source driver circuit of a thin film transistor liquid crystal display.

9. A semiconductor device, characterized in that, Manufactured and formed by the manufacturing method of the semiconductor device according to any one of claims 1-8.

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