Tunneling logic device and method of making the same

Abstract

The application discloses a through-hole logic device and a manufacturing method thereof. The through-hole logic device comprises a through-hole device basic structure; a filling layer formed by filling material meeting preset fluidity conditions is arranged on the device basic structure; and an oxidation layer with a first preset thickness is arranged on the filling layer. By filling the through-hole with the filling material meeting the preset fluidity conditions, the application can avoid the use of the filling and planarization process, improve the flatness of the surface of the filling layer, and more conveniently realize the through-hole filling of the small node logic device and the subsequent manufacturing of the logic device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic devices, and particularly relates to a logic device with a through hole and a manufacturing method thereof. BACKGROUND

[0002] The through hole process is usually used in a radio frequency insulating silicon substrate device. The electrode of the logic device is connected with the substrate by the through hole, so that the opening or closing capacity of the channel is improved. After the through hole structure is set, other related structures, such as a contact layer and an oxide layer, need to be set.

[0003] In the prior art, the manufacturing process of the logic device is mainly to fill the through hole in the logic device by a bottom anti-reflective coating to form a double-layer structure, and then to perform a planarization treatment on the filled surface to obtain the stacked double-layer structure. With the continuous progress of science and technology, the process node is continuously reduced, and the setting area that can be led out by the electrode after the planarization treatment is smaller and smaller. The manufacturing process flow of the above double-layer structure cannot meet the through hole filling of the small node below 90 nm and the subsequent manufacturing process of the logic device.

[0004] The above content is only used to assist in understanding the technical solutions of the present application and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0005] The main purpose of the present application is to provide a logic device with a through hole and a manufacturing method thereof, which aims to solve the problem that it is difficult to fill the through hole of the small node in the prior art.

[0006] To achieve the above purpose, the present application provides a logic device with a through hole, comprising:

[0007] a device basic structure with a through hole;

[0008] a filling layer formed by a filling material meeting a preset fluidity condition is arranged on the device basic structure;

[0009] an oxide layer with a first preset thickness is arranged on the filling layer.

[0010] Optionally, the filling layer comprises:

[0011] a smooth surface layer and a filling body same as the through hole structure;

[0012] the filling body is arranged in the through hole;

[0013] the smooth surface layer is arranged on the upper surface of the filled device basic structure, and the upper surface of the smooth surface layer is in contact with the lower surface of the oxide layer.

[0014] Optionally, the logic device with a through hole further comprises a connection layer with a second preset thickness.

[0015] The second preset thickness connection layer is arranged on the oxidation layer.

[0016] Optionally, the connection layer comprises a preset number of connection leads and a photoetching layer.

[0017] The photoetching layer is provided with a preset number of lead holes; each connection lead is connected with a corresponding electrode in the device base structure through a corresponding lead hole.

[0018] Optionally, the through-hole logic device further comprises:

[0019] a substrate;

[0020] The through-hole device base structure is arranged on the substrate.

[0021] In addition, to achieve the above-mentioned purpose, the application further provides a through-hole logic device manufacturing method, which comprises:

[0022] obtaining a through-hole device base structure;

[0023] filling the through hole of the device base structure with a filling material satisfying a preset flowability condition to obtain a filled logic device;

[0024] depositing an oxidation layer with a first preset thickness on the filled logic device by chemical vapor deposition;

[0025] obtaining the logic device after the oxidation layer is arranged as a through-hole logic device.

[0026] Optionally, after the step of depositing an oxidation layer with a first preset thickness on the filled logic device by chemical vapor deposition, the method further comprises:

[0027] arranging a connection layer with a second preset thickness on the oxidation layer;

[0028] obtaining the logic device after the connection layer is arranged as a through-hole logic device.

[0029] Optionally, the step of arranging a connection layer with a second preset thickness on the oxidation layer comprises:

[0030] arranging a photoetching layer with the second preset thickness on the oxidation layer;

[0031] etching a preset number of lead holes on the photoetching layer;

[0032] arranging a connection lead connected with an electrode in the device base structure in each lead hole to form a connection layer.

[0033] Optionally, the step of filling the via of the logic device with the filling material satisfying the preset flowability condition comprises:

[0034] filling the via of the logic device with the filling material satisfying the preset flowability condition to form a filling body same as the via structure;

[0035] forming a smooth surface layer on the filling body and the surface of the non-via region of the logic device with the filling material.

[0036] Optionally, the step of obtaining the via-equipped device base structure comprises:

[0037] forming a device base structure of a logic device on a substrate;

[0038] forming a via on the device base structure with a via process to obtain a logic device with a via to be filled.

[0039] The present application provides a via-equipped logic device and a manufacturing method thereof, the via-equipped logic device comprising a via-equipped device base structure; a filling layer formed of a filling material satisfying a preset flowability condition is arranged on the device base structure; and an oxidation layer with a first preset thickness is arranged on the filling layer. By filling the via with the filling material satisfying the preset flowability condition, the present application can avoid using a filling-and-planarization process, improve the flatness of the surface of the filling layer, and more conveniently realize the via filling of a small-node logic device and the subsequent manufacturing of the logic device. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only show some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from the structures shown in the drawings without any creative effort.

[0041] Figure 1 a structural schematic diagram of a first embodiment of the via-equipped logic device of the present application;

[0042] Figure 2 a first structural schematic diagram of a second embodiment of the via-equipped logic device of the present application;

[0043] Figure 3 a first structural schematic diagram of a second embodiment of the via-equipped logic device of the present application;

[0044] Figure 4 a via structure diagram in the prior art and the via-equipped logic device of the present application;

[0045] Figure 5 The flow chart of the first embodiment of the method for manufacturing the logic device with through holes;

[0046] Figure 6 The flow chart of the second embodiment of the method for manufacturing the logic device with through holes.

[0047] BRIEF DESCRIPTION OF DRAWINGS

[0048] Reference Name Reference Name 10 Device infrastructure 20 Fill layer 30 Oxidation layer 40 Connection layer 50 Substrate 201 Smooth surface layer 202 Filler body 401 Connection lead 402 Lithography layer

[0049] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0050] It should be understood that the specific embodiments described herein merely set forth preferred combinations of components and / or other features, and that persons of ordinary skill in the art will appreciate that many modifications are possible and can in fact be desirable in certain circumstances.

[0051] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application.

[0052] Reference Figure 1 , Figure 1 The structure schematic diagram of the logic device with through holes is provided for the first embodiment of the present application, in the embodiment, the logic device with through holes comprises: a device basic structure 10 with through holes;

[0053] The filling layer 20 formed by the filling material meeting the preset flowability condition is arranged on the device basic structure 10; the oxidation layer 30 with the first preset thickness is arranged on the filling layer 20.

[0054] It should be understood that in the specific structure of the logic device, a via structure is usually provided for inputting or outputting charge to the logic device, for example, the electrode materials of the gate, source and drain of the MOS tube are usually arranged inside the chip structure of the MOS tube, and the input voltage or output voltage of the gate, source or drain is arranged by means of lead wire. In the process of manufacturing the logic device, the via structure needs to be filled. The existing filling scheme is to directly arrange a bottom anti-reflective related coating on the surface of the logic device basic structure 10 to fill the via. Due to the poor filling capacity of such materials, the structure of the wafer surface after filling is uneven. For example, when using AR40 bottom anti-reflective material to fill the via, since the AR40 material does not have filling capacity and has poor fluidity, the smoothness of the wafer surface structure after filling with this material is poor, and related return processes need to be performed for planarization treatment. In addition, since different specific logic devices have different requirements for the smoothness of the wafer surface, it is difficult to determine the end point of the planarization related process flow. The planarization related process flow usually uses etching, which may cause other problems, for example, etching the bottom anti-reflective related coating on the device basic structure 10, although it effectively improves the flatness of the wafer surface structure, but the edge alignment accuracy between the etched device basic structure 10 and the bottom anti-reflective related coating is low, which is difficult to meet the process requirements below 90nm.

[0055] It should be noted that the device basic structure 10 refers to the basic structure of the logic device. The device basic structure 10 has the function of the logic device, but the device basic structure 10 has not completed the related packaging process and is a semi-finished product, which cannot be directly used. Among them, the logic device refers to an electronic component with certain logic control function, such as diode, triode, MOS tube, etc. The preset fluidity condition is a condition for limiting the fluidity of the filling material. When the fluidity of the filling material meets the preset fluidity condition, the filling material can directly form a smooth surface on the device basic structure without the need for planarization process. The filling material can be a material in the Nylon Floating Coating (NFC) series, and specifically, a material of HM8133 model can be selected as the filling material. The filling layer 20 can be used to fill the via in the logic device with via. The oxide layer 30 is a bottom anti-reflective coating. The oxide layer 30 can be used to improve the bottom reflection. The first preset thickness is the thickness of the oxide layer 30, which is preset. In the case of arranging the oxide layer 30 with the first preset thickness, the bottom reflection can be effectively avoided to affect the surface of the logic device. Among them, the filling layer 20 and the oxide layer 30 are structures composed of insulating materials.

[0056] In the manufacturing process of the logic device, the via structure can be arranged on the device base structure 10 of the logic device by using the via process, then the via is filled by using the filling material meeting the preset condition to form the filling layer 20, and finally a layer of oxide layer 30 is arranged on the surface of the filling layer 20 by using the chemical vapor deposition to form the specific structure of the logic device.

[0057] In the embodiment, a via logic device is provided, which comprises a via device base structure; a filling layer formed by a filling material meeting a preset flowability condition is arranged on the device base structure; and a first preset thickness of oxide layer is arranged on the filling layer. In the embodiment, the filling material meeting the preset flowability condition is used to fill the via, so that the flatness of the surface of the filling layer is improved without using the planarization process after filling, and the oxide layer is arranged on the filling layer, so that the via filling of the small node logic device and the subsequent manufacturing of the logic device are more conveniently realized.

[0058] Based on the first embodiment of the via logic device, a second embodiment of the via logic device is provided.

[0059] Reference is made to Figure 2 In the embodiment, the filling layer comprises:

[0060] a smooth surface layer 201 and a filling body 202 which is the same as the via structure;

[0061] The filling body 202 is arranged in the via;

[0062] The smooth surface layer 201 is arranged on the upper surface of the device base structure 10 after filling, and the upper surface of the smooth surface layer 201 is in contact with the lower surface of the oxide layer 30.

[0063] Reference is made to Figure 2 It should be understood that the filling body 202 is a structure for filling the via. The structure of the filling body 202 is completely the same as the via structure to be filled and is composed of the filling material meeting the preset flowability condition, so that the complete filling of the via structure is realized. The smooth surface layer 201 is a smooth structure formed on the filling body 202 and the surface of the base structure, and the flatness of which meets the requirement. The oxide layer 30 can be directly arranged on the smooth surface layer 201 without any treatment on the surface. In the embodiment, the specific thickness of the smooth surface layer is not limited. The smooth surface layer 201 and the filling body 202 are both structures composed of the NFC series material meeting the preset flowability condition.

[0064] In a specific implementation, the filling material of the NFC series can be directly injected into the through hole, and the filling body 202 is formed in the through hole by using the fluidity of the filling material, and then the filling material is continuously added until the smooth surface layer 201 is formed on the surface of the device base structure 10. Of course, the filling material can also be directly injected into the through hole until the through hole is filled and a smooth surface layer is formed on the surface of the device base structure 10.

[0065] Referring to Figure 3 In the embodiment, the logic device with through holes further comprises a connection layer 40 with a second preset thickness.

[0066] The connection layer 40 with the second preset thickness is arranged on the oxide layer 30.

[0067] The connection layer 40 comprises a preset number of lead holes and a preset number of connection leads. Each connection lead is connected to a corresponding electrode in the device base structure 10 through a corresponding lead hole.

[0068] It should be understood that the connection layer 40 is a structure for connecting the logic device to an external circuit. The connection layer 40 comprises a photoetching layer 402 and connection leads 401. The connection leads 401 can be connected to the electrodes in the logic device through the through holes arranged on the connection layer 40. The preset number refers to the number of lead holes and connection leads 401. The number of connection leads 401 is the same as the number of lead holes and is related to the specific logic device. For example, a logic device such as a diode comprises an anode and a cathode, and two connection holes and two corresponding connection leads 401 can be arranged on the connection layer 40; while a logic device such as a triode or MOS tube comprises three electrodes, and three lead holes and three connection leads 401 should be arranged on the connection layer 40, and the three connection leads 401 are connected to the corresponding electrodes through different lead holes. Figure 3 In the embodiment, taking a diode logic device as an example, two connection leads 401 pass through the oxide layer 30 and the filling layer 20 through corresponding lead holes to connect to the corresponding anode or cathode. When the diode works, a voltage can be input to the connection lead 401 corresponding to the anode of the diode, and then a complete circuit is formed by outputting through the connection lead 401 corresponding to the cathode of the diode, so that the diode can be normally controlled to work. The second preset thickness is the thickness of the connection layer 40, which can be set according to the specific device. In the embodiment, the thickness of the oxide layer 30 can be set to 800A, and the thickness of the connection layer 40 can be set to 1500A.

[0069] In a specific implementation, a photoetching layer 402 with a second preset thickness can be arranged on the surface of the oxide layer 30, and then a preset number of lead holes are photoetched on the photoetching layer 402 by photoetching, and the connection leads 401 are connected to the corresponding electrodes through the lead holes.

[0070] In the embodiment, through the three-layer structure composed of the device base structure 10, the filling layer 20 and the oxidation layer 30, the via structure with smoother edge structure can be formed in the photoetching process. Referring to Figure 4 , Figure 4 The left drawing in FIG. 1 is the specific structure of the via obtained by the double-layer structure in the prior art after photoetching, Figure 4 The right drawing in FIG. 1 is the specific structure of the via obtained by the three-layer structure in the embodiment after photoetching. The smoothing effect of the surface via of the logic device formed by the three-layer structure after filling with the filling material satisfying the preset filling condition is obviously better than that of the surface via of the logic device of the double-layer structure. Moreover, the alignment accuracy between the layers of the logic device of the three-layer structure is also better than that of the logic device of the double-layer structure.

[0071] In the embodiment, the via logic device further comprises:

[0072] A substrate 50; the device base structure 10 with the via is arranged on the substrate 50.

[0073] It can be understood that the substrate 50 is a structure for carrying the entire logic device. The substrate 50 can be a silicon substrate, and the surface area of the silicon substrate can be appropriately larger than the bottom area of the logic device base structure.

[0074] In the embodiment, by using the filling material satisfying the preset fluidity condition to fill the via, the case of using the filling and planarization process can be avoided, the flatness of the surface of the filling layer is improved, the oxidation layer is arranged on the filling layer, and the via filling of the small node logic device is more conveniently realized; and the three-layer structure logic device obtained can further improve the smoothing effect of the via edge and the alignment accuracy between the layers.

[0075] In addition, to achieve the above object, referring to Figure 5 , Figure 5 FIG. 1 is a flow diagram of the first embodiment of the method for manufacturing the logic device with via according to the embodiment of the present application. Based on Figure 5 The present application further provides a method for manufacturing a logic device with via, which comprises:

[0076] Step S10: obtaining a device base structure with via.

[0077] Step S20: filling the via of the device base structure with a filling material satisfying a preset fluidity condition to obtain the logic device after filling.

[0078] Step S30: depositing an oxidation layer with a first preset thickness on the logic device after filling by chemical vapor deposition.

[0079] Step S40: Obtain the logic device after setting the oxidation layer as a logic device with a via.

[0080] It should be noted that the device base structure refers to the base structure of the logic device. The device base structure has the function of the logic device, but the device base structure has not completed the related packaging process, and is a semi-finished product device, which cannot be directly used. Among them, the logic device refers to an electronic component with certain logic control function, such as diode, triode, MOS tube, etc. The preset flow condition is a condition for limiting the flow of the filling material. When the flow of the filling material meets the preset flow condition, the filling material can directly form a smooth surface on the device base structure without the need for a planarization process. The filling material can be a material in the Nylon Floating Coating (NFC) series, and specifically, a material of model HM8133 can be selected as the filling material. The filling layer 20 can be used to fill the via in the logic device with a via. The oxidation layer is a bottom antireflection coating. The oxidation layer can be used to improve the bottom reflection. The first preset thickness is the thickness of the oxidation layer, which is preset. In the case of setting the oxidation layer with the first preset thickness, the bottom reflection can be effectively avoided to affect the surface of the logic device. The filling layer and the oxidation layer are both structures composed of insulating materials.

[0081] In the manufacturing process of the logic device, a via structure can be set on the device base structure of the logic device by using a via process, then a filling layer is formed by filling the via with a filling material meeting the preset condition, and finally an oxidation layer 30 is set on the surface of the filling layer by using chemical vapor deposition to form the specific structure of the logic device.

[0082] Referring to Figure 6 , Figure 6 is a flow diagram of a second embodiment of the method for manufacturing a logic device with a via according to the present application. Based on the first embodiment of the method for manufacturing a logic device with a via according to the present application, the second embodiment of the method for manufacturing a logic device with a via according to the present application is proposed.

[0083] In this embodiment, the step S20 specifically comprises:

[0084] Step S201: filling the via of the logic device with a filling material meeting a preset flow condition to form a filling body same as the via structure.

[0085] Step S202: setting a smooth surface layer on the surface of the filling body and the non-via region of the logic device by using the filling material to obtain the logic device after filling.

[0086] It should be understood that the filling body is a structure for filling the through hole. The filling body has the same structure as the through hole to be filled and is composed of a filling material with a flowability meeting a preset flowability condition, so as to achieve complete filling of the through hole structure. The smooth surface layer is a smooth structure formed on the surface of the filling body and the underlying structure during which the smoothness meets the requirements. On the smooth surface layer, an oxidation layer can be directly arranged without any treatment on the surface. In the embodiment, the specific thickness of the smooth surface layer is not limited. The smooth surface layer and the filling body are both structures composed of an NFC series material meeting the preset flowability condition. The surface of the device underlying structure with a through hole includes a filling area and a non-filling area. In the filling area, the filling body is filled by using the filling material, and the smooth surface layer is arranged on the surface of the filling body; and in the non-filling area, only the smooth surface layer is arranged on the surface.

[0087] In a specific implementation, the filling material of the NFC series can be directly injected into the through hole, the filling body 202 is formed in the through hole by using the flowability of the filling material, and then the filling material is continuously added on the surface of the filling body 202 and the device underlying structure until the smooth surface layer 201 is formed. Of course, the filling material can also be directly injected into the through hole until the through hole is completely filled and a smooth surface layer is formed on the surface of the device underlying structure.

[0088] After the step S30, the method further includes:

[0089] Step S301: arranging a connection layer with a second preset thickness on the oxidation layer.

[0090] Step S302: obtaining the logic device after the connection layer is arranged as a logic device with a through hole.

[0091] The connection layer 40 is a structure for connecting the logic device with an external circuit. The connection layer 40 includes a photoetching layer 402 and a connection lead 401. The connection lead 401 can be connected with an electrode in the logic device through a through hole arranged on the connection layer 40. The preset number refers to the number of lead holes and the connection leads 401. The number of the connection leads 401 is the same as that of the lead holes and is related to a specific logic device. For example, a logic device such as a diode includes an anode and a cathode, two connection holes and two corresponding connection leads 401 can be arranged on the connection layer 40; and a logic device such as a triode or a MOS tube includes three electrodes, so three lead holes and three connection leads 401 should be arranged on the connection layer 40, and the three connection leads 401 are respectively connected with the corresponding electrodes through different lead holes. Figure 3In the embodiment, taking a diode as an example, two connection leads 401 pass through the oxide layer 30 and the filling layer 20 through corresponding lead holes to connect corresponding anodes or cathodes. When the diode works, a complete loop can be formed by inputting voltage to the connection lead 401 corresponding to the anode of the diode and then outputting through the connection lead 401 corresponding to the cathode of the diode, so that the diode can work normally. The second preset thickness is the thickness of the connection layer 40, which can be set according to the specific device. In the embodiment, the thickness of the oxide layer 30 can be set to 800 A, and the thickness of the connection layer 40 can be set to 1500 A.

[0092] The step S301 specifically comprises:

[0093] Step S3011: disposing a photoetching layer of the second preset thickness on the oxide layer;

[0094] Step S3012: etching a preset number of lead holes on the photoetching layer;

[0095] Step S3013: disposing a connection lead connected with an electrode in the device basic structure in each lead hole to form a connection layer.

[0096] In the embodiment, a photoetching layer 402 of the second preset thickness can be disposed on the surface of the oxide layer 30, and then a preset number of lead holes can be etched on the photoetching layer 402 by photoetching, so that the connection lead 401 is connected with the corresponding electrode through the lead hole.

[0097] In the embodiment, through the three-layer structure composed of the device basic structure, the filling layer 20 and the oxide layer 30, a through hole structure with a smoother edge structure can be formed in the photoetching process. Referring to Figure 4 , Figure 4 The left drawing in the embodiment shows a specific structure of a through hole obtained by photoetching of a double-layer structure in the prior art, Figure 4 The right drawing in the embodiment shows a specific structure of a through hole obtained by photoetching of a three-layer structure in the embodiment. The smooth effect of the surface through hole of the logic device of the three-layer structure filled by the filling material satisfying the preset filling condition is obviously better than that of the surface through hole of the logic device of the double-layer structure. Moreover, the alignment accuracy between the layers of the logic device of the three-layer structure is also better than that between the layers of the logic device of the double-layer structure.

[0098] In addition, in the embodiment, the step S10 specifically comprises:

[0099] disposing a device basic structure of a logic device on a substrate;

[0100] disposing a through hole on the device basic structure by a through hole process to obtain a logic device with a through hole to be filled.

[0101] It can be understood that the substrate is a structure for carrying the whole logic device. The substrate can be a silicon substrate, and the surface area of the silicon substrate can be appropriately larger than the bottom area of the logic device base mechanism.

[0102] In the embodiment, by filling the through hole with the filling material satisfying the preset fluidity condition, the flatness of the surface of the filling layer can be improved without using the planarization process after filling, and the oxidation layer is arranged on the filling layer, so that the through hole filling of the small node logic device is more conveniently realized. The three-layer structure logic device obtained can further improve the smoothness of the edge of the through hole and the alignment accuracy between layers.

[0103] The above are only preferred embodiments of the present application, and do not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation obtained by using the content of the specification and drawings of the present application, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

[0104] Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0105] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative positional relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly.

[0106] In addition, the description of "first", "second" and the like in the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the protection scope required by the present application.

Claims

1. A logic device with a via, characterized by, include: A basic device structure with through-holes; the through-holes are through-holes with nodes below 90nm; The device's basic structure is provided with a filling layer formed by a filling material that meets preset flowability conditions; The filling layer is provided with an oxide layer of a first preset thickness, which is used to prevent bottom reflection from affecting the surface of the logic device with through-hole; The filling layer includes: a filler identical to the through-hole structure; The filler is disposed within the through hole; The logic device with through-holes further includes: a connection layer of a second preset thickness; The second preset thickness connecting layer is disposed on the oxide layer.

2. The via logic device of claim 1, wherein, The filling layer further includes: Smooth surface; The smooth surface layer is disposed on the upper surface of the device base structure after filling, and the upper surface of the smooth surface layer is in contact with the lower surface of the oxide layer.

3. The via logic device of claim 1, wherein, The connection layer includes a predetermined number of connection leads and a photolithography layer; The photolithography layer has a predetermined number of lead holes; each of the connecting leads is connected to the corresponding electrode in the basic structure of the device through the corresponding lead hole.

4. The via logic device of claim 1, wherein, The logic device with through-hole also includes: Substrate; The basic structure of the device with through-holes is disposed on the substrate.

5. A method for fabricating a via logic device, comprising: The method for fabricating the logic device with through-hole includes: Obtain the basic structure of a device with vias; the vias are vias with nodes below 90nm; The logic device is obtained by filling the through-holes of the device base structure with a filling material that meets preset flowability conditions. An oxide layer of a first predetermined thickness is deposited on the filled logic device by chemical vapor deposition; the oxide layer is used to prevent bottom reflections from affecting the surface of the logic device with vias; Obtain the logic device with oxide layer applied as a logic device with through-hole; The step of filling the through-holes of the device base structure with a filling material that meets preset flowability conditions to obtain the filled logic device includes: The through-holes of the logic device are filled with a filling material that meets preset flowability conditions to form a filling body with the same structure as the through-holes; The logic device is obtained by forming a smooth surface layer on the surface of the filler and the non-through-hole area of ​​the logic device using the filling material; Following the step of depositing an oxide layer of a first predetermined thickness on the filled logic device by chemical vapor deposition, the method further includes: A connecting layer of a second preset thickness is provided on the oxide layer; The logic device after the connection layer is set is obtained as a via logic device.

6. The method of claim 5, wherein the via is formed by a process selected from the group consisting of mechanical drilling, laser drilling, and plasma etching. The step of forming a connecting layer of a second preset thickness on the oxide layer includes: A photolithography layer of the second preset thickness is formed on the oxide layer; A predetermined number of lead holes are etched on the photolithography layer; A connection layer is formed by connecting leads that connect to the electrodes inside the device's basic structure within each of the lead holes.

7. The method of claim 5, wherein the step of forming the via is performed by a method selected from the group consisting of: a mechanical drilling method, a laser drilling method, a plasma etching method, and a combination thereof. The steps for obtaining the basic structure of the device with through-holes include: The basic structure of a device on which logic devices are placed; A logic device with through-holes to be filled is obtained by using through-hole technology to create through-holes on the device's basic structure.

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