GaN-based high electron mobility transistor integrated device structure and fabrication method

Abstract

This invention relates to a GaN-based high electron mobility transistor integrated device structure and its manufacturing method. The device structure includes: a channel layer; a barrier layer disposed on the channel layer; a first gate structure disposed on the barrier layer, the first gate structure being made of P-type doped GaN; a first gate electrode disposed on the first gate structure; a dielectric layer disposed on the barrier layer; a second gate electrode disposed on the dielectric layer; a source electrode disposed on the barrier layer and located on the side of the first gate structure away from the second gate electrode; and a drain electrode disposed on the barrier layer and located on the side of the second gate electrode away from the first gate structure. This invention can reduce the peak electric field at the P-type gate edge near the drain, effectively improving the reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a GaN-based high electron mobility transistor integrated device structure, and also to a method for manufacturing a GaN-based high electron mobility transistor integrated device structure. Background Technology

[0002] Under high voltage, the main pressure-bearing location of a P-gate GaN HEMT (High Electron Mobility Transistor) device is the depletion region between the gate and the drain. The strong electric field peak is located near the edge of the drain end of the gate. The larger the peak value of this electric field, the worse the reliability of the device. Summary of the Invention

[0003] Therefore, it is necessary to provide a more reliable GaN-based high electron mobility transistor integrated device structure and its manufacturing method.

[0004] A GaN-based high electron mobility transistor integrated device structure includes: a channel layer; a barrier layer disposed on the channel layer; a first gate structure disposed on the barrier layer, the material of the first gate structure comprising p-type doped GaN; a first gate electrode disposed on the first gate structure; a dielectric layer disposed on the barrier layer; a second gate electrode disposed on the dielectric layer; a source electrode disposed on the barrier layer and located on the side of the first gate structure away from the second gate electrode; and a drain electrode disposed on the barrier layer and located on the side of the second gate electrode away from the first gate structure; wherein, the GaN-based high electron mobility transistor integrated device... The device structure includes a P-type gate HEMT and a MISFET. The first gate electrode serves as the gate of the P-type gate HEMT, the second gate electrode serves as the gate of the MISFET, the source electrode serves as the source electrode of the P-type gate HEMT, and the drain electrode serves as the drain electrode of the MISFET. The portion of the barrier layer located between the first gate structure and the second gate electrode serves as the drain region of the P-type gate HEMT and the source region of the MISFET. The MISFET is a first voltage device, and the P-type gate HEMT is a second voltage device. The breakdown voltage of the first voltage device is greater than the breakdown voltage of the second voltage device.

[0005] In one embodiment, the second gate electrode is electrically connected to the source electrode.

[0006] In one embodiment, the second gate electrode is electrically connected to the first gate electrode.

[0007] In one embodiment, the P-type doped GaN is in direct contact with the barrier layer.

[0008] In one embodiment, the first gate electrode is in direct contact with the first gate structure.

[0009] In one embodiment, the first gate electrode forms a Schottky contact with the first gate structure.

[0010] In one embodiment, the absolute value of the threshold voltage of the MISFET is less than the gate voltage swing of the P-type gate HEMT.

[0011] In one embodiment, the GaN-based high electron mobility transistor integrated device structure further includes a buffer layer, and the channel layer is disposed on the buffer layer.

[0012] In one embodiment, the barrier layer is made of AlGaN.

[0013] In one embodiment, the channel layer is made of GaN.

[0014] In one embodiment, the material of the buffer layer includes at least one or a combination of three materials selected from GaN, AlN, and AlGaN.

[0015] In one embodiment, the source electrode is in direct contact with the barrier layer.

[0016] In one embodiment, the drain electrode is in direct contact with the barrier layer.

[0017] In one embodiment, the source electrode is made of a metal and / or an alloy.

[0018] In one embodiment, the material of the drain electrode includes metals and / or alloys.

[0019] In one embodiment, the material of the first gate electrode includes metals and / or alloys.

[0020] In one embodiment, the material of the second gate electrode includes metals and / or alloys.

[0021] A method for manufacturing a GaN-based high electron mobility transistor integrated device structure includes: forming a first gate structure on a substrate; the substrate including a channel layer and a barrier layer on the channel layer, the first gate structure being disposed on the barrier layer, the first gate structure being made of p-type doped GaN; forming a dielectric layer on the barrier layer; forming a source electrode, a drain electrode, a first gate electrode, and a second gate electrode; the first gate electrode being disposed on the first gate structure; the second gate electrode being disposed on the dielectric layer; the source electrode being disposed on the barrier layer and located on the side of the first gate structure away from the second gate electrode; the drain electrode being disposed on the barrier layer and located on the side of the second gate electrode away from the first gate structure. One side; wherein, the GaN-based high electron mobility transistor integrated device structure includes a P-type gate HEMT and a MISFET, the first gate electrode serves as the gate of the P-type gate HEMT, the second gate electrode serves as the gate of the MISFET, the source electrode serves as the source electrode of the P-type gate HEMT, the drain electrode serves as the drain electrode of the MISFET, the portion of the barrier layer located between the first gate structure and the second gate electrode serves as the drain region of the P-type gate HEMT and the source region of the MISFET; the MISFET is a first voltage device, the P-type gate HEMT is a second voltage device, and the breakdown voltage of the first voltage device is greater than the breakdown voltage of the second voltage device.

[0022] The aforementioned GaN-based high electron mobility transistor integrated device structure and its fabrication method integrate a P-type gate HEMT (high electron mobility transistor) and a MISFET (insulated gate field-effect transistor). The MISFET acts as a high-voltage device, while the P-type gate HEMT acts as a low-voltage device. When the integrated device structure is subjected to high voltage, the P-type gate HEMT and MISFET divide the voltage, allowing the MISFET to withstand the high voltage. The electric field peak is located at the edge of the second gate electrode near the drain electrode, rather than at the edge of the P-GaN near the drain electrode in a traditional P-type gate HEMT. Because the device has an MIS (metal-dielectric-semiconductor) structure at the second gate electrode, it can withstand a larger electric field peak than the edge of the first gate structure near the drain electrode, thus resulting in higher device reliability. Attached Figure Description

[0023] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0024] Figure 1 This is a schematic cross-sectional view of a GaN-based high electron mobility transistor integrated device structure in one embodiment;

[0025] Figure 2 yes Figure 1 The circuit schematic of the GaN-based high electron mobility transistor integrated device structure is shown.

[0026] Figure 3 This is a cross-sectional schematic diagram of the GaN-based high electron mobility transistor integrated device structure in another embodiment;

[0027] Figure 4 yes Figure 3 The circuit schematic of the GaN-based high electron mobility transistor integrated device structure is shown.

[0028] Figure 5 This is a flowchart of a method for manufacturing a GaN-based high electron mobility transistor integrated device structure in one embodiment;

[0029] Figure 6a and Figure 6b This is one embodiment of the method used. Figure 5 A cross-sectional schematic diagram of the device during the fabrication of the GaN-based high electron mobility transistor integrated device structure using the method described above. Detailed Implementation

[0030] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0033] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0035] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0036] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0037] Traditional P-gate GaN HEMT devices primarily employ two gate electrode schemes: Schottky contact gate electrode and ohmic contact gate electrode. The ohmic contact gate electrode scheme is a current-driven device, which improves gate reliability, but current-driven operation is complex, frequency-limited, and consumes more power. Currently, most manufacturers use the Schottky contact gate electrode scheme. However, due to limitations in P-GaN material growth quality and Mg doping activation efficiency, the reliability of P-GaN Schottky contact gate electrode devices has become a critical issue.

[0038] In traditional GaN-based devices, the field plate is the most common structure for adjusting the electric field. The electric field strength and peak value between the gate and drain can be controlled by adjusting the length of the gate and source field plates and the thickness of the dielectric layer under the field plate.

[0039] This application provides a GaN-based high electron mobility transistor integrated device structure, which includes a P-gate HEMT and a MISFET, wherein the P-gate HEMT serves as a low-voltage device and the MISFET serves as a high-voltage device. Figure 1 This is a schematic cross-sectional view of a GaN-based high electron mobility transistor integrated device structure in one embodiment. Figure 2 yes Figure 1 The circuit schematic shown is of a GaN-based high electron mobility transistor integrated device structure. Figure 1In the illustrated embodiment, the GaN-based high electron mobility transistor integrated device structure includes a channel layer 120, a barrier layer 130, a first gate structure 152, a first gate electrode 154, a second gate electrode 164, a dielectric layer 140, a source electrode 172, and a drain electrode 174.

[0040] exist Figure 1 In the illustrated embodiment, a barrier layer 130 is disposed on a channel layer 120. A first gate structure 152 is disposed on the barrier layer 130, and the material of the first gate structure 152 is p-type doped GaN. A first gate electrode 154 is disposed on the first gate structure 152. A dielectric layer 140 is disposed on the barrier layer 130. A second gate electrode 164 is disposed on the dielectric layer 140, and the dielectric layer 140 serves as the gate dielectric layer of the second gate electrode 164. A source electrode 172 is disposed on the barrier layer 130 and is located on the side of the first gate structure 152 away from the second gate electrode 164. A drain electrode 174 is disposed on the barrier layer 130 and is located on the side of the second gate electrode 164 away from the first gate structure 152. That is, the first gate structure 152 and the second gate electrode 164 are disposed between the source electrode 172 and the drain electrode 174.

[0041] The aforementioned GaN-based high electron mobility transistor integrated device structure integrates a P-type gate HEMT and a MISFET. The MISFET acts as a high-voltage device, while the P-type gate HEMT acts as a low-voltage device. When the integrated device structure is subjected to high voltage, the P-type gate HEMT and MISFET divide the voltage. Based on the capacitive voltage division design of the P-type gate HEMT and MISFET, the MISFET can withstand high voltage, with the electric field peak at the edge of the second gate electrode near the drain electrode, rather than at the edge of the P-GaN near the drain electrode in a traditional HEMT. Because the device has a MIS (metal-dielectric-semiconductor) structure at the second gate electrode 164, it can withstand a larger electric field peak than the edge of the first gate structure 152 near the drain electrode, thus resulting in higher device reliability.

[0042] Please refer to the following: Figure 2 ,exist Figure 1 and Figure 2 In the illustrated embodiment, the first gate electrode 154 serves as the gate G of a P-type gate HEMT, the second gate electrode 164 serves as the gate of a MISFET, the source electrode 172 serves as the source electrode S of a P-type gate HEMT, the drain electrode 174 serves as the drain electrode D of a MISFET, the portion of the barrier layer 130 located between the first gate structure 152 and the second gate electrode 164 serves as the drain region of the P-type gate HEMT and the source region of the MISFET, and the second gate electrode 164 is electrically connected to the source electrode 172.

[0043] exist Figure 1 In the illustrated embodiment, the absolute value of the threshold voltage of the MISFET is smaller than the gate voltage swing of the P-type gate HEMT.

[0044] Figure 3 This is a cross-sectional schematic diagram of a GaN-based high electron mobility transistor integrated device structure in another embodiment. Figure 4 yes Figure 3 The circuit schematic shown is of a GaN-based high electron mobility transistor integrated device structure. Figure 3 In the illustrated embodiment, the GaN-based high electron mobility transistor integrated device structure includes a channel layer 120, a barrier layer 130, a first gate structure 152, a first gate electrode 154, a second gate electrode 164, a dielectric layer 140, a source electrode 172, and a drain electrode 174.

[0045] exist Figure 1 In the illustrated embodiment, a barrier layer 130 is disposed on a channel layer 120. A first gate structure 152 is disposed on the barrier layer 130, and the material of the first gate structure 152 is p-type doped GaN. A first gate electrode 154 is disposed on the first gate structure 152. A dielectric layer 140 is disposed on the barrier layer 130. A second gate electrode 164 is disposed on the dielectric layer 140, and the dielectric layer 140 serves as the gate dielectric layer of the second gate electrode 164. A source electrode 172 is disposed on the barrier layer 130 and is located on the side of the first gate structure 152 away from the second gate electrode 164. A drain electrode 174 is disposed on the barrier layer 130 and is located on the side of the second gate electrode 164 away from the first gate structure 152. That is, the first gate structure 152 and the second gate electrode 164 are disposed between the source electrode 172 and the drain electrode 174.

[0046] Please refer to the following: Figure 4 ,exist Figure 3 and Figure 4 In the illustrated embodiment, the second gate electrode 164 is electrically connected to the first gate electrode 154. The first gate electrode 154 serves as the gate G of the P-type gate HEMT and is electrically connected to the gate (second gate electrode 164) of the MISFET. The source electrode 172 serves as the source electrode S of the P-type gate HEMT, and the drain electrode 174 serves as the drain electrode D of the MISFET. The portion of the barrier layer 130 located between the first gate structure 152 and the second gate electrode 164 serves as the drain region of the P-type gate HEMT and the source region of the MISFET.

[0047] In one embodiment of this application, the first gate structure 152 is in direct contact with the barrier layer 130.

[0048] In one embodiment of this application, the source electrode 172 is in direct contact with the barrier layer 130.

[0049] In one embodiment of this application, the drain electrode 174 is in direct contact with the barrier layer 130.

[0050] Furthermore, the dielectric layer 140 is not provided at the positions of the first gate structure 152, the source electrode 172, and the drain electrode 174.

[0051] In one embodiment of this application, the first gate electrode 154 is in direct contact with the first gate structure 152.

[0052] In one embodiment of this application, the first gate electrode 154 forms a Schottky contact with the first gate structure 152.

[0053] In one embodiment of this application, the GaN-based high electron mobility transistor integrated device structure further includes a buffer layer 110. A channel layer 120 and a barrier layer 130 are formed on the buffer layer 110. It is understood that other structures of HEMT devices known in the art, such as a substrate, may also be provided under the buffer layer 110.

[0054] In one embodiment of this application, the buffer layer 110 is a GaN buffer. In other embodiments, the material of the buffer layer 110 is GaN, AlN, AlGaN, or a combination of the three materials.

[0055] In one embodiment of this application, the channel layer 120 is a GaN layer.

[0056] In one embodiment of this application, the barrier layer 130 is an AlGaN layer.

[0057] In one embodiment of this application, the above-described GaN-based high electron mobility transistor integrated device structure can be combined with a field plate structure to better regulate the high voltage electric field.

[0058] In one embodiment, the source electrode 172, drain electrode 174, first gate electrode 154, and second gate electrode 164 are made of metal and / or alloy.

[0059] This application provides a method for manufacturing a GaN-based high electron mobility transistor integrated device structure. Figure 5 This is a flowchart of a method for manufacturing a GaN-based high electron mobility transistor integrated device structure, including the following steps:

[0060] S510 forms a first gate structure on the substrate.

[0061] The substrate includes a channel layer 120 and a barrier layer 130 on the channel layer 120. A first gate structure 152 is disposed on the barrier layer 130, and the material of the first gate structure 152 is P-type doped GaN.

[0062] In one embodiment of this application, the first gate structure 152 may be formed by photolithography and etching of the P-GaN layer 150 on the barrier layer 130, see [link to relevant documentation]. Figure 6a and Figure 6b P-type doped GaN is in direct contact with the barrier layer 130.

[0063] S520 forms a dielectric layer on the barrier layer.

[0064] In one embodiment of this application, a dielectric layer 140 can be formed on the barrier layer 130 by a deposition process, and the dielectric layer 140 is subsequently used as the gate dielectric layer of the MISFET.

[0065] S530 forms a source electrode, a drain electrode, a first gate electrode, and a second gate electrode.

[0066] In one embodiment of this application, the source electrode 172, drain electrode 174, first gate electrode 154, and second gate electrode 164 can be formed by metal sputtering. Since the source electrode 172, drain electrode 174, first gate electrode 154, and second gate electrode 164 all need to be in direct contact with their respective underlying device structures (semiconductor structures), before forming the source electrode 172, drain electrode 174, first gate electrode 154, and second gate electrode 164, the dielectric layer 140 at the locations where the source electrode 172, drain electrode 174, first gate electrode 154, and second gate electrode 164 will be formed needs to be removed by a patterning process. Specifically, patterning can be performed using photolithography and etching processes.

[0067] The structure of the device after step S530 can be found in [reference needed]. Figure 1 and Figure 3 The GaN-based high electron mobility transistor integrated device structure includes a P-gate HEMT and a MISFET. The P-gate HEMT serves as a low-voltage device, and the MISFET serves as a high-voltage device. The first gate electrode 154 serves as the gate G of the P-gate HEMT, the second gate electrode 164 serves as the gate of the MISFET, the source electrode 172 serves as the source electrode S of the P-gate HEMT, and the drain electrode 174 serves as the drain electrode D of the MISFET. The portion of the barrier layer 130 located between the first gate structure 152 and the second gate electrode 164 serves as the drain region of the P-gate HEMT and the source region of the MISFET.

[0068] The fabrication method of the aforementioned GaN-based high electron mobility transistor integrated device structure integrates a P-type gate HEMT (high electron mobility transistor) and a MISFET (insulated gate field-effect transistor). The MISFET acts as a high-voltage device, and the P-type gate HEMT acts as a low-voltage device. When the integrated device structure is subjected to high voltage, the P-type gate HEMT and the MISFET divide the voltage, enabling the MISFET to withstand the high voltage. The electric field peak is located at the edge of the second gate electrode near the drain electrode, rather than at the edge of the P-GaN near the drain electrode in a traditional P-type gate HEMT. Because the device has an MIS (metal-dielectric-semiconductor) structure at the second gate electrode, it can withstand a larger electric field peak than the edge of the first gate structure near the drain electrode, thus resulting in higher device reliability.

[0069] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0070] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0071] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0072] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A GaN-based high electron mobility transistor integrated device structure, characterized by, The application relates to a GaN-based high electron mobility transistor integrated device structure, comprising: a channel layer; a barrier layer arranged on the channel layer; a first gate structure arranged on the barrier layer, wherein the material of the first gate structure comprises P-doped GaN; a first gate electrode arranged on the first gate structure; a dielectric layer arranged on the barrier layer, wherein the dielectric layer is not arranged between the top of the first gate structure and the bottom of the first gate electrode; a second gate electrode arranged on the dielectric layer; a source electrode arranged on the barrier layer and located on the side of the first gate structure away from the second gate electrode, wherein the bottom of the source electrode is in direct contact with the barrier layer; a drain electrode arranged on the barrier layer and located on the side of the second gate electrode away from the first gate structure, wherein the bottom of the drain electrode is in direct contact with the barrier layer; wherein the GaN-based high electron mobility transistor integrated device structure comprises a P-gate HEMT and a MISFET, the first gate electrode serves as the gate of the P-gate HEMT, the second gate electrode serves as the gate of the MISFET, the source electrode serves as the source electrode of the P-gate HEMT, the drain electrode serves as the drain electrode of the MISFET, and the part of the barrier layer between the first gate structure and the second gate electrode serves as the drain region of the P-gate HEMT and the source region of the MISFET; the MISFET is a first voltage device, the P-gate HEMT is a second voltage device, and the breakdown voltage of the first voltage device is greater than the breakdown voltage of the second voltage device.

2. The GaN-based high electron mobility transistor integrated device structure of claim 1, wherein, The second gate electrode is electrically connected with the source electrode.

3. The GaN-based high electron mobility transistor integrated device structure of claim 1, wherein, The second gate electrode is electrically connected with the first gate electrode.

4. The GaN-based high electron mobility transistor integrated device structure of claim 1, wherein, The P-doped GaN is in direct contact with the barrier layer.

5. The GaN-based high electron mobility transistor integrated device structure of claim 1, wherein, The first gate electrode forms a Schottky contact with the first gate structure.

6. The GaN-based high electron mobility transistor integrated device structure of claim 2, wherein, The absolute value of the threshold voltage of the MISFET is less than the gate voltage swing of the P-gate HEMT.

7. The GaN-based high electron mobility transistor integrated device structure of claim 1, wherein, A buffer layer is further arranged, and the channel layer is arranged on the buffer layer.

8. The GaN-based high electron mobility transistor integrated device structure of claim 1, wherein, The material of the barrier layer comprises AlGaN.

9. The GaN-based high electron mobility transistor integrated device structure of claim 7, wherein, The material of the channel layer comprises GaN, and the material of the buffer layer comprises GaN, AlN, AlGaN and a combination of the three materials.

10. A manufacturing method of a GaN-based high electron mobility transistor integrated device structure, comprising: forming a first gate structure on a substrate; the substrate comprises a channel layer and a barrier layer on the channel layer, the first gate structure is arranged on the barrier layer, and the material of the first gate structure is P-doped GaN; forming a dielectric layer on the barrier layer; Forming a source electrode, a drain electrode, a first gate electrode and a second gate electrode; the first gate electrode is arranged on the first gate structure, and the top of the first gate structure and the bottom of the first gate electrode are not provided with the dielectric layer; the second gate electrode is arranged on the dielectric layer; the source electrode is arranged on the barrier layer and is located on the side of the first gate structure away from the second gate electrode, and the bottom of the source electrode directly contacts the barrier layer; the drain electrode is arranged on the barrier layer and is located on the side of the second gate electrode away from the first gate structure, and the bottom of the drain electrode directly contacts the barrier layer; Wherein, the GaN-based high electron mobility transistor integrated device structure includes a P-type gate HEMT and a MISFET, the first gate electrode serves as the gate of the P-type gate HEMT, the second gate electrode serves as the gate of the MISFET, the source electrode serves as the source electrode of the P-type gate HEMT, the drain electrode serves as the drain electrode of the MISFET, and the part of the barrier layer between the first gate structure and the second gate electrode serves as the drain region of the P-type gate HEMT and the source region of the MISFET; the MISFET is a first voltage device, the P-type gate HEMT is a second voltage device, and the breakdown voltage of the first voltage device is greater than the breakdown voltage of the second voltage device.

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