Monolithic integrated multi-channel fin-shaped gate HEMT and groove SBD and preparation method thereof

Abstract

The invention provides a monolithic integration multi-channel fin-shaped gate HEMT and a groove SBD and a preparation method thereof. The monolithic integration multi-channel fin-shaped gate HEMT comprises a substrate layer, a multi-channel fin-shaped gate HEMT and a groove anode SBD, the multi-channel fin-shaped gate HEMT comprises a first buffer layer, a first barrier layer, a first channel layer, a p-GaN layer, a source electrode, a drain electrode, a dielectric layer, a gate electrode and a plurality of grooves, wherein the first barrier layer and the first channel layer are stacked repeatedly. The plurality of grooves are arranged at intervals along the parallel direction from the source electrode to the drain electrode, are arranged in the middle region of the p-GaN layer at intervals, and sequentially penetrate through the p-GaN layer, the first channel layer and the first barrier layer to enter the first buffer layer; the trench anode SBD includes a second buffer layer, a second barrier layer and a second channel layer repeatedly stacked, a cathode, an anode, and an anode trench. Therefore, reverse conduction loss can be remarkably reduced, parasitic parameters are reduced, the size of the power conversion unit is reduced, the overall cost of a product is reduced, and the stability and reliability of a system are improved.

Description

Technical Field

[0001] This invention relates to the field of power electronic systems technology, and in particular to a monolithically integrated multi-channel fin-gate high electron mobility transistor (HEMT) and a grooved Schottky barrier diode (SBD) and their fabrication methods. Background Technology

[0002] Power electronic systems such as synchronous buck or boost converters have seen significant improvements through the adoption of gallium nitride (GaN)-based power devices. However, these devices inevitably enter a reverse conduction state during operation. For GaN-based HEMTs, the reverse conduction voltage drop can be much higher than that of silicon (Si)-based or silicon carbide (SiC)-based power devices, resulting in additional power losses. Therefore, improving the reverse conduction capability of GaN high electron mobility transistors is crucial for further reducing power losses in GaN-based power electronic systems.

[0003] Existing technologies for reducing power loss in gallium nitride-based power electronic systems include using a Schottky source and connecting a parallel SBD as a freewheeling diode. However, the reverse conduction voltage of existing technologies is relatively high, resulting in significant reverse conduction losses. When connecting a parallel SBD as a freewheeling diode, the devices are connected through external circuitry, which introduces large parasitic inductance and resistance, leading to high parasitic parameters. Each of the two discrete chips needs to be packaged separately, occupying considerable space. Combined with the connecting lines and solder joints on the circuit board, this results in a large and costly power conversion unit. Furthermore, the connection points (such as solder joints) between discrete devices in existing technologies are susceptible to loosening and oxidation due to long-term use caused by temperature changes and vibrations, leading to poor electrical connections, circuit failures, signal transmission delays and interference between devices, affecting the collaborative performance of discrete devices and reducing system stability and reliability. Summary of the Invention

[0004] The purpose of this invention is to provide a monolithic integrated multi-channel fin gate HEMT and grooved SBD and their fabrication method, which solves the problems of high reverse conduction loss, large parasitic parameters, large size and high cost of power conversion unit, and reduced system stability and reliability in the prior art.

[0005] To address the aforementioned technical problems, the embodiments of the present invention provide the following technical solutions: The first aspect of the present invention provides a monolithic integrated multi-channel fin gate HEMT and a grooved anode SBD, comprising: a substrate layer, a multi-channel fin gate HEMT and a grooved anode SBD respectively located on two side edge regions of the substrate layer; The multi-channel fin gate HEMT includes a first buffer layer, a first barrier layer, and a first channel layer sequentially disposed from bottom to top on a substrate, with the first barrier layer and the first channel layer being repeatedly stacked; a p-GaN layer located in the middle region of the first barrier layer; a source electrode located on the edge region of the first barrier layer away from the recessed anode SBD; a drain electrode located on the edge region of the first barrier layer near the recessed anode SBD, with neither the source nor the drain electrode in contact with the p-GaN layer; multiple recesses spaced apart along a parallel direction from the source to the drain electrode, and spaced apart within the middle region of the p-GaN layer, the multiple recesses sequentially penetrating the p-GaN layer, the first channel layer, and the first barrier layer into the first buffer layer; a dielectric layer located on the sidewalls and bottom of the multiple recesses, and on the p-GaN layer; and a gate electrode located on the dielectric layer. The grooved anode SBD includes a second buffer layer, a second barrier layer, and a second channel layer disposed sequentially from bottom to top on a substrate layer, with the second barrier layer and the second channel layer being repeatedly stacked; a cathode is formed on the edge region of the second barrier layer near the drain; an anode groove extends sequentially through the second barrier layer and the second channel layer into the second buffer layer; and an anode is formed on the sidewalls and bottom of the anode groove, as well as on a portion of the second barrier layer.

[0006] A second aspect of the present invention provides a method for fabricating a monolithic integrated multi-channel fin gate HEMT and a grooved SBD, comprising: Clean the epitaxial wafer, which includes a substrate layer, a buffer layer, a channel layer, a barrier layer and a p-GaN layer arranged sequentially from bottom to top, with the barrier layer and the channel layer being stacked repeatedly; Using a slow etching process, anode grooves are etched in the p-GaN layer near the two edge regions, and multiple grooves are arranged at intervals in the parallel direction along the transverse direction of the epitaxial wafer. The multiple grooves pass through the p-GaN layer, barrier layer and channel layer in sequence, and into the channel layer. The anode grooves pass through the p-GaN layer, barrier layer and channel layer in sequence, and into the buffer layer. The p-GaN layer in the remaining area except the target area is etched away. The target area is the area between multiple grooves and the target sidewalls close to the multiple grooves. The target sidewalls are the sidewalls in the vertical direction along the transverse direction of the epitaxial wafer. Device isolation is fabricated in the middle region of the barrier layer. The device isolation sequentially penetrates the barrier layer, the channel layer and the buffer layer to the upper surface of the substrate layer to isolate a first structure with multiple grooves and a second structure with an anode groove. Atomic layer deposition technology was used to grow dielectric layers on the sidewalls and bottom of multiple grooves and on the p-GaN layer; Source and drain electrodes are fabricated on the two edge regions of the barrier layer of the first structure, respectively, and the drain electrode is isolated from the device. A cathode is fabricated on one edge region of the barrier layer of the second structure, and the cathode is isolated from the device. Using an electron beam evaporation apparatus, a first metal is deposited on the dielectric layer to form a Schottky contact, thereby fabricating a gate and obtaining a multi-channel fin gate HEMT; A second metal is sputtered on the sidewalls and bottom of the anode groove and on the barrier layer near the sidewalls of the anode groove using a magnetron sputtering equipment. The second metal is then thermally annealed to form a Schottky contact to prepare the anode, thus obtaining the grooved anode SBD. The source and anode, and the drain and cathode are interconnected by metal.

[0007] Compared to existing technologies, the present invention provides a monolithically integrated multi-channel fin gate HEMT and a recessed anode SBD, and a method for fabricating them. The monolithically integrated multi-channel fin gate HEMT and recessed anode SBD include: a substrate layer, a multi-channel fin gate HEMT and a recessed anode SBD located on opposite edge regions of the substrate layer; the multi-channel fin gate HEMT includes a first buffer layer, a first barrier layer and a first channel layer sequentially disposed from bottom to top on the substrate layer, the first barrier layer and the first channel layer being repeatedly stacked; a p-GaN layer located in the middle region of the first barrier layer; a source electrode located on the edge region of the first barrier layer away from the recessed anode SBD; and a drain electrode located on the edge region of the first barrier layer near the recessed anode SBD, wherein neither the source nor the drain electrode is in contact with the p-GaN layer. Multiple grooves are spaced apart along a parallel direction from the source to the drain, and are spaced apart in the middle region of the p-GaN layer. The multiple grooves sequentially penetrate the p-GaN layer, the first channel layer, and the first barrier layer into the first buffer layer. A dielectric layer is located on the sidewalls and bottom of the multiple grooves, and on the p-GaN layer. A gate is located on the dielectric layer. The grooved anode SBD includes a second buffer layer, a second barrier layer, and a second channel layer sequentially disposed from bottom to top on the substrate layer, with the second barrier layer and the second channel layer being repeatedly stacked. A cathode is formed on the edge region of the second barrier layer near the drain. An anode groove sequentially penetrates the second barrier layer and the second channel layer into the second buffer layer. An anode is formed on the sidewalls and bottom of the anode groove, and on a portion of the second barrier layer. In this way, by monolithically integrating the multi-channel fin-gate HEMT and Si SBD, the low turn-on voltage of Si SBD significantly reduces reverse conduction losses; by monolithically integrating the multi-channel fin-gate HEMT and Si SBD, the parasitic inductance and resistance of external connections between devices are reduced; by using monolithic integration technology, the number of packages and external connection lines are reduced, the size of the power conversion unit is reduced, the miniaturization requirements of electronic devices are met, and the costs of packaging, testing, and assembly are reduced, thus lowering the overall product cost; by reducing the number of connection points between devices, the risk of failure due to connection point problems is avoided, the internal chip design is optimized, and the multi-channel fin-gate HEMT and Si SBD work together better, reducing signal transmission delay and interference, improving system stability and reliability, and adapting to complex working environments. Attached Figure Description

[0008] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, with the same or corresponding reference numerals denoteing the same or corresponding parts, wherein: Figure 1 A schematic diagram of a monolithic integrated multichannel fin gate HEMT and a grooved SBD is shown. Figure 2 A schematic flowchart illustrating the fabrication method of monolithic integrated multichannel fin gate HEMT and grooved SBD is shown. Figure 3 A schematic diagram of an epitaxial wafer is shown. Figure 4 A schematic flowchart illustrating the fabrication process of etching multiple grooves is shown. Figure 5 A schematic flowchart illustrating the fabrication process for creating device isolation is shown. Figure 6 A schematic flowchart illustrating the fabrication process of the anode is shown. Figure 7 A schematic flowchart illustrating the fabrication process of metal interconnects is shown. Figure 8 A schematic diagram of a buck circuit with parallel grooved anode SBD and a buck circuit without parallel grooved anode SBD is shown. Figure 9 Simulation waveforms of a buck circuit with parallel grooved anode SBDs and without parallel grooved anode SBDs are schematically shown.

[0009] Explanation of reference numerals in the attached figures 1. Substrate layer; 2. Multi-channel fin gate HEMT; 21. First buffer layer; 22. First barrier layer; 23. First channel layer; 24. p-GaN layer; 25. Source; 26. Drain; 27. Multiple grooves; 28. Dielectric layer; 29. ​​Gate; 3. Groove anode (SBD); 31. Second buffer layer; 32. Second barrier layer; 33. Second channel layer; 34. Cathode; 35. Anode groove; 36. Anode. Detailed Implementation

[0010] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0011] It should be noted that, unless otherwise stated, the technical or scientific terms used in this invention should have the ordinary meaning as understood by one of ordinary skill in the art.

[0012] The methods described in the embodiments of the present invention will be explained in detail below.

[0013] Figure 1 The schematic diagram illustrates the structure of a monolithic integrated multi-channel fin gate HEMT and a grooved SBD, which includes: Substrate 1, multi-channel fin gate HEMT2 and grooved anode SBD3 located on the two side edge regions of substrate 1 respectively; The multi-channel fin gate HEMT2 includes a first buffer layer 21, a first barrier layer 22, and a first channel layer 23 sequentially disposed from bottom to top on a substrate layer 1, wherein the first barrier layer 22 and the first channel layer 23 are repeatedly stacked; a p-GaN layer 24 is located in the middle region of the first barrier layer 22; a source 25 is located on the edge region of the first barrier layer 22 away from the recessed anode SBD3; and a drain 26 is located on the edge region of the first barrier layer 22 close to the recessed anode SBD3, and the source 25... Both source 25 and drain 26 are not in contact with p-GaN layer 24; multiple grooves 27 are spaced apart along the parallel direction from source 25 to drain 26, and are spaced apart in the middle region of p-GaN layer 24. The multiple grooves 27 sequentially penetrate p-GaN layer 24, first channel layer 23 and first barrier layer 22, and into first buffer layer 21; dielectric layer 28 is located on the sidewalls and bottom of multiple grooves 27, and on p-GaN layer 24; gate 29 is located on dielectric layer 28; The recessed anode SBD3 includes a second buffer layer 31, a second barrier layer 32, and a second channel layer 33 sequentially disposed from bottom to top on the substrate layer 1, with the second barrier layer 32 and the second channel layer 33 being repeatedly stacked; a cathode 34 is formed on the edge region of the second barrier layer 32 near the drain 26; an anode recess 35 sequentially penetrates the second barrier layer 32 and the second channel layer 33 into the second buffer layer 31; and an anode 36 is formed on the sidewalls and bottom of the anode recess 35, as well as on a portion of the second barrier layer 32.

[0014] Specifically, along the lateral direction of the device, from one side to the other, there are a source 25, a gate 29, and a drain 26, and along the lateral direction of the device, from one side to the other, there are a cathode 34 and an anode 36. The grooved anode SBD3 can be a grooved anode GaN SBD or a grooved anode Si SBD.

[0015] This invention integrates a multi-channel fin gate HEMT2 with a grooved anode GaN SBD. In order to reduce the reverse conduction loss of p-GaN HEMT devices, while increasing integration density, reducing size, reducing parasitic parameters, and eliminating external packaging and additional inductance in traditional solutions, the multi-channel fin gate HEMT2 and the grooved anode SBD3 are fabricated on the same substrate layer 1.

[0016] The HEMT2 employs a multi-channel fin-gate structure, which effectively controls the switching of multiple channels. Simultaneously, the fin-gate enables enhancement-mode operation and provides strong gate control. A multi-channel structure, consisting of repeated stacked layers of the first barrier layer 22 and the first channel layer 23, is introduced to form multiple conductive channels using an AlGaN / GaN stack, reducing the device's forward on-resistance and improving its forward current capability. An anode recess 35 structure enhances the breakdown voltage and current handling capacity, effectively reducing the breakdown voltage while maintaining good reliability in high-voltage applications. The anode 36 uses a low-work-function metal to reduce the on-state voltage.

[0017] As an optional embodiment of the present invention, the source 25 and the anode 36, and the drain 26 and the cathode 34 are all interconnected by metal.

[0018] As an optional embodiment of the present invention, the source electrode 25 is made of any one of Ni, Pt, Au, and Ti metals, or a Ni / Pt / Au / Ti multilayer metal; the drain electrode 26 is made of any one of Ni, Pt, Au, and Ti metals, or a Ni / Pt / Au / Ti multilayer metal; and the gate electrode 29 is made of any one or a combination of Ti, Al, Ni, and Au metals.

[0019] As an optional embodiment of the present invention, the anode 36 is made of Ni or Ni / Au multilayer metal; the cathode 34 is made of Al or any one or a combination of Ti / Al / Ni / Au multilayer metal.

[0020] As an optional embodiment of the present invention, the first barrier layer 22 and the first channel layer 23 are stacked repeatedly 3-5 times, and the second barrier layer 32 and the second channel layer 33 are stacked repeatedly 3-5 times.

[0021] As an optional embodiment of the present invention, the materials of the first barrier layer 22 and the second barrier layer 32 are both AlN or AlGaN, and the materials of the first channel layer 23 and the second channel layer 33 are both GaN, AlN or AlGaN; the thickness of the first barrier layer 22 and the second barrier layer 32 is 10-50nm, and the thickness of the first channel layer 23 and the second channel layer 33 is 50nm-300nm.

[0022] The thickness of the p-GaN layer 24 can be 70 nm.

[0023] As an optional embodiment of the present invention, the anode 36 forms a Schottky contact with the second barrier layer 32.

[0024] As an optional embodiment of the present invention, the substrate layer 1 is made of GaN, SiC, Si or sapphire, and the thickness of the substrate layer 1 is 100nm-1000μm; the buffer layer is made of GaN, AlN or AlGaN, and the thickness of the buffer layer is 1μm-5μm; the dielectric layer 28 is made of Si3N4 or Al2O3, and the thickness of the dielectric layer 28 is 10-50nm.

[0025] Specifically, in bridge topologies (such as Buck and LLC), reverse conduction of GaN HEMTs typically occurs during the dead time, i.e., the gap between when one device is turned off and the next is not turned on. At this time, the reverse voltage has not yet fully decreased, and the reverse current has already begun to rise. The energy dissipation during this period is an important component of reverse conduction losses.

[0026] Generally, there is a voltage drop of about 2V during reverse conduction, which results in large reverse conduction losses. This invention uses a Si SBD as the reverse conduction path. Since the Si SBD has a low on-resistance, the current flows preferentially through the SBD. Because the turn-on voltage of the Si SBD is only 0.7V, the power loss during reverse conduction can be greatly reduced.

[0027] Based on the above Figure 1As can be seen from the implementation, the monolithic integrated multi-channel fin gate HEMT2 and recessed anode SBD of this embodiment include: a substrate layer 1, a multi-channel fin gate HEMT2 and a recessed anode SBD3 respectively located on the two side edge regions of the substrate layer 1; the multi-channel fin gate HEMT2 includes a first buffer layer 21, a first barrier layer 22 and a first channel layer 23 sequentially disposed from bottom to top on the substrate layer 1, the first barrier layer 22 and the first channel layer 23 being repeatedly stacked; a p-GaN layer 24 located in the middle region of the first barrier layer 22; a source 25 located on the edge region of the first barrier layer 22 away from the recessed anode SBD3; a drain 26 located on the edge region of the first barrier layer 22 close to the recessed anode SBD3, and neither the source 25 nor the drain 26 is in contact with the p-GaN layer 24; and a plurality of recesses 27 along the parallel direction from the source 25 to the drain 26. Multiple grooves 27 are arranged at intervals in the middle region of the p-GaN layer 24, and sequentially penetrate the p-GaN layer 24, the first channel layer 23, and the first barrier layer 22 into the first buffer layer 21; a dielectric layer 28 is located on the sidewalls and bottom of the multiple grooves 27 and on the p-GaN layer 24; a gate 29 is located on the dielectric layer 28; the groove anode SBD3 includes a second buffer layer 31, a second barrier layer 32, and a second channel layer 33 sequentially disposed from bottom to top on the substrate layer 1, with the second barrier layer 32 and the second channel layer 33 being repeatedly stacked; a cathode 34 is formed on the edge region of the second barrier layer 32 near the drain 26; an anode groove 35 sequentially penetrates the second barrier layer 32 and the second channel layer 33 into the second buffer layer 31; and an anode 36 is formed on the sidewalls and bottom of the anode groove 35 and on a portion of the second barrier layer 32. In this way, by monolithically integrating the multi-channel fin gate HEMT2 and Si SBD, the low turn-on voltage of Si SBD significantly reduces reverse conduction losses; by monolithically integrating the multi-channel fin gate HEMT2 and Si SBD, the parasitic inductance and resistance of external connections between devices are reduced; by using monolithic integration technology, the number of packages and external connection lines are reduced, the size of the power conversion unit is reduced, the miniaturization requirements of electronic devices are met, and the costs of packaging, testing, and assembly are reduced, thus lowering the overall product cost; by reducing the number of connection points between devices, the risk of failure due to connection point problems is avoided, the internal chip design is optimized, and the multi-channel fin gate HEMT2 and Si SBD work together better, reducing signal transmission delay and interference, improving system stability and reliability, and adapting to complex working environments.

[0028] Figure 2 The fabrication method of the monolithic integrated multi-channel fin gate HEMT and the grooved SBD in an embodiment of the present invention is illustrated schematically. See [link to documentation]. Figure 2 As shown, the fabrication method of this monolithic integrated multi-channel fin gate HEMT and grooved SBD may include: S201. Clean the epitaxial wafer.

[0029] Specifically, before step S201, an epitaxial wafer needs to be provided.

[0030] in, Figure 3 A schematic diagram of an epitaxial wafer is shown below. (See attached diagram) Figure 3 As shown, the epitaxial wafer includes a substrate layer 1, a buffer layer, a channel layer, a barrier layer and a p-GaN layer 24 arranged sequentially from bottom to top, with the barrier layer and the channel layer being stacked repeatedly.

[0031] The substrate layer 1 can be made of Si, GaN, sapphire, or SiC, with a thickness of 100 nm to 1000 μm. The buffer layer can be made of GaN, AlN, or AlGaN, with a thickness of 1 μm to 5 μm. The channel layer can be made of GaN, AlN, or AlGaN, with a thickness of 50 nm to 300 nm. The barrier layer can be made of AlGaN or AlN, with a thickness of 10 nm to 50 nm. The P-GaN layer 24 has a thickness of 70 nm.

[0032] Cleaning the epitaxial wafer involves removing impurities, dust, oxides, organic matter, and so on. First, the epitaxial wafer is ultrasonically cleaned in acetone for 2 minutes, then heated in a 60°C stripping solution water bath for about 10 minutes, followed by cleaning in acetone for 3 minutes, then sequentially cleaning in ethanol and ultrapure water for 2 minutes each, and finally dried with nitrogen (N2).

[0033] S202. Using a slow etching process, anode grooves 35 are etched in the p-GaN layer 24 near the two side edges, and multiple grooves 27 are arranged at intervals in the parallel direction along the transverse direction of the epitaxial wafer. The multiple grooves 27 pass through the p-GaN layer 24, the barrier layer and the channel layer in sequence, and into the channel layer. The anode grooves 35 pass through the p-GaN layer 24, the barrier layer and the channel layer in sequence, and into the buffer layer.

[0034] Specifically, Figure 4 A schematic flowchart illustrating the fabrication process of etching multiple grooves 27 is shown below. Figure 4As shown, according to the defined trench locations (i.e., the locations of the p-GaN layer 24 near the two side edges), the barrier layer, channel layer, and p-GaN cap layer of the epitaxial wafer are etched to obtain multiple trenches 27 and anode trenches 35 exhibiting a fin-like structure. Specifically, the trench locations are defined using photolithography, and the trenches are etched using ICP. The slow etching process for the SBD anode trench 35 is an optimized slow, low-damage process. The gas used in the slow etching process is BCl3 with a flow rate of 25 sccm, a chamber pressure of 6 mTor, an ICP power of 0 W, and an RF power of 55 W. This etching process mainly achieves low-damage slow etching through ion bombardment. To prevent inhomogeneities during the etching process, the anode trench 35 employs an over-etching process, slightly over-etching to the buffer layer to completely remove the multi-channel layer (i.e., the repeatedly stacked barrier layer and channel layer).

[0035] S203, Etch away the p-GaN layer in the remaining area except for the target area 24.

[0036] The target area is the area between and near the target sidewalls of the multiple grooves 27, and the target sidewalls are the sidewalls in the vertical direction along the transverse direction of the epitaxial wafer.

[0037] Specifically, photoresist is coated on the p-GaN layer 24, and the p-GaN region to be etched is exposed on the photoresist using photolithography. A Cl2 / N2 / O2 mixed gas is introduced and an inductively coupled plasma etching (ICP) process is used to etch the p-GaN layer 24 with high selectivity without damaging the multi-channel layer. The p-GaN layer 24 in other areas below the required gate (i.e., the areas between and near the multiple grooves 27, and the sidewalls in the vertical direction along the lateral direction of the epitaxial wafer) is removed. Finally, the photoresist is removed.

[0038] S204. Device isolation is fabricated in the middle region of the barrier layer. The device isolation extends sequentially through the barrier layer, the channel layer, and the buffer layer to the upper surface of the substrate layer 1 to isolate a first structure with multiple grooves 27 and a second structure with an anode groove 35.

[0039] Specifically, Figure 5 A schematic flowchart illustrating the fabrication process for creating device isolation is shown below. Figure 5 As shown, inductively coupled plasma (ICP) etching is used to etch the epitaxial wafer to form device isolation. Cl-based gas (BCl3 / Cl2) is used for etching to the lower surface of the GaN buffer layer to separate the device regions from each other and prevent unnecessary interference.

[0040] After isolating the first structure with multiple grooves 27 and the second structure with an anode groove 35, it is equivalent to dividing the original device into two parts through isolation. The barrier layer in the isolated first structure with multiple grooves 27 can be called the first barrier layer 22, the channel layer in the first structure can be called the first channel layer 23, and the buffer layer in the first structure can be called the first buffer layer 21. The barrier layer in the second structure with an anode groove 35 can be called the second barrier layer 32, the channel layer in the second structure can be called the second channel layer 33, and the buffer layer in the second structure can be called the second buffer layer 31.

[0041] S205. Using atomic layer deposition technology, dielectric layers 28 are grown on the sidewalls and bottom of multiple grooves 27 and on the p-GaN layer 24.

[0042] Specifically, in the region below the gate 29 (i.e. on the sidewalls and bottom of the multiple recesses 27 and on the p-GaN layer 24), an atomic layer deposition (ALD) is used to deposit a passivation layer to grow a dielectric layer 28. The dielectric layer 28 can be made of SiN or SiO2 and has a thickness of 25 nm.

[0043] S206. A source electrode 25 and a drain electrode 26 are respectively fabricated on the two side edge regions of the barrier layer of the first structure, and the drain electrode 26 is adjacent to the device and isolated. A cathode 34 is fabricated on one side edge region of the barrier layer of the second structure, and the cathode 34 is adjacent to the device and isolated.

[0044] Specifically, source 25 and drain 26 are fabricated on the two edge regions of the barrier layer of the first structure, respectively, and cathode 34 is fabricated on one edge region of the barrier layer of the second structure. In this embodiment, source 25, drain 26, and cathode 34 adopt ohmic contacts. The ohmic metal of source and drain 26 is a combination of Ni, Pt, Au, or Ti metal or a Ni / Pt / Au / Ti metal stack, and the metal of cathode 34 is a combination of Al or Ti / Al / Ni / Au metal stack. Specifically, photolithography is first performed to coat the epitaxial structure with photoresist, and selective exposure and development are performed on the photolithography machine, at which time the area requiring ohmic contacts is washed away. Next, electron beam evaporation is performed on the epitaxial structure on the evaporation stage, and the ohmic metal is stripped off after evaporation. At this time, the metal and semiconductor are Schottky contacts, which need to be annealed to become ohmic contacts. Optionally, the annealing conditions are a temperature of 850°C and a time of 30s. High-temperature annealing is performed in a rapid annealing furnace to form good ohmic contact, thus producing source electrode 25, drain electrode 26 and cathode 34.

[0045] S207. Using an electron beam evaporation apparatus, a first metal is deposited on the dielectric layer 28 to form a Schottky contact, thereby fabricating the gate 29 and obtaining the multi-channel fin gate HEMT2.

[0046] The gate 29 is fabricated on the dielectric layer 28. Specifically, photolithography is performed first; then, electron beam evaporation is performed on the epitaxial structure on the evaporation stage. After evaporation, the metal is stripped off. At this time, the metal and the dielectric layer 28 are in Schottky contact.

[0047] S208. Using a magnetron sputtering device, a second metal is sputtered on the sidewalls and bottom of the anode groove 35, as well as on the barrier layer near the sidewalls of the anode groove 35. The second metal is then thermally annealed to form a Schottky contact, thereby preparing the anode 36 and obtaining the groove anode SBD3.

[0048] Specifically, Figure 6 A schematic flowchart illustrating the fabrication process of the anode is shown below. Figure 6 As shown, the anode metal deposition process employed magnetron sputtering equipment to sputter a W / Au (30 / 200nm) metal stack. W served as the Schottky contact layer, while Au was used to improve the conductivity of the anode metal stack and prevent W oxidation. After anode metal stripping, the metal was reinserted into an RTP furnace and subjected to thermal annealing at 450°C for 5 minutes under a nitrogen atmosphere to form a good Schottky contact.

[0049] S209, the source 25 and anode 36, and the drain 26 and cathode 34 are all interconnected by metal.

[0050] Figure 7 A schematic flowchart illustrating the fabrication process of metal interconnects is shown below. Figure 7 As shown, the drain 26 of the multi-channel fin gate HEMT2 is connected to the cathode 34 of the recessed anode SBD3; the source 25 of the multi-channel fin gate HEMT2 is connected to the anode 36 of the recessed anode SBD3; and the gate electrode 29 of the multi-channel fin gate HEMT2 is led out. Specifically, metal deposition interconnection is achieved by directly depositing Ni / Au metal for planar interconnection.

[0051] Figure 8 A schematic diagram of a buck circuit with parallel recessed anode SBD3 and a buck circuit without parallel recessed anode SBD3 is shown. See [link / reference]. Figure 8 As shown, Figure 8 (a) is a schematic diagram of the buck circuit for the parallel grooved anode SBD3. Figure 8 (b) is a schematic diagram of a buck circuit with a non-parallel grooved anode SBD3. During the operation of the circuit, a very short period of time must be allowed between the switching of the upper and lower transistors to ensure that both transistors are in the off state at the same time. It is a buck circuit built using LTspice.

[0052] Figure 9Simulation waveforms of a buck circuit with parallel recessed anode SBD3 and a buck circuit without parallel recessed anode SBD3 are schematically shown. See [link to documentation]. Figure 9 As shown, Figure 9 (a) in the figure is a simulation waveform diagram of the buck circuit with parallel grooved anode SBD3. Figure 9 (b) in the figure is a simulation waveform diagram of the buck circuit without parallel grooved anode SBD3. Figure 9 In both (a) and (b), the x-axis represents time and the y-axis represents voltage. Connecting the diode in parallel significantly reduces the reverse conduction voltage drop from 2V to 0.7V. Based on existing formulas for calculating reverse conduction losses... Figure 9 The reverse conduction loss in (a) is 0.44W. Figure 9 The reverse conduction loss in (b) is 0.15W. This invention can significantly reduce the reverse conduction loss.

[0053] The finned gate structure of this invention effectively reduces leakage current, especially in high-voltage or high-temperature environments. Because the finned gate increases the control of the channel by the gate 29, it enhances the effective effect of the gate 29 electric field on the channel, resulting in a significant reduction in leakage current. This structure improves the accuracy of threshold voltage control and avoids the leakage current problem caused by the gate 29 effect in traditional planar devices. The p-GaN HEMT and Si SBD in this invention are integrated on the same chip without external wiring connections, optimizing the parasitic inductance and resistance present in external wiring. Compared to the cascading of discrete devices, it better utilizes the switching speed and power conversion efficiency of GaN devices, reducing parasitic parameters. This invention integrates the p-GaN HEMT and Si SBD on a single chip through monolithic integration, eliminating the need for multiple packages of discrete devices and numerous external connection lines, thus reducing size and cost. This invention integrates the internal electrical connections of the chip (such as stable connections ensured by interconnect metals), reducing the connection points between discrete devices and lowering the risk of system failures due to poor connections, solder joint failures, etc., thereby increasing reliability. When applied in circuits, this invention results in lower reverse conduction losses, leading to lower overall circuit losses and less heat generation. Under the same loss conditions, this invention offers greater current capability and optimizes thermal management. The fin-gate structure of this invention not only improves the performance of GaN devices but also provides excellent scalability, adapting to different power range requirements. The size and arrangement of the fins can be adjusted according to different design needs, thus adapting to various application scenarios. This invention uses a Si SBD as the reverse conduction path. Since the turn-on voltage of the Si SBD is only 0.7V, significantly lower than the reverse conduction voltage drop of existing technologies, it can greatly reduce power loss during reverse conduction. This invention utilizes a grooved anode GaN SBD to provide a low-loss reverse path. The grooved anode diode uses a low work function of the anode 36 metal, achieving a lower threshold voltage, and the device can significantly reduce reverse conduction losses.

[0054] It should be noted that the descriptions of the above embodiments of the fabrication method for monolithically integrated multi-channel fin gate HEMT and grooved SBD are similar to those of the above embodiments of monolithically integrated multi-channel fin gate HEMT and grooved SBD, and have similar beneficial effects. For technical details not disclosed in the embodiments of the fabrication method for monolithically integrated multi-channel fin gate HEMT and grooved SBD of this invention, please refer to the description of the embodiments of monolithically integrated multi-channel fin gate HEMT and grooved SBD of this invention for understanding.

[0055] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A monolithically integrated multi-channel fin gate HEMT and grooved SBD, characterized in that, include: A substrate layer, a multi-channel fin gate HEMT and a grooved anode SBD located on the two side edge regions of the substrate layer respectively; The multi-channel fin gate HEMT includes a first buffer layer, a first barrier layer, and a first channel layer sequentially disposed from bottom to top on the substrate, wherein the first barrier layer and the first channel layer are repeatedly stacked; and a p-GaN layer located in the middle region of the first barrier layer. The source electrode is located on the edge region of the first barrier layer away from the grooved anode SBD; The drain is located on the edge region of the first barrier layer near the grooved anode SBD, and neither the source nor the drain is in contact with the p-GaN layer; a plurality of grooves are spaced apart along the parallel direction from the source to the drain, and are spaced apart in the middle region of the p-GaN layer, and the plurality of grooves sequentially penetrate the p-GaN layer, the first channel layer and the first barrier layer, into the first buffer layer; A dielectric layer is located on the sidewalls and bottom of the plurality of grooves, and on the p-GaN layer; The gate is located on the dielectric layer; The grooved anode SBD includes a second buffer layer, a second barrier layer and a second channel layer disposed sequentially from bottom to top on the substrate layer, wherein the second barrier layer and the second channel layer are repeatedly stacked. The cathode is formed on the edge region of the second barrier layer near the drain electrode; the anode groove penetrates the second barrier layer and the second channel layer in sequence into the second buffer layer. The anode is formed on the sidewalls and bottom of the anode groove, as well as on a portion of the second barrier layer.

2. The monolithically integrated multi-channel fin gate HEMT and grooved SBD according to claim 1, characterized in that, The source electrode and the anode, as well as the drain electrode and the cathode, are interconnected by metal.

3. The monolithically integrated multi-channel fin gate HEMT and grooved SBD according to claim 1, characterized in that, The source electrode is made of any one of Ni, Pt, Au, and Ti metals, or a Ni / Pt / Au / Ti multilayer metal; the drain electrode is made of any one of Ni, Pt, Au, and Ti metals, or a Ni / Pt / Au / Ti multilayer metal; and the gate electrode is made of any one or a combination of Ti, Al, Ni, and Au metals.

4. The monolithically integrated multi-channel fin gate HEMT and grooved SBD according to claim 1, characterized in that, The anode is made of Ni or Ni / Au multilayer metal; the cathode is made of Al or any one or a combination of Ti / Al / Ni / Au multilayer metal.

5. The monolithically integrated multi-channel finned gate HEMT and grooved SBD according to claim 1, characterized in that, The first barrier layer and the first channel layer are stacked repeatedly 3-5 times, as are the second barrier layer and the second channel layer.

6. The monolithically integrated multi-channel fin gate HEMT and grooved SBD according to claim 1, characterized in that, The materials of the first barrier layer and the second barrier layer are both AlN or AlGaN, and the materials of the first channel layer and the second channel layer are both GaN, AlN or AlGaN; the thickness of the first barrier layer and the second barrier layer is 10-50nm, and the thickness of the first channel layer and the second channel layer is 50nm-300nm.

7. The monolithically integrated multi-channel fin gate HEMT and grooved SBD according to claim 1, characterized in that, The anode forms a Schottky contact with the second barrier layer.

8. The monolithically integrated multi-channel fin gate HEMT and grooved SBD according to claim 1, characterized in that, The substrate layer is made of GaN, SiC, Si, or sapphire, and its thickness is 100nm-1000μm; the buffer layer is made of GaN, AlN, or AlGaN, and its thickness is 1μm-5μm; the dielectric layer is made of Si3N4 or Al2O3, and its thickness is 10-50nm.

9. A method for fabricating a monolithically integrated multi-channel finned gate HEMT and a grooved SBD, characterized in that, The monolithic integrated multichannel fin gate HEMT and grooved SBD according to any one of claims 1-8, comprising: Clean the epitaxial wafer, which includes a substrate layer, a buffer layer, a channel layer, a barrier layer and a p-GaN layer arranged sequentially from bottom to top, wherein the barrier layer and the channel layer are repeatedly stacked. Using a slow etching process, anode grooves are etched in the p-GaN layer near the two side edges, and multiple grooves are spaced apart in a parallel direction along the transverse direction of the epitaxial wafer. The multiple grooves sequentially penetrate the p-GaN layer, the barrier layer, and the channel layer into the channel layer. The anode grooves sequentially penetrate the p-GaN layer, the barrier layer, and the channel layer into the buffer layer. The p-GaN layer is etched away from the remaining area except for the target area, where the target area is the area between the plurality of grooves and the target sidewalls near the plurality of grooves, and the target sidewalls are the sidewalls in the direction perpendicular to the transverse direction of the epitaxial wafer; Device isolation is fabricated in the middle region of the barrier layer, the device isolation sequentially penetrating the barrier layer, the channel layer and the buffer layer to the upper surface of the substrate layer, so as to isolate a first structure having the plurality of grooves and a second structure having the anode groove; A dielectric layer is grown on the sidewalls and bottom of the plurality of grooves and on the p-GaN layer using atomic layer deposition technology; A source and a drain are respectively fabricated on the two edge regions of the barrier layer of the first structure, and the drain is isolated from the device. A cathode is fabricated on one edge region of the barrier layer of the second structure, and the cathode is isolated from the device. Using an electron beam evaporation apparatus, a first metal is deposited on the dielectric layer to form a Schottky contact, thereby fabricating a gate and obtaining a multi-channel fin gate HEMT. A second metal is sputtered onto the sidewalls and bottom of the anode groove and onto the barrier layer near the sidewalls of the anode groove using a magnetron sputtering device. The second metal is then thermally annealed to form a Schottky contact to prepare the anode, resulting in a grooved anode (SBD). The source electrode and the anode, as well as the drain electrode and the cathode, are interconnected by metal.

10. The method for fabricating a monolithic integrated multi-channel fin gate HEMT and a grooved SBD according to claim 9, characterized in that, The slow etching process uses BCl3 gas at a flow rate of 25 sccm, a chamber pressure of 6 mTor, an ICP power of 0 W, and an RF power of 55 W.

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