Methods for optimizing and compensating switching losses, conduction losses and short-circuit withstand capability of a power semiconductor and / or a power module

Abstract

Method (1) for optimizing the switching losses and conduction losses and the short-circuit withstand capability of at least one power semiconductor (152.1, 152.2) and / or one power module in a logic switch, comprising a two-stage turn-on, a gate, a drain and a source, at least one gate driver providing multi-stage gate forming, wherein the method (1) comprises at least the following steps: a. Initiating (2) a predefined inrush current (54) of the gate by the gate driver, b. Performing (4) a first current injection (56) by injecting at least one first gate current (55), c. Performing (8) a second current injection (58) of a hold-gate current (80), during which a short-circuit detection (10) is performed and, if a short circuit is detected, a procedure step iv. is initiated, and, if no short circuit is detected, a procedure step v. and vi. is initiated. d. Switching off (13 of the power semiconductor and / or the power module, initiating a switch-off process (13) which includes a number of forming processes (60), e. Applying (14) a maximum gate current (78), and f. Performing (16) a third current injection (82) of a gate current.

Description

Technical field

[0001] The invention relates to a method for optimizing and balancing the switching behavior, conductivity, and short-circuit withstand capability of a power semiconductor and / or a power module comprising at least one gate driver that provides multi-stage gate forming. The invention further relates to a use of the method. State of the art

[0002] WO2023046607A1 presents a method for increasing switching performance by reducing switching energy, based on gate signal shaping (GS). The switching on of the isolated-gate semiconductor device occurs in several steps according to the described method. First, a gate of the isolated-gate semiconductor device is driven by a predefined inrush current. A defined inrush current is applied by a current-controlled gate driver to initiate the switching process of the semiconductor device. Subsequently, a first turn-on phase point is determined, representing the attainment of the semiconductor device's threshold voltage. This is achieved by detecting a rising current edge in a load path.The gate driver then controls the gate of the semiconductor device with a second predefined inrush current, which differs from the first predefined inrush current, at the determined first inrush phase time, in order to continue the inrush process based on the second inrush current.

[0003] Furthermore, a reduction in gate voltage to decrease the stress on power semiconductors during short circuits can be achieved through two-stage turn-on during the active turn-on process. This stress reduction is achieved by limiting the short-circuit current during a short-circuit event, which extends the short-circuit detection and short-circuit withstand times. Voltage or current source gate drivers can be used to achieve two-stage turn-on, as described in US 2023 / 126 070 A1.

[0004] US Patent 2023 / 126 070 A1 describes a driver circuit for a low-inductance power module, which has one input and one output. The input can be connected to the source contact of the power transistor, while the output can be connected to the gate contact of the power transistor. The driver circuit is configured such that, in the first operating mode, it generates a first gate-source voltage for the gate contact of the power transistor and provides this first gate-source voltage at the output of the driver circuit. Furthermore, in a second operating mode, the driver circuit is configured to generate a lower second gate-source voltage for the gate contact of the power transistor for at least a preset minimum duration and provide this second gate-source voltage at the output of the driver circuit. Disclosure of the invention

[0005] According to the invention, a method for optimizing and balancing the switching behavior, conductivity and short-circuit strength of at least one power semiconductor and / or one power module in a logic switch, comprising a two-stage turn-on, a gate, a drain and a source and at least one gate driver providing multi-stage gate forming, is presented.

[0006] The procedure includes at least the following steps: i. Initiating a predefined gate inrush current by the gate driver, ii. Performing a first current injection by at least one injection of at least a first gate current, wherein, in the case of multiple injections of several gate currents, the gate currents are different, wherein a final injection of the first current injection is performed by a final gate current set such that the value of a gate-source voltage is greater than a plateau end voltage and less than a nominal gate turn-on voltage, iii. Performing a second current injection of a holding gate current, in which the holding gate current is injected in such a way that the gate-source voltage is maintained at a first constant level, and during this time a short-circuit detection is performed, and if a short circuit is detected, procedure step iv. is initiated, and if no short circuit is detected, procedure steps v. and vi. are initiated. iv. Switching off the power semiconductor and / or the power module, initiating a shutdown process that includes a number of shaping operations, v. Applying a maximum gate current, wherein the maximum gate current is supplied in such a way that the nominal gate turn-on voltage is reached, and vi. Performing a third current injection of a hold-gate current, whereby the hold-gate current is applied such that the gate-source voltage is held at a second constant level and the gate-source voltage is held at the nominal gate turn-on voltage.

[0007] The solution proposed according to the invention optimizes the switching performance and / or short-circuit withstand capability of a power semiconductor and / or power module. This optimization of switching performance and short-circuit robustness is achieved through the use of a gate driver capable of generating multi-stage gate forming. By adapting the amplitudes and intervals of individual switching stages, the solution according to the invention optimizes switching losses and reduces the load during a short circuit. Due to the reduced short-circuit-induced load, the short-circuit detection time and the short-circuit withstand time are extended.

[0008] A gate driver according to the invention is a circuit for controlling power semiconductors such as MOSFETs, IGBTs, or power modules, which includes multi-stage gate forming. The gate driver ensures optimal voltage regulation through current injection. Multi-stage gate forming leads to an increase in the efficiency and reliability of switching operations by employing a multitude of current stages in the gate path during turn-on and turn-off. During the turn-on process of the power semiconductor and / or the power module, different current stages are applied to the gate sequentially. This ensures a controlled current rise rate, minimizes overvoltage spikes in a short-circuit event, and guarantees a balanced current injection.Current injection in gate drivers refers to a process in which either a single continuous gate current or several different gate currents are supplied in rapid succession to the gate of a power semiconductor and / or power module (such as a MOSFET or IGBT). A controlled current injection according to the solution of the invention results in a controlled sequence of voltage levels. This is achieved by the gate driver designed according to the invention. The gate driver consists of several output stages and is configured to provide different current values ​​within predefined time intervals. The gate driver ensures that the current values ​​are maintained precisely and stably, thereby optimizing the switching operations of the power semiconductor and / or power module.-One gate driver used according to the intended procedure is, for example, a so-called current source gate driver (CSGD). This can be operated in constant current or gate-shaping mode, as well as with a two-stage turn-on.

[0009] A logic switch is defined as a combination of several parallel silicon carbide metal oxide field-effect transistors (MOSFETs) and / or IGBTs, arranged, for example, within a power module, with their gates connected separately. Alternatively, a logic switch can also be defined as a combination of several parallel power modules, each consisting of parallel silicon carbide MOSFETs, with common gate control. Alternatively, a logic switch can also be defined as a single silicon carbide MOSFET or IGBT.

[0010] According to the invention, a two-stage switching-on is understood to be an electronic gate driver circuit for the precise generation of a reduced gate voltage, thereby making it possible to extend the short-circuit detection time and short-circuit resistance.

[0011] In a first step of the process according to the invention, a predefined inrush current of the gate is initiated by the gate driver. This predefined inrush current is then maintained for a first time interval. The predefined inrush current is, for example, set for the gate driver in constant current mode, preferably taking into account stable switching behavior with optimized switching energy.

[0012] The first time interval is determined as follows: First, a desired current commutation rate for the maximum phase current is defined. Based on this, in the second step, a current commutation time of, for example, 10% to 90% of the phase current is calculated to determine the time interval. Then, in the third step, a predefined inrush current is selected from the desired current commutation time and a gate charge to charge a gate capacitance from the threshold voltage to a gate voltage at phase current. Finally, in the fourth step, a time is calculated from the corresponding gate charges and the predefined inrush current to charge a gate-source capacitance from the gate voltage at phase current to the plateau start voltage and from the plateau start voltage to the plateau end voltage.The sum of the times in the third and fourth steps for determining the time interval is equal to the first time interval in the gate driver in constant current.

[0013] In the case of a gate driver, for example in gate-shaping mode, the predefined inrush current is set until the maximum level of the gate driver's gate current in gate-shaping mode is reached. This results in a reduction of the blanking time and dead time, for example between the upper and lower switches in a half-bridge or in a power module, because a threshold voltage is reached faster than with constant current.

[0014] In step ii of the inventive process, a first current is injected by at least one gate current. If multiple gate currents are injected, the gate currents are different. The first gate current is applied such that its current value is lower than the predefined input current. In the case of a gate driver, for example in gate-shaping mode, this results in a current rise rate that leads to optimal turn-on losses during current commutation. A final injection of the first current is performed by a final gate current set such that the gate-source voltage is greater than a plateau end voltage and less than a nominal gate turn-on voltage.A first current injection in gate drivers comprises a process in which either a single continuous gate current or several different gate currents are sequentially injected into the gate of a power semiconductor and / or power module by the gate driver proposed according to the invention. The first current injection includes a final injection by the last gate current. In the case of a single injection, the last gate current is identical to the first gate current. In the case of multiple injections, however, the last gate current in a series of injections corresponds to the final gate current injected in the first current injection. The first current injection is performed such that each injection of the respective gate current is paused at time intervals.

[0015] In this regard, within the framework of the inventive process step ii., a first current injection takes place during a time interval, which is defined, for example, for gate drivers in constant current, with such an increased gate-source voltage that the gate-source voltage exceeds a plateau end-voltage level by a few volts.

[0016] In step ii of the inventive process, for example, a first current injection occurs during a specific time interval. This can be defined, for example, for gate drivers in gate-shaping mode with multiple injections of several gate currents, such as four gate currents. The initial step involves selecting a desired current commutation rate at maximum phase current. Based on this, a current commutation time is calculated from the desired current commutation rate and 10%–90% of the phase current, during which the first gate current is injected. The second gate current at the first current injection is selected such that it controls a current commutation slope between the maximum drain-source current and the phase current.Furthermore, a third gate current is injected, defined by dividing the drain-source voltage at maximum drain-source current during normal switching by the desired voltage commutation rate. Following the first current injection, a fourth gate current is injected, defined by an injection within a time interval in which the gate-source voltage is charged a few volts higher than the plateau end voltage.

[0017] In the case of a gate driver in gate-shaping mode, an initial current injection occurs through a multitude of gate current injections. This approach is particularly preferred when injections are made by at least a first gate current, a second gate current, a third gate current, and a fourth gate current, with the fourth gate current consequently acting as the final gate current. The first gate current is advantageously applied such that its current value is lower than the predefined input current. This ensures efficient current control. The second gate current injection is advantageously applied such that its value is further reduced compared to the first gate current. This reduces a peak current due to backfeeding, for example, from a diode on the complementary side of a half-bridge.The third gate current injection of the first is preferably applied such that the third gate current is slightly higher than the second gate current. This can be achieved, for example, by increasing the third gate current by a few milliamperes, to approximately 10 mA to 50 mA. This allows for an optimal voltage drop rate, resulting in optimal turn-on losses during voltage switching. A final injection of the first current is applied via a fourth gate current, set such that the gate-source voltage is greater than the plateau end voltage and less than the nominal gate turn-on voltage.

[0018] In the third process step iii, a second current injection of the holding gate current is performed. The holding gate current is injected in such a way that the gate-source voltage is maintained at a first constant level. Simultaneously, short-circuit detection is carried out. If a short circuit is detected, the fourth process step iv is initiated, while if no short circuit is detected, process steps v and vi are initiated. In this context, the holding gate current is injected in such a way that a constant gate-source voltage is ensured without any further charging. The holding gate current is preferably set to a few tens of milliamperes (mA), although deviations above or below this value are also possible. The holding gate current is kept constant within a defined holding gate current time interval.The hold-gate current time interval is determined, for example, using short-circuit detection and the gate driver's response time. This response time can be quantified, for example, in the range of 100 ns to 300 ns.

[0019] Upon detection of a short circuit, process step iv is initiated, which causes the power semiconductor and / or power module to be switched off. This switch-off initiates a shutdown process comprising a number of forming operations. A forming operation is a method according to the invention in which gate currents are selectively injected into a power semiconductor and / or power module. The forming operation is carried out by selectively injecting a defined number of gate currents. The number of injected gate currents can vary between one and several gate currents to realize the forming operation. The forming operation aims to reduce the overvoltage at the semiconductor during a shutdown operation. This results in a reduction of the short-circuit withstand energy during the shutdown operation, since a smaller current needs to be switched off.This leads to a reduction in both short-circuit withstand energy and overvoltage at the semiconductor. Such an overvoltage load can occur, for example, in a power semiconductor like a field-effect transistor (MOSFET) during the turn-off process. The reduction in short-circuit withstand energy due to double turn-on, in turn, increases short-circuit withstand capability and short-circuit detection time.

[0020] Furthermore, in a gate driver operating in constant current or gate shaping mode, in the event of a short circuit, an injection is made through the shaping process to realize an initial discharge gate current injection, which is carried out in such a way that the drain-source voltage is smaller than the maximum drain-source overvoltage.

[0021] If a short circuit is detected and identified in a gate driver operating in constant current or gate-shaping mode, multiple gate current injections are applied during the shaping process using multiple discharge gate currents of varying current intensities. One example of a shaping process is triple shaping, where three discharge gate currents are injected: a first, a second, and a third. The current intensities of the discharge gate currents increase successively. Advantageously, the second discharge gate current is chosen to be slightly higher than the first to discharge the gate-source voltage to the threshold voltage, while the drain-source voltage is kept 30% to 80% lower than the maximum drain-source overvoltage during the shutdown process following a short circuit of the power semiconductor and / or power module.The short-circuit energy is also reduced because a smaller short-circuit current needs to be switched off during triple forming after a short circuit. The time intervals during the forming process help to reduce the overvoltage stress on the power module and / or power semiconductor. Furthermore, the third discharge gate current, which is slightly higher than the second discharge gate current, is injected, allowing the gate-source voltage to quickly reach the value of a nominal gate turn-off voltage.

[0022] If a short circuit is not present, process step v is executed instead of process step iv. This step involves applying a maximum gate current while maintaining the nominal gate turn-on voltage. Subsequently, process step vi. is initiated. This involves a third current injection of the gate current, which is applied in such a way that the gate-source voltage is maintained at a second constant level and the gate-source voltage is kept at the nominal gate turn-on voltage.

[0023] In an advantageous further development of the method proposed according to the invention, in process step iii. the gate current is supplied such that the value of the gate current is in the range between 5 mA and 10 mA, preferably at a value of 10 mA.

[0024] In an advantageous further development of the method proposed according to the invention, the gate driver is operated in constant current (CC) mode, followed by a two-stage turn-on process. A constant current (CC) gate driver is an electronic circuit used, for example, to drive power transistors such as bipolar transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs). The constant current (CC) gate driver ensures a stable current flow during the charging process of the transistor's gate capacitor. Consequently, an optimal switching speed of the transistor and the maintenance of a consistent switching time are ensured.

[0025] In an advantageous further development of the method proposed according to the invention, the gate driver is operated in gate-shaping mode GS, followed by a two-stage turn-on. A gate driver in gate-shaping mode represents a circuit solution for the precise control of the signal waveform, particularly with regard to the rise times of the drain-source current and the fall times of the drain-source voltage. The term "gate-shaping mode" encompasses a specific operating mode of gate drivers in power electronics, in which the output signal of the gate driver is shaped to optimize the rise time of the current and the fall time of the voltage. This shaping contributes to controlling the switching speed and leads to a reduction in switching losses.

[0026] In a further advantageous embodiment of the method proposed according to the invention, a first current injection according to step ii. is carried out by a first gate current, a second gate current and a third gate current. The first gate current is selected to be smaller than the predetermined inrush current, the second gate current smaller than the first gate current and the third gate current larger than the second gate current.

[0027] In a further advantageous embodiment of the method proposed according to the invention, the shaping process is carried out by at least one shaping of the gate current.

[0028] In an advantageous further development of the method proposed according to the invention, the forming process is carried out by a forming process initiated by a first discharge gate current. Subsequently, the gate current (iG) is set to 0 A. The gate-source voltage is thereby discharged to a continuous turn-off voltage.

[0029] In a further advantageous embodiment of the method proposed according to the invention, the forming process is carried out by means of a single forming operation. The single forming operation is performed by means of a first discharge gate current.

[0030] In a further advantageous embodiment of the method proposed according to the invention, the forming process is carried out by a triple forming process, which is effected by a first discharge gate current, a second discharge gate current and a third discharge gate current. The current intensity of the discharge gate currents increases successively.

[0031] In a further advantageous embodiment of the method proposed according to the invention, an optimization and compensation of switching and power losses are carried out when the logic switch comprises at least two power semiconductors and / or power modules with at least two power semiconductors.

[0032] Optimizing switching and power losses is a crucial aspect because power semiconductors, such as silicon carbide metal oxide field-effect transistors (MOSFETs), exhibit numerous differences due to their manufacturing processes. This necessitates a differentiated approach. This approach involves considering various threshold voltages, plateau voltages, and on-state drain-source resistances. A mismatch in the on-state drain-source resistance between silicon carbide MOSFETs in a logic switch results in unequal drain-source currents and unequal power losses per power semiconductor within that logic switch.Consequently, varying loads are transferred to the power semiconductors within a logic switch, which significantly influence the lifetime of the power semiconductor or the power module. The optimization of power losses according to the invention advantageously reduces the load, resulting in a positive effect on the lifetime.

[0033] In a further advantageous embodiment of the method proposed according to the invention, the optimization and compensation of switching and power losses are achieved by adjusting the amplitudes of gate currents and time intervals. The optimization and compensation of switching and power losses comprises at least the following steps, including compensation of the junction temperature: a. Estimation of junction temperatures of each power semiconductor, b. Determining a reference junction temperature, c. Calculate at least one gate-source voltage, d. Generating at least one gate profile and e. Balancing the at least one gate profile, whereby a difference in the estimated junction temperatures is reduced and the balancing is carried out such that the estimated junction temperatures are below the reference junction temperature.

[0034] As part of the procedure, compensation is carried out for at least one gate profile by reducing a difference in the estimated junction temperatures to a value of, for example, less than 3 Kelvin.

[0035] Alternatively, the process can be carried out by optimizing and compensating for switching and conduction losses by adjusting the amplitudes of the gate currents and the time intervals. An exemplary method involves optimizing switching and power losses and includes, for example, at least the following steps, compensating for total losses, which are calculated as the sum of switching and power losses: a. Estimation of the total power output of each power semiconductor b. Determining a reference total power loss, c. Calculate at least one gate-source voltage, d. Generating at least one gate profile and e. Balancing the at least one gate profile, reducing a difference in the estimated total power loss, wherein balancing switching and conduction losses is carried out such that the estimated total losses and a reference total losses have the same value and the estimated total powers are below a reference total power.

[0036] Alternatively, the process can be carried out by optimizing and compensating for conduction losses by adjusting the amplitudes of the gate currents and the time intervals. Optimizing conduction losses includes, for example, at least the following steps, compensating for the drain-source resistance: a. Estimation of junction temperatures of each power semiconductor, b. Determining the reference drain-source resistance, c. Calculate at least one gate-source voltage, d. Generating at least one gate profile and e. Balancing the at least one gate profile, reducing a difference in the estimated drain-source resistances, wherein the balancing is carried out such that the estimated drain-source resistances and a reference drain-source resistance have the same value.

[0037] Optimizing conduction losses can be advantageous for increasing switching, switching, and conduction performance. This can be achieved by using a gate driver that generates multi-stage gate forming. Adjusting the amplitudes of the gate currents and the timing of individual steps allows for optimization of the switching and conduction losses of a logic switch. Furthermore, switching and conduction losses between parallel power semiconductors can be balanced. Additionally, the short-circuit withstand capability of power modules can be increased by using a two-stage turn-on process.

[0038] As an example, consider a logic switch for optimizing conduction losses, consisting of two parallel power semiconductors. It's important to note that both power semiconductors have differing static parameters. The optimization aims to ensure that both power semiconductors avoid exceeding a reference junction temperature. The reference junction temperature represents a maximum permissible limit set by the power semiconductor manufacturer. This is achieved by balancing the power losses of both power semiconductors.Taking into account the dependence of the threshold voltage, plateau voltage and on-resistance on a junction temperature, a battery voltage and the drain-source current, the nominal gate-source voltages for both power semiconductors are calculated and a gate current profile is created for each power semiconductor.

[0039] Subsequently, the gate current profiles are adjusted to compensate for switching and power losses until a difference of zero Kelvin is reached between the estimated junction temperature of the power semiconductors and the estimated junction temperatures are also below the reference junction temperature.

[0040] The junction temperature of a power semiconductor is the temperature at which the junction—an insulating oxide layer between the gate and a channel—functions reliably, and there are neither significant leakage currents nor conduction losses. Junction temperatures can be estimated, for example, by using temperature-sensitive electrical parameters of the power semiconductor. These include measurements of the internal gate resistance of a power semiconductor, current measurements within a power semiconductor, and calculation of the junction temperature using observer-based temperature monitoring and a temperature sensor on the power module.

[0041] In a further advantageous embodiment of the method proposed according to the invention, the method is carried out during a gate driver turn-on process and / or a gate driver turn-off process.

[0042] Furthermore, the method is proposed for use in controlling power semiconductors, hybrid switches such as SiC-MOSFET and IGBT in parallel, power modules with separate or common gates, or several parallel-connected power modules with common gates in an inverter.

[0043] Alternatively, the method can be used to adjust the gate-source voltage in the conducting state such that a minimum gate voltage value is higher than the plateau voltage, and a maximum gate voltage value is lower than a specified maximum gate-source voltage. Furthermore, the method can be used, for example, with a voltage-source gate driver with two adjustable output voltage levels. It can also be used with a hybrid gate driver that combines a voltage-source gate driver and a current-source gate driver. In this case, the voltage-source gate driver controls the output voltages, and the current-source gate driver controls the switching operations. Advantages of the invention

[0044] The solution proposed according to the invention achieves optimization and balancing of the switching performance, conduction performance, and short-circuit withstand capability of power semiconductors and power modules, based on an innovative methodological approach. This optimization and balancing are achieved through the use of an advanced gate driver capable of generating multi-stage gate forming. Due to this multi-stage gate forming, switching processes are controlled more precisely than in the prior art, resulting in a significant improvement in the performance of the electronic components of the power modules and / or power semiconductors.

[0045] In this regard, it should be noted that a key aspect of the inventive method is realized in the careful adjustment of the amplitudes and intervals of individual switching stages within the process. Precise control of these parameters results in a significant reduction of switching losses, which in turn increases the energy efficiency of the system. Simultaneously, a substantial reduction in both the short-circuit current and the overvoltage during a short-circuit event is achieved. This leads to a minimization of thermal and mechanical stresses on the respective power semiconductor and / or the power module, thereby ensuring its integrity.

[0046] Furthermore, the described method offers the advantage of an extended short-circuit detection time. By reducing potential stresses on the power semiconductor and / or the power module (with separate and shared gates), the time until a critical state is reached is extended, thus ensuring more effective and longer-lasting functionality of the integrated protection mechanisms. Consequently, the power semiconductor and / or the power module remains stable for longer during a short circuit and is damaged to a lesser extent, ultimately leading to an increased short-circuit withstand time.

[0047] This improved robustness and reliability prove particularly advantageous in applications involving high currents and voltages, such as power electronics. Furthermore, this solution minimizes switching losses while simultaneously increasing short-circuit resistance, thus generating exceptional added value for the sustainable and efficient development of electronic systems.

[0048] A two-stage switching-on allows for advantageous adjustment of the nominal gate voltage to increased values, while short-circuit detection remains independent of the nominal switch-on voltage. This results in a reduction of the drain-source resistance of the power semiconductors as well as a reduction in power losses.

[0049] The method according to the invention reduces both the blanking saturation and the dead time, which can be observed or measured in gate-shaping mode with a current source-gate driver. Reducing the dead time is a crucial factor in high-frequency applications, firstly to minimize diode conduction loss, and secondly to optimize the overall system efficiency.

[0050] A further advantage of the method according to the invention results in a significant reduction of switching and power losses in inverters.

[0051] By specifically adapting and optimizing the losses using the solution according to the invention in accordance with the requirements of the worldwide standardized test procedure for light vehicles (WLTP), an efficiency gain of the inverters is achieved, which leads to an extension of the range of electric vehicles.

[0052] Furthermore, the optimization according to the invention results in an increase in various performance parameters, including switching power, short-circuit withstand capability, and conduction power. An adjustment of the gate current amplitudes and the timing of individual steps according to the invention allows for the optimization of the switching and conduction losses of a logic switch. Moreover, the method according to the invention allows for the compensation of switching and conduction losses between parallel power semiconductors. Finally, the method according to the invention enables an increase in the short-circuit withstand capability of power modules, which is achieved by means of a two-stage switching process.

[0053] Taking into account the manufacturer-related process variations when setting the gate profiles, the scattering losses of the semiconductor are advantageously reduced. Brief description of the drawings

[0054] Embodiments of the invention are explained in more detail with reference to the drawings and the following description.

[0055] They show: Fig. 1 a schematic representation of the procedure, Fig. 2 a schematic representation of a five-stage gate forming with a two-stage switching-on with and without short circuit and a single forming in case of short circuit, Fig. 3 a schematic representation of a five-stage gate forming with a two-stage switching-on with and without short circuit and a triple forming in case of short circuit, Fig. 4 a schematic representation of an eight-stage gate forming with a two-stage switching-on with and without short circuit and a single forming in case of short circuit, Fig. 5 a schematic representation of an eight-stage gate forming with a two-stage switching-on with and without short circuit and a triple forming in case of short circuit, Fig. 6 a schematic representation of a method for optimizing switching losses, conduction losses and short-circuit withstand capability by compensating for junction temperatures, Fig. 7 a schematic representation of a five-stage gate forming of two power semiconductors during a gate driver turn-on process, Fig. 8 A schematic representation of an eight-stage gate forming of two power semiconductors during a gate driver turn-on process Fig. 9 a schematic representation of a single-stage gate forming of two power semiconductors during a gate driver turn-off process and Fig. 10 a schematic representation of a four-stage gate forming of two power semiconductors during a gate driver turn-off process. Embodiments of the invention

[0056] In the following description of embodiments of the invention, identical or similar elements are designated by the same reference numerals, and repeated descriptions of these elements are omitted in individual cases. The figures represent the subject matter of the invention only schematically.

[0057] In Fig. A method 1 for optimizing the switching behavior and short-circuit withstand capability of a power semiconductor and / or a power module, comprising a gate, a drain, and a source, and at least one gate driver providing multi-stage gate forming, is described. This method 1 is subdivided into at least the following successive steps.

[0058] In the first method step i. according to the invention, a predefined inrush current 54 of the gate is initiated by the gate driver.

[0059] In the second process step ii., a first current injection 56 is performed by at least one injection of at least one first gate current 55, whereby in the case of multiple injections, several gate currents 55, 116, 114, 118 are taken into account. The gate currents 55, 116, 114, 118 differ from each other. A final injection of the first current injection 56 is performed by a final gate current set in such a way that the value of a gate-source voltage is greater than a plateau end voltage 66 and less than a nominal gate turn-on voltage 68.

[0060] In the third process step iii according to the invention, a second current 58 of a holding gate current 80 is injected. The holding gate current 80 is injected such that the gate-source voltage is maintained at a first constant level 62.1. While the gate-source voltage is maintained at a first constant level 62.1, a short-circuit detection 10 takes place. If a short circuit is detected, process step iv. is initiated; otherwise, process steps v and vi.

[0061] In the event of a short circuit being detected by process step iv. the gate-source voltage remains at a first constant level 62.1 and a shutdown 13 of the power semiconductor and / or the power module is initiated, initiating a shutdown process 13 which includes a number of forming processes 60.

[0062] If no short circuit is detected, a process step v. is initiated, which introduces the application 14 of a maximum gate current 78. The maximum gate current 78 is injected such that the nominal gate turn-on voltage 68 is reached. Subsequently, process step vi. is carried out by performing 16 a third current injection 82. The gate-source voltage is maintained at a second constant level 62.2 by injecting a holding gate current 80, thus maintaining the gate-source voltage at the nominal gate turn-on voltage 68.

[0063] Fig. Figure 2 shows a schematic representation of a five-stage gate forming with a two-stage switching-on with and without a short circuit and a single forming in the event of a short circuit. Fig. Figure 2 also shows a schematic representation of superimposed diagrams depicting the time course of various electrical quantities. A horizontal axis (x-axis) represents time 20, with time points t0 (22), t1 (24), t2 (26), t3 (28), t4 (30), and t5 (32), while a vertical axis (y-axis) represents the respective measured quantities in the diagrams. The following diagrams are shown from bottom to top: The bottom diagram shows the time course of the drain-source current 34, measured in amperes (A). Immediately above it is the diagram of the time course of a drain-source voltage 36, measured in volts (V). The next diagram shows the time course of the gate current 38, also measured in amperes (A). At the top is the diagram of the gate-source voltage 18, measured in volts (V).The time axis (x-axis) is identical in all four diagrams and extends across the entire width of the . Fig. 2. Time 20 is given in nanoseconds (ns). The drain-source current waveform 34 shows how the drain-source current changes over time. The drain-source voltage waveform 36 represents the drain-source voltage, which exhibits characteristic voltage spikes or transients during the operating cycles of the power semiconductor. The upper diagram shows the gate-source voltage waveform 18 over time 20, which provides information about the switching state of the power semiconductor. All four diagrams show a short-circuit waveform 40 and a short-circuit-free waveform 42.

[0064] Furthermore, it shows Fig. 2. Initiation of a predefined inrush current 54 within a time period between time t22 and time t124. Within this period, the gate driver selects a predefined inrush current 54 of the gate to achieve stable switching behavior with optimized switching energy. Furthermore, in Fig. Figure 2 shows a time course between time t1 24 and time t2 26. During the time interval t1-t2, an initial current injection 56 occurs via a first gate current 55, which is selected, for example, such that the gate-source voltage rises slightly, so that the value of the gate-source voltage is greater than the plateau end voltage 66 and less than the nominal gate turn-on voltage 68 in order to limit the maximum value of the short-circuit withstand current 98.1. Furthermore, in Fig. Figure 2 shows a plateau starting voltage of 70. Furthermore, in Fig. Figure 2 shows a time sequence between time t2 (26) and time t3 (28). Within the time interval t2-t3, a second current injection 58 of a holding gate current 80 occurs. The holding gate current 80 is injected such that the gate-source voltage is maintained at a first constant level 62.1. While the gate-source voltage is maintained at a first constant level 62.1, a short-circuit detection 10 takes place. In the event of a short circuit detection, the power semiconductor and / or the power module is switched off 13. This process is described in Fig. Figure 2 shows a forming process 60 of a simple forming process 86. In Fig. Figure 2 shows that the forming process 60 is initiated by a first discharge gate current 84. Furthermore, if no short circuit detection occurs, as in Fig. Figure 2 shows that the current increase is raised by an injection so that a maximum gate current of 78 is reached. This is injected in such a way that a nominal gate turn-on voltage of 68 is achieved. Furthermore, Figure 2 shows that the current rise is increased by an injection so that a maximum gate current of 78 is reached. Fig. 2 a time course between time t4 30 and t5 32. Within the time interval t4 - t5, if a short circuit is detected, the gate current is set to 0 A, whereby the gate-source voltage is discharged to a continuous turn-off voltage 76. In the case of no short circuit, a third current injection 82 of a holding gate current 80 occurs such that the gate-source voltage is held at a second constant level 62.2 and the gate-source voltage is maintained at the nominal gate turn-on voltage 68.

[0065] Fig. Figure 3 shows a schematic representation of a five-stage gate forming with a two-stage switching-on with and without short circuit and a triple forming in case of short circuit. Fig. Figure 3 also shows a schematic representation of superimposed diagrams depicting the time course of various electrical quantities. A horizontal axis (x-axis) represents time 20, with time points t0 (22), t1 (24), t2 (26), t3 (28), t4 (30), t5 (32), t6 (102), and t7 (104). A vertical axis (y-axis) represents the respective measured quantities in the diagrams. From bottom to top, the diagrams show the following: The bottom diagram shows the time course of the drain-source current 34, measured in amperes (A). Immediately above it is the diagram of the time course of a drain-source voltage 36, measured in volts (V). The next diagram shows the time course of the gate current 38, also measured in amperes (A).The graph above shows the course of the gate-source voltage 18, measured in volts (V). The time axis (x-axis) is identical in all four graphs and extends across the entire width of the graph. Fig. 3. Time 20 is given in nanoseconds (ns). The drain-source current curve 34 shows how the drain-source current changes over time. The drain-source voltage curve 36 represents the drain-source voltage, which exhibits characteristic voltage spikes or transients during the operating cycles of the power semiconductor. The upper diagram shows the gate-source voltage 18 over time 20, which provides information about the switching state of the power semiconductor. All four diagrams show a short-circuit curve 40 and a short-circuit-free curve 42.

[0066] Furthermore, it shows Fig. 3. Initiation of a predefined inrush current 54 over a period of time between t0 22 and t1 24. Within this period, the gate driver selects a predefined inrush current 54 of the gate to achieve stable switching behavior with optimized switching energy. Furthermore, in Fig. Figure 3 shows a time course between time t1 24 and time t2 26. During the time interval t1-t2, an initial current injection 56 occurs via a first gate current 55, which is selected, for example, such that the gate-source voltage rises slightly, so that the value of the gate-source voltage is greater than the plateau end voltage 66 and less than the nominal gate turn-on voltage 68 in order to limit the maximum value of the short-circuit withstand current (peak short-circuit current?) 98.1. Furthermore, in Fig. Figure 3 shows a plateau starting voltage of 70. Furthermore, in Fig. Figure 3 shows a time course between time t2 (26) and time t3 (28). Within the time interval t2-t3, a second current injection 58 of a holding gate current 80 occurs. The holding gate current 80 is injected such that the gate-source voltage is maintained at a first constant level 62.1. While the gate-source voltage is maintained at a first constant level 62.1, a short-circuit detection 10 takes place. In the event of a short circuit detection, the power semiconductor and / or the power module is switched off during the time interval t3-t6 (see short-circuit curve 40). The switch-off process is characterized by a forming process 60, which has a triple forming action. Fig. Figure 3 depicts the forming process 60 as being represented by a first discharge gate current 84, a second discharge gate current 106, and a third discharge gate current 108. The current intensity of the discharge gate currents 84, 104, and 106 increases successively. Furthermore, in Fig. 3. In a short-circuit-free state 42 of the gate current 38, an increase in the gate current occurs due to an injection, such that a maximum gate current 78 is reached. This is injected in such a way that the nominal gate turn-on voltage 68 is reached. Furthermore, it shows Fig. 3 a time course between time t6 102 and t7 104. During the time interval t6-t7, if a short circuit is detected, as shown in the short-circuit curve 40, the gate current iG is set to 0 A, whereby the gate-source voltage is discharged to a continuous turn-off voltage 76. In the case of no short circuit, a third current injection 82 of a holding gate current 80 occurs such that the gate-source voltage is held at a second constant level 62.2 and the gate-source voltage is maintained at the nominal gate turn-on voltage 68.

[0067] Fig. Figure 4 shows a schematic representation of an eight-stage gate forming with a two-stage switching-on with and without short circuit and a single forming in case of short circuit. Fig. Figure 4 also shows a schematic representation of superimposed diagrams depicting the time course of various electrical quantities. A horizontal axis (x-axis) plots time 20, which also includes time points t0 22, t1 24, t2 26, t3 28, t4 30, t5 32, t6 102, t7 104, and t8 110. A vertical axis (y-axis) represents the respective measured quantities in the diagrams. From bottom to top, the following diagrams show the time course of the drain-source current 34, measured in amperes (A). Immediately above it is the diagram of the time course of a drain-source voltage 36, measured in volts (V). The next diagram shows the time course of the gate current 38, also measured in amperes (A).The graph above shows the course of the gate-source voltage 18, measured in volts (V). The time axis (x-axis) is identical in all four graphs and extends across the entire width of the graph. Fig. 4. Time 20 is given in nanoseconds (ns). The drain-source current curve 34 shows how the drain-source current changes over time. The drain-source voltage curve 36 represents the drain-source voltage, which exhibits characteristic voltage spikes or transients during the operating cycles of the power semiconductor. The upper diagram shows the gate-source voltage 18 over time 20, which provides information about the switching state of the power semiconductor. All four diagrams show a short-circuit curve 40 and a short-circuit-free curve 42.

[0068] Furthermore, it shows Fig. 4. Initiation 2 of a predefined inrush current 54 within a time period between time t0 22 and t1 24. Within this period, the gate driver selects a predefined inrush current 54 of the gate in gate-shaping mode. Furthermore, in Fig. Figure 4 shows a time course between time t1 24 and time t5 32. During the time interval t1-t5, a first current injection 56 occurs through a first gate current 55, a second gate current 116, a third gate current 114, and a fourth gate current 118, where the first gate current 55 is chosen to be smaller than the specified inrush current 54, the second gate current 116 is chosen to be smaller than the first gate current 55, and the third gate current 114 is chosen to be larger than the second gate current 116, as shown in Figure 4. Fig. Figure 4 illustrates how to achieve stable switching behavior with optimized switching energy. Furthermore, in Fig. Figure 4 shows a plateau start voltage 70, which is relevant, for example, for gate charge calculation or measurement. The plateau start voltage 70 is used to calculate the gate charge of the second gate current 116 and the third gate current 114 in the gate driver in gate-shaping mode. During the time interval t1-t5, a first current injection 56 occurs, so that a fourth gate current 118, which is selected, for example, such that the gate-source voltage rises slightly, such that the value of the gate-source voltage is greater than the plateau end voltage 66 and less than the nominal gate turn-on voltage 68, in order to limit the maximum value of the peak short-circuit current 98.1. Furthermore, in Fig. Figure 4 shows a time course between time t5 32 and time t6 102. Within the time interval t5-t6, a second current injection 58 of a holding gate current 80 occurs. The holding gate current 80 is injected such that the gate-source voltage is maintained at a first constant level 62.1. While the gate-source voltage is maintained at a first constant level 62.1, a short-circuit detection 10 occurs. In the event of a short-circuit detection, the power semiconductor and / or the power module is switched off during the time interval t6-t7 (see short-circuit curve 40). In the event of a short-circuit detection, the power semiconductor and / or the power module is switched off 13. This process is described in Fig. Figure 4 shows a forming process 60 of a simple forming process 86. In Fig. Figure 4 shows that the forming process 60 is initiated by a first discharge gate current 84. Furthermore, if no short circuit detection occurs, as in Fig. Figure 4 shows that the current increase is raised by an injection, so that a maximum gate current of 78V is reached. This is injected in such a way that a nominal gate turn-on voltage of 68V is achieved. Furthermore, Figure 4 shows that the current rise is increased by an injection, so that a maximum gate current of 78V is reached. Fig. 4 a time course between time t7 104 and t8 110. During the time interval t7-t8, if a short circuit is detected, as shown in the short-circuit curve 40, the gate current iG is set to 0 A, whereby the gate-source voltage is discharged to a continuous turn-off voltage 76. In the case of no short circuit, a third current injection 82 of a holding gate current 80 occurs such that the gate-source voltage is held at a second constant level 62.2 and the gate-source voltage is maintained at the nominal gate turn-on voltage 68.

[0069] Fig. Figure 5 shows a schematic representation of an eight-stage gate forming with a two-stage switching-on with and without short circuit and a triple forming in case of short circuit.

[0070] Fig. Figure 5 also shows a schematic representation of superimposed diagrams depicting the time course of various electrical quantities. A time 20 is plotted on a horizontal axis (x-axis), corresponding to time t0 22, time t1 24, time t2 26, time t3 28, time t4 30, time t5 32, time t6 102, time t7 104, time t8 110, time t9 122, and time t 10The graph has 124, while a vertical axis (y-axis) represents the respective measured quantities of the diagrams. The following diagrams, from bottom to top, are as follows: The bottom diagram shows the time course of the drain-source current 34, measured in amperes (A). Immediately above it is the diagram of the time course of a drain-source voltage 36, measured in volts (V). The next diagram shows the time course of the gate current 38, also measured in amperes (A). At the top is the diagram of the gate-source voltage 18, measured in volts (V). The time axis (x-axis) is identical for all four diagrams and extends across the entire width of the graph. Fig. 5. Time 20 is given in nanoseconds (ns). The drain-source current curve 34 shows how the drain-source current changes over time. The drain-source voltage curve 36 represents the drain-source voltage, which exhibits characteristic voltage spikes or transients during the operating cycles of the power semiconductor. The upper diagram shows the gate-source voltage 18 over time 20, which provides information about the switching state of the power semiconductor. All four diagrams show a short-circuit curve 40 and a short-circuit-free curve 42.

[0071] Furthermore, it shows Fig. 5. Initiation 2 of a predefined inrush current 54 within a time period between time t0 22 and t1 24. Within this period, the gate driver selects a predefined inrush current 54 of the gate in gate-shaping mode. Furthermore, in Fig. Figure 5 shows a time course between time t1 24 and time t5 32. During the time interval t1-t5, a first current injection 56 occurs through a first gate current 55, a second gate current 116, a third gate current 114, and a fourth gate current 118, where the first gate current 55 is chosen to be smaller than the specified inrush current 54, the second gate current 116 is chosen to be smaller than the first gate current 55, and the third gate current 114 is chosen to be larger than the second gate current 116, as shown in Figure 5. Fig. 5 shown, to achieve stable switching behavior with optimized switching energy. Furthermore, in Fig. Figure 5 shows a plateau start voltage 70, which is relevant, for example, for gate charge calculation or measurement. The plateau start voltage 70 is used to calculate the gate charge of the second gate current 116 and the third gate current 114 in the gate driver in gate-shaping mode. During the time interval t1-t5, a first current injection 56 occurs, so that a fourth gate current 118, which is selected, for example, such that the gate-source voltage rises slightly, is applied. This ensures that the gate-source voltage is greater than the plateau end voltage 66 and less than the nominal gate turn-on voltage 68, in order to limit the maximum value of the peak short-circuit current 98.1. Furthermore, in Fig. Figure 5 shows a time course between time t5 32 and time t6 102. Within the time interval t5-t6, a second current injection 58 of a holding gate current 80 occurs. The holding gate current 80 is injected such that the gate-source voltage is maintained at a first constant level 62.1. While the gate-source voltage is maintained at a first constant level 62.1, a short-circuit detection 10 takes place. In the event of a short circuit detection, the power semiconductor and / or the power module is switched off during the time interval t6-t9 (see short-circuit curve 40). The switch-off process is characterized by a forming process 60, which has a triple forming action. Fig. Figure 5 illustrates the forming process 60 by a first discharge gate current 84, a second discharge gate current 106, and a third discharge gate current 108. The current intensity of the discharge gate currents 84, 104, and 106 increases successively. Furthermore, in Fig. 5. In a short-circuit-free state 42 of the gate-source current 38, an increase in the gate current occurs due to an injection, such that a maximum gate current 78 is reached. This is injected in such a way that the nominal gate turn-on voltage 68 is reached. Furthermore, it shows Fig. 5 a time course between time t9 122 and t 10 124. During the time interval t9-t 10In the event of a detected short circuit, as shown in the short-circuit diagram 40, the gate current iG is set to 0 A, whereby the gate-source voltage is discharged to a continuous turn-off voltage 76. In the case of no short circuit, a third current injection 82 of a holding gate current 80 occurs such that the gate-source voltage is maintained at a second constant level 62.2 and the gate-source voltage is maintained at the nominal gate turn-on voltage 68.

[0072] The following section outlines further parameters that are considered in the Fig. Reference is made to sections 2 to 5. The parameters mentioned are used, for example, in the calculation of required gate charges and corresponding times, which in turn are used to determine gate currents.

[0073] In the Fig. Figures 2 to 5 show a gate voltage at phase current 72, which can be used, for example, for gate charge calculation or measurement. Such a calculation or measurement is relevant, for example, for the gate current or gate currents during the first current injection 56. Furthermore, in the Fig. Figures 2 to 5 illustrate a threshold voltage 74. The threshold voltage 74 represents a parameter in the calculation or measurement of a gate charge, which occurs during the injection of a predefined inrush current 54 into the Fig. 4 and Fig. 5 is determined. Furthermore, in the Fig. Figures 2 to 5 show a maximum drain-source voltage 88 during the shutdown process after a short circuit. For example, the maximum drain-source voltage 88 during the shutdown process after a short circuit can be used to design a forming process 60. In addition, a battery voltage 90 is also shown, which is used during an initial current injection 56 to calculate a voltage communication time in the Fig. 4 and Fig. 5 can be used. The voltage communication time refers to the time interval in which a first current injection 56 into Fig. 4 and Fig. 5. Furthermore, a drain-source voltage 92 during current commutation during the normal switching process is also shown, which is relevant for calculating or measuring a gate charge in voltage commutation during the first current injection 56. In the Fig. 2 to 5 also includes a peak short-circuit current of 98.1 and in the Fig. 3 and Fig. Figure 5 additionally shows a peak disconnect current 98.2. The peak short-circuit current 98.1 is relevant for the peak disconnect current 98.2. The peak disconnect current 98.2 is calculated, for example, as 30% of the peak short-circuit current 98.1. For a calculation of the times t4 30 in Fig. 3 and t7 104 in Fig. 5 requires a peak current of 98.2.

[0074] Furthermore, in the Fig. Figures 2 to 5 show a maximum drain-source current of 99 during normal operation. This maximum drain-source current is important for calculating or measuring the gate charge, which is then relevant for calculating the gate current of a gate driver. Fig. Figures 2 to 5 additionally show a phase current 100 and a drain-source voltage 120 between the phase current 100 and the maximum drain-source current 99, wherein a phase current 100 is used, for example, during the current commutation time of the method according to the invention, namely for injecting gate currents or a gate current during a first current injection 56. The drain-source voltage 120 is used, for example, to calculate the gate charge in the gate driver in a voltage commutation phase within the time interval during the first current injection 56.

[0075] Fig. Figure 6 shows a schematic representation of an optimization process 130 of switching losses and conduction losses of two power semiconductors. Fig. Figure 6 illustrates the process and decision-making. The optimization 130 begins with a gate-forming module 132. The gate-forming module 132 is assigned the following input parameters: a reference layer temperature 131, an instantaneous phase current 133, a battery voltage 134, an estimated junction temperature A 150.1, and an estimated junction temperature B 150.2. The gate-forming module 132 uses the estimated junction temperatures A 150.1 and B 150.2, the instantaneous phase current 133, and the battery voltage 134 as input parameters. Considering the dependence of the threshold voltage, plateau voltage, and on-resistance on a junction temperature, a battery voltage, and the instantaneous phase current 133, the gate-source voltages for both power semiconductors are calculated, and a gate current profile A 136.1 and a gate current profile B 136.2 are generated. The gate current profile A 136.1 and the gate current profile B 136.2 are then supplied to the power module 138.The gate current profiles A and B 136.1, 136.2 generate switching losses 140 and conduction losses 142 in the power module 138 at a battery voltage 134, an instantaneous phase current 133, and junction temperatures A 150.1 and B 150.2. The total power loss 144 is calculated from the switching losses and conduction losses. Based on the power loss, the junction temperatures 150.1 and 150.2 are estimated using the junction temperature estimator 148. Subsequently, the gate current profiles A 136.1 and B 136.2 are adjusted to compensate for switching losses and conduction losses by a gate forming module 132 until a difference between the estimated junction temperature A 150.1 and the estimated junction temperature B 150.2 is reduced to a value of, for example, less than 3 Kelvin and both the estimated junction temperature A 150.1 and the estimated junction temperature B 150.2 are below the reference junction temperature 131.

[0076] Fig. Figure 7 shows a schematic representation of a five-stage gate forming of two power semiconductors 152.1, 152.2 during a gate driver turn-on process. For example, power semiconductor A 152.1 exhibits a higher power output than power semiconductor B 152.2. Fig. Figure 7 also shows a schematic representation of superimposed diagrams depicting the time course of various electrical quantities. A horizontal axis (x-axis) plots time 20, which includes time points t0 22, t1 24, t2 26, t2 28, t4 30, and t5 32, while a vertical axis (y-axis) represents the respective measured quantities in the diagrams. The following diagrams, from bottom to top, show the time course of energy 156 in millijoules. Above this is a time course of power 154 in watts. Immediately above this is the diagram of the time course of drain-source voltage 36, measured in volts (V). Above this is a diagram of drain-source current 34, measured in amperes (A).The next diagram shows the time course of the gate current 38, also measured in amperes (A). Above is the diagram of the gate-source voltage 18, measured in volts (V). The time axis (x-axis) is identical in all four diagrams and extends across the entire width of the graph. Fig. 7. The time 20 is given in nanoseconds (ns).

[0077] Furthermore, in Fig. Figure 7 shows an initiation 2 of a predefined inrush current A 54.1 and a predefined inrush current B 54.2 between time t0 22 and time t1 24. The initiation 2 is carried out such that the predefined inrush current A 54.1 and the predefined inrush current B 54.2 are set such that the two power semiconductors A 152.1 and B 152.2 have the same switching speed during a first current injection 56, namely a current commutation. As a result, the power semiconductors A 152.1 and B 152.2 exhibit the same current slew rates and the same maximum drain-source current A 99.1 and B 99.2 during current commutation, and therefore also the same first switching energy A 172.1 and B 172.2 for each power semiconductor. The currents per power semiconductor A 152.1 and B 152.2.However, the two phase currents during a voltage switch are different, as defined by a second phase current A 160.1 and a second phase current B 160.2, since the gate currents per power semiconductor A 152.1 and B 152.2 are not matched. Furthermore, in . Fig. Figure 7 shows a time sequence between time t1 24 and time t2 26. During the time interval t1-t2, an initial current injection 56 occurs through a first gate current A 55.1 and a first gate current B 55.2, which is chosen, for example, such that the gate-source voltage increases slightly, so that the value of the gate-source voltage is greater than a plateau end voltage A 66.1 and a plateau end voltage B 66.2 and less than a nominal gate turn-on voltage A 68.1 and a nominal gate turn-on voltage B 68.2, in order to limit the maximum value of the peak short-circuit current 98.1 and the peak turn-off current 98.2. The first gate current A 55.1 and the first gate current B 55.2 are set to different values, so that both power semiconductors A 152.1 and power semiconductor B 152.2 simultaneously generate an associated gate-source voltage A 64 during a first constant level 62.1 in a two-stage turn-on process.1 and a gate-source voltage B 64.2. The gate-source voltage A 64.1 and the gate-source voltage B 64.2 have different values ​​to balance the drain-source currents and reduce the difference between the third and fourth switching energies A 174.1, 176.1 and the third and fourth switching energies B 174.2, 176.2 between the power semiconductors A 152.1 and B 152.2. In . Fig. Figure 7 also shows a plateau start voltage A 70.1 and a plateau start voltage B 70.2. Additionally, in Fig. Figure 7 shows a time course between time t2 26 and time t3 28. During this time, a hold gate current A 80.1 and a hold gate current B 80.2 are equal in magnitude and set to the minimum output gate current of the gate driver to ensure that no charging of the gate-source voltage occurs during this time.

[0078] The gate-source voltage B64.2 is chosen such that it is greater than the plateau end voltage B66.2 to ensure that a switching operation can be completed, and less than a nominal gate turn-on voltage B68.2 to limit the peak short-circuit current 98.1. Similarly, the gate-source voltage A64.1 is chosen. During this time, the gate-source voltage B64.2 is greater than the gate-source voltage A64.1 to compensate for the short-circuit current in the event of a short circuit. Short-circuit detection 10 takes place during the time interval between time t2 26 and time t3 28. Furthermore, it shows Fig. 7 the time course between times t3 28 and t4 30. Within this period, the gate-source voltage B 64.2 is greater than the gate-source voltage A 64.1 so that both power semiconductors A 152.1 and B 152.2 simultaneously reach the nominal gate turn-on voltage A 68.1 and the nominal gate turn-on voltage B 68.2. The nominal gate turn-on voltage B 68.2 is chosen to be slightly higher than a nominal gate turn-on voltage A 68.1 so that the turn-on drain-source resistances for both power semiconductors A 152.1 and B 152.2 are equal in order to compensate for the conduction losses according to an optimization 130. Furthermore, it shows Fig. 7 the time course between times t4 30 and t5 32. During this time, the gate current profiles A 136.1 and B 136.2 are set to the minimum holding gate current A 80.1 and B 80.2 to ensure that no charging of the gate-source voltage takes place during this time and that the line losses are compensated.

[0079] Fig. Figure 8 shows a schematic representation of an eight-stage gate forming process of two power semiconductors A 152.1 and B 152.2 during a gate driver turn-on process. For example, power semiconductor A 152.1 exhibits a faster power output than power semiconductor B 152.2. Fig. Figure 8 also shows a schematic representation of superimposed diagrams depicting the time course of various electrical quantities. A horizontal axis (x-axis) plots time 20, which includes time points t0 22, t1 24, t2 26, t2 28, t4 30, t5 32, t6 102, t7 104, and t8 110, while a vertical axis (y-axis) represents the respective measured quantities in the diagrams. The following diagrams, from bottom to top, show: The bottom diagram depicts the time course of energy 156 in millijoules. Above this is a time course of power 154 in watts. Immediately above this is the diagram of the time course of drain-source voltage 36, measured in volts (V). The graph shows the drain-source current 34, measured in amperes (A).The next diagram shows the time course of the gate current 38, also measured in amperes (A). At the very top is the diagram of the gate-source voltage 18, measured in volts (V). The time axis (x-axis) is identical in all four diagrams and extends across the entire width of the graph. Fig. 8. The time 20 is given in nanoseconds (ns).

[0080] Furthermore, in Fig. Figure 8 shows an initiation 2 of a predefined inrush current A 54.1 and a predefined inrush current B 54.2 between time t0 22 and time t1 24. Initiation 2 is carried out such that the predefined inrush current A 54.1 and the predefined inrush current B 54.2 are set such that the predefined inrush current B 54.2 is greater than the predefined inrush current A 54.1, such that the gate-source voltage of the two power semiconductors A 152.1 and B 152.2 simultaneously reaches a threshold voltage A 74.1 and a threshold voltage B 74.2. Furthermore, in Fig. Figure 8 shows a time sequence between time t1 24 and time t2 26. During this time, the power semiconductor A 152.1 and the power semiconductor B 152.2 exhibit a first gate current A 55.1 and first gate current B 55.2 with similar switching energies, as shown in the diagram in Fig. 8 with a profile of energy over a time interval between time t1 24 and time t2 26, in order to obtain an optimal current rise rate of the logic switch. Additionally, in Fig. Figure 8 shows a time course between time t2 26 and time t3 28. During this time, a second gate current A 116.1 and a second gate current B 116.2 are shown, such that the second gate current B 116.2 is larger than the second gate current A 116.1, such that the gate-source voltage simultaneously reaches a plateau start voltage A 70.1 and a plateau start voltage B 70.2. During this time, the second gate current A 116.1 is further reduced compared to the second gate current B 116.2 to obtain an optimal maximum reverse recovery current and an optimal reverse recovery charge of a diode on one complementary side. Furthermore, Figure 8 shows... Fig. Figure 8 shows the time course between times t3 28 and t4 30. During this time, a third gate current A 114.1 and a third gate current B 114.2 are reduced such that the third gate current B 114.2 is smaller than the third gate current A 114.1, so that the gate-source voltage simultaneously reaches a plateau end voltage A 66.1 and a plateau end voltage B 66.2. This results in a similar voltage drop rate. The third gate current A 114.1 is slightly higher than the third gate current B 114.2 during this time to achieve an optimal drain-source voltage drop rate. Additionally, Figure 8 shows that... Fig. Figure 8 describes the time course between times t4 30 and t5 32. During this period, a fourth gate current A 118.1 and a fourth gate current B 118.2 are applied. The fourth gate current B 118.2 is larger than the fourth gate current A 118.1, resulting in a gate-source voltage A 64.1 and a gate-source voltage B 64.2 at the power semiconductors A 152.1 and B 152.2, respectively, of a first constant level 62.1. During this time, the fourth gate current A 118.1 is selected to allow for a slight increase in the gate-source voltage, if necessary, so that the gate voltage can reach the value of the gate-source voltage A 64.1. The fourth gate current B 118.2 is chosen such that the gate-source voltage is greater than the plateau end voltage B 66.2 so that a switching operation can be completed, and is less than the nominal gate turn-on voltage 68.2 to limit the peak current, for example during a short circuit.Similarly, the fourth gate current A 118.1 is chosen. The gate-source voltage A 64.1 is chosen to be smaller than the gate-source voltage B 64.2 to balance the first phase current A 100.1 and the first phase current B 100.2 during normal operation and to compensate for short-circuit currents in the event of a short circuit. A third switching energy A 174.1 and a third switching energy B 174.1 of the two power semiconductors A 152.1 and B 152.2 at the end of the step between t4 30 and t5 32 are equal. Furthermore, [the following appears to be unrelated and possibly a separate document:] . Fig. 8 the time course between times t5 32 and t6 102. During this time, a holding gate current A 80.1 and a holding gate current B 80.2 are equal in magnitude, so that the gate voltage for the two power semiconductors A 152.1 and B 152.2 remains constant without further charging. One gate current is set, for example, to a few tens of milliamperes. In this step, short-circuit detection 10 takes place. Furthermore, it shows Fig. 8 the time course between times t6 102 and t7 104. Within the time course between times t6 102 and t7 104, the gate-source voltage B 64.2 is greater than the gate-source voltage A 64.1, so that both power semiconductors A 152.1 and B 152.2 simultaneously reach the nominal gate turn-on voltage A 68.1 and the nominal gate turn-on voltage B 68.2.

[0081] Furthermore, it shows Fig. The time course between times t7 104 and t8 110. During this time, a holding gate current A 80.1 and a holding gate current B 80.2 with the same current value are injected. The nominal gate turn-on voltage B 68.2 is greater than the nominal gate turn-on voltage A 68.1 so that both power semiconductors A 152.1 and B 152.2 exhibit similar conduction losses.

[0082] In Fig. Figure 8 additionally shows a waveform during gate forming, depicting changes in switching power (164.1, 164.2, 164.1, 165.2, 166.1, 166.2, 168.1, 168.2 and 170.1, 170.2) at the respective gate current injections. Additionally, Figure 36 shows a waveform of the drain-source voltage during gate forming, depicting changes in drain-source voltage (92.1, 92.2, 120.1, 120.2, 94.1, 94.2 and 96.1, 96.2) at the respective gate current injections.

[0083] Furthermore, in the Fig. 7 and Fig. Figure 8 shows a maximum drain-source current A99.1 and a maximum drain-source current B99.2. Also shown are a drain-source voltage A120.1 between the phase current and the maximum drain-source current, and a drain-source voltage B120.2 between the phase current and the maximum drain-source current. The drain-source voltage A120 between the phase current and the maximum drain-source current is used, for example, to calculate the gate charge in the gate driver during a voltage commutation phase within the time interval during the first current injection 56.

[0084] Fig. Figure 9 schematically shows a single-stage gate forming of two power semiconductors A 152.1 and B 152.2 during a gate driver turn-off process. For example, power semiconductor A 152.1 exhibits a faster power output than power semiconductor B 152.2. The individual turn-off gate currents and turn-off gate-source voltages, turn-off drain-source currents, turn-off drain-source voltages A, B 198.1, 198.2, 200.1 and 200.2, as well as instantaneous powers A 202.1 and B 202.2 and turn-off energies of the two power semiconductors A 152.1 and B 152.2, are shown over a period between time t0 22 and time t1 24. The bottom diagram shows the time course of an energy 156 in millijoules. Above this is a graph showing the time course of a power output of 154 watts. Directly above this is a graph showing the time course of a drain-source voltage of 36, measured in volts (V).The first diagram shows the drain-source current 34, measured in amperes (A). The next diagram shows the time course of the gate current 38, also measured in amperes (A). At the very top is the diagram of the gate-source voltage 18, measured in volts (V). The time axis (x-axis) is identical in all four diagrams and extends across the entire width of the graph. Fig. 9. The time 20 is given in nanoseconds (ns).

[0085] During a period between time t0 22 and time t1 24, a shutdown gate current A 192.1 and a shutdown gate current B 192.2 are impressed such that shutdown gate current A 192.1 is greater than shutdown gate current B 192.2, so that the gate-source voltage of the two power semiconductors A 152.1 and B 152.2 simultaneously reaches a shutdown plateau start voltage A 184.1 and a shutdown plateau start voltage B 184.2. This reduces the shutdown delay of the logic switch. During the voltage change, however, the turn-off current A 196.1 and the turn-off current B 196.2 differ because the gate currents are not matched, resulting in a difference in the turn-off energies A 206.1 and B 206.2. A similar situation arises during the current commutation phase, where a difference occurs between a turn-off energy A 204.1 and a turn-off energy B 204.2 because the gate current profiles A 136.1 and B 136.2 are not matched.

[0086] Fig. Figure 10 schematically shows a four-stage gate-forming process of two power semiconductors A 152.1 and B 152.2 during a gate driver turn-off process. For example, power semiconductor A 152.1 exhibits a faster power output than power semiconductor B 152.2. Fig. Figure 10 also shows a schematic representation of superimposed diagrams depicting the time course of various electrical quantities. A horizontal axis (x-axis) represents time 20, with time points t0 22, t1 24, t2 26, t3 28, and t4 30, while a vertical axis (y-axis) represents the respective measured quantities in the diagrams. The following diagrams, from bottom to top, show: The bottom diagram shows the time course of energy 156 in millijoules. Above this is a time course of power 154 in watts. Immediately above this is the diagram of the time course of drain-source voltage 36, measured in volts (V). Above this is a diagram of drain-source current 34, measured in amperes (A). The next diagram shows the time course of gate current 38, also measured in amperes (A).At the top is the diagram showing the course of the gate-source voltage 18, measured in volts (V). The time axis (x-axis) is identical in all four diagrams and extends across the entire width of the graph. Fig. 10. The time 20 is given in nanoseconds (ns).

[0087] During a time interval between time t0 22 and time t1 24, a shutdown gate current A 192.1 and a shutdown gate current B 192.2 are impressed such that the shutdown gate current A 192.1 is greater than the shutdown gate current B 192.2 and has a shutdown drain current A 194.1 and a shutdown drain current B 194.2, so that the gate-source voltage of the two power semiconductors A 152.1 and B 152.2 simultaneously reaches a shutdown plateau start voltage A 184.1 and a shutdown plateau start voltage B 184.2. During a time interval between time t1 24 and time t2 26, a shutdown gate current A 193.1 and a shutdown gate current B 193.2 are set such that the shutdown gate current A 193.1 is greater than the shutdown gate current B 193.2, thereby reaching a shutdown plateau voltage A 186.1 and a shutdown plateau voltage B 186.2. This ensures that the two power semiconductors A 152.1 and B 152.Two similar switching energies are present, as shown by turn-off energy A 206.1 and turn-off energy B 206.2. During a time interval between time t2 26 and time t3 28, a turn-off gate current A 191.1 and a turn-off gate current B 191.2 are impressed such that the turn-off gate current A 191.1 is smaller than the turn-off gate current B 191.2, so that the gate-source voltage of the power semiconductors A 152.1 and B 152.2 simultaneously reaches a turn-off threshold voltage A 188.1 and a turn-off threshold voltage B 188.2. During a time interval between time t3 28 and time t4 30, a shutdown gate current A 189.1 and a shutdown gate current B 189.2 are impressed such that the shutdown gate current A 189.1 is smaller than the shutdown gate current B 189.2, so that the gate-source voltage of the power semiconductors A 152.1 and B 152.2 simultaneously reaches a shutdown threshold voltage A 190.1 and a shutdown threshold voltage B 190.2.

[0088] The invention is not limited to the embodiments described here and the aspects highlighted therein. Rather, within the scope specified by the claims, a multitude of modifications are possible that fall within the bounds of what is considered skilled in the art. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] WO 2023046607A1

[0002] US 2023 / 126 070 A1 [0003, 0004]

Claims

[1] Method (1) for optimizing and compensating the switching losses, conduction losses and short-circuit withstand capability of at least one power semiconductor (152.1, 152.2) and / or one power module (138) in a logic switch comprising a two-stage turn-on, a gate, a drain and a source, at least one gate driver providing multi-stage gate forming, wherein the method (1) comprises at least the following steps: i. Initiating (2) a predefined inrush current (54) of the gate by the gate driver, ii. Performing (4) a first current injection (56) by means of at least one injection of at least one first gate current (55), wherein, in the case of multiple injections of several gate currents (55, 116, 114, 118), the gate currents (55, 116, 114, 118) are different, wherein a final injection of the first current injection (56) is performed by a final gate current set such that the value of a gate-source voltage is greater than a plateau end voltage (66) and less than a nominal gate turn-on voltage (68), iii. Performing (8) a second current injection (58) of a holding gate current (80), wherein the holding gate current (80) is injected such that the gate-source voltage is maintained at a first constant level (62.1) and during this time a short-circuit detection (10) is performed and, in the event of a detected short circuit, a procedure step iv. is initiated, wherein, in the event of a missing short circuit, procedure steps v. and vi. are initiated. iv. Switching off (13) the power semiconductor and / or the power module, wherein a switch-off process (13) is initiated which includes a number of forming processes (60), v. Applying (14) a maximum gate current (78), wherein the maximum gate current (78) is supplied such that the nominal gate turn-on voltage (68) is reached, and vi. Performing (16) a third current injection (82) of a hold gate current (80), wherein the hold gate current (80) is applied such that the gate source voltage is held at a second constant level (62.2) and the gate source voltage is maintained at the nominal gate turn-on voltage (68). [2] Method (1) according to claim 1, wherein the gate driver is operated in constant current followed by a two-stage turn-on. [3] Method (1) according to claim 1 or 2, wherein the gate driver is operated in gate-shaping mode GS, followed by a two-stage turn-on. [4] Method (1) according to one of the preceding claims, wherein a first current injection (56) according to step ii. is carried out by a first gate current (55), a second gate current (116), a third gate current (114) and a fourth gate current (118), wherein the first gate current (55) is selected to be smaller than the predetermined inrush current (54), the second gate current (116) is selected to be smaller than the first gate current (55) and the third gate current (114) is selected to be larger than the second gate current (116). [5] Method (1) according to one of the preceding claims, wherein the forming process (60) is carried out by at least one forming of the gate current. [6] Method (1) according to claim 5, wherein the forming process (60) is carried out by forming which is initiated by a first discharge gate current (84), followed by a setting of the gate current iG to 0 A, wherein the gate source voltage is discharged to a continuous cut-off voltage (76). [7] Method (1) according to claim 6, wherein the forming process (60) is carried out by a single forming operation, wherein the single forming operation (86) is carried out by means of a first discharge gate current (84). [8] Method (1) according to claim 6, wherein the forming process (60) is carried out by a triple forming process, which is carried out by the first discharge gate current (84), a second discharge gate current (106) and a third discharge gate current (108), wherein a current intensity of the discharge gate currents (84, 106, 108) successively increases. [9] Method (1) according to one of the preceding claims, wherein an optimization and compensation of switching losses, conduction losses and short-circuit strength is carried out when the logic switch comprises at least two power semiconductors (152.1, 152.2) and / or power modules (138) with at least two power semiconductors. [10] Method (1) according to claim 10, wherein the optimization and compensation of switching losses and conduction losses and the short-circuit strength is achieved by adjusting the amplitudes of gate currents and time intervals, with at least the following steps while compensating the junction temperatures: a. Estimation (148) of junction temperatures of each power semiconductor (152.1, 152.1), b. Determining a reference junction temperature (131), c. Calculate at least one gate-source voltage, d. Generating at least one gate current profile (136.1, 136.2), e. Balancing the at least one gate current profile (136.1, 136.2) by reducing the difference in the estimated junction temperatures (150.1, 150.2), wherein the balancing is carried out such that the estimated junction temperatures (150.1, 150.2) are below the reference junction temperature (131). [11] Method (1) according to one of the preceding claims, wherein the method (1) is carried out during a gate driver turn-on process and / or a gate driver turn-off process. [12] Use of the method (1) according to one of the preceding claims for controlling power semiconductors (152.1, 152.2), hybrid switches such as SiC MOSFETs and IGBTs in parallel, power modules with separate or common gates or of several parallel-connected power modules with common gates in an inverter.

Images