Three-phase t-type three-level inverter device and control method

Abstract

The application provides a three-phase T-type three-level inverter device and a control method, the method comprising: using SiC-IGBT to replace traditional Si-IGBT to improve its withstand voltage and high-temperature stability, and combining Si-MOSFET to construct a hybrid switching structure, using the low conduction loss characteristic of Si-MOSFET at light load to complement the high efficiency performance of SiC-IGBT at heavy load. Secondly, a discrete-time mathematical model of the T-type three-level inverter is established. Then, the ChOA is improved based on composite chaotic mapping, dynamic convergence factor and dynamic position updating strategy, and the parameters in the FCS-MPC are optimized based on the improved ChOA. Finally, according to the updated optimal control parameters, the multi-objective high-performance control of the T-type three-level inverter is realized based on the FCS-MPC. Thus, the collaborative optimization of current tracking, midpoint voltage balance, common-mode voltage control and switching loss suppression is realized.

Description

Technical Field

[0001] This application relates to the field of inverters, and more particularly to a three-phase T-type three-level inverter device and control method. Background Technology

[0002] As a crucial energy conversion hub connecting new energy power generation systems and the power grid, the performance of inverters directly impacts the stability, efficiency, and power quality of the entire power system. Among various inverter topologies, the T-type three-level inverter, with its higher voltage and power level adaptability, has become a hot research topic in high-voltage, high-power inverters. In the application of high-voltage, high-power inverters, the T-type three-level inverter not only has lower grid-connected current harmonics but also effectively reduces electromagnetic interference levels. However, the T-type three-level inverter circuit topology has an inherent defect of DC-side neutral point potential imbalance. Its control methods often struggle to comprehensively consider multiple factors such as grid current, neutral point voltage, and common-mode voltage, and the control accuracy needs further improvement. How to optimize the inverter's control accuracy and comprehensively coordinate and optimize multiple factors has become a key issue in improving the overall performance of the inverter. Summary of the Invention

[0003] The purpose of this application is to provide a three-phase T-type three-level inverter device and control method, which achieves synergistic optimization of current tracking, neutral point voltage balance, common-mode voltage control and switching loss suppression, and provides an efficient and reliable solution for multi-objective synergistic optimization control of T-type three-level inverters.

[0004] To achieve the above objectives, this application provides a three-phase T-type three-level inverter device, comprising: a three-phase bridge arm, wherein each phase bridge arm includes at least four hybrid switching units; at least two hybrid switching units in the horizontal direction of each phase bridge arm form two sets of symmetrical series branches through internal switching components, wherein the series branches consist of at least two internal switching components of the same type, and the two sets of series branches are connected in parallel and connected to the midpoint of the DC-side capacitor; wherein the hybrid switching unit is composed of two types of internal switching components: SiC-IGBT and Si-MOSFET.

[0005] In the aforementioned inverter device, optionally, the number of internal switching components in the two sets of series branches is equal.

[0006] In the above-mentioned inverter device, optionally, the emitter of the SiC-IGBT and the source of the Si-MOSFET are connected to the AC output terminal, and the collector of the SiC-IGBT and the drain of the Si-MOSFET are connected to the DC bus.

[0007] In the aforementioned inverter device, optionally, the hybrid switching unit in the vertical direction of each phase arm of the three-phase bridge arm is composed of SiC-IGBT and Si-MOSFET connected in parallel.

[0008] This application also provides a control method applied to the aforementioned three-phase T-type three-level inverter device. The method includes: constructing a discrete-time mathematical model based on the three-phase T-type three-level inverter device; constructing an objective function through the discrete-time mathematical model, and adjusting the parameters in the FCS-MPC algorithm using an improved Chimp Optimization Algorithm (ChOA) to obtain an adjusted FCS-MPC algorithm; calculating second sampled data after a preset period based on first sampled data of the three-phase T-type three-level inverter device using the adjusted FCS-MPC algorithm; obtaining multiple objective function values ​​based on the first sampled data and the second sampled data through the objective function, and filtering the objective function values ​​to obtain corresponding control switch sequences; controlling the three-phase T-type three-level inverter device through the control switch sequences; wherein the multiple objective function values ​​respectively correspond to the switching action sequences of the hybrid switching units in the three-phase T-type three-level inverter device.

[0009] In the above control method, optionally, constructing a discrete-time mathematical model based on the three-phase T-type three-level inverter device includes: constructing a corresponding dynamic model based on the state of the three-phase T-type three-level inverter device connected to the grid through a common coupling point; obtaining a dynamic model in the coordinate system by Clarke transformation of the dynamic model, and discretizing the dynamic model in the coordinate system using the forward Euler method to obtain a grid current prediction model; obtaining a grid current reference model based on the grid current prediction model and the Lagrange extrapolation theorem, and constructing a neutral point voltage model based on the balance influence of different capacitor parameters and different loads on the DC-side capacitor voltage; and obtaining a discrete-time mathematical model based on the grid current prediction model and the neutral point voltage model.

[0010] Optionally, in the above control method, the improved chimpanzee algorithm includes: increasing the diversity of the initial population in the chimpanzee algorithm through the Fuch-Circle composite chaotic mapping; and performing quasi-backward learning through individual chimpanzees based on the Fuch-Circle composite chaotic mapping results.

[0011] In the above control method, optionally, the improved chimpanzee algorithm includes: improving the convergence speed of the chimpanzee algorithm during the iterative process through a dynamic nonlinear convergence factor; the dynamic nonlinear convergence factor includes:

[0012] ;

[0013] Among them, gin Let be the initial convergence factor, with a value of 1.5, and l with a value of 0.05. t max The maximum number of iterations is given by , beta is the beta distribution function, and h and g are the beta distribution parameters, taking values ​​of 4 and 1 respectively.

[0014] Optionally, in the above control method, the improved chimpanzee algorithm includes: dynamically adjusting the distance between the individual chimpanzee and its prey through a periodic oscillation mechanism of a sine and cosine algorithm.

[0015] Optionally, in the above control method, adjusting the parameters in the objective function using an improved chimpanzee algorithm to obtain the adjusted FCS-MPC algorithm includes: adjusting the prediction step size and weight system parameters in the objective function using an improved chimpanzee algorithm to obtain the adjusted FCS-MPC algorithm.

[0016] In the above control method, optionally, obtaining the corresponding control switch sequence based on the objective function value includes: selecting the switch action sequence corresponding to the smallest objective function value based on the objective function value, and generating a control switch sequence.

[0017] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-described method.

[0018] This application also provides a computer-readable storage medium storing a computer program that performs the above-described methods.

[0019] This application also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the above-described method.

[0020] This application can significantly improve the efficiency of inverters. SiC-IGBTs, with their higher switching frequency, lower switching losses, and superior thermal performance, enable the inverter to operate stably even under high voltage and high temperature environments. The improved Gorilla algorithm in this application also makes the solution space distribution more reasonable, laying the foundation for rapid convergence. Its fast and accurate convergence characteristics allow the algorithm to quickly lock the optimal solution neighborhood when optimizing the prediction step size and weight coefficients of FCS-MPC, and to obtain better parameter combinations through fine-grained search, thus exhibiting optimal comprehensive optimization performance. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, do not constitute a limitation thereof. In the drawings:

[0022] Figure 1 This is a schematic diagram of the circuit topology of a three-phase T-type three-level inverter device provided in an embodiment of this application;

[0023] Figure 2A This is a schematic diagram of the control method provided in an embodiment of this application;

[0024] Figure 2B This is a schematic diagram illustrating the principle of a control method provided in an embodiment of this application;

[0025] Figure 3 This is a schematic diagram of the discrete-time mathematical model construction process provided in an embodiment of this application;

[0026] Figure 4 A schematic diagram comparing the iterative convergence results of the control method provided in an embodiment of this application with those of existing control logic;

[0027] Figure 5 This is a schematic diagram comparing the output current and the reference current of a control method provided in an embodiment of this application.

[0028] Figure 6 A schematic diagram of the DC-side capacitor voltage change waveform of a control method provided in an embodiment of this application;

[0029] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0030] The following will describe in detail the implementation methods of this application with reference to the accompanying drawings and embodiments, so as to fully understand how this application uses technical means to solve technical problems and achieve technical effects, and to implement it accordingly. It should be noted that, as long as there is no conflict, the various embodiments and features in each embodiment of this application can be combined with each other, and the resulting technical solutions are all within the protection scope of this application.

[0031] Furthermore, the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0032] Please refer to Figure 1As shown, the three-phase T-type three-level inverter device provided in this application includes: a three-phase bridge arm, wherein each phase bridge arm contains at least four hybrid switching units; at least two hybrid switching units in the horizontal direction of each phase bridge arm form two sets of symmetrical series branches through internal switching components, wherein the series branches consist of at least two internal switching components of the same type, and the two sets of series branches are connected in parallel and connected to the midpoint of the DC-side capacitor; wherein the hybrid switching unit is composed of two types of internal switching components: SiC-IGBT and Si-MOSFET.

[0033] In this embodiment, the number of internal switching components in the two sets of series branches is equal. Furthermore, the emitter of the SiC-IGBT and the source of the Si-MOSFET are connected to the AC output terminal, and the collector of the SiC-IGBT and the drain of the Si-MOSFET are connected to the DC bus. In another embodiment, the hybrid switching unit in the vertical direction of each phase arm of the three-phase bridge arm is composed of SiC-IGBTs and Si-MOSFETs connected in parallel.

[0034] In practical applications, this application addresses the issues of high switching losses and poor high-temperature stability inherent in traditional Si-IGBTs. It replaces traditional Si-IGBTs with SiC-IGBTs to improve their voltage withstand capability and high-temperature stability, and combines them with Si-MOSFETs to construct a hybrid switching structure. This leverages the low conduction loss characteristic of Si-MOSFETs under light loads to complement the high efficiency of SiC-IGBTs under heavy loads. Compared to traditional Si-IGBTs, SiC-IGBTs exhibit lower on-state voltage drop and superior thermal performance, offering significant advantages in high-current and high-power applications. Due to the properties of SiC material, SiC-IGBTs can effectively reduce conduction losses under high-current conditions, and their enhanced high-temperature resistance allows for stable operation in harsh environments. Compared to traditional Si-IGBTs, SiC-IGBTs significantly improve system efficiency and reduce heat generation caused by conduction losses under high load conditions. Based on this, this application provides a hybrid switching T-type three-level inverter architecture based on SiC-IGBTs and Si-MOSFETs. The three-phase T-type three-level inverter mainly consists of three phase arms, each containing at least four hybrid switches. The two horizontal hybrid switches in each phase arm are designed with a "series-then-parallel" topology. Under light load conditions, current primarily flows through Si-MOSFETs, utilizing their low on-state voltage drop and low switching losses to optimize efficiency under light loads. Under high load and high current conditions, current flows through SiC-IGBTs. This hybrid switching scheme allows the system to flexibly adjust according to load conditions, maximizing power conversion efficiency and minimizing energy loss.

[0035] Specifically, the two hybrid switching units in the horizontal direction of each phase bridge arm are designed with a "series-then-parallel" topology. This can be understood as having two parallel branch structures in the horizontal direction of each phase bridge arm. Each branch structure contains two internal switching components of the same type connected in series, such as two Si-MOSFETs or two SiC-IGBTs. The series branch containing the two Si-MOSFETs and the series branch containing the two SiC-IGBTs are then connected in parallel and connected to the midpoint of the DC-side capacitor. It is important to note that the internal switching components (SiC-IGBT or Si-MOSFET) in the series branches must be of the same type. Conversely, if one series branch is determined to be a series connection of Si-MOSFET type internal switching components, the other series branch, based on the requirements of the hybrid switching unit, must be a series connection of SiC-IGBT type internal switching components. Thus, under light load conditions, the current mainly flows through the Si-MOSFETs, utilizing their low on-state voltage drop and low switching losses to optimize efficiency under light loads; while under high load and high current conditions, the current flows through the SiC-IGBTs. This hybrid switching scheme allows the system to adjust flexibly according to the load, maximizing power conversion efficiency and reducing energy loss.

[0036] Please refer to Figure 2A As shown, in one embodiment of this application, this application also provides a control method applied to the aforementioned three-phase T-type three-level inverter device, the method comprising:

[0037] S201: Construct a discrete-time mathematical model based on a three-phase T-type three-level inverter device;

[0038] S202: Construct an objective function using the discrete-time mathematical model, and adjust the parameters in the FCS-MPC algorithm using the improved chimpanzee algorithm to obtain the adjusted FCS-MPC algorithm;

[0039] S203: Based on the first sampled data of the three-phase T-type three-level inverter device, the second sampled data after a preset period is calculated by the adjusted FCS-MPC algorithm;

[0040] S204: Based on the first sampled data and the second sampled data, obtain multiple target function values ​​through the target function, and filter the target function values ​​to obtain the corresponding control switch sequence;

[0041] S205: Control the three-phase T-type three-level inverter device through the control switch sequence;

[0042] Among them, multiple objective function values ​​correspond to the switching action sequence of the hybrid switching unit in the three-phase T-type three-level inverter device.

[0043] In practical work, please refer to Figure 2B As shown, the control method provided in this application, when applied, firstly considers the problems of large switching losses and poor high-temperature stability of traditional Si-IGBTs, and uses SiC-IGBTs to replace traditional Si-IGBTs to improve their withstand voltage and high-temperature stability. It also combines Si-MOSFETs to construct a hybrid switching structure, utilizing the low conduction loss characteristics of Si-MOSFETs under light loads to complement the high efficiency of SiC-IGBTs under heavy loads. Secondly, a discrete-time mathematical model of the T-type three-level inverter is established. Then, the ChOA is improved based on composite chaotic mapping, dynamic convergence factor, and dynamic position update strategy, and the parameters in FCS-MPC are optimized based on the improved ChOA. Finally, based on the updated optimal control parameters, multi-objective high-performance control of the T-type three-level inverter is achieved using FCS-MPC. Therefore, the control strategy for the T-type three-level inverter can achieve synergistic optimization of current tracking, midpoint voltage balance, common-mode voltage control, and switching loss suppression, providing an efficient and reliable solution for multi-objective synergistic optimization control of the T-type three-level inverter. The specific implementation logic of each step will be described in detail in subsequent embodiments, and will not be elaborated here.

[0044] Please refer to Figure 3 As shown, in one embodiment of this application, constructing a discrete-time mathematical model based on a three-phase T-type three-level inverter device includes:

[0045] S301 constructs a corresponding dynamic model based on the state of the three-phase T-type three-level inverter device connected to the grid through a common coupling point;

[0046] S302 obtains the dynamic model in the coordinate system by Clarke transformation of the dynamic model, and then discretizes the dynamic model in the coordinate system by forward Euler method to obtain the power grid current prediction model.

[0047] S303 obtains a grid current reference model based on the Lagrange extrapolation theorem through the grid current prediction model, and constructs a neutral point voltage model based on the balance effect of different capacitor parameters and different loads on the DC side capacitor voltage.

[0048] S304 obtains a discrete-time mathematical model based on the power grid current prediction model and the neutral point voltage model.

[0049] Specifically, in practical applications, this application constructs a T-type three-level inverter connected to the power grid via a point of common coupling (PCC). The dynamic model of the T-type three-level inverter can be described as follows:

[0050] ;

[0051] Among them, e a e b e c and i a i b i c Let L and R be the three-phase voltage and current of the power grid, respectively, and let u be the inductance and equivalent resistance of the line, respectively. ao u bo u co These are the output voltages of the three-phase bridge arms of the inverter, u on This refers to the voltage offset between the inverter neutral point and the grid center point.

[0052] The dynamic model of the T-type three-level inverter is transformed into the α-β coordinate system using the Clarke transformation:

[0053] ;

[0054] Among them, i α i β and e α e β These represent the grid current and voltage in the α-β coordinate system, respectively, u α and u β This represents the output voltage of the inverter in the α-β coordinate system.

[0055] Discretize the dynamic model in the α-β coordinate system using the forward Euler method to obtain the predicted grid current:

[0056] ;

[0057] Among them, i α (k+1) and i β (k+1) is the predicted value of the grid current at time k+1, T s To control the cycle, i α (k) and i β (k) represents the grid current at time k, u α (k) and u β (k) represents the output voltage of the inverter at time k, e α (k) and e β (k) represents the grid voltage at time k.

[0058] The reference value for the grid current is obtained according to the Lagrange extrapolation theorem:

[0059] ;

[0060] Among them, i m * (k+1), i m *(k), i m * (k-1), i m * (k-2) (m=α, β) are the reference values ​​of the grid current at times k+1, k, k-1, and k-2, respectively.

[0061] Different capacitor parameters and unbalanced loads can affect the balance of the DC voltages between the two capacitors. Neutral point voltage u o (k) can be represented as:

[0062] ;

[0063] Among them, u c1 (k) and u c2 (k) is the voltage of the series capacitor on the DC side.

[0064] u o The dynamic process can be modeled as follows:

[0065] ;

[0066] ;

[0067] Among them, i o For neutral point current, S a S b S c The inverter switching state for each phase arm, with values ​​ranging from {-1, 0, 1}, i abc =[i a i b i c ] T .

[0068] The predicted value of the neutral point voltage at time k+1 is:

[0069] ;

[0070] Excessive common-mode voltage can cause leakage current and shorten the inverter's lifespan. The common-mode voltage V of a T-type three-stop inverter... cm The voltage between the inverter neutral point and the grid neutral point can be described as:

[0071] ;

[0072] ;

[0073] Among them, u dc It is a DC voltage source.

[0074] Considering the switching frequency of the inverter, the number of changes in the switching devices within one sampling period is defined as the switching frequency, which can be expressed as:

[0075] ;

[0076] Among them, S a (k+1), S b (k+1), S c (k+1) and S a (k), S b (k), S c (k) represents the three-phase bridge arm switch states at time k+1 and time k, respectively.

[0077] Therefore, the discrete-time mathematical model can be obtained through the above model.

[0078] In one embodiment of this application, the improved chimpanzee algorithm includes: increasing the diversity of the initial population in the chimpanzee algorithm through Fuch-Circle composite chaotic mapping; and improving the convergence speed of the chimpanzee algorithm in the iterative process by performing quasi-backward learning by individual chimpanzees and by using a dynamic nonlinear convergence factor based on the Fuch-Circle composite chaotic mapping results; the dynamic nonlinear convergence factor includes:

[0079] ;

[0080] Among them, g in Let be the initial convergence factor, with a value of 1.5, and l with a value of 0.05. t max The maximum number of iterations is given by , beta is the beta distribution function, and h and g are the beta distribution parameters, taking values ​​of 4 and 1 respectively.

[0081] Furthermore, the distance between individual chimpanzees and their prey is dynamically adjusted through a periodic oscillation mechanism using sine and cosine algorithms.

[0082] The method of adjusting the parameters in the objective function using the improved chimpanzee algorithm to obtain the adjusted FCS-MPC algorithm includes: adjusting the prediction step size and weight system parameters in the objective function using the improved chimpanzee algorithm to obtain the adjusted FCS-MPC algorithm.

[0083] Specifically, in practical applications, this application uses the FCS-MPC algorithm to control a T-type three-level inverter. Based on the aforementioned discrete-time mathematical model, the control objective is determined, and the objective function is set as follows:

[0084] ;

[0085] in, This is the weighting factor.

[0086] This application utilizes an improved chimpanzee algorithm to predict the step size N in FCS-MPC. p and weighting coefficients The optimizations to the chimpanzee algorithm include the following improvements:

[0087] (1) Composite chaotic mapping

[0088] Individuals generated through random initialization are difficult to distribute uniformly in the search space. Therefore, this application employs a composite chaotic map to enhance population diversity and enable the algorithm to escape local optima during population initialization. A diverse initial population is generated through the Fuch-Circle composite chaotic map. The improved population initialization can be expressed as:

[0089] ;

[0090] Where mod(a,b) represents the modulo operation between a and b, X t and X t+1 Let represent the position vectors of the chimpanzee individual in the t-th and t+1-th iterations, respectively.

[0091] After the complex chaotic mapping, the chimpanzee individual will perform quasi-backward learning again, which can be represented as follows:

[0092] ;

[0093] ;

[0094] ;

[0095] Among them, X i The quasi-reverse solution is generated by quasi-reverse learning. CS is the midpoint of the upper and lower bounds of the search space, MP is the standard reverse solution, LB and UB are the upper and lower bounds of the search space, respectively, and rand is a random number in [0,1].

[0096] (2) Dynamic nonlinear convergence factor

[0097] Utilizing a convergence factor can accelerate the convergence speed of subsequent iterations and promote the algorithm's local evolution. Simultaneously, the beta distribution can prevent the convergence factor from converging to 0 prematurely, enhancing the optimality-seeking ability and better escaping local optima. The dynamically nonlinearly decreasing convergence factor g... n It can be as follows:

[0098] ;

[0099] Among them, g in Let be the initial convergence factor, with a value of 1.5, and l with a value of 0.05. t maxThe maximum number of iterations is given by , beta is the beta distribution function, and h and g are the beta distribution parameters, taking values ​​of 4 and 1 respectively.

[0100] (3) Update of individual chimpanzee locations

[0101] In the chimpanzee algorithm, the attacker, driver, hindrance, and chaser update their positions based on their distance from the prey. This application optimizes the distance between the chimpanzee and the prey through the periodic oscillation mechanism of the Sine cosine algorithm (SCA). The distance is dynamically adjusted using the sin / cos function of SCA to solve the local optimum problem of the algorithm.

[0102] ;

[0103] ;

[0104] ;

[0105] ;

[0106] Where, d attacker d barrier d chaser d driver c1, c2, c3, and c4 are the distances between the attacker, driver, hindrance, and pursuer chimpanzees and their prey, respectively; c1, c2, c3, and c4 are the coefficient vectors of the corresponding position vectors; m1, m2, m3, and m4 are the corresponding chaos factors; and x is the current position vector of the chimpanzee.

[0107] For details, please refer to [link / reference]. Figure 4 As shown, through Figure 4 As can be seen, the improved ChOA proposed in this application converges significantly faster than PSO, GWO, and the standard ChOA, and its convergence value in the steady state is also lower than the other three algorithms. This is mainly due to the following improvements adopted in this application: First, a composite chaotic mapping is used to generate the initial population, making the distribution of the solution space more reasonable and laying the foundation for fast convergence; second, the dynamic convergence factor designed based on the beta distribution can automatically adjust the search intensity according to the iteration process, ensuring both the efficiency of global exploration in the early stage and the accuracy of local optimization in the later stage; finally, the periodic position update mechanism of the sine and cosine algorithm is introduced, which effectively enhances the algorithm's ability to escape local optima. This fast and accurate convergence characteristic enables the algorithm to quickly lock the neighborhood of the optimal solution when optimizing the prediction step size and weight coefficients of FCS-MPC, and to obtain a better parameter combination through fine search, thus exhibiting the best comprehensive optimization performance.

[0108] In one embodiment of this application, obtaining the corresponding control switch sequence based on the objective function value includes: selecting the switch action sequence corresponding to the smallest objective function value based on the objective function value, and generating a control switch sequence.

[0109] Specifically, after determining the optimized and adjusted FCS-MPC algorithm through the above embodiments, the T-type three-level inverter can be controlled. The control scheme steps are as follows:

[0110] (1) Sampling time k: grid current i α (k), i β (k), grid voltage e α (k), e β (k), inverter output voltage u α (k), u β (k) and DC side upper and lower capacitor voltage u c1 (k), u c2 (k);

[0111] (2) Optimize the parameters of the FCS-MPC controller based on the improved ChOA and output the optimal parameters;

[0112] (3) Based on the FCS-MPC controller with optimal parameters, the state variables at time k are substituted to obtain the predicted values ​​at time k+1;

[0113] (4) Substitute the components at time k and time k+1 into the objective function f to obtain the objective function values ​​corresponding to all switching action sequences;

[0114] (5) Select the control switch sequence that minimizes the objective function f and apply it to the inverter control.

[0115] Please refer to Figure 5 and Figure 6 As shown, through Figure 5 The comparison graph of the output current and the reference current shows that, judging from the waveform curves, the predicted current can quickly and accurately track changes in the reference current. During the dynamic response process, the system exhibits good tracking characteristics, with a smooth current waveform and no significant overshoot, verifying that the control method provided in this application has high-precision steady-state tracking performance. Figure 6 The waveform diagram showing the DC-side capacitor voltage change indicates that after 0.1 seconds, the voltage difference between the two DC-side capacitors stabilizes within a small fluctuation range of 0-15V, demonstrating good voltage balance characteristics. This demonstrates that the control scheme proposed in this application can effectively maintain the neutral point voltage balance of the T-type three-level inverter.

[0116] Therefore, this application can significantly improve the efficiency of the inverter. SiC-IGBTs, with their higher switching frequency, lower switching losses, and superior thermal performance, enable the inverter to operate stably even under high voltage and high temperature environments. The improved Gorilla algorithm in this application also makes the solution space distribution more reasonable, laying the foundation for rapid convergence. Its fast and accurate convergence characteristics allow the algorithm to quickly lock the optimal solution neighborhood when optimizing the prediction step size and weight coefficients of FCS-MPC, and to obtain better parameter combinations through fine-grained search, thus exhibiting optimal comprehensive optimization performance.

[0117] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-described method.

[0118] This application also provides a computer-readable storage medium storing a computer program that performs the above-described methods.

[0119] This application also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the above-described method.

[0120] like Figure 7 As shown, the electronic device 600 may also include: a communication module 110, an input unit 120, an audio processor 130, a display 160, and a power supply 170. It is worth noting that the electronic device 600 does not necessarily need to include these components. Figure 7 All components shown; in addition, the electronic device 600 may also include Figure 7 For components not shown, please refer to existing technologies.

[0121] like Figure 7 As shown, the central processing unit 100, sometimes also referred to as a controller or operating control, may include a microprocessor or other processor device and / or logic device. The central processing unit 100 receives inputs and controls the operation of various components of the electronic device 600.

[0122] The memory 140 may be, for example, one or more of a cache, flash memory, hard drive, removable media, volatile memory, non-volatile memory, or other suitable devices. It may store the aforementioned failure-related information, and also store a program for executing that information. The central processing unit 100 may execute the program stored in the memory 140 to perform information storage or processing, etc.

[0123] Input unit 120 provides input to central processing unit 100. Input unit 120 may be, for example, a keypad or touch input device. Power supply 170 provides power to electronic device 600. Display 160 displays images and text. Display may be, for example, an LCD display, but is not limited thereto.

[0124] The memory 140 can be a solid-state memory, such as a read-only memory (ROM), random access memory (RAM), a SIM card, etc. It can also be a memory that retains information even when power is off, can be selectively erased, and contains more data; examples of this type of memory are sometimes referred to as EPROMs. The memory 140 can also be some other type of device. The memory 140 includes a buffer memory 141 (sometimes referred to as a buffer). The memory 140 may include an application / function storage unit 142 for storing application programs and function programs or processes for executing the operation of the electronic device 600 via the central processing unit 100.

[0125] The memory 140 may also include a data storage unit (data 143) for storing data, such as contacts, digital data, pictures, sounds, and / or any other data used by the electronic device. The driver storage unit (driver 144) of the memory 140 may include various drivers for the electronic device's communication functions and / or for performing other functions of the electronic device (such as messaging applications, address book applications, etc.).

[0126] The communication module 110 is a transmitter / receiver 110 that transmits and receives signals via antenna 111. The communication module (transmitter / receiver) 110 is coupled to the central processing unit 100 to provide input signals and receive output signals, which can be the same as in a conventional mobile communication terminal.

[0127] Based on different communication technologies, multiple communication modules 110 can be configured in the same electronic device, such as cellular network modules, Bluetooth modules, and / or wireless LAN modules. The communication module (transmitter / receiver) 110 is also coupled to a speaker 131 and a microphone 132 via an audio processor 130 to provide audio output via the speaker 131 and receive audio input from the microphone 132, thereby enabling typical telecommunications functions. The audio processor 130 may include any suitable buffer, decoder, amplifier, etc. Additionally, the audio processor 130 is coupled to a central processing unit 100, enabling on-device recording via the microphone 132 and on-device playback of stored audio via the speaker 131.

[0128] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0129] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0130] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0131] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0132] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A three-phase T-type three-level inverter arrangement, characterized by The device comprises: a three-phase bridge arm, each phase bridge arm comprising at least four hybrid switching units; at least two hybrid switching units of each phase bridge arm in the horizontal direction form two groups of structure-symmetrical series branches through internal switching components, the series branches are composed of at least two internal switching components of the same type, and the two groups of series branches are connected in parallel to the DC side capacitor midpoint; wherein the hybrid switching unit is composed of SiC-IGBT and Si-MOSFET two internal switching components, the emitter of the SiC-IGBT and the source of the Si-MOSFET are connected to the AC output end, and the collector of the SiC-IGBT and the drain of the Si-MOSFET are connected to the DC bus; the hybrid switching unit of each phase bridge arm in the three-phase bridge arm in the vertical direction is composed of SiC-IGBT and Si-MOSFET in parallel.

2. The inverter apparatus according to claim 1, characterized by, The number of internal switching components in the two groups of series branches is equal.

3. A control method for the three-phase T-type three-level inverter device according to any one of claims 1 or 2, characterized in that, The method comprises: constructing a discrete-time mathematical model according to a three-phase T-type three-level inverter device; constructing an objective function through the discrete-time mathematical model, adjusting the parameters in the FCS-MPC algorithm by using the chimpanzee algorithm improved based on the composite chaotic mapping, dynamic nonlinear convergence factor and periodic oscillation mechanism of the sine cosine algorithm to obtain the adjusted FCS-MPC algorithm; obtaining second sampling data after a preset period through the adjusted FCS-MPC algorithm according to the first sampling data of the three-phase T-type three-level inverter device; obtaining a plurality of objective function values through the objective function according to the first sampling data and the second sampling data, and obtaining the corresponding control switch sequence according to the objective function values; controlling the three-phase T-type three-level inverter device through the control switch sequence; wherein a plurality of objective function values correspond to the switching action sequence of the hybrid switching unit in the three-phase T-type three-level inverter device.

4. The control method according to claim 3, characterized by Constructing a discrete-time mathematical model according to a three-phase T-type three-level inverter device comprises: constructing a corresponding dynamic model according to the state of the three-phase T-type three-level inverter device connected to the power grid through the common coupling point; obtaining a dynamic model in the coordinate system through Clarke transformation of the dynamic model, and discretizing the dynamic model in the coordinate system by using the forward Euler method to obtain a power grid current prediction model; obtaining a power grid current reference model according to the Lagrange extrapolation theorem through the power grid current prediction model, and constructing a neutral point voltage model according to the influence of different capacitor parameters and different loads on the balance of DC side capacitor voltage; obtaining a discrete-time mathematical model according to the power grid current prediction model and the neutral point voltage model.

5. The control method according to claim 3, characterized by, The improved chimpanzee algorithm comprises: increasing the diversity of the initialized population in the chimpanzee algorithm through Fuch-Circle composite chaotic mapping; performing quasi-reverse learning by chimpanzee individuals according to the Fuch-Circle composite chaotic mapping result.

6. The control method according to claim 3, characterized by The improved chimpanzee algorithm comprises: improving the convergence speed of the chimpanzee algorithm in the iteration process through a dynamic nonlinear convergence factor; the dynamic nonlinear convergence factor comprises: ； where g in is an initial convergence factor with a value of 1.5, l has a value of 0.05, t max is the maximum number of iterations, beta is a beta distribution function, h, g are beta distribution parameters with values of 4 and 1, respectively.

7. The control method according to claim 3, characterized by, The improved chimpanzee algorithm comprises: The distance between the chimpanzee individual and the prey is dynamically adjusted through the periodic oscillation mechanism of the sine-cosine algorithm.

8. The control method according to claim 3, characterized by, The improved chimpanzee algorithm is used to adjust the parameters in the target function to obtain an adjusted FCS-MPC algorithm, which comprises: The improved chimpanzee algorithm is used to adjust the prediction step and the weight system parameters in the target function to obtain an adjusted FCS-MPC algorithm.

9. The control method according to claim 3, characterized by, According to the target function value screening, a corresponding control switch sequence is obtained, which comprises: According to the target function value screening, a switch action sequence corresponding to the minimum target function value is generated to obtain a control switch sequence.

10. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the method of any one of claims 3 to 9.

11. A computer readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the method of any one of claims 3 to 9.

12. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instruction is executed by the processor to implement the steps of the method of any one of claims 3 to 9.

Images