A pulse source for SiC MOSFET high field stress reliability test

Abstract

The application discloses a pulse source for SiC MOSFET high-field stress reliability test, which comprises a main switch circuit, a high-voltage module, a driving circuit and an auxiliary power supply; the main switch circuit is connected with the high-voltage module and the driving circuit respectively, and the driving circuit is connected with the auxiliary power supply; the high-voltage module provides high voltage with sufficient power for the main switch circuit; the auxiliary power supply is used for providing various required voltages for the driving circuit; the driving circuit provides a gate driving signal with sufficient power for the main switch circuit; the main switch circuit bears high voltage output by the high-voltage module, performs switching action according to the gate driving signal output by the driving circuit, and outputs a specified high-voltage pulse waveform. The application can apply drain-source voltage with a voltage change rate as high as several thousand volts to SiC MOSFET high-field stress reliability test, and the voltage pulse waveform is controllable, and the application has the advantages of small size, high voltage resistance, simple driving, high power density and the like.

Description

Technical Field

[0001] This invention relates to the field of SiC MOSFET reliability testing technology, and in particular to a pulse source for high field strength stress reliability testing of SiC MOSFETs. Background Technology

[0002] In recent years, with the widespread application of power electronic systems in new energy vehicles, wind power generation, smart grids, and other fields, the demand for high-temperature, high-frequency, and high-voltage devices has been increasing. Traditional silicon-based power devices have long dominated the market due to their superior performance, low cost, and ease of parallel connection. However, due to limitations in their material properties, their performance is gradually approaching its theoretical limits. Meanwhile, third-generation semiconductor materials, represented by SiC, have also developed rapidly. SiC MOSFETs, as one of the most promising and application-oriented devices among third-generation semiconductor materials, have achieved breakthroughs in many fields. However, the aging mechanism of SiC MOSFETs under extreme environments remains unclear. Further research is needed on the aging mechanism of SiC MOSFETs under high field strength stress and the extraction of their characterization parameters to improve their performance and application range, meeting practical application requirements.

[0003] Existing pulse sources for high field strength stress reliability testing of SiC MOSFETs can output voltages of several kilovolts, but their voltage change rate does not exceed 5V / ns, failing to meet the latest revised standards such as AQG-324, which require applying square wave pulses with a voltage change rate exceeding 50V / ns to SiC MOSFETs. In research, Marx and linear transformer-driven (LTD) topologies offer controllable pulse waveforms, high voltage change rates, and strong scalability, but require numerous switching devices and suffer from difficulties in synchronizing switching actions, placing high demands on the drive circuitry. Resonant discharge topologies require only one or two discharge switches in the primary circuit; sufficiently high voltage pulses can be obtained with a large enough turns ratio. However, due to the large inductance of the secondary winding, it is difficult to obtain pulses with a fast rising edge, and the pulse waveform approximates a half-wave sine, which does not match the square wave waveform required for reliability testing. Pulse forming network (PFN) and pulse forming line (PFL) topologies require only one switching device to control the waveform, but they require a large number of passive components such as capacitors and inductors, which increases the size of the pulse source. Both require the load and the pulse source circuit to meet impedance matching, otherwise waveform oscillation will occur, which can easily damage the device under test. When the model of the device under test changes, the pulse source circuit needs to be redesigned, which lacks universality. Summary of the Invention

[0004] The purpose of this invention is to provide a pulse source for high field strength stress reliability testing of SiC MOSFETs. This invention can apply drain-source voltages of up to several kilovolts with a large voltage change rate for high field strength stress reliability testing of SiC MOSFETs, and the voltage pulse waveform is controllable. It has the advantages of small size, high withstand voltage, simple driving, and high power density.

[0005] The technical solution of this invention is as follows: A pulse source for high field strength stress reliability testing of SiC MOSFETs, comprising a main switching circuit, a high-voltage module, a driving circuit, and an auxiliary power supply; the main switching circuit is connected to both the high-voltage module and the driving circuit, and the driving circuit is connected to the auxiliary power supply; the high-voltage module provides sufficient high voltage to the main switching circuit; the auxiliary power supply provides various required voltages to the driving circuit; the driving circuit provides sufficient gate drive signals to the main switching circuit; the main switching circuit withstands the high voltage output by the high-voltage module, performs switching actions according to the gate drive signals output by the driving circuit, and outputs a specified high-voltage pulse waveform.

[0006] The aforementioned pulse source for high field strength stress reliability testing of SiC MOSFETs includes a high-voltage module comprising a first low-voltage power supply, a Zener diode D1, electrolytic capacitors C1, C2, C3, and C4, a common-mode inductor L1, and a voltage converter U1. The positive terminal of the first low-voltage power supply is connected to the anode of Zener diode D1, the positive terminal of electrolytic capacitor C1, one end of capacitor C2, and one end of the common-mode inductor L1. The negative terminal of the first low-voltage power supply is connected to the cathode of Zener diode D1, the negative terminal of electrolytic capacitor C1, and the other end of capacitor C2. The other end of the common-mode inductor L1 is connected to the same terminal; one end of the other set of terminals of the common-mode inductor L1 is connected to one end of capacitor C3 and one end of the input terminal of voltage converter U1; the other end of the other set of terminals of the common-mode inductor L1 is connected to the other end of capacitor C3 and the other end of the input terminal of voltage converter U1; one end of the output terminal of voltage converter U1 is connected to one end of C4, marked as HV; the other end of the output terminal of voltage converter U1 is connected to the other end of C4, marked as HGND.

[0007] The aforementioned pulse source for high field strength stress reliability testing of SiC MOSFETs includes an auxiliary power supply comprising a second low-voltage power supply, electrolytic capacitors C5, C8, C9, C12, C15, C16, C6, C7, C10, C11, C13, C14, C17, C18, C19, C20, C21, differential mode inductors L2, L3, and L4, power modules U2, U3, and U4; the positive terminal of the second low-voltage power supply is connected to the positive terminal of electrolytic capacitor C5 and electrolytic capacitor C12. The positive terminal of the power module U2 is connected to one end of capacitors C6, C13, C19, differential mode inductors L2, L3, and L4; the other end of differential mode inductor L2 is connected to one end of capacitor C7 and the input terminal Vin of power module U2; the other end of differential mode inductor L3 is connected to one end of capacitor C14 and the input terminal Vin of power module U3; the other end of differential mode inductor L4 is connected to one end of capacitor C20 and the input terminal Vin of power module U4; the output terminal +Vo of power module U2 is connected to the positive terminal of electrolytic capacitor C8 and one end of capacitor C10, and is labeled VDDA; the power module U2's... The output terminal 0V is connected to the negative terminal of electrolytic capacitor C8, the positive terminal of electrolytic capacitor C9, the other end of capacitor C10, and one end of capacitor C11, marked as GNDA; the output terminal -Vo of power module U2 is connected to the negative terminal of electrolytic capacitor C9 and the other end of capacitor C11, marked as VSSA; the output terminal +Vo of power module U3 is connected to the positive terminal of electrolytic capacitor C15 and one end of capacitor C17, marked as VDDB; the output terminal 0V of power module U3 is connected to the negative terminal of electrolytic capacitor C15, the positive terminal of electrolytic capacitor C16, the other end of capacitor C17, and one end of capacitor C18, marked as GNDB; the power module... The output terminal -Vo of block U3 is connected to the negative terminal of electrolytic capacitor C16 and the other end of capacitor C18, marked as VSSB; the negative terminal of the second low-voltage power supply is connected to the negative terminals of electrolytic capacitor C5, electrolytic capacitor C12, the other end of capacitor C6, the other end of capacitor C7, the other end of capacitor C13, the other end of capacitor C14, the other end of capacitor C19, the other end of capacitor C20, one end of capacitor C21, the GND of power module U2, the GND of power module U3, and the GND of power module U4, marked as GND; the output terminal Vo of power module U4 is connected to the other end of capacitor C21, marked as 5V.

[0008] The aforementioned pulse source for high field strength stress reliability testing of SiC MOSFETs includes a driving circuit comprising capacitors C22 and C23, resistors R1, R2, R3, R4, and R5, a driving chip U5, a power amplifier U6, and a power amplifier U7. The input terminal VCCI of the driving chip U5 is connected to the 5V output of the auxiliary power supply and one end of capacitor C22. The input terminal GND of the driving chip U5 is connected to the GND output of the auxiliary power supply and the other end of capacitor C22. The input terminals INA and INB of the driving chip U5 are used to receive specified driving signals. The input terminal DT of the driving chip U5 is connected to one end of resistor R1 and capacitor C23, and the other end of resistor R1 and capacitor C23 is connected to GND. The input terminals VDDA, VSSA, VDDB, and VSSB of the driver chip U5 are connected to the output terminals VDDA, VSSA, VDDB, and VSSB of the auxiliary power supply, respectively. The output terminal OUTA of the driver chip U5 is connected to one end of resistor R3, and the other end of resistor R3 is connected to the positive input terminal of power amplifier U6. The inverting input terminal of power amplifier U6 is connected to VDDA through resistor R2, and the output terminal of power amplifier U6 is marked as GA. The output terminal OUTB of the driver chip U5 is connected to one end of resistor R4, and the other end of resistor R4 is connected to the positive input terminal of power amplifier U7. The inverting input terminal of power amplifier U7 is connected to VDDB through resistor R5, and the output terminal of power amplifier U7 is marked as GB.

[0009] The aforementioned pulse source for high field strength stress reliability testing of SiC MOSFETs includes a main switching circuit comprising MOSFETs Q1 and Q2, resistors R6 and R7, Zener diodes ZD1, ZD2, ZD3, and ZD4. The drain of MOSFET Q1, one end of resistor R6, and the anode of Zener diode ZD1 are connected to the HV output of the high-voltage module and marked as HV+. The source of MOSFET Q1 is connected to the drain of MOSFET Q2, the other end of R6, one end of R7, the cathode of Zener diode ZD2, and the anode of Zener diode ZD3 and marked as HV_COM. The source of MOSFET Q2, the other end of resistor R7, and the cathode of Zener diode ZD4 are connected to the HGND output of the high-voltage module and marked as HV_GND.

[0010] Compared with existing technologies, this invention utilizes the small size, high voltage withstand capability, and simple driving principle of MOSFETs to achieve a high power density pulse source design. While possessing advantages such as controllable circuit waveform, high voltage change rate, and strong scalability, it reduces the number of switching and passive components by using high-voltage components, thus shrinking the pulse source size and increasing its power density. Due to the reduced number of switches, this invention ensures synchronous transmission of the drive signal, improves the reliability of the pulse source, and facilitates the construction of a high field strength stress reliability testing platform. Furthermore, the auxiliary power supply, drive circuit, and main switching circuit of this invention can be integrated on a single PCB, significantly reducing product size and achieving high-voltage, high-dv / dt pulse generation with higher power density. Further, this invention can simultaneously connect two high-voltage modules to the main switching circuit to achieve ±1kV pulse output; it can also achieve higher voltage output through multiple systems connected in series. In addition to the MOSFETs shown, the main switching circuit of this invention can also include other switching device types such as IGBTs. In summary, this invention achieves the application of a small-volume, high-power-density pulse source, meeting the stringent requirements of high-voltage, high-dv / dt pulses for reliability testing of SiC MOSFETs under high field strength stress. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the structure of the present invention;

[0012] Figure 2 This is a circuit diagram of the high-voltage module;

[0013] Figure 3 This is a circuit diagram of the auxiliary power supply;

[0014] Figure 4 This is a schematic diagram of the drive circuit.

[0015] Figure 5 This is a schematic diagram of the main switch circuit;

[0016] Figure 6 This is the schematic diagram of the main switching circuit module with an output range of ±1kV pulses;

[0017] Figure 7 These are the relevant operating waveforms of the main switching circuit module with an output range of ±1kV pulses;

[0018] Figure 8 This is the schematic diagram of the main switch circuit module with an output range of 0 to nkV.

[0019] The present invention will be further described below with reference to the accompanying drawings and embodiments, but this should not be construed as limiting the present invention.

[0020] Example 1: A pulse source for high field strength stress reliability testing of SiC MOSFETs, such as... Figure 1 As shown, the system includes a main switching circuit, a high-voltage module, a drive circuit, and an auxiliary power supply. The main switching circuit is connected to both the high-voltage module and the drive circuit, and the drive circuit is connected to the auxiliary power supply. The high-voltage module provides sufficient high voltage to the main switching circuit. The auxiliary power supply provides various required voltages to the drive circuit, including VDDA / VDDB (15V), VSSA / VSSB (-5V), 5V, and ground signals such as GND, GNDA, and GNDB. The drive circuit provides sufficient gate drive signals, i.e., GA and GB signals, to the main switching circuit. The main switching circuit withstands the high voltage output from the high-voltage module and performs switching actions according to the gate drive signals output by the drive circuit, outputting a specified high-voltage pulse waveform (high-voltage high dv / dt pulse).

[0021] like Figure 2 As shown, the high-voltage module includes a first low-voltage power supply (24V), a Zener diode D1, electrolytic capacitors C1, C2, C3, and C4, a common-mode inductor L1, and a voltage converter U1 (24V / 1KV). The positive terminal of the first low-voltage power supply is connected to the anode of the Zener diode D1, the positive terminal of the electrolytic capacitor C1, one end of the capacitor C2, and one end of the common-mode inductor L1. The negative terminal of the first low-voltage power supply is connected to the cathode of the Zener diode D1, the negative terminal of the electrolytic capacitor C1, the other end of the capacitor C2, and the common-mode inductor L1. The other end of the common-mode inductor L1 is connected to the same terminal; one end of the other set of terminals of the common-mode inductor L1 is connected to one end of capacitor C3 and one end of the input terminal of voltage converter U1; the other end of the other set of terminals of the common-mode inductor L1 is connected to the other end of capacitor C3 and the other end of the input terminal of voltage converter U1; one end of the output terminal of voltage converter U1 is connected to one end of C4, marked as HV; the other end of the output terminal of voltage converter U1 is connected to the other end of C4, marked as HGND. In this embodiment, the high-voltage module can output a stable voltage of 0–1kV, laying the foundation for the main switching circuit to output high-voltage, high-dv / dt pulses.

[0022] like Figure 3As shown, the auxiliary power supply includes a second low-voltage power supply (15V), electrolytic capacitors C5, C8, C9, C12, C15, C16, C6, C7, C10, C11, C13, C14, C17, C18, C19, C20, C21, differential-mode inductors L2, L3, and L4, power modules U2, U3, and U4; the positive terminal of the second low-voltage power supply is connected to the positive terminals of electrolytic capacitors C5, C12, C6, and C21. One end of capacitors C13 and C19, differential mode inductors L2, L3, and L4 are connected; the other end of differential mode inductor L2 is connected to one end of capacitor C7 and the input terminal Vin of power module U2; the other end of differential mode inductor L3 is connected to one end of capacitor C14 and the input terminal Vin of power module U3; the other end of differential mode inductor L4 is connected to one end of capacitor C20 and the input terminal Vin of power module U4; the output terminal +Vo of power module U2 is connected to the positive terminal of electrolytic capacitor C8 and one end of capacitor C10, labeled VDDA; the output terminal 0V of power module U2 is connected to... The negative terminal of electrolytic capacitor C8, the positive terminal of electrolytic capacitor C9, the other end of capacitor C10, and one end of capacitor C11 are connected together, marked as GNDA; the output terminal -Vo of power module U2 is connected to the negative terminal of electrolytic capacitor C9 and the other end of capacitor C11, marked as VSSA; the output terminal +Vo of power module U3 is connected to the positive terminal of electrolytic capacitor C15 and one end of capacitor C17, marked as VDDB; the output terminal 0V of power module U3 is connected to the negative terminal of electrolytic capacitor C15, the positive terminal of electrolytic capacitor C16, the other end of capacitor C17, and one end of capacitor C18, marked as GNDB; the power module U3's... The output terminal -Vo is connected to the negative terminal of electrolytic capacitor C16 and the other end of capacitor C18, marked as VSSB; the negative terminal of the second low-voltage power supply is connected to the negative terminals of electrolytic capacitors C5 and C12, the other end of capacitors C6, C7, C13, C14, C19, C20, and one end of capacitor C21, as well as the GND of power module U2, power module U3, and power module U4, marked as GND; the output terminal Vo of power module U4 is connected to the other end of capacitor C21, marked as 5V.The core of the auxiliary power supply in this embodiment consists of three integrated power supply modules, U2, U3, and U4, which can convert the input 15V voltage into +15V / -5V, +15V / -5V, and 5V voltages, respectively. The two +15V / -5V voltages can provide the required positive and negative voltages to the driver chip U5, power amplifier U6, and power amplifier U7 in the drive circuit, enabling them to output stable +15V / -5V drive pulse signals to stably drive the two switching devices (MOSFET Q1 and MOSFET Q2) of the main switching circuit. The 5V voltage provides power to the driver chip U5, ensuring its stable operation.

[0023] In this embodiment, as Figure 4 As shown, the driving circuit includes capacitors C22 and C23, resistors R1, R2, R3, R4, and R5, a driving chip U5, a power amplifier U6, and a power amplifier U7. The input terminal VCCI of the driving chip U5 is connected to the 5V output of the auxiliary power supply and one end of capacitor C22. The input terminal GND of the driving chip U5 is connected to the GND output of the auxiliary power supply and the other end of capacitor C22. The input terminals INA and INB of the driving chip U5 are used to receive specified driving signals, which are provided by the user's signal generator. The input terminal DT of the driving chip U5 is connected to one end of resistor R1 and capacitor C23, and the other end of resistor R1 and capacitor C23 is connected to GND. The input terminals VDDA, VSSA, VDDB, and VSSB of the driver chip U5 are connected to the output terminals VDDA, VSSA, VDDB, and VSSB of the auxiliary power supply, respectively. The output terminal OUTA of the driver chip U5 is connected to one end of resistor R3, and the other end of resistor R3 is connected to the positive input terminal of power amplifier U6. The inverting input terminal of power amplifier U6 is connected to VDDA through resistor R2, and the output terminal of power amplifier U6 is marked GA. The output terminal OUTB of the driver chip U5 is connected to one end of resistor R4, and the other end of resistor R4 is connected to the positive input terminal of power amplifier U7. The inverting input terminal of power amplifier U7 is connected to VDDB through resistor R5, and the output terminal of power amplifier U7 is marked GB. The main function of the driver circuit in this embodiment is to receive high and low level signals provided by the user and convert them into gate drive signals sufficient to drive the switching devices. The DT pin is used to set the dead time, and the specific calculation formula is t... d =10×R1, where R1 is in kΩ and the dead time is in ns. When DT is pulled up to 5V, the two gate drive signals are output synchronously without dead time.

[0024] In this embodiment, the output range of the main switching circuit is 0 to 1kV pulse, and its principle is as follows: Figure 5As shown, the system includes MOSFETs Q1 and Q2, resistors R6 and R7, Zener diodes ZD1, ZD2, ZD3, and ZD4. The drain of MOSFET Q1, one end of resistor R6, and the anode of Zener diode ZD1 are connected to the HV output of the high-voltage module and marked as HV+. The source of MOSFET Q1 is connected to the drain of MOSFET Q2, the other end of R6, one end of R7, the cathode of Zener diode ZD2, and the anode of Zener diode ZD3 and marked as HV_COM. The source of MOSFET Q2, the other end of resistor R7, and the cathode of Zener diode ZD4 are connected to the HGND output of the high-voltage module and marked as HV_GND. When this embodiment is used for reliability testing, the user needs to input two specified synchronous pulse waveforms so that the two switching devices can switch simultaneously. By connecting the drain and source of the load (usually a SiC MOSFET) to HV+ and HV_GND respectively, it can withstand the high voltage and high dv / dt pulses output by this invention, so as to perform the high field strength stress reliability test required by the user.

[0025] Example 2: In this example, the circuit structure of the main switch circuit, high-voltage module, drive circuit, and auxiliary power supply is the same as in Example 1. Two high-voltage modules are used to achieve an output range of ±1kV pulses. In this example, the user needs to input two complementary pulse signals to achieve the ±1kV pulse output. Figure 6 As shown, HV1+ and HGND1 of high-voltage module 1 are connected to the drain and source (i.e., drain of Q2) of Q1 in the main switching circuit, respectively; HV2+ and HGND2 of high-voltage module 2 are connected to the drain (i.e., source of Q1) and source of Q2 in the main switching circuit, respectively; in addition, the DT pin of the driver chip U5 in the drive circuit module is connected as follows: Figure 4 The resistors R1 and C23 shown are connected to prevent both devices from turning on simultaneously and causing a short circuit fault. When this embodiment is used for reliability testing, the user needs to input two specified complementary pulse waveforms so that the two switching devices can switch. By connecting the drain and source of the load (usually a SiC MOSFET) to HV+ and HV- respectively, it can withstand the high voltage and high dv / dt pulse output by this invention, so as to carry out the high field strength stress reliability test required by the user.

[0026] Figure 7The relevant operating waveforms of the main switching circuit with an output pulse range of ±1kV are as follows: When GA and GB are both low, MOSFETs Q1 and Q2 are turned off, and 0V voltage is output across HV+ / HV-; when GA is high and GB is low, MOSFET Q1 is turned on and MOSFET Q2 is turned off, and +1kV voltage is output across HV+ / HV-; when GA is low and GB is high, MOSFET Q2 is turned on and MOSFET Q1 is turned off, and -1kV voltage is output across HV+ / HV-; when GA is high and GB is high, MOSFETs Q1 and Q2 are turned on, and +1kV voltage is output across HV+ / HV-.

[0027] Example 3: In this example, the circuit structures of the main switching circuit, high-voltage module, drive circuit, and auxiliary power supply are the same as in Example 1. Multiple high-voltage modules are used to achieve an output pulse range of 0 to nkV. In this example, the voltage output range of the pulse source can be extended by connecting n main switching circuit modules in series. Simultaneously, to ensure the synchronization of the switching actions of multiple devices, the gate drive signal of the drive module can be connected to multiple switching devices within its output capability.

[0028] In summary, this invention utilizes the principles of small size, high voltage withstand capability, and simple driving of MOSFETs to achieve a high power density pulse source design. While possessing advantages such as controllable circuit waveform, high voltage change rate, and strong scalability, it reduces the number of switching and passive components by using high-voltage components, thus shrinking the pulse source size and increasing its power density. The reduced number of switches ensures synchronous transmission of the drive signal, improving the reliability of the pulse source and facilitating the construction of a high-field-strength stress reliability testing platform. Furthermore, the auxiliary power supply, drive circuit, and main switching circuit of this invention can be integrated onto a single PCB, significantly reducing product size and achieving high-voltage, high-dv / dt pulse generation with higher power density. Moreover, this invention can simultaneously connect two high-voltage modules to the main switching circuit to achieve ±1kV pulse output; it can also achieve higher voltage output through multiple systems connected in series. Therefore, this invention achieves the application of a small-volume, high-power-density pulse source, meeting the stringent requirements of high-voltage, high-dv / dt pulses for the reliability testing of SiCMOSFETs under high field-strength stress.

Claims

1. A pulse source for SiC MOSFET high field stress reliability testing, characterized by: Including main switch circuit, high voltage module, drive circuit and auxiliary power supply;The main switch circuit is connected with high voltage module and drive circuit respectively, and the drive circuit is connected with auxiliary power supply;The high voltage module provides sufficient power high voltage for the main switch circuit;The auxiliary power supply is used for providing various required voltages to the drive circuit;The drive circuit provides sufficient power gate drive signal for the main switch circuit;The main switch circuit bears the high voltage output by the high voltage module, and performs switching action according to the gate drive signal output by the drive circuit, and outputs specified high voltage pulse waveform; The high voltage module includes first low voltage power supply, voltage stabilizing tube D1, electrolytic capacitor C1, capacitor C2, capacitor C3, capacitor C4, common mode inductor L1 and voltage converter U1;The positive electrode of the first low voltage power supply is connected with the anode of the voltage stabilizing tube D1, the positive electrode of the electrolytic capacitor C1, one end of the capacitor C2 and one end of the common mode inductor L1;The negative electrode of the first low voltage power supply is connected with the cathode of the voltage stabilizing tube D1, the negative electrode of the electrolytic capacitor C1, the other end of the capacitor C2, the other end of the common mode inductor L1;One end of the other group of common mode inductor L1 is connected with one end of the capacitor C3 and one end of the voltage converter U1 input end;The other end of the other group of common mode inductor L1 is connected with the other end of the capacitor C3 and the other end of the voltage converter U1 input end;One end of the voltage converter U1 output end is connected with one end of C4, marked as HV;The other end of the voltage converter U1 output end is connected with the other end of C4, marked as HGND.

2. The pulse source for SiC MOSFET high field stress reliability test according to claim 1, characterized in that: The auxiliary power supply includes a second low-voltage power supply, an electrolytic capacitor C5, an electrolytic capacitor C8, an electrolytic capacitor C9, an electrolytic capacitor C12, an electrolytic capacitor C15, an electrolytic capacitor C16, a capacitor C6, a capacitor C7, a capacitor C10, a capacitor C11, a capacitor C13, a capacitor C14, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, a differential mode inductor L2, a differential mode inductor L3, a differential mode inductor L4, a power module U2, a power module U3, and a power module U4; the positive electrode of the second low-voltage power supply is connected with the positive electrode of the electrolytic capacitor C5, the positive electrode of the electrolytic capacitor C12, the capacitor C6, the capacitor C13, the capacitor C19, one end of the differential mode inductor L2, one end of the differential mode inductor L3, and one end of the differential mode inductor L4; the other end of the differential mode inductor L2 is connected with one end of the capacitor C7 and an input end Vin of the power module U2; the other end of the differential mode inductor L3 is connected with one end of the capacitor C14 and an input end Vin of the power module U3; the other end of the differential mode inductor L4 is connected with one end of the capacitor C20 and an input end Vin of the power module U4; an output end +Vo of the power module U2 is connected with the positive electrode of the electrolytic capacitor C8 and one end of the capacitor C10, which is marked as VDDA; an output end 0V of the power module U2 is connected with the negative electrode of the electrolytic capacitor C8, the positive electrode of the electrolytic capacitor C9, the other end of the capacitor C10, and one end of the capacitor C11, which is marked as GNDA; an output end -Vo of the power module U2 is connected with the negative electrode of the electrolytic capacitor C9 and the other end of the capacitor C11, which is marked as VSSA; an output end +Vo of the power module U3 is connected with the positive electrode of the electrolytic capacitor C15 and one end of the capacitor C17, which is marked as VDDB; an output end 0V of the power module U3 is connected with the negative electrode of the electrolytic capacitor C15, the positive electrode of the electrolytic capacitor C16, the other end of the capacitor C17, and one end of the capacitor C18, which is marked as GNDB; an output end -Vo of the power module U3 is connected with the negative electrode of the electrolytic capacitor C16 and the other end of the capacitor C18, which is marked as VSSB; the negative electrode of the second low-voltage power supply is connected with the negative electrode of the electrolytic capacitor C5, the negative electrode of the electrolytic capacitor C12, the other end of the capacitor C6, the other end of the capacitor C7, the other end of the capacitor C13, the other end of the capacitor C14, the other end of the capacitor C19, the other end of the capacitor C20, one end of the capacitor C21, the GND of the power module U2, the GND of the power module U3, and the GND of the power module U4, which is marked as GND; and an output end Vo of the power module U4 is connected with the other end of the capacitor C21, which is marked as 5V.

3. The pulse source for SiC MOSFET high field stress reliability test according to claim 1, characterized in that: The driving circuit includes capacitor C22, capacitor C23, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, driving chip U5, power amplifier U6 and power amplifier U7;The input end VCCI of the driving chip U5 is connected with the 5V output by the auxiliary power supply and one end of the capacitor C22;The input end GND of the driving chip U5 is connected with the GND output by the auxiliary power supply and the other end of the capacitor C22;The input end INA and the input end INB of the driving chip U5 are connected with the driving signal for accepting designation;The input end DT of the driving chip U5 is connected with the resistor R1 and one end of the capacitor C23, and the other end of the resistor R1 and the capacitor C23 is connected with GND;The input end VDDA, VSSA, VDDB, VSSB of the driving chip U5 is connected with the VDDA, VSSA, VDDB, VSSB output by the auxiliary power supply respectively;The output end OUTA of the driving chip U5 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with the positive input end of the power amplifier U6;The reverse input end of the power amplifier U6 is connected with VDDA through the resistor R2, and the output end of the power amplifier U6 is marked as GA;The output end OUTB of the driving chip U5 is connected with one end of the resistor R4, and the other end of the resistor R4 is connected with the positive input end of the power amplifier U7;The reverse input end of the power amplifier U7 is connected with VDDB through R5;The output end of the power amplifier U7 is marked as GB.

4. The pulsed source for SiC MOSFET high field stress reliability testing of claim 1, wherein: The main switch circuit includes MOSFET tube Q1, MOSFET tube Q2, resistor R6, resistor R7, voltage stabilizing tube ZD1, voltage stabilizing tube ZD2, voltage stabilizing tube ZD3, voltage stabilizing tube ZD4;The drain of the MOSFET tube Q1, one end of the resistor R6 and the anode of the voltage stabilizing tube ZD1 are connected with the HV output by the high voltage module together, and are marked as HV+;The source of the MOSFET tube Q1 is connected with the drain of the MOSFET tube Q2, the other end of the resistor R6, one end of the resistor R7, the cathode of the voltage stabilizing tube ZD2 and the anode of the voltage stabilizing tube ZD3, and is marked as HV_COM;The source of the MOSFET tube Q2, the other end of the resistor R7 and the cathode of the voltage stabilizing tube ZD4 are connected with the HGND output by the high voltage module together, and are marked as HV_GND.

Images