Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

Embodiments of the present invention provide a semiconductor memory device and a manufacturing method of the semiconductor memory device, which can realize an increase in the number of contacts and miniaturization of a contact portion. A semiconductor memory device according to an embodiment of the present invention includes a memory cell array and a contact portion. The memory cell array is formed by three-dimensionally arranging memory cells on a laminate, which has a plurality of unit layers including a group of a conductive layer and an insulating layer. The contact portion connects the memory cell array and the conductive layer and a contact. The contact portion has a descending step portion and an ascending step portion. The descending step portion has a plurality of step portions that are sequentially stepped in a first direction away from the memory cell array. The ascending step portion is adjacent to the descending step portion in a second direction orthogonal to the first direction. The ascending step portion has a plurality of step portions that are sequentially stepped in the first direction. The contact arranged at the step portion of the descending step portion and the contact arranged at the step portion of the ascending step portion are arranged in the second direction.

Description

[0001] [Reference to relevant applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-100304 (filed June 16, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The present invention relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Background Technology

[0004] As a semiconductor memory device, a three-dimensional stacked non-volatile memory with stacked memory cells has been proposed. In the three-dimensional stacked non-volatile memory, the contact portions from which word lines are led out of each layer of the memory cells arranged in the height direction sometimes adopt a stepped structure. For example, a contact portion with a structure in which a first stepped portion and a second stepped portion are arranged in a facing manner has been proposed, wherein the first stepped portion has a plurality of stepped portions that decrease in order of magnitude in the direction away from the memory cell, and the second stepped portion has a plurality of stepped portions that increase in order of magnitude in the direction away from the memory cell. However, conventional structures contain many stepped portions from which contacts cannot be arranged, making it difficult to increase the number of contacts and miniaturize the contact portion. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a method for manufacturing a semiconductor memory device and a semiconductor manufacturing apparatus that can increase the number of contacts and miniaturize the contact portion.

[0006] According to one embodiment of the present invention, a semiconductor memory device having a memory cell array and a contact portion is provided. The memory cell array is formed by three-dimensionally arranging memory cells on a multilayer stack, the multilayer stack having multiple cell layers comprising groups of conductive layers and insulating layers. The contact portion connects the memory cell array to the conductive layers and contacts. The contact portion has a step-down portion and a step-up portion. The step-down portion has multiple stepped portions that are progressively stepped away from the memory cell array in a first direction. The step-up portion and the step-down portion are adjacent in a second direction orthogonal to the first direction. The step-up portion has multiple stepped portions that are progressively stepped away from the first direction. The contacts disposed on the stepped portions of the step-down portion and the contacts disposed on the stepped portions of the step-up portion are arranged along the second direction. Attached Figure Description

[0007] Figure 1 This is a perspective view showing an example of the configuration of a memory cell array in a semiconductor memory device according to an embodiment.

[0008] Figure 2This is a cross-sectional perspective view showing an example of the configuration of the contact portion of a semiconductor memory device according to an embodiment.

[0009] Figure 3 This is a top view showing an example of the structure of the contact portion in the embodiment.

[0010] Figure 4 yes Figure 3 The IV-IV sectional view shows an example of the structure of the contact portion in the embodiment.

[0011] Figure 5 This is a top view showing an example of the state of the contact portion WC in the first stage of the manufacturing method of the semiconductor memory device according to the embodiment.

[0012] Figure 6 yes Figure 5 The VI-VI cross-sectional view shows an example of the state of the contact portion WC in the first stage of the manufacturing method of the semiconductor memory device according to the embodiment.

[0013] Figure 7 This is a top view showing an example of the state of the contact portion WC in the second stage of the manufacturing method of the semiconductor memory device according to the embodiment.

[0014] Figure 8 yes Figure 7 The VIII-VIII cross-sectional view shows an example of the state of the contact portion WC in the second stage of the manufacturing method of the semiconductor memory device according to the embodiment.

[0015] Figure 9 This is a top view showing an example of the state of the contact portion WC in the third stage of the manufacturing method of the semiconductor memory device according to the embodiment.

[0016] Figure 10 yes Figure 9 The XX cross-sectional view shows an example of the state of the contact portion WC in the third stage of the manufacturing method of the semiconductor memory device according to the embodiment.

[0017] Figure 11 This is a top view showing an example of the state of the contact portion WC in the fourth stage of the manufacturing method of the semiconductor memory device according to the embodiment.

[0018] Figure 12 yes Figure 11 The XII-XII cross-sectional view shows an example of the state of the contact portion WC in the fourth stage of the manufacturing method of the semiconductor memory device according to the embodiment. Detailed Implementation

[0019] Hereinafter, with reference to the accompanying drawings, a semiconductor memory device according to an embodiment and a method for manufacturing the same will be described in detail. However, the present invention is not limited to this embodiment. Furthermore, the cross-sectional views, etc., of the semiconductor memory devices used in the following embodiments are schematic diagrams, and the relationship between layer thickness and width, and the ratio of the thickness of each layer, may sometimes differ from the actual object. Additionally, hereafter, a non-volatile memory with a three-dimensional structure will be used as an example of a semiconductor memory device.

[0020] Figure 1 This is a perspective view showing an example of the configuration of the memory cell array MA of the semiconductor memory device 10 according to an embodiment. Figure 1 In this design, two directions parallel to and orthogonal to the main surface of the substrate (Sub) are designated as the X direction (an example of the first direction) and the Y direction (an example of the second direction). The direction orthogonal to both the X and Y directions is designated as the Z direction. The direction from right to left on the paper is designated as the positive X direction; similarly, the direction from near the front to the deep side is designated as the positive Y direction; and similarly, the direction from bottom to top is designated as the positive Z direction. Furthermore, Figure 1 Interlayer insulation layers, etc., are omitted.

[0021] like Figure 1 As shown, a source line SL, composed of a conductive layer, is provided on the substrate Sub of the semiconductor memory device 10. Multiple pillars P, made of silicon oxide or the like, extending along the Z-direction, are provided on the source line SL. Each pillar P has a channel layer made of polysilicon or the like and a memory layer on its side, on which multiple insulating layers are stacked. The insulating layers have, for example, a tunnel insulating film, a charge storage film, and a barrier insulating film stacked from the channel layer side. Furthermore, a stacked body LB, not shown, is provided on the source line SL across an interlayer insulating layer. This stacked body LB alternately stacks multiple conductive layers made of tungsten or the like and insulating layers made of silicon oxide or the like. Each pillar P penetrates the stacked body LB.

[0022] In the stacked layer LB, the bottom conductive layer functions as the source-side select gate line SGS, and the top conductive layer functions as the drain-side select gate line SGD. The select gate line SGD is divided corresponding to each pillar P arranged along the X direction. The multiple conductive layers sandwiched between the select gate lines SGS and SGD function as multiple word lines WL. In other words, the word lines WL are examples of "conductive layers". Figure 1 The number of word lines WL shown is an example. The insulating layer between the gate lines SGS, SGD and multiple word lines WL is selected as an interlayer insulating layer (not shown) to perform its function.

[0023] Each strut P is connected to a bit line BL on the stacked volume LB. Each bit line BL is connected to multiple struts P arranged along the Y direction.

[0024] With the above configuration, memory cells MC are arranged along the height direction of each pillar P at the connection points between each pillar P and each word line WL. Source-side selection transistors STS and drain-side selection transistors STD are respectively arranged at the connection points between each pillar P and the select gate lines SGS and SGD. The select transistors STS arranged along the height direction of one pillar P, the multiple memory cells MC, and the select transistors STD constitute a memory string MS. Furthermore, a memory cell array MA is formed by the memory cells MC arranged in a three-dimensional matrix.

[0025] The select gate lines SGS, SGD, and multiple word lines WL are led out of the memory cell array MA to form a stepped contact section. In this example, the contact section is located on the positive side of the memory cell array MA in the X direction.

[0026] Figure 2 This is a cross-sectional perspective view showing an example of the configuration of the contact portion WC of the semiconductor memory device 10 according to the embodiment. Figure 3 This is a top view showing an example of the structure of the contact portion WC in the embodiment. Figure 4 yes Figure 3 The IV-IV sectional view shows an example of the structure of the contact portion WC in the embodiment. Figure 2 and Figure 4 Substrate (Sub) is omitted in the text. Later, sometimes word line WL is not distinguished from select gate lines SGS and SGD, and both are simply referred to as word line WL.

[0027] The contact portion WC is electrically separated from the contact portion adjacent in the Y direction through a plurality of slits S extending in the X direction. In other words, the contact portion WC formed between two slits S constitutes a connection unit. Figures 2-4 The structure of the contact part WC, which is equivalent to one connection unit, will be explained.

[0028] The contact section WC is disposed on the outside of the positive side of the memory cell array MA in the X direction, connecting the word line WL of the memory cell array MA to the contact CT. In the contact section WC of this embodiment, the stacked body LB formed by stacking multiple cell layers in the Z direction has a stepped structure. The cell layer includes a group of word lines WL and insulating layers IS disposed on the word lines WL. Each step of the stepped structure is composed of a group of cell layers containing word lines WL and insulating layers IS.

[0029] The stepped structure illustrated here includes three descending sections DS1 to DS3 (first descending section DS1, second descending section DS2, and third descending section DS3) and three ascending sections US1 to US3 (first ascending section US1, second ascending section US2, and third ascending section US3). Each descending section DS1 to DS3 has multiple (six in this embodiment) stepped sections TD1 to TD6 that descend progressively in the X direction. Each ascending section US1 to US3 has multiple (six in this embodiment) stepped sections TU1 to TU6 that ascend progressively in the X direction. Stepped sections TD1 to TD6 and TU1 to TU6 include an insulating layer IS.

[0030] like Figure 3 As shown, the three reduced-order portions DS1 to DS3 are arranged in a staggered configuration in top view, as are the three increased-order portions US1 to US3. Thus, the first reduced-order portion DS1, the first increased-order portion US1, the third reduced-order portion DS3, and the third increased-order portion US3 are arranged along the X-direction. Furthermore, the first increased-order portion US1 and the second reduced-order portion DS2 are arranged along the Y-direction, and the third reduced-order portion DS3 and the second increased-order portion US2 are also arranged along the Y-direction.

[0031] In addition, such as Figure 4 As shown, the lowest step portion TD1 of the first descending section DS1 is located higher than the highest step portion TU6 of the first ascending section US1, which is adjacent to the first descending section DS1 in the X direction (higher in the positive direction of the Z direction). Furthermore, the lowest step portion TD1 of the third descending section DS3 is located higher than the highest step portion TU6 of the third ascending section US3, which is adjacent to the third descending section DS3 in the X direction. Additionally, the highest step portion TD6 of the second descending section DS2 is located lower than the lowest step portion TD1 of the first descending section DS1, and the lowest step portion TD1 of the second descending section DS2 is located higher than the highest step portion TU6 of the first ascending section US1.

[0032] exist Figures 2-4In the illustrated configuration, 30 contact points (CTs) are arranged in six units each in the first descending section DS1, the second descending section DS2, the first ascending section US1, the third descending section DS3, and the third ascending section US3. The step portions TD1-TD6 of the first descending section DS1, the step portions TD1-TD6 of the second descending section DS2, the step portions TU1-TU6 of the first ascending section US1, the step portions TD1-TD6 of the third descending section DS3, and the step portions TU1-TU6 of the third ascending section US3 each contain an insulating layer IS composed of different unit layers. The 30 contact points (CTs) are connected to different word lines (WLs) via contact holes formed in the step portions TD1-TD6 and TU1-TU6 of the first descending section DS1, the second descending section DS2, the first ascending section US1, the third descending section DS3, and the third ascending section US3. Furthermore, the reason why the contact CT is not configured in the second step US2 is that the step sections TU1 to TU6 constituting the second step US2 cannot be composed of independent unit layers.

[0033] With the aforementioned configuration, the step portions TD1-TD6 of the first descending section DS1, the step portions TD1-TD6 of the second descending section DS2, the step portions TU1-TU6 of the first ascending section US1, the step portions TD1-TD6 of the third descending section DS3, and the step portions TU1-TU6 of the third ascending section US3 can each be formed from different layers (unit layers comprising word lines WL and insulating layers IS). Thus, 30 contact points CT can be connected to mutually different word lines WL.

[0034] In this embodiment, such as Figure 3 As shown, in the first descending section DS1, the first ascending section US1, the third descending section DS3, and the third ascending section US3, the 24 contact CTs are arranged in a straight line along the X direction when viewed from above. Furthermore, in this embodiment, the six contact CTs each of the step sections TD1 to TD6 in the second descending section DS2 and the six contact CTs each of the step sections TU1 to TU6 in the first ascending section US1 are arranged along the Y direction. Thus, multiple contact CTs can be arranged side-by-side along the X direction.

[0035] also, Figures 2-4 The example illustrates a connection portion WC comprising a single connecting unit (formed inside the two slits S) with three descending sections and three ascending sections, each descending and ascending section having a configuration of six stepped sections. However, the number of descending and ascending sections, as well as the number of stepped sections, is not limited to this. For example, four or more descending and ascending sections may be provided in each of the connection portions WC constituting a single connecting unit. Furthermore, the number of stepped sections may be seven or more, or five or fewer, in each of the descending and ascending sections.

[0036] With this configuration, the area of ​​the contact section WC can be effectively utilized, thereby forming a stepped section capable of accommodating numerous contact CTs. Thus, the number of contact CTs that can be configured can be increased without enlarging the contact section WC.

[0037] The manufacturing method of the contact part WC as described above will be explained below.

[0038] Figure 5 This is a top view showing an example of the state of the contact portion WC in the first stage of the manufacturing method of the semiconductor memory device according to the embodiment. Figure 6 yes Figure 5 The VI-VI cross-sectional view shows an example of the state of the contact portion WC in the first stage of the manufacturing method of the semiconductor memory device according to the embodiment. Figure 6 In the text, only the top 6 layers of the stacked volume LB are recorded, omitting the parts below the 7th layer.

[0039] like Figure 5 As shown, firstly, three mortar-shaped recesses M1 to M3 (first recess M1, second recess M2, and third recess M3) are formed in a staggered manner on the laminated body LB constituting the contact portion WC, viewed from above. The recesses M1 to M3 can be formed, for example, by alternately performing etching and refinement to create recesses M1 to M3 with a specified number (six in this embodiment) of steps, but this is not particularly limited. For example, firstly, a resist pattern is formed so that the bottom layers B1 to B3 corresponding to the recesses M1 to M3 are exposed in a staggered manner, and the exposed layer is etched using an etching technique such as RIE (Reactive Ion Etching). Then, using isotropic etching, the resist pattern is refined from the ends in the X and Y directions with a width equivalent to the step portion of the step structure. The refined resist pattern is then used as a mask for further etching to refine the resist pattern. By repeating this process a specified number of times, mortar-shaped recesses M1 to M3 are formed, with their area (diagonal length) expanding in a stepped manner from the bottom B1 to B3.

[0040] Figure 7 This is a top view showing an example of the state of the contact portion WC in the second stage of the manufacturing method of the semiconductor memory device according to the embodiment. Figure 8 yes Figure 7 Section VIII-VIII shows an example of the state of the contact portion WC in the second stage of the manufacturing method of the semiconductor memory device according to the embodiment. Figure 8 In the text, only the top 12 layers of the stacked volume LB are recorded, omitting the parts below the 13th layer.

[0041] In Phase 2, such as Figure 7As shown, a resist pattern R is formed covering half of the negative X-direction side (near the memory cell array MA) of the first recess M1 and the entire second recess M2. Etching is performed in this state, and as... Figure 8 As shown, half of the positive X-direction side (the side farther from the memory cell array MA) of the first recess M1 and the entire third recess M3 are moved downwards (to the negative Z-direction). Thus, the first recess M1 is divided into upper and lower parts, forming the first descending section DS1 and the first ascending section US1. At this time, the lowest step TD1 of the first descending section DS1 is located one layer higher than the highest step TU6 of the first ascending section US1.

[0042] Figure 9 This is a top view showing an example of the state of the contact portion WC in the third stage of the manufacturing method of the semiconductor memory device according to the embodiment. Figure 10 yes Figure 9 The XX cross-sectional view shows an example of the state of the contact portion WC in the third stage of the manufacturing method of the semiconductor memory device according to the embodiment. Figure 10 In the text, only the top 18 layers of the stacked volume LB are recorded, omitting the parts below the 19th layer.

[0043] In Phase 3, such as Figure 9 As shown, a resist pattern R is formed by covering half of the negative X-direction side of the first recess M1, half of the positive X-direction side of the second recess M2, and half of the negative X-direction side of the third recess M3. Etching is performed in this state, and as... Figure 10 As shown, half of the positive X-direction side of the first recess M1, half of the negative X-direction side of the second recess M2, and half of the positive X-direction side of the third recess M3 are moved downwards. Thus, the second recess M2 is divided into upper and lower parts, forming the second descending recess DS2 and the second ascending recess US2. Similarly, the third recess M3 is divided into upper and lower parts, forming the third descending recess DS3 and the third ascending recess US3. At this point, the lowest step TD1 of the first descending recess DS1 is located 7 layers higher than the highest step TU6 of the first ascending recess US1. Furthermore, the lowest step TD1 of the third descending recess DS3 is located 1 layer higher than the highest step TU6 of the third ascending recess US3.

[0044] Figure 11 This is a top view showing an example of the state of the contact portion WC in the fourth stage of the manufacturing method of the semiconductor memory device according to the embodiment. Figure 12 yes Figure 11 The XII-XII cross-sectional view shows an example of the state of the contact portion WC in the fourth stage of the manufacturing method of the semiconductor memory device according to the embodiment. Figure 12 The document describes all 30 layers of the laminate LB of this embodiment.

[0045] In stage 4, such as Figure 11 As shown, a resist pattern R is formed such that it covers half of the negative X-direction side of both the first recess M1 and the second recess M2. Etching is then performed in this state, and as... Figure 12 As shown, half of the positive side of the second recess M2 in the X direction and the entire third recess M3 move downwards. At this time, the uppermost step TD6 of the second descending section DS2 is located one level lower than the lowermost step TD1 of the first descending section DS1, and the lowermost step TD1 of the second descending section DS2 is located one level higher than the uppermost step TU6 of the first ascending section US1. Other parts are... Figure 10 The state is the same in stage 3 shown.

[0046] By using the manufacturing method described above, it is possible to manufacture a semiconductor memory device having a contact portion WC that can be configured with a large number of contact CTs in a compact configuration.

[0047] Several embodiments of the present invention have been described above, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0048] [Explanation of Symbols]

[0049] 10 Semiconductor memory devices

[0050] B1~B3 Bottom

[0051] CT contacts

[0052] DS1~DS3 De-order section

[0053] IS insulation layer

[0054] LB stack

[0055] M1~M3 concave part

[0056] MA memory cell array

[0057] MC storage unit

[0058] R Anti-corrosion pattern

[0059] S slit

[0060] Substrate

[0061] TD1~TD6, TU1~TU6 stepped sections

[0062] US1~US3 Upgrade Section

[0063] WL lettering.

Claims

1. A semiconductor memory device, comprising a memory cell array and a contact portion, The memory cell array is formed by arranging memory cells in three dimensions on a stacked volume, and the stacked volume has multiple cell layers containing groups of conductive layers and insulating layers; the contact portion connects the conductive layer and the contact; and The contact portion includes a step-down portion and a step-up portion. The step-down portion has a plurality of steps that gradually decrease in order in a first direction away from the memory cell array. The step-up portion and the step-down portion are adjacent to each other in a second direction orthogonal to the first direction. The ascending section has multiple stepped sections that ascend step by step in the first direction, and the multiple ascending sections are arranged in a staggered manner when viewed from above; The contact point of the stepped portion of the descending portion and the contact point of the stepped portion of the ascending portion are arranged along the second direction, and the plurality of descending portions are arranged in a staggered manner when viewed from above.

2. The semiconductor memory device according to claim 1, wherein The lowest step of the descending section is located above the highest step of the ascending section that is adjacent to the descending section in the first direction.

3. The semiconductor memory device according to claim 1, wherein... The position of the lowest step of the reduced-order section is higher than the position of the highest step of the reduced-order section, which is located at a position farther away from the memory cell array than the reduced-order section.

4. The semiconductor memory device according to claim 1, wherein The lowest step of the descending section is located above the highest step of the ascending section that is adjacent to the descending section in the second direction.

5. The semiconductor memory device according to claim 1, wherein... It has multiple of the aforementioned contact portions, and The two adjacent contact portions in the second direction are electrically separated by a slit extending along the first direction.

6. The semiconductor memory device according to claim 5, wherein One of the contact portions formed inside the two slits includes three or more of the reduced-order portions and three or more of the increased-order portions.

7. The semiconductor memory device according to claim 6, wherein The descending section has six or more of the aforementioned stepped sections. Each of the ascending sections has more than six stepped sections.

8. The semiconductor memory device according to claim 1, wherein The contact portion includes the ascending portion where no contact is configured.

9. The semiconductor memory device according to claim 1, wherein The conductive layer at the bottom of the stacked layer functions as the source-side gate selection line. The conductive layer at the top of the stacked body functions as the drain-side gate selector line.

10. A method for manufacturing a semiconductor memory device, comprising a memory cell array and a contact portion, wherein the memory cell array is formed by three-dimensionally arranging memory cells on a multilayer, the multilayer having a plurality of cell layers comprising conductive layers and insulating layers; and the contact portion connects the conductive layers and the contact portion; and The method for manufacturing the semiconductor memory device includes the following steps: At the contact point, multiple recesses in the shape of a mortar are formed in a staggered manner when viewed from above; A descending section and a ascending section are formed by dividing the plurality of recessed portions into two parts along a first direction away from the memory cell array. The descending section has a plurality of stepped sections that descend gradually in the first direction, and the ascending section has a plurality of stepped sections that ascend gradually in the first direction, and is adjacent to the descending section in a second direction orthogonal to the first direction; and The contact point of the stepped portion disposed in the descending section and the contact point of the stepped portion disposed in the ascending section are arranged along the second direction.

11. The method for manufacturing a semiconductor memory device according to claim 10, wherein... It also includes the following steps: The plurality of the reduced-order portions are arranged in a staggered manner when viewed from above; and The multiple ascending parts are arranged in a staggered manner when viewed from above.

12. The method for manufacturing a semiconductor memory device according to claim 11, wherein... It also includes the following steps: positioning the lowest step of the descending part above the uppermost step of the ascending part that is adjacent to the descending part in the first direction.

13. The method for manufacturing a semiconductor memory device according to claim 11, wherein... It also includes the following steps: positioning the lowest step of the reduced-order section above the uppermost step of the reduced-order section, which is located at a position farther from the memory cell array than the reduced-order section.

14. The method for manufacturing a semiconductor memory device according to claim 11, wherein... It also includes the following steps: positioning the lowest step of the descending part above the uppermost step of the ascending part that is adjacent to the descending part in the second direction.

15. The method for manufacturing a semiconductor memory device according to claim 10, wherein... It also includes the steps of: forming a plurality of said contact portions adjacent to each other in the second direction, and the plurality of said contact portions being electrically separated by a slit extending along the first direction.

16. The method for manufacturing a semiconductor memory device according to claim 15, wherein... It also includes the following steps: forming three or more descending portions and three or more ascending portions in one of the contact portions formed inside the two slits.

17. The method for manufacturing a semiconductor memory device according to claim 16, wherein... It also includes the following steps: In each of the descending sections, six or more of the stepped sections are formed; and In each of the aforementioned ascending sections, six or more of the aforementioned stepped sections are formed.

18. The method for manufacturing a semiconductor memory device according to claim 10, wherein... It also includes the following step: forming the raised section where the contact is not configured.

19. The method for manufacturing a semiconductor memory device according to claim 10, wherein... It also includes the following steps: The conductive layer forming the bottommost layer of the stacked body serves as the source-side gate selection line; and The conductive layer forming the uppermost layer of the stacked body serves as the drain-side selected gate line.

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