Display panel and display device

Abstract

The present application provides a display panel and a display device, including a display area and a step area outside the display area; the display panel includes a substrate and a plurality of power lines arranged along a first direction and extending along a second direction on the substrate and located in the display area, wherein the first direction is perpendicular to the second direction; a functional device area including a plurality of functional devices and a power signal lead area including a first power lead pattern extending along the first direction are arranged on the substrate and located in the step area; a first insulating layer is provided between the film layer where the first power lead pattern is located and all the film layers used by the functional device. The present application forms a three-dimensional space structure in which the first power lead pattern and the functional device are stacked up and down, reduces the width of the step area, and meets the specification requirements of the extreme narrow step.

Description

[0001] This application is a divisional application with the application date of May 31, 2019, application number 201910471748.2, and invention name “A display panel and display device”. [Technical field]

[0002] The present invention relates to the field of display technology, and in particular to a display panel and a display device. [Background technology]

[0003] With the development of the information society, people's demand for display devices is growing. Display devices such as liquid crystal display devices and organic light-emitting diode (OLED) display devices have been rapidly developed. Among them, OLED display devices are gradually occupying a dominant position in the display field due to their many advantages such as active light emission, high contrast, fast response speed, and light weight. At present, OLED display devices have been widely used in various high-performance display fields such as mobile phones, televisions, computers, and smart watches.

[0004] Consumers are pursuing narrow borders, so in the field of OLED display technology, how to reduce the borders is a technical issue that everyone is studying. [Summary of the invention]

[0005] In view of this, embodiments of the present invention provide a display panel and a display device to solve the above technical problems.

[0006] On the one hand, an embodiment of the present invention provides a display panel, comprising a display area and a step area located outside the display area; the display panel comprises a base substrate and a plurality of power lines arranged along a first direction and extending along a second direction, which are arranged on the base substrate and located in the display area, and the first direction is perpendicular to the second direction; a functional device area comprising a plurality of functional devices and a power signal lead area comprising a first power lead pattern extending along the first direction are arranged on the base substrate and located in the step area; a first insulating layer is provided between the film layer where the first power lead pattern is located and all film layers used by the functional devices.

[0007] On the other hand, an embodiment of the present invention provides a display device, which includes the above-mentioned display panel.

[0008] A display panel and a display device provided by an embodiment of the present invention form a three-dimensional spatial structure in which the first power lead pattern and the functional device are stacked up and down by setting a first insulating layer between the first power lead pattern and the functional device, thereby achieving their respective functions while reducing the width of the step area to meet the specification requirements of the extreme narrow step.

Brief Description of the Drawings

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0010] Figure 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present application;

[0011] Figure 2 yes Figure 1 A schematic cross-sectional view of AA' in the display panel;

[0012] Figure 3 yes Figure 1 A partial enlarged schematic diagram of a step area in a display panel;

[0013] Figure 4 It is a partial enlarged schematic diagram of a step area in the display panel of the present application;

[0014] Figure 5 is another partial enlarged schematic diagram of the step area in the display panel of the present application;

[0015] Figure 6 This is another partial enlarged schematic diagram of the step area in the display panel of the present application;

[0016] Figure 7 yes Figure 1 A schematic cross-sectional view of AA' in another embodiment of a display panel;

[0017] Figure 8 yes Figure 1 A schematic cross-sectional view taken along line AA' in another embodiment of a display panel;

[0018] Fig. 9 yes Figure 1 A schematic cross-sectional view taken along line AA' in another embodiment of a display panel;

[0019] Fig.10 yes Figure 1 A schematic cross-sectional view taken along line AA' in another embodiment of a display panel;

[0020] Fig.11 yes Figure 1 Another partial enlarged schematic diagram of a step area in a display panel;

[0021] Fig.12 yes Fig.11 A schematic cross-sectional view of a display panel BB';

[0022] Fig.13is a schematic diagram of a display device according to an embodiment of the present application; [Specific implementation method]

[0023] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0024] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0026] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0027] It should be understood that, although the terms first, second, third, etc. may be used to describe the power lead patterns in the embodiments of the present invention, these power lead patterns should not be limited to these terms. These terms are only used to distinguish the power lead patterns from each other. For example, without departing from the scope of the embodiments of the present invention, the first power lead pattern may also be referred to as the second power lead pattern, and similarly, the second power lead pattern may also be referred to as the first power lead pattern.

[0028] As described in the background technology, the current "full screen" has become a new trend in the field of display technology. In addition to the screen-to-body ratio, the uniformity of the border area is also an important factor in measuring the full screen. In a traditional display panel, the display panel includes four borders, namely, the upper, lower, left and right borders. The upper border usually does not need to be provided with special functional devices except for the packaging area; the left and right widening usually requires the setting of a gate drive circuit and a packaging area; and the lower border, that is, the step area, usually needs to be provided with a variety of functional circuits, power leads, packaging areas and binding terminals, and the devices required to be provided are far more than the upper border and the left and right borders. Therefore, the width of the step area is much larger than the width of the upper border and the left and right borders, which makes the uniformity of the width of the display panel border poor, and the "full screen" effect is poor. Based on this, the present application provides a display panel that can shorten the width of the step area to meet the specification requirements of the extreme narrow step. And the border width tends to be uniform, achieving an excellent full-screen display effect.

[0029] Please refer to Figure 1 , Figure 2 and Figure 3 , Figure 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present application; Figure 2 yes Figure 1 A schematic cross-sectional view of AA' in the display panel; Figure 3 yes Figure 1 A partial enlarged schematic diagram of a step area in a display panel;

[0030] like Figure 1 , Figure 2 and Figure 3 As shown, the display panel is provided with a display area AA and a step area STP located outside the display area 1. The display panel includes a base substrate 110 and a plurality of power lines 201 arranged along a first direction D1 and extending along a second direction D2 on the base substrate 110 and located in the display area AA, wherein the first direction is perpendicular to the second direction. Figure 1 , Figure 2 and Figure 3 As shown, a functional device area 30 including a plurality of functional devices 300 and a power signal lead area 20 including a first power lead pattern 202a extending along a first direction are provided on the base substrate 110 and located in the step area STP. A first insulating layer 144 is provided between the film layer where the first power lead pattern 202a is located and all the film layers used by the functional device 300. The first insulating layer 144 has an insulating and isolating effect on the first power lead pattern 202a and the functional device 300, thereby preventing a short circuit from occurring between the first power lead pattern 202a and the structure in the functional device 300, thereby reducing the product defect rate of the display panel, and further improving the display effect of the picture.

[0031] In the embodiment of the present invention, the first power lead pattern 202a and the functional device 300 are located in different film layers, so the first power lead pattern 202a and the functional device 300 can be stacked in upper and lower layers to form a three-dimensional space structure. There is no need to arrange them in parallel in the first direction, which reduces the space occupied by the first power lead pattern 202a and the functional device 300 in the step area, so that the display device can achieve a narrower step design. While achieving their respective functions, the width of the step area is reduced to meet the specification requirements of the extreme narrow step.

[0032] Please continue to refer to Figure 2As shown, the orthographic projections of the power signal lead area 20 and the functional device area 30 on the plane where the substrate 110 is located at least partially overlap, reducing the space occupied by the first power lead pattern and the functional device wiring in the step area, so that the display device can achieve a narrower step design. Among them, the overlapping area of ​​the power signal lead area 20 and the functional device area 30 is greater than or equal to 50% of the area of ​​the functional device area 30, further reducing the space occupied by the first power lead pattern and the functional device wiring in the step area, so that the display device can further achieve a narrower step design.

[0033] In the embodiment of the present invention, the functional device region 30 includes at least one of a gating circuit region, a short circuit region or an ESD circuit region.

[0034] Please refer to Figure 4 , Figure 5 and Figure 6 , Figure 4 It is a partial enlarged schematic diagram of a step area in the display panel of the present application; Figure 5 is another partial enlarged schematic diagram of the step area in the display panel of the present application; Figure 6 This is another partial enlarged schematic diagram of the step area in the display panel of the present application;

[0035] Please refer to Figure 4 , Figure 4 The short circuit area is shown, and the short circuit area includes a plurality of short circuit units 301. The short circuit 301 includes a short transistor, and the short transistor includes a short transistor active layer 301P and a short transistor gate 301G overlapping therewith. The short transistor source 301S is connected to the signal input line 3011, the short transistor drain 301D is connected to each data fan-out line 402, and each short transistor gate 301G is connected to the control signal line 3012. When the control signal line 3012 inputs a conduction level, each short transistor is turned on, and the signal input line 3011 inputs the data signal to each data fan-out line 402 through the short transistor, and transmits it to the data line 401 located in the display area. In this way, only the same data signal is needed to realize the lighting of the entire display panel. There is no need for the driver chip IC to participate in lighting, and the screen can be tested without binding the driver chip IC, avoiding discovering screen problems after binding the driver chip IC and avoiding wasting the driver chip. Because the driver chip is one of the most expensive components in the display panel, setting a short circuit can greatly reduce production costs.

[0036] Please refer to Figure 5 , Figure 5The ESD circuit area, that is, the electrostatic protection circuit area, is shown. The ESD circuit area includes multiple ESD circuit units 302, and the ESD circuit unit 302 includes a first transistor and a second transistor. The gate 3021G of the first transistor is connected to the drain 3021D of the first transistor, and is also connected to the data fan-out line 402, and the source 3021S of the first transistor is connected to the low-level signal line VGL; the gate 3022G of the second transistor is connected to the drain 3022D of the second transistor, and is also connected to the high-level signal line VGH, and the source 3022S of the second transistor is connected to the data fan-out line 402. When the data line 401 is subjected to static electricity, it is transmitted to the data fan-out line 402; if it is ultra-high level static electricity, since the ultra-high level is much higher than the high level signal of the second transistor gate 3022G, the second transistor is turned on, and the ultra-high level static electricity is exported to the high level signal line VGH through the second transistor; if it is ultra-low level static electricity, since the ultra-low level static electricity is transmitted to the first transistor gate 3021G, this potential is much lower than the low level signal of the first transistor source 3021S, the first transistor is turned on, and the ultra-low level is exported to the low level signal line VGH through the first transistor. In a normal state, the voltage of the data fan-out line 402 is between the high level and the low level, and the first transistor and the second transistor are cut off, which does not affect the normal operation of the display panel. The ESD circuit of this embodiment can avoid static electricity accumulating on the data line 401 and the data fan-out line 402 and damaging the data line, resulting in display abnormality.

[0037] Please continue to refer to Figure 6 , Figure 6 A gating circuit area is shown, which includes multiple gating circuit units 303, and the gating circuit unit 303 includes a third transistor and a fourth transistor; the gate 3031G of the third transistor is connected to the first gating signal line CKH1, and the drain 3031D of the third transistor is connected to a data line 401; the gate 3032G of the fourth transistor is connected to the second gating signal line CKH2, and the drain 3032D of the fourth transistor is connected to another data line 401; the source 303S of the third transistor and the fourth transistor are simultaneously connected to the driver chip IC. In this embodiment, for example, the drain 3031D of the third transistor is connected to the data lines of the odd array, and the drain 3032D of the fourth transistor is connected to the data lines of the even array. When the first selection signal line CKH1 outputs a conduction level and the second selection signal line CKH2 outputs a cut-off level, the data signal is transmitted from the driver chip IC to the data lines of the odd array through the third transistor; when the first selection signal line CKH1 outputs a cut-off level and the second selection signal line CKH2 outputs a conduction level, the data signal is transmitted from the driver chip IC to the data lines of the even array through the fourth transistor; in this way, the number of data fan-out lines connected to the driver chip IC will be halved, which can greatly reduce the space occupied by the data fan-out lines, reduce the width of the step area, and achieve a narrow frame.

[0038] In an embodiment of the present invention, the functional device area 30 includes at least one of a gating circuit area, a short circuit area or an ESD circuit area. The power signal lead area 20 overlaps with the orthographic projection of any one of the gating circuit area, the short circuit area and the ESD circuit area on the plane where the substrate 110 is located; or, the power signal lead area 20 overlaps with the orthographic projection of any two of the gating circuit area, the short circuit area and the ESD circuit area on the plane where the substrate 3 is located; or, the power signal lead area 20 overlaps with the orthographic projections of the gating circuit area, the short circuit area and the ESD circuit area on the plane where the substrate 3 is located. Figure 7 As shown, Figure 7 yes Figure 1 A schematic cross-sectional view of AA' in another embodiment of a display panel; Figure 7 It shows a situation that the power signal lead area 20 overlaps with the short circuit area 3010 and the gate circuit area 3030 at the same time, but does not overlap with the ESD circuit area 3020.

[0039] In the embodiment of the present invention, a plurality of functional devices 300 may be arranged in the functional device area 30. Figure 4 , Figure 5 and Figure 6 Only three functional devices 300 are shown as examples. The functional device 300 may also include other functional devices, which are not listed here one by one.

[0040] like Figure 2 and Figure 8 As shown, Figure 8 yes Figure 1 A schematic cross-sectional view of AA' in another embodiment of the display panel; in the embodiment of the present invention, each power line 201 is electrically connected to the first power lead pattern 202a through a first connecting line 203, and the first connecting line 203 is located in the step area. The first connecting line 203 can be an extension of the power line 201, that is, the first connecting line 203 is an extension of the power line 201 extending from the display area AA to the step area STP; or, the first connecting line 203 can also be a separately arranged connecting line. In the embodiment of the present invention, the power line 201 can be a VDD signal line, which is used to drive the circuit to generate a driving current.

[0041] Furthermore, in an embodiment of the present invention, the functional device area 30 includes a first metal layer 131 and a second metal layer 133 stacked from close to the base substrate 110 to away from the base substrate 110, and the film layer used by the first power lead pattern 202a is the third metal layer 134, and the third metal layer 134 is located on the side of the first insulating layer 144 away from the base substrate 110.

[0042] Specifically, Figure 8As shown, the display panel of the present application includes a base substrate 110, an active layer 120, a first metal layer 131, a capacitor metal layer 132, a second metal layer 133, and a light-emitting device electrically connected to the second metal layer, and a packaging substrate 160, which are sequentially arranged on the base substrate 110; the light-emitting device includes a first electrode layer 151, a second electrode layer 153, and an organic light-emitting layer 152 located between the first electrode layer 151 and the second electrode layer 153. A gate insulating layer 141 is arranged between the active layer 120 and the first metal layer 131; a first interlayer insulating layer 142 is arranged between the first metal layer 131 and the capacitor metal layer 132; a second interlayer insulating layer 143 is arranged between the capacitor metal layer 132 and the second metal layer 133; a first insulating layer 144 is arranged on the side of the second metal layer 133 away from the base substrate 110; and a second insulating layer 145 is arranged between the first electrode 151 and the third metal layer 134. The planarization layer 144 between the third metal layer 134 and the first electrode layer 151 and the pixel definition layer 146 disposed between the first electrode layer 151 and the second electrode layer 153. In the embodiment of the present application, the first electrode layer is used as an anode and the second electrode layer is used as a cathode.

[0043] The functional device 300 in the functional device area 30 needs to set up a corresponding transistor to realize the function of the device, and the setting of the transistor requires the active layer 120 as a semiconductor, the first metal layer 131 as a gate, the second metal layer 133 as a source and drain, and the insulating layer therebetween to form a transistor. Therefore, the present application sets up a third metal layer 134 and a first insulating layer 144, sets the first power lead pattern 202a on the third metal layer 134, and overlaps with the functional device 300 to form a three-dimensional space structure stacked up and down, while realizing their respective functions, reducing the width of the step area to meet the specification requirements of the extreme narrow step.

[0044] For further information, please continue to refer to Figure 8, the film layer used for the power line 201 is the second metal layer 133. In the display panel, the first metal layer is used to set the scan line as the gate of the transistor. The second metal layer is used to set the data line. Since the data line is used to transmit data signals and determines the accuracy of the brightness of the light-emitting device, the data line requires a small resistance, while the scan line only needs to turn on the transistor, and the voltage accuracy requirement is not high. Therefore, the square resistance of the second metal layer is much smaller than the square resistance of the first metal layer. The present application sets the power line 201 in the second metal layer 133, which can reduce the voltage drop of the power line 201 and make the display panel display uniform. The extension line 203 of the second metal layer power line is located in the step area STP, and the extension line 203 of the power line is electrically connected to the first power lead pattern 202a through the first via H1 set in the first insulating layer 144; the power signal is transmitted to the power line 201 through the first power lead pattern 202a. The first insulating layer 144 is separated between the first power lead pattern 202a and the functional device 300 to form a three-dimensional space structure stacked up and down, which can realize their respective functions while reducing the width of the step area to meet the specification requirements of the extreme narrow step.

[0045] In another embodiment of the present application, please refer to Fig.10 , Fig.10 yes Figure 1 A schematic cross-sectional view of AA' in another embodiment of the display panel; the film layer used for the power line 201 is the third metal layer 134, the extension line 203 of the power line 201 is located in the STP step area, and the extension line 203 of the power line is directly electrically connected to the first power lead pattern 202a; since the third metal layer 134 is provided with the first power lead pattern 203, the square resistance of the third metal layer is relatively small, and the power line 201 is provided in the third metal layer 134. The resistance of the power line 201 can be reduced, and the voltage drop of the power line can be reduced. At the same time, the space of the second metal layer can be vacated for the data line, the width of the data line is widened, and the voltage drop on the data line is reduced. In addition, the overlapping arrangement of the data line and the power line can reduce the area of ​​the opaque area of ​​the display panel and increase the light transmittance of the display panel, which is conducive to the realization of under-screen fingerprint recognition or under-screen camera.

[0046] In another embodiment of the present application, please refer to Fig. 9The power line 201 includes a first power line 201a and a second power line 201b. The film layer used by the first power line 201a is the second metal layer 133, and the film layer used by the second power line 201b is the third metal layer 134. The extension line 203b of the second power line 201b is located in the step area STP. The extension line 203b of the second power line 201b is directly electrically connected to the first power lead pattern 202a. The extension line 203a of the first power line is electrically connected to the first power lead pattern 202a through the first via H1 set in the first insulating layer 144. As mentioned above, the second metal layer 133 and the third metal layer 134 are both made of materials with relatively low square resistance, and in this embodiment, the first power line and the second power line are both connected to the first power lead pattern, which is equivalent to connecting the first power line and the second power line in parallel, which can further reduce the resistance of the power line and reduce the voltage drop of the power line. In addition, the width of the power line can be narrowed in parallel, which can reduce the area of ​​the opaque area of ​​the display panel and increase the transmittance of the display panel, which is conducive to the realization of under-screen fingerprint recognition or under-screen camera.

[0047] In another embodiment of the present application, please refer to Fig. 9 , Fig. 9 yes Figure 1 A cross-sectional schematic diagram of AA' in another embodiment of the display panel; the display panel of this embodiment includes a power signal lead area 20 and also includes a second power lead pattern 202b, the second power lead pattern 202b and the first power lead pattern 202a are located in the same film layer; the display panel also includes a second insulating layer 145 located on the side of the second power lead pattern 202b away from the base substrate 110, a conductive connecting layer 40 located on the side of the second insulating layer 145 away from the base substrate 110, and a third insulating layer 146 located on the side of the conductive connecting layer 40 away from the base substrate 110; the display panel also includes a cathode layer 153 located on the side of the second power lead pattern 202b away from the base substrate 110, the cathode layer 153 is electrically connected to the conductive connecting layer 40 through a second via H2 set in the third insulating layer 146; the conductive connecting layer 40 is electrically connected to the second power lead pattern 202b through a third via H3 set in the second insulating layer 145.

[0048] The display panel generates a driving current by the pixel driving circuit, and the driving current flows through the light-emitting device to make the OLED display panel emit light. The first power supply voltage VDD transmitted by the first power supply lead pattern 202a is transmitted to the corresponding source of the driving transistor, and the data voltage signal of the gate of the driving transistor generates a driving current, which flows from the anode 151 of the light-emitting device to the cathode 153 of the light-emitting device. The cathode potential transmitted by the second power supply lead pattern 202b is transmitted to the cathode of the light-emitting device. Therefore, when the entire display panel emits light, all sub-pixels of the entire display panel generate a driving current. Therefore, the first power supply lead pattern 202a and the second power supply lead pattern 202b need to withstand the passage of a large current. The present application sets the first power supply lead pattern 202a and the second power supply lead pattern 202b to be located in the third metal layer 134 to reduce resistance and reduce voltage drop. And the first power supply lead pattern 202a and the second power supply lead pattern 202b are arranged to overlap with the functional device 300 to form a three-dimensional spatial structure, while increasing the area of ​​the first power supply lead pattern and the second power supply lead pattern, reducing the width of the step area. Furthermore, by increasing the areas of the first power lead pattern and the second power lead pattern, the current tolerance can be increased, thereby improving the stability of the display panel.

[0049] Furthermore, the thickness of the second insulating layer 145 and / or the first insulating layer 144 in the third direction is equal to 1.5 μm, and the third direction is a direction perpendicular to the plane where the substrate is located, so as to reduce the coupling between signal lines, avoid affecting the operation of the functional device 300, and avoid display abnormality.

[0050] In another embodiment of the present application, please continue to refer to Fig. 9 Since the cathode 153 is disposed in the entire display area through an evaporation process, in the present application, the cathode 153 extends to the step area, and is connected to the conductive connection layer 40 through the second via H2, and is connected to the second power lead pattern 202b through the third via H3, thereby conducting the cathode potential. Further, the conductive connection layer 40 and the anode 151 are disposed in the same layer, and the conductive connection layer 40 covers at least part of the first power lead pattern 202a and the second power lead pattern 202b, which can increase the contact area, reduce the contact resistance, and reduce the voltage drop of the cathode potential.

[0051] In another embodiment of the present application, please continue to refer to Fig.10 , Fig.10 yes Figure 1A cross-sectional schematic diagram of AA' in another embodiment of the display panel; the second power lead pattern 202b is located on a side of the first power lead pattern 202a away from the display area, and the conductive connection layer 40 is electrically connected to the cathode layer 153 extending from the display area to the step area through the second via H2; if the second power lead pattern 202b is set on a side of the first power lead pattern 202a close to the display area, the second power lead pattern 202b will block the connection between the first power lead pattern 202a and the power line 201. Therefore, in this embodiment, the second power lead pattern 202b is set away from the display area, and is connected to the cathode 153 through the conductive connection layer 40, thereby realizing potential conduction between the power line 201 and the cathode 153.

[0052] Furthermore, since the cathode is deposited by an evaporation process, and since there is a gap between the evaporation mask and the display panel during the evaporation process, the deposited material will enter the portion covered by the mask through the gap. When the boundary of the cathode 153 is too close to the functional device 300, the cathode 153 may be evaporated to the binding terminal located on the side of the functional device 300 close to the cutting edge, thereby short-circuiting the binding terminal. Therefore, in this embodiment, the cathode 153 is arranged not to overlap with the second power lead pattern 202b. Therefore, the edge of the cathode 153 can be kept away from the binding terminal to avoid short-circuiting the binding terminal during cathode evaporation.

[0053] For further information, please refer to Fig.11 and Fig.12 , Fig.11 yes Figure 1 Another partial enlarged schematic diagram of a step area in a display panel; Fig.12 yes Fig.11 A schematic cross-sectional view of the display panel BB'; the display panel also includes a frame area NA located on the left and right sides of the display area AA, the frame area NA is arranged adjacent to the step area and extends along the second direction. The second power lead pattern 202b is located on the side of the first power lead pattern 202a close to the frame area and extends from the step area to the frame area, the conductive connection layer 40 is electrically connected to the cathode layer 153 extending from the display area to the frame area through the second via H2, and the frame area NA is located at the periphery of the display area and is arranged on both sides of the display area AA along the second direction. This embodiment can transmit the cathode potential from the periphery of the display panel to the middle of the display panel, reduce the voltage drop of the cathode potential, and improve the display uniformity of the display panel. Furthermore, the second power lead pattern 202b can overlap with the gate drive circuit VSR, reduce the width of the frame area NA, and meet the demand for a narrow frame.

[0054] The embodiment of the present invention further provides a display device, such as Fig.13 As shown, Fig.13The structure diagram of the display device provided in the embodiment of the present invention is as follows. The display device includes the above-mentioned display panel. The specific structure of the display panel has been described in detail in the above-mentioned embodiment and will not be repeated here. Fig.13 The display module shown is only for illustration purposes, and the display module may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader, or a television.

[0055] An embodiment of the present invention provides a light-emitting display panel and a display device. By setting a first insulating layer between a first power lead pattern and a functional device, the first power lead pattern and the functional device form a three-dimensional spatial structure stacked up and down, thereby achieving their respective functions while reducing the width of the step area to meet the specification requirements of the extreme narrow step.

[0056] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: The display panel is provided with a display area and a step area located outside the display area; The display panel includes a base substrate and a plurality of power lines arranged along a first direction and extending along a second direction on the base substrate and located in the display area, wherein the first direction is perpendicular to the second direction; A functional device area including a plurality of functional devices and a power signal lead area including a first power lead pattern extending along the first direction are arranged on the base substrate and located in the step area, wherein the functional device area includes a gating circuit area, and the gating circuit area extends along the first direction; A first insulating layer is provided between the film layer where the first power lead pattern is located and all the film layers used by the functional device; In a direction perpendicular to the plane where the display panel is located, the first power lead pattern and the orthographic projection of the gate circuit area on the plane where the substrate is located at least partially overlap; The functional device area includes a first metal layer, a second metal layer and a third metal layer stacked from close to the substrate to far away from the substrate, the first metal layer is used as the gate of the transistor in the functional device area, the second metal layer is used as the source and drain of the transistor in the functional device area, the first insulating layer is arranged on a side of the second metal layer away from the substrate, the third metal layer is located on a side of the first insulating layer away from the substrate, and the third metal layer is a film layer used by the first power lead pattern; The film layer used for the power line is the second metal layer, the extension line of the power line is located in the step area, and the extension line of the power line is electrically connected to the first power lead pattern through a first via hole provided in the first insulating layer; or, The film layer used for the power line is the third metal layer, the extension line of the power line is located in the step area, and the extension line of the power line is directly electrically connected to the first power lead pattern; or, The power line includes a first power line and a second power line, the film layer used by the first power line is the second metal layer, the film layer used by the second power line is the third metal layer, the extension line of the second power line is located in the step area, the extension line of the second power line is directly electrically connected to the first power lead pattern, and the extension line of the first power line is electrically connected to the first power lead pattern through a first via hole set in the first insulating layer.

2. The display panel according to claim 1, characterized in that: The orthographic projections of the power signal lead area and the functional device area on the plane where the substrate base plate is located at least partially overlap.

3. The display panel according to claim 2, characterized in that: The overlapping area of ​​the power signal lead area and the functional device area is greater than or equal to 50% of the area of ​​the functional device area.

4. The display panel according to claim 1, characterized in that: Each of the power lines is electrically connected to the first power lead pattern via a first connecting line.

5. The display panel according to claim 1, characterized in that: The functional device area includes at least one of a short circuit area and an ESD circuit area.

6. The display panel according to claim 5, characterized in that: The power signal lead area overlaps with any one of the gating circuit area, the short circuit area and the ESD circuit area in the orthographic projection on the plane where the substrate is located; or, The power signal lead area overlaps with any two of the gating circuit area, the short circuit area and the ESD circuit area in their orthographic projection on the plane where the substrate is located; or, The power signal lead area overlaps with the gating circuit area, the short circuit area and the ESD circuit area in their orthographic projections on the plane where the substrate base plate is located.

7. The display panel according to claim 1, characterized in that: The power signal lead area further includes a second power lead pattern, and the second power lead pattern and the first power lead pattern are located in the same film layer; The display panel further comprises a second insulating layer located on a side of the second power lead pattern away from the base substrate, a conductive connecting layer located on a side of the second insulating layer away from the base substrate, and a third insulating layer located on a side of the conductive connecting layer away from the base substrate; The display panel further comprises a cathode layer located on a side of the second power lead pattern away from the base substrate, the cathode layer being electrically connected to the conductive connection layer through a second via hole provided in the third insulating layer; The conductive connection layer is electrically connected to the second power lead pattern through a third via hole provided in the second insulating layer.

8. The display panel according to claim 7, characterized in that: The second power lead pattern is located at a side of the first power lead pattern away from the display area, and the conductive connection layer is electrically connected to the cathode layer extending from the display area to the step area through the second via hole; or, The second power lead pattern is located on a side of the first power lead pattern close to the border area and extends from the step area to the border area. The conductive connection layer is electrically connected to the cathode layer extending from the display area to the border area through the second via hole. The border area is located at the periphery of the display area and is arranged along the second direction.

9. The display panel according to claim 7, characterized in that: The thickness of the first insulating layer in a third direction is greater than or equal to 1.5 μm, and the third direction is a direction perpendicular to the plane where the substrate is located.

10. The display panel according to claim 7, characterized in that: The thickness of the second insulating layer in a third direction is greater than or equal to 1.5 μm, and the third direction is a direction perpendicular to the plane where the base substrate is located.

11. A display device, characterized in that: A display panel comprising any one of claims 1 to 10.

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