High flatness hvpe gallium nitride single crystal substrate and method of making

Abstract

The application discloses a high-flatness HVPE gallium nitride single crystal substrate and a preparation method thereof. When the high-flatness HVPE gallium nitride single crystal substrate is 2'', TTV is less than 3 microns, Bow is less than ±3 microns, and Warp is less than 8 microns. When the high-flatness HVPE gallium nitride single crystal substrate is 4'', TTV is less than 5 microns, Bow is less than ±5 microns, and Warp is less than 10 microns. The application has the beneficial effect that the flatness of the surface of a gallium nitride substrate sheet can be effectively improved after twice annealing treatment, and the TTV, Bow and Warp of the obtained gallium nitride single crystal substrate are obviously improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor substrate material processing, and in particular to HVPE gallium nitride single crystal substrates and their preparation methods. Background Technology

[0002] Gallium nitride (GaN) is an important representative of third-generation semiconductor materials. It has excellent physicochemical properties such as direct bandgap, wide bandgap, high saturated electron drift velocity, high breakdown electric field and high thermal conductivity. It has also received widespread attention in microelectronic applications. It is superior to silicon carbide (SiC) in power devices and laser devices.

[0003] Hydride vapor phase epitaxy (HVPE), used to obtain self-supporting GaN substrates, involves growing GaN on sapphire or GaAs substrates and offers relatively fast growth rates. During growth, the temperature gradient within the growth chamber and the inconsistent growth rates of different parts of the crystal lead to stress accumulation within the GaN crystal. Furthermore, as the GaN crystal thickness increases, the corresponding temperature gradient also increases, resulting in greater internal stress. This uneven stress distribution causes varying degrees of distortion and deformation, ultimately causing the GaN single crystal to "self-peel" from the sapphire substrate.

[0004] After gallium nitride crystal growth, a primary substrate can be fabricated using diamond wire cutting and subsequent double-sided grinding, or by laser cutting and thinning. Regardless of the processing technique, stress will re-accumulate, leading to a deterioration in flatness. Flatness indicators include total thickness variation (TTV), bending radius (BOW), and warp, with warp and bow deteriorating particularly significantly. Although subsequent double-sided or single-sided polishing processes occur, their impact on improving warp and bow is minimal. TTV refers to total thickness variation, BOW to bending radius, and WARP to warp radius.

[0005] The epitaxy and subsequent fabrication of GaN materials have strict requirements for the substrate surface; a poor surface will have a significant impact on the yield of epitaxy.

[0006] Chinese invention patent publication number CN115020215A discloses a method for processing gallium nitride (GaN) substrates, which mentions stress reduction treatment of double-sided polished GaN substrates. The stress reduction treatment of double-sided polished GaN substrates includes: annealing the double-sided polished GaN substrates at an annealing temperature greater than 1000°C and for an annealing time greater than 30 minutes. This method mainly utilizes double-sided polishing to counteract the warping caused by stress and the inherent characteristics of the GaN substrate, making the surface of the GaN substrate more flat.

[0007] Chinese Invention Patent Publication No. CN109003879B discloses a method for forming a gate dielectric layer. Although it discloses two annealing processes, the purpose is to perform the annealing process twice in an oxygen-containing atmosphere to effectively repair the interface between the semiconductor substrate and the first oxide layer, thereby achieving good continuity and flatness at the interface between the semiconductor substrate and the first oxide layer and improving the mobility.

[0008] Chinese invention patent publication number CN113284941A discloses a high-quality silicon carbide substrate and its preparation method. The target is a silicon carbide substrate. In the annealing process, a first cover plate and a second cover plate are covered on the upper and lower surfaces of the silicon carbide crystal. The first cover plate and the second cover plate dissipate heat, reducing the temperature of the silicon carbide crystal seed surface and the growth surface, thereby reducing the stress on the silicon carbide crystal seed surface and the growth surface. Summary of the Invention

[0009] The technical problem to be solved by the present invention is that the existing growth method of gallium nitride single crystal substrate determines that the single crystal has a large internal stress, which in turn determines that the flatness of the processed substrate is poor. This brings great disadvantages to gallium nitride epitaxy and deep processing. To this end, a high flatness HVPE gallium nitride single crystal substrate and its preparation method are provided.

[0010] The technical solution of the present invention is: a high-flatness HVPE gallium nitride single crystal substrate, wherein when the high-flatness HVPE gallium nitride single crystal substrate is 2", TTV < 3μm, Bow < ±3μm, Warp < 8μm; and when the high-flatness HVPE gallium nitride single crystal substrate is 4", TTV < 5μm, Bow < ±5μm, Warp < 10μm.

[0011] The preparation method of high flatness HVPE gallium nitride single crystal substrate includes the following steps: (1) First annealing: the gallium nitride single crystal substrate after HVPE is annealed in the original growth furnace, held at 800℃-1000℃ for 2h-4h, then reduced to 300℃ at a rate of 2℃ / min, and then reduced to room temperature; (2) Second annealing: the gallium nitride single crystal substrate after the first annealing is placed horizontally on the annealing rack in the annealing furnace, held at 700℃-950℃ for 2h-3h, then reduced to 300℃ at a rate of 3℃ / min, and then reduced to room temperature.

[0012] The annealing rack described in the above scheme is made of high-purity graphite with a purity of 99.9999%.

[0013] The annealing rack described in the above scheme includes a rectangular frame and a multi-layer placement plate adapted within the rectangular frame, with a 4mm high step at the loading port of each layer placement plate.

[0014] The above scheme also includes step (3), double-sided rough polishing.

[0015] The above scheme also includes step (4), single-sided semi-finish polishing.

[0016] The above scheme also includes step (5), fine polishing.

[0017] The beneficial effect of this invention is that after two annealing treatments, the flatness of the gallium nitride substrate surface can be effectively improved, and the TTV, Bow and Warp of the obtained gallium nitride single crystal substrate are significantly improved. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the annealing frame of the present invention. Detailed Implementation

[0019] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments implemented by those skilled in the art without creative effort are within the protection scope of the present invention.

[0020] A processing technology and method for obtaining high flatness HVPE gallium nitride wafers, the method comprising: performing a first annealing on gallium nitride ingots after growth.

[0021] The first annealing refers to the in-situ annealing of the HVPE ingot in the original growth furnace. After growth, instead of rapid natural cooling to room temperature, it is held at 800-1000℃ for 2-4 hours, and then slowly reduced to 300℃ at a rate of 2℃ / min. Finally, the heating power of the growth furnace is turned off, allowing it to cool naturally to room temperature.

[0022] The second annealing refers to placing the substrate to be annealed horizontally on a dedicated annealing rack, such as... Figure 1 As shown, the annealing rack is made of high-purity graphite with a purity of 99.9999%. The wafer is kept at a constant temperature of 700℃-950℃ for 2-3 hours, then the temperature is reduced to 300℃ at a rate of 3℃ / min. Finally, the power supply to the annealing furnace is turned off, allowing it to cool naturally to room temperature.

[0023] The first annealing requirement is as follows:

[0024] The temperature is kept constant at 800℃-1000℃ in the growth furnace;

[0025] The temperature can be maintained for 2-4 hours.

[0026] Cooling rate: 2°C per minute;

[0027] Temperature at which cooling ends: 300℃.

[0028] The second annealing requirement is as follows:

[0029] A special annealing rack is used (see drawings for dimensions).

[0030] The special annealing rack is made of graphite. In addition to certain requirements on spacing and size, each layer of the loading port has a 4mm step.

[0031] Graphite material purity: 99.9999 or higher.

[0032] The constant temperature is 700℃-950℃;

[0033] The temperature is maintained for 2-3 hours.

[0034] Cooling rate: 3°C per minute;

[0035] Cooling end temperature: 300℃.

[0036] After two annealing processes, the substrate was subjected to normal subsequent processing, including double-sided rough polishing, single-sided semi-fine polishing, and fine polishing. Finally, a flatness test was performed, and the data obtained are as follows:

[0037] 2" substrate: TTV < 3μm, Bow < ±3μm, Warp < 8μm;

[0038] 4" substrate: TTV < 5 μm, Bow < ± 5 μm, Warp < 10 μm.

[0039] Ten secondary annealing experiments were conducted on five 2" substrates and five 4" substrates under different temperature and time conditions. The data obtained are shown in Table 1.

[0040]

[0041] Table 2 shows the flatness data obtained from 10 experimental groups using a Tropel 200 flatness gauge (USA).

[0042]

[0043] Five 2" substrates and five 4" substrates from the same batch of products were then selected and subjected to 10 non-annealing tests under different temperature and time conditions. The comparative data obtained are shown in Table 3.

[0044]

Claims

1. A method for preparing a high-flatness HVPE gallium nitride single crystal substrate, characterized by: Includes the following steps: Step (1) First annealing: The gallium nitride single crystal substrate after HVPE is annealed in situ in the original growth furnace at 800℃-1000℃ for 2h-4h, then cooled to 300℃ at a rate of 2℃ / min, and then cooled to room temperature; Step (2) Second annealing: The gallium nitride single crystal substrate after the first annealing is placed horizontally on the annealing rack in the annealing furnace, and kept at 700℃-950℃ for 2h-3h, then cooled to 300℃ at a rate of 3℃ / min, and then cooled to room temperature; Step (3) Double-sided rough polishing; Step (4) Single-sided semi-fine polishing; Step (5) Fine polishing. When the high flatness HVPE gallium nitride single crystal substrate is 2", TTV < 3μm, Bow < ±3μm, Warp < 8μm. When the high flatness HVPE gallium nitride single crystal substrate is 4", TTV < 5μm, Bow < ±5μm, Warp < 10μm.

2. The method for preparing a high-flatness HVPE gallium nitride single crystal substrate as described in claim 1, characterized in that: The annealing rack is made of high-purity graphite with a purity of 99.9999%.

3. The method for preparing a high-flatness HVPE gallium nitride single crystal substrate as described in claim 1, characterized in that: The annealing rack includes a rectangular frame and multiple placement plates adapted within the rectangular frame, with each placement plate having a 4mm high step at its loading port.

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