Magnetoresistive random access memory element and manufacturing method thereof

Abstract

The present invention discloses a magnetoresistive random access memory element and a method for manufacturing the same. The method for manufacturing the magnetoresistive random access memory element mainly comprises first forming a magnetic tunneling junction (MTJ) stack structure on a substrate, then forming a first top electrode on the MTJ stack structure, and then forming a second top electrode on the first top electrode, wherein the first top electrode includes a concentration gradient and the second top electrode preferably includes no concentration gradient.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor element, and in particular to a method for manufacturing a magnetoresistive random access memory (MRAM) element. Background Art

[0002] The magnetoresistance (MR) effect is known to occur when a material's electrical resistance changes with an applied magnetic field. Its physical quantity is defined as the difference in resistance in the presence and absence of a magnetic field divided by the original resistance, representing the rate of change of resistance. Currently, the magnetoresistance effect has been successfully applied to hard drive production and holds significant commercial value. Furthermore, by exploiting the characteristic of giant magnetoresistance materials exhibiting varying resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can be fabricated, which has the advantage of retaining stored data even when power is off.

[0003] The magnetoresistance effect is also used in the field of magnetic field sensing. For example, the electronic compass components of the global positioning system (GPS) in mobile phones are used to provide information such as the user's movement direction. Currently, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned existing technologies generally include: occupying more chip area, more expensive manufacturing process, higher power consumption, insufficient sensitivity, and being easily affected by temperature changes, etc., and further improvement is necessary. Summary of the Invention

[0004] One embodiment of the present invention discloses a method for fabricating a magnetoresistive random access memory device. The method mainly forms a magnetic tunneling junction (MTJ) stack structure on a substrate, then forms a first top electrode on the MTJ stack structure, and then forms a second top electrode on the first top electrode. The first top electrode includes a concentration gradient, while the second top electrode preferably does not include a concentration gradient.

[0005] Another embodiment of the present invention discloses a method for manufacturing a magnetoresistive random access memory device, which mainly includes a magnetic tunneling junction (MTJ) disposed on a substrate and a top electrode disposed on the MTJ, wherein the top electrode includes a first top electrode disposed on the MTJ and a second top electrode disposed on the first top electrode, wherein the first top electrode includes a concentration gradient and the second top electrode includes no concentration gradient. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 6 FIG. 1 is a schematic diagram of a method for fabricating an MRAM cell according to an embodiment of the present invention.

[0007] Description of main component symbols

[0008] 12: Base

[0009] 14: MRAM area

[0010] 16:Logical Area

[0011] 18: Interlayer dielectric layer

[0012] 20: Metal interconnect structure

[0013] 22: Metal interconnect structure

[0014] 24: Intermetallic dielectric layer

[0015] 26: Metal interconnects

[0016] 28: Stop layer

[0017] 30: Intermetallic dielectric layer

[0018] 32: Metal interconnects

[0019] 34: Barrier layer

[0020] 36:Metal layer

[0021] 38:MTJ stacking structure

[0022] 42: Lower electrode

[0023] 44: Fixed layer

[0024] 46: Barrier layer

[0025] 48: Free layer

[0026] 50: Upper electrode

[0027] 52:MTJ

[0028] 56: Covering layer

[0029] 58: gap wall

[0030] 60: gap wall

[0031] 62: Intermetallic dielectric layer

[0032] 70:Metal interconnect

[0033] 72: Stop layer

[0034] 74: Intermetallic dielectric layer

[0035] 76:Metal interconnect

[0036] 78: Stop layer

[0037] 82: first upper electrode

[0038] 84: Second upper electrode

[0039] 86: First floor

[0040] 88: Second floor

[0041] 90: Third floor DETAILED DESCRIPTION

[0042] Please refer to Figures 1 to 6 , Figures 1 to 6 FIG. 1 is a schematic diagram of a method for manufacturing an MRAM cell according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region 16 are preferably defined on the substrate 12.

[0043] The substrate 12 may include active devices such as metal-oxide semiconductor (MOS) transistors, passive devices, conductive layers, and dielectric layers such as an interlayer dielectric (ILD) 16 covering the substrate 12. More specifically, the substrate 12 may include planar or non-planar MOS transistors (e.g., fin-structured transistors), wherein the MOS transistors may include a gate structure (e.g., a metal gate) and transistor components such as source / drain regions, spacers, epitaxial layers, and contact etch stop layers. An interlayer dielectric 18 may be disposed on the substrate 12 and cover the MOS transistors. The interlayer dielectric 18 may have a plurality of contact plugs electrically connected to the gate and / or source / drain regions of the MOS transistors. Since the manufacturing processes for planar or non-planar transistors and interlayer dielectrics are well known in the art, they are not further described here.

[0044] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 to electrically connect the aforementioned contact plugs, wherein the metal interconnect structure 20 includes an intermetallic dielectric layer 24 and a metal interconnect 26 embedded in the intermetallic dielectric layer 24, and the metal interconnect structure 22 includes a stop layer 28, an intermetallic dielectric layer 30, and a metal interconnect 32 embedded in the stop layer 28 and the intermetallic dielectric layer 30.

[0045] In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably comprises a trench conductor, while the metal interconnect 32 in the metal interconnect structure 22 disposed in the MRAM region 14 comprises a via conductor. Furthermore, each metal interconnect 26, 32 in each metal interconnect structure 20, 22 may be inlaid in the intermetal dielectric layer 24, 30 and / or the stop layer 28 using a single damascene process or a dual damascene process and electrically connected to each other. For example, each metal interconnect 26, 32 may further comprise a barrier layer 34 and a metal layer 36. The barrier layer 34 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer 36 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single damascene or dual damascene fabrication processes are well known in the art, they will not be further described here. Furthermore, in this embodiment, metal layer 36 in metal interconnect 26 preferably comprises copper, metal layer 36 in metal interconnect 32 preferably comprises tungsten, intermetallic dielectric layers 24 and 30 preferably comprise silicon oxide such as tetraethylorthosilicate (TEOS), and stop layer 28 comprises, but is not limited to, nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN).

[0046] Next, a lower electrode 42, an MTJ stack structure 38, a top electrode 50, and a patterned mask (not shown) are formed on the metal interconnect structure 22. In this embodiment, the MTJ stack structure 38 can be formed by first sequentially forming a pinned layer 44, a barrier layer 46, and a free layer 48 on the lower electrode 42. In this embodiment, the lower electrode 42 and the top electrode 50 preferably comprise a conductive material, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer 44 can comprise a ferromagnetic material, such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), cobalt (Co), etc. In addition, the pinned layer 44 may also be made of an antiferromagnetic (AFM) material, such as iron manganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), etc., to fix or limit the magnetic moment direction of the adjacent layer. The barrier layer 46 may be made of an insulating material including an oxide, such as aluminum oxide (AlO x ) or magnesium oxide (MgO), but are not limited thereto. The free layer 48 can be made of a ferromagnetic material, such as, but not limited to, iron, cobalt, nickel, or alloys thereof, such as cobalt-iron-boron (CoFeB). The magnetization direction of the free layer 48 is "free" to change in response to an external magnetic field.

[0047] It is worth noting that when forming the upper electrode 50 in this embodiment, it is preferably included first forming a first upper electrode 82 on the MTJ stack structure 38, and then forming a second upper electrode 84 on the first upper electrode 82, wherein the first upper electrode 82 includes a concentration gradient, and the second upper electrode 84 includes no concentration gradient. The first upper electrode 82 and the second upper electrode 84 preferably include titanium nitride, and the ratio of nitrogen to titanium in the first upper electrode 82 increases from the bottom surface of the first upper electrode 82 toward the top surface of the first upper electrode 82.

[0048] More specifically, the method of forming the first top electrode 82 and the second top electrode 84 in the top electrode 50 of this embodiment includes first performing a first plasma treatment process to introduce a reaction gas such as nitrogen and / or argon into a reaction chamber to provide an environment, then performing a first tuning process to adjust the ratio of nitrogen, argon, and titanium to form a first layer 86 of the first top electrode 82 on the MTJ stack structure 38. Next, a second plasma treatment process is performed to introduce nitrogen to form a second layer 88 of the first top electrode 82 on the surface of the first layer 86, then a second tuning process is performed to further adjust the ratio of nitrogen, argon, and titanium to form a third layer 90 of the first top electrode 82 on the surface of the second layer 88, and finally a third plasma treatment process is performed to introduce nitrogen to form the second top electrode 84 on the third layer 90 of the first top electrode 82.

[0049] It should be noted that, because the first top electrode 82 sequentially forms multiple material layers composed of titanium nitride with varying ratios on the MTJ stack structure 38 via the aforementioned multi-pass plasma treatment and adjustment processes, the first top electrode 82, or more specifically, from the bottom surface to the top surface of the first top electrode 82, preferably comprises a concentration gradient, wherein the nitrogen to titanium ratio preferably increases from the bottom surface to the top surface of the first top electrode 82. Furthermore, in this embodiment, the nitrogen to titanium ratio reaches a saturation value or critical value by the time it reaches the top surface of the first top electrode 82. Therefore, once the nitrogen to titanium ratio exceeds the boundary between the first top electrode 82 and the second top electrode 84, the nitrogen to titanium concentration throughout the second top electrode 84, starting from the bottom surface of the second top electrode 84, does not increase or decrease, but rather exhibits a uniform distribution. In other words, the nitrogen and titanium concentrations throughout the second top electrode 84, or more specifically, from the bottom surface to the top surface of the second top electrode 84, are uniform or have no concentration gradient.

[0050] In this embodiment, the nitrogen-to-titanium ratio of the second layer 88 of the first top electrode 82 is preferably greater than that of the first layer 86, the nitrogen-to-titanium ratio of the third layer 90 is greater than that of the second layer 88, and the nitrogen-to-titanium ratio of the second top electrode 84 is greater than that of any other layer of the first top electrode 82, including the nitrogen-to-titanium ratio of the second top electrode 84 being greater than that of the third layer 90, the nitrogen-to-titanium ratio of the second top electrode 84 being greater than that of the second layer 88, and the nitrogen-to-titanium ratio of the second top electrode 84 being greater than that of the first layer 86. In terms of thickness, the first layer 86 is preferably thinner than the second layer 88, and the second layer 88 is thinner than the third layer 90. The first layer 86 is preferably about 45-55 angstroms thick, or preferably about 50 angstroms thick, the second layer 88 is preferably about 110-130 angstroms thick, or preferably about 120 angstroms thick, and the third layer 90 is about 520-630 angstroms thick, or preferably about 570 angstroms thick. In addition, although the thickness of the second upper electrode 84 in this embodiment is slightly smaller than the overall thickness of the first upper electrode 82, it is not limited to this. According to other embodiments of the present invention, the thickness of the second upper electrode 84 can be selected to be less than, equal to, or greater than the overall thickness of the first upper electrode 82. These variations are all within the scope of the present invention.

[0051] Overall, although the first upper electrode 82 in this embodiment is an example of three layers of material composed of titanium nitride, it is not limited to this. According to other embodiments of the present invention, the method of forming three layers of titanium nitride can be used to form a first upper electrode 82 with a concentration gradient greater than or less than three layers, such as four layers, five layers or even six layers, on the MTJ stack structure 38 according to the aforementioned method of forming three layers of titanium nitride, and then a second upper electrode 84 without a concentration gradient is formed on the surface of the first upper electrode 82. This variation also falls within the scope of the present invention.

[0052] Then as Figure 2As shown, one or more etching processes are performed using a patterned mask as a mask to remove a portion of the top electrode 50, a portion of the MTJ stack structure 38, a portion of the bottom electrode 42, and a portion of the intermetallic dielectric layer 30 to form a plurality of MTJs 52 in the MRAM region 14. It is worth noting that the etching process performed in patterning the top electrode 50, the MTJ stack structure 38, the bottom electrode 42, and the intermetallic dielectric layer 30 in this embodiment may include a reactive ion etching process (RIE) and / or an ion beam etching process (IBE). Due to the characteristics of the ion beam etching process, the top surface of the remaining intermetallic dielectric layer 30 is preferably slightly lower than the top surface of the metal interconnect 32, and the top surface of the intermetallic dielectric layer 30 preferably presents a curved or arc-shaped surface. It should also be noted that in this embodiment, when the ion beam etching process is used to remove a portion of the IMD layer 30 , it is preferred to also remove a portion of the metal interconnect 32 so that the metal interconnect 32 forms an inclined sidewall near the junction of the MTJ 52 .

[0053] A capping layer 56 is then formed on the MTJ 52 and covers the surface of the intermetallic dielectric layer 30 in the MRAM region 14 and the logic region 16. In this embodiment, the capping layer 56 preferably comprises silicon nitride, but other dielectric materials such as but not limited to silicon oxide, silicon oxynitride, or silicon carbide nitride may be selected based on manufacturing process requirements.

[0054] Then as Figure 3 As shown, a portion of the capping layer 56 is first removed by etching back to form spacers 58 and 60 on the sidewalls of each MTJ 52. Then, a flowable chemical vapor deposition (FCVD) process or an atomic layer deposition (ALD) process is performed to form an intermetallic dielectric layer 62 covering each MTJ 52 and the intermetallic dielectric layer 30 of the logic region 16. In this embodiment, the intermetallic dielectric layer 62 preferably includes an ultra-low-k dielectric layer, for example, a porous dielectric material such as, but not limited to, silicon oxycarbide (SiOC) or silicon oxycarbide hydrogen (SiOCH). It should be noted that after the IMD layer is formed using the aforementioned FCVD process or ALD process, the top surface of the IMD layer 62 in the logic region 16 may be slightly lower than the top surface of the IMD layer 62 in the MRAM region 14. The height difference between the IMD layers 62 in the MRAM region 14 and the logic region 16 is preferably approximately 400 angstroms.

[0055] like Figure 4As shown, a planarization process is then performed, such as using a chemical mechanical polishing (CMP) process to remove a portion of the intermetallic dielectric layer 62 of the MRAM region 14 and the logic region 16 so that the top of the intermetallic dielectric layer 62 of the MRAM region 14 and the logic region 16 is approximately flush.

[0056] Then as Figure 5 As shown, a pattern transfer process is performed, for example, using a patterned mask (not shown) to remove portions of the IMD layer 62, IMD layer 30, and stop layer 28 in the logic region 16 to form contact holes (not shown) and expose the underlying metal interconnects 26. The contact holes are then filled with a desired metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and a low-resistance metal layer selected from a low-resistance material such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof. A planarization process is then performed, such as chemical mechanical polishing (CMP) to remove portions of the metal material to form contact plugs or metal interconnects 70 within the contact holes to electrically connect to the metal interconnects 26.

[0057] Then as Figure 6 As shown, a stop layer 72 is first formed in the MRAM region 14 and the logic region 16, covering the IMD layer 62 and the metal interconnect 70. An IMD layer 74 is then formed on the stop layer 72. One or more photolithography and etching processes are then performed to remove portions of the IMD layer 74, the stop layer 72, and the IMD layer 62 in the MRAM region 14 and the logic region to form contact holes (not shown). A conductive material is then filled into each contact hole, and a planarization process, such as CMP, is then performed to form metal interconnects 76 in the MRAM region 14 and the logic region 16, connecting the underlying MTJ 52 and metal interconnect 70. The metal interconnect 76 in the MRAM region 14 preferably directly contacts the underlying top electrode 50, while the metal interconnect 76 in the logic region 16 contacts the underlying metal interconnect 70. Another stop layer 78 is then formed on the IMD layer 70, covering the metal interconnect 76.

[0058] In this embodiment, stop layer 72 and stop layer 78 may comprise the same or different materials, and both may be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). Like the metal interconnects formed above, metal interconnect 76 disposed within IMD layer 74 may be inlaid within IMD layer 74 using a single damascene process or a dual damascene process. For example, metal interconnect 76 may further comprise a barrier layer and a metal layer, wherein the barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer may be selected from the group consisting of, but not limited to, tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), and cobalt tungsten phosphide (CoWP). Since the single damascene or dual damascene manufacturing process is well known in the art, it will not be further described here. Thus, the manufacturing of the semiconductor device according to one embodiment of the present invention is completed.

[0059] In summary, the present invention primarily forms a top electrode consisting of a first top electrode and a second top electrode on an MTJ, wherein the first top electrode includes a concentration gradient and the second top electrode does not include a concentration gradient. More specifically, both the first top electrode and the second top electrode preferably include titanium nitride, and the ratio of nitrogen to titanium in the first top electrode preferably increases from the bottom surface of the first top electrode toward the top surface of the first top electrode, while the concentration ratio between nitrogen and titanium in the second top electrode exhibits a uniform distribution without any increase or decrease. According to a preferred embodiment of the present invention, the combination of a top electrode having a concentration gradient in the lower layer and a uniform concentration in the upper layer can be used to improve the tunnel magnetoresistance (TMR) performance of a magnetoresistive random access memory device and enhance device performance.

[0060] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a magnetoresistive random access memory element, characterized in that: Include: forming a magnetic tunneling junction (MTJ) stack structure on a substrate; forming a first top electrode on the magnetic tunneling junction stack structure, wherein the first top electrode comprises a concentration gradient; as well as A second upper electrode is formed on the first upper electrode, wherein the second upper electrode directly contacts the first upper electrode and has no concentration gradient. 2 . The method of claim 1 , wherein a ratio of nitrogen to titanium increases from a bottom surface of the first upper electrode toward a top surface of the first upper electrode.

3. The method of claim 1, further comprising: Performing a first plasma treatment process to introduce nitrogen gas into the reaction chamber; Performing a first adjustment process to form a first layer of the first top electrode; Performing a second plasma treatment process to form a second layer of the first upper electrode; as well as A second adjustment process is performed to form a third layer of the first top electrode.

4. The method of claim 3, wherein the ratio of nitrogen to titanium of the second layer is greater than the ratio of nitrogen to titanium of the first layer.

5. The method of claim 3, wherein a ratio of nitrogen to titanium of the third layer is greater than a ratio of nitrogen to titanium of the second layer.

6. The method of claim 3, wherein a ratio of nitrogen to titanium of the second top electrode is greater than a ratio of nitrogen to titanium of the third layer.

7. The method of claim 3, wherein the ratio of nitrogen to titanium of the second top electrode is greater than the ratio of nitrogen to titanium of the second layer.

8. The method of claim 3, wherein the ratio of nitrogen to titanium of the second top electrode is greater than the ratio of nitrogen to titanium of the first layer. The method of claim 3 , wherein the thickness of the first layer is less than the thickness of the second layer.

10. The method of claim 3, wherein the second layer thickness is less than the third layer thickness.

11. A magnetoresistive random access memory element, characterized in that: Include: A magnetic tunneling junction (MTJ) is provided on the substrate; A first top electrode is disposed on the magnetic tunneling junction, wherein the first top electrode comprises a concentration gradient; as well as The second upper electrode is disposed on the first upper electrode, wherein the second upper electrode directly contacts the first upper electrode and has no concentration gradient. 12 . The magnetoresistive random access memory device as claimed in claim 11 , wherein a ratio of nitrogen to titanium increases from a bottom surface of the first upper electrode toward a top surface of the first upper electrode.

13. The magnetoresistive random access memory device according to claim 11 , wherein the first upper electrode comprises: A first layer is provided on the magnetic tunnel junction; a second layer disposed on the first layer; and The third layer is arranged on the second layer. 14 . The magnetoresistive random access memory device of claim 13 , wherein a ratio of nitrogen to titanium in the second layer is greater than a ratio of nitrogen to titanium in the first layer. 15 . The magnetoresistive random access memory device of claim 13 , wherein a ratio of nitrogen to titanium in the third layer is greater than a ratio of nitrogen to titanium in the second layer. 16 . The magnetoresistive random access memory device of claim 13 , wherein a ratio of nitrogen to titanium in the second top electrode is greater than a ratio of nitrogen to titanium in the third layer. 17 . The magnetoresistive random access memory device of claim 13 , wherein a ratio of nitrogen to titanium in the second top electrode is greater than a ratio of nitrogen to titanium in the second layer. 18 . The magnetoresistive random access memory device of claim 13 , wherein a ratio of nitrogen to titanium in the second top electrode is greater than a ratio of nitrogen to titanium in the first layer.

19. The magnetoresistive random access memory device as claimed in claim 13, wherein the thickness of the first layer is smaller than the thickness of the second layer. 20 . The magnetoresistive random access memory device as claimed in claim 13 , wherein a thickness of the second layer is smaller than a thickness of the third layer.

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