A dynamic amplifier calibration circuit

Abstract

The present invention discloses a dynamic amplifier calibration circuit, comprising three parts: a matching voltage generation circuit, a voltage-time conversion circuit, and a dynamic amplifier circuit. The circuit involves conversion from the voltage domain to the time domain and back to the voltage domain. In the overall structure, the matching voltage generation circuit is connected to a fixed differential input and transmits the amplified voltage to the input of the voltage-time conversion circuit, converting the voltage quantity into a time quantity to control the dynamic amplifier to complete gain calibration. The present invention combines a replica circuit of the dynamic amplifier with a current mirror to generate a voltage ramp curve whose slew rate changes with PVT changes. This voltage signal is converted into a corresponding time signal by a voltage-time converter. This calibration method reduces the gain deviation of the dynamic amplifier caused by PVT changes.

Description

Technical Field

[0001] The invention relates to a novel dynamic amplifier calibration technology circuit, belonging to the field of analog-to-digital converters. Background Art

[0002] The advancement of technologies such as the Internet of Things (IoT) and next-generation wireless communications has led to a significant increase in demand for high-precision, low-power analog-to-digital converters (ADCs), driving the rapid development of successive approximation register analog-to-digital converters (SARADCs) and ∑Δ analog-to-digital converters (ADCs). Leveraging the noise-shaping properties of the ∑Δ modulator, noise-shaping SARADCs overcome the accuracy limitations of traditional SARADC architectures while largely maintaining their original simplicity. However, to achieve robust noise-shaping capabilities and higher accuracy, noise-shaping SARADCs require amplification of the residual voltage to achieve a perfect noise transfer function. This makes the amplifier a critical building block in the ADC, severely limiting the converter's overall performance.

[0003] As integrated circuit processes become increasingly demanding under the continuous push of Moore's Law, shrinking process geometries and lowering power supply voltages have made the design of high-performance operational amplifiers increasingly difficult. While techniques such as gain boosting and multi-stage amplification can be used to alleviate this problem, these often result in reduced signal swing or increased power consumption, making them unsuitable for low-power, high-precision applications. Therefore, to avoid unnecessary power consumption, a differential flip-flop voltage follower (DFVF) dynamic amplifier (DA) with a CMOS input pair has emerged as a solution to overcome these issues. Thanks to the amplifier's dynamic structure and partially settling operation, it consumes no quiescent current while reducing dynamic current, achieving excellent power efficiency. Furthermore, the differential flip-flop voltage follower within this dynamic amplifier improves gain linearity through negative feedback, enabling the amplifier to meet the low-power and high-precision requirements of noise shaping (SAR ADC).

[0004] Unfortunately, the advantages of these dynamic amplifiers come with some undesirable characteristics, such as sensitivity to process, voltage, and temperature (PVT) and clock jitter. In particular, the amplifier's voltage gain can vary significantly with PVT, resulting in a loss in the ADC's signal-to-noise ratio (SNR), a key issue hindering the performance improvement of dynamic amplifiers. Traditionally, compensating for gain instability involves continuous background calibration. However, these calibrations often require input signal constraints or long convergence times, resulting in complex circuitry. This article proposes a simple analog method for this type of dynamic amplifier that effectively stabilizes the voltage gain over PVT variations. This stability also responds to environmental changes within a single conversion cycle. Consequently, stable operation is achieved almost immediately after power-up, enabling its application in high-precision applications with short ADC startup times. Summary of the Invention

[0005] The present invention utilizes a matching voltage generation circuit and a voltage-to-time converter (VTC) to implement dynamic amplifier gain calibration, offering advantages such as low static power consumption, a simple structure, and strong calibration capabilities. The present invention divides the overall circuit into three parts. The first part provides a fixed voltage input to the amplifier's replica circuit via a switched capacitor. The dynamic amplifier's replica circuit amplifies this fixed input voltage, generating a differential-mode output that varies with the PVT after amplification. This differential-mode output voltage is then converted to a single-ended output via a current mirror structure to match the VTC structure. The single-ended output of the current mirror in the second part is generated by the VTC to generate an operating clock that matches the current PVT, thereby controlling the on and off of the dynamic amplifier. The third dynamic amplifier is controlled by a timing signal generated by the VTC, resulting in a stable voltage gain that does not vary with PVT.

[0006] The above objectives are achieved through the following technical solutions:

[0007] A novel dynamic amplifier calibration circuit consists of three parts: a matching voltage generation circuit, a voltage-to-time conversion circuit, and a dynamic amplifier circuit. This circuit involves conversion from the voltage domain to the time domain and back to the voltage domain. In the overall structure, the matching voltage generation circuit connects to a fixed differential input and transmits the amplified voltage to the input of the voltage-to-time conversion circuit, converting the voltage into a time quantity to control the dynamic amplifier and complete gain calibration.

[0008] The dynamic amplifier circuit includes transistors M1-M13, of which M1-M8 are dynamic amplifier input transistors, with their gates connected to differential-mode input signals Vip and Vin. The drains of M1-M4 serve as the amplifier's output terminals Vop and Von. The gates of M9 and M11 are connected to the drains of M5 and M7, the gates of M10 and M12 are connected to the drains of M6 and M8, the sources of M1 and M5 are connected to the drain of M9, the sources of M2 and M6 are connected to the drain of M10, the sources of M3 and M7 are connected to the drain of M11, the sources of M4 and M8 are connected to the drain of M12, the sources of M11 and M12 are connected to the drain of M13, and the gate of M13 is connected to the amplifier control signal CLK.

[0009] The matching voltage generation circuit includes a replica circuit of a dynamic amplifier, a current mirror circuit, and a fixed voltage generation circuit. The gate of transistor M13 in the replica circuit of the dynamic amplifier is connected to Vdd. The current mirror structure consists of transistors M14, M15, M16, and M17, and a pair of S1 switches. The sources of M14 and M15 are connected to Vdd, and their gates are connected to the drains of M14 and M16. The drains of M14 and M15 are connected to the drains of M16 and M17. The gates of M16 and M17 are connected to Vdd, and their sources are connected to S1. The fixed voltage generation circuit consists of two pairs of C1 capacitors, two pairs of C2 capacitors, two pairs of S2 switches, two pairs of S3 switches, and two pairs of S3B switches. S2 connects Vcm to C1, C2, and the input of the replica circuit, while S3 and S3B are connected to the other end of C2, Vref, and ground. The output end of the replica circuit is connected to the source ends of M16 and M17 and S1. The other end of S1 is connected to Vbias. The source end of M17 is connected to S1 and the output end of the replica circuit as the output of the matching voltage generating circuit.

[0010] The voltage-to-time conversion circuit includes seven inverters, a pair of S4 switches, a pair of S5 switches, a pair of S6B switches, a pair of S6 switches, a pair of S7 switches, a pair of S8 switches, capacitors C3-C6, a pair of C7 capacitors, and a NOR gate. S4 is connected to the output of the matching voltage generation circuit, S7, and C7; the upper end S5 is connected to the bias voltage Vbias, C4, C6, and S7; the lower end S5 is connected to the bias voltage Vbias, C3, C5, and S7; C3 and C4 are connected to S6 and S6B; S8 is connected to C7 and the input and output of the I1 inverter; I1, I2, I3, and I4 are connected end to end; the outputs of I3 and I4 are connected to the two inputs of the NOR gate; and the output of the NOR gate is the control clock CLK of the dynamic amplifier.

[0011] The present invention combines a replica circuit of a dynamic amplifier with a current mirror to generate a voltage ramp curve whose slew rate changes with PVT variations. This voltage ramp curve inherently includes the error caused by PVT variations. A voltage-to-time converter converts this voltage signal into a corresponding time signal. This time signal, containing the PVT error, offsets the error of the dynamic amplifier itself due to PVT. This calibration method reduces the gain deviation of the dynamic amplifier caused by PVT variations. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a circuit structure block diagram of the present invention.

[0013] Figure 2 It is the principle diagram of the dynamic amplifier of the present invention.

[0014] Figure 3 It is a circuit principle structure diagram of the present invention. DETAILED DESCRIPTION

[0015] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0016] A novel dynamic amplifier calibration circuit structure is disclosed. The phases of switches S1, S2, S3, S3B, S4, S5, S6, S6B, S7, and S8 are correlated, with switches S3 and S3B operating in opposite phases, and switches S6 and S6B operating in opposite phases. In the first phase, switches S1, S2, S3, S5, S6, S7, and S8 are closed, and switch S4 is open. The output of the dynamic amplifier replica circuit is set to Vbias, the input of the dynamic amplifier replica circuit and the voltages on the upper plates of capacitors C1 and C2 are reset to common mode, the bottom plate voltage of capacitor C2 at the positive input is set to ground, the bottom plate voltage of capacitor C2 at the negative input is set to Vref, the upper plates of capacitors C3, C4, C5, C6, and C7 are set to Vbias, the lower plates of capacitors C3 and C4 are set to ground, the input and output of the I1 inverter are shorted, and the CLK voltage is low. In the second phase, the switches S1, S2, S3, S7, and S8 are closed, and the switches S4, S5, and S6 are opened. The lower plates of the capacitors C3 and C4 are set to Vref, the capacitors C3, C4, C5, C6, and C7 perform charge redistribution, and the CLK voltage is low. In the third phase, the switches S4, S5, and S6 are closed. The switches S1, S2, S3, S7, and S8 are opened. The bottom plate voltage of the capacitor C2 at the positive input terminal of the dynamic amplifier replica circuit is set to Vref, and the bottom plate voltage of the capacitor C2 at the reverse input terminal is set to ground. The capacitors C1 and C2 perform charge redistribution. The upper plate voltage of C7 follows the output voltage of the matching voltage generation circuit. The potential at the CLK point changes from low to high and then to low. The dynamic amplifier amplifies and obtains the corresponding output voltage.

[0017] The operating principle of the present invention is as follows: in the first phase, switches S1, S2, S3, S5, S6, S7, and S8 are closed, and switch S4 is open. The inputs of the dynamic amplifier replica circuit are reset to the common-mode voltage, and the outputs are set to the Vbias potential, so that the forward and reverse outputs have the same initial value when the dynamic amplifier replica circuit amplifies the voltage. The dynamic amplifier replica circuit and the current mirror circuit are inoperative during this phase. The I1 inverter is in auto-zero mode, causing the two inputs of the NOR gate to be in opposite phases, resulting in a low CLK voltage and the dynamic amplifier being inoperative. In the second phase, switches S1, S2, S3, S7, and S8 are closed, and switches S4, S5, and S6 are open. Due to the different values ​​of C3 and C5 and C4 and C6, the two threshold voltages of the VTC are set to Vthp and Vthn. In the third phase, switches S4, S5, and S6 are closed. Switches S1, S2, S3, S7, and S8 are open. The dynamic amplifier replica circuit generates a fixed differential input voltage at its input and begins amplification. A current mirror converts the differential output into a single-ended output to charge capacitor C7. Initially, the voltage at the I1 input does not reach the smaller of Vthp and Vthn, so neither I1 inverter flips, the CLK voltage remains low, and the dynamic amplifier does not operate. Subsequently, the I1 input voltage reaches the smaller of Vthp and Vthn, causing the smaller VTC threshold voltage of the two I1 inverters to flip, increasing the CLK voltage and enabling the dynamic amplifier to operate. Subsequently, the I1 input voltage reaches the larger of Vthp and Vthn, causing both I1 inverters to flip, decreasing the CLK voltage, and disabling the dynamic amplifier. When the circuit's PVT changes, the dynamic amplifier and the dynamic amplifier replica circuit are affected in the same way. Increasing the gain of the dynamic amplifier replica circuit increases the slew rate of the voltage charged at the I1 input, reducing the interval between the I1 inverter flips across VTC and shortening the dynamic amplifier's amplification time. In this paper, the dynamic amplifier gain is proportional to the amplification time. This ensures the stability of the voltage gain of the dynamic amplifier under different PVT conditions and achieves gain calibration.

[0018] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the scope of protection of the present invention.

Claims

1. A dynamic amplifier calibration circuit, characterized in that: include: Matching voltage generation circuit, voltage-time conversion circuit, dynamic amplifier circuit; involving the conversion from voltage domain, time domain and then to voltage domain; In the overall structure, the matching voltage generation circuit is connected to a fixed differential input and transmits the amplified voltage to the input of the voltage-to-time conversion circuit, converting the voltage quantity into a time quantity and controlling the dynamic amplifier to complete the gain calibration work; The matching voltage generating circuit includes a replica circuit of a dynamic amplifier, a current mirror circuit, and a fixed voltage generating circuit; the gate of the M13 tube in the replica circuit of the dynamic amplifier is connected to Vdd; the current mirror structure is composed of M14, M15 , M16, M17 tubes and a pair of S1 switches; the sources of M14 and M15 are connected to Vdd, and the gates are connected to the drains of M14 and M16. The drains of M14 and M15 are connected to the drains of M16 and M17. The gates of M16 and M17 are connected to Vdd, and the sources are connected to the S1 switch. The fixed voltage generating circuit is composed of two pairs of C1 capacitors, two pairs of C2 capacitors, two pairs of S2 switches, two pairs of S3 switches, and two pairs of S3B switches. The S2 switch connects Vcm to C1, C2, and the input of the replica circuit, and S3 and S3B are connected to the other end of C2, Vref, and ground. The output of the replica circuit is connected to the sources of M16 and M17 and the S1 switch. The other end of the S1 switch is connected to Vbias. The source of M17 is connected to S1 and the output of the replica circuit as the output of the matching voltage generating circuit. The voltage-to-time conversion circuit includes seven inverters, a pair of S4 switches, a pair of S5 switches, a pair of S6B switches, a pair of S6 switches, a pair of S7 switches, a pair of S8 switches, C3-C6 capacitors, a pair of C7 capacitors, and an NOR gate; wherein S4 is connected to the output of the matching voltage generation circuit, S7, and C7, the upper end S5 is connected to the bias voltage Vbias, C4, C6, and S7, and the upper ends I1, I2, and I3 are connected end to end; the lower end S5 is connected to the bias voltage Vbias, C3, C5, and S7, C3 and C4 are connected to S6, S6B, S8 is connected to C7, the input and output ends of the I1 inverter, the lower ends I1, I2, I3, and I4 are connected end to end, the output ends of I3 and I4 are connected to the two input ends of the NOR gate, and the output of the NOR gate is the control clock CLK of the dynamic amplifier.

2. A dynamic amplifier calibration circuit according to claim 1, characterized in that: The dynamic amplifier circuit includes M1-M13 transistors, wherein M1-M8 are dynamic amplifier input transistors, whose gates are connected to differential mode input signals Vip and Vin, and the drains of M1-M4 are the output terminals Vop and Von of the amplifier; the gates of M9 and M11 are connected to the drains of M5 and M7, the gates of M10 and M12 are connected to the drains of M6 and M8, the sources of M1 and M5 are connected to the drain of M9, the sources of M2 and M6 are connected to the drain of M10, the sources of M3 and M7 are connected to the drain of M11, the sources of M4 and M8 are connected to the drain of M12, the sources of M11 and M12 are connected to the drain of M13, and the gate of M13 is connected to the amplifier control signal CLK.

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