Silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) with short-circuit protection

Abstract

Fabricated from a silicon carbide (SiC) wafer, the integrated MOSFET-JFET device features an N+ source, a P-body diode, and an upper N region, forming a vertical MOSFET on the sidewalls of the polysilicon gate. The N substrate beneath the upper N region forms a drift region, which is sandwiched by the JFET to limit the saturation current. A trench is formed between the MOSFETs. The JFET is formed by doping the bottom and sidewalls of the trench to form a P+ tap on the N substrate. P islands are formed within the N substrate beneath the P+ taps. These P islands are wide near the surface but gradually narrow as the vertical spacing increases deeper into the N substrate. This tapering of the P islands creates a tapered shape for the JFET depletion region, which sandwiches the MOSFET drift region in the N substrate to limit the saturation current and reduce the on-resistance in the linear region.

Description

Technical Field

[0001] The present invention relates to a short circuit protection circuit, in particular to a protection device for a high voltage transistor. Background Art

[0002] Power electronics must deliver large currents at high voltages. Standard silicon metal oxide semiconductor (MOS) process transistors cannot handle such high voltages and currents, so silicon carbide (SiC) substrates can be used instead of silicon. Integrated circuits (ICs) are easily damaged by short circuits, where the load is suddenly reduced, causing destructive overcurrent.

[0003] Figure 1 shows the current-voltage curve of a prior art SiC MOS transistor. SiC and Si metal oxide semiconductor field effect transistors (MOSFETs) have similar IV curves, but SiC transistors can carry higher currents and operate at higher voltages. To improve efficiency and prevent overheating, the drain-source on-resistance R is increased when using high currents. DSON Needs to be a lower value. R DSON is the slope of curve 102 at lower voltages, which is in the linear region of transistor operation. At higher drain voltages, the transistor enters the saturation region, where the drain current I D Drain voltage V DS The saturation current I DSAT It cannot be too high, otherwise damage may occur when a short circuit causes saturation current to flow.

[0004] Therefore, it is desirable to have a lower on-resistance R DSON and lower saturation current I DSAT , to obtain more efficient SiC devices with good short-circuit protection.

[0005] In addition to MOSFET devices, junction field effect transistor (JFET) devices can also be formed using SiC manufacturing processes. JFET devices do not have an oxide gate, but instead have a pn junction depletion region that extends to clamp the conductive channel, thereby regulating current. Compared to MOSFET devices, JFET devices tend to have a lower on-resistance R DSON and lower saturation current I DSAT However, JFET devices are normally-on devices, while MOSFET devices are normally-off devices. Although JFET devices have good IV characteristics, this normally-on characteristic of JFET devices makes circuit design difficult.

[0006] Figure 2 shows a prior art SiC cascade JFET co-packaged device. A silicon MOSFET and a silicon carbide JFET are packaged together as a commercial product. Bonding wires connect the silicon die to the SiC die within the co-package.

[0007] The drain of Si MOSFET 304 is connected to the source of SiC JFET 306. When the gate G of Si MOSFET 304 is driven low, Si MOSFET 304 stops conducting current, thereby preventing current from flowing through the normally-on SiC JFET 306 between the package terminals D and S.

[0008] FIG3 shows the IV characteristics of the prior art SiC cascade JFET co-package device of FIG2. Curve 108 is the IV characteristic of the cascade co-package device of FIG2, while curve 104 is the IV characteristic of a standard SiC MOSFET. Curve 108 has a higher initial slope in the linear region, which means that it has a higher R than the conventional MOSFET. DSON , but with a lower saturation current I DSAT Therefore, the cascaded JFET-MOSFET device achieves better short-circuit performance than a single MOSFET while being able to be turned off with lower short-circuit energy dissipation.

[0009] While useful, co-packaged devices are bulky and expensive. It would be desirable to have an integrated device that combines both a JFET and a MOSFET. It would be desirable to have an integrated device that combines both a MOSFET and a JFET formed from SiC. It would be desirable to have a SiC MOSFET device with good short-circuit protection and low on-resistance. It would be desirable to have an integrated SiC MOSFET-JFET device that can shape its IV curve for better linear efficiency and improved short-circuit protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 shows a current-voltage curve of a conventional SiC MOS transistor.

[0011] FIG2 shows a prior art SiC cascade JFET co-package device.

[0012] FIG. 3 shows the IV characteristics of the prior art SiC cascade JFET co-package device of FIG. 2 .

[0013] Figure 4 Figure 1 is a cross-sectional view of an integrated MOSFET-JFET device with an on-resistance-tuned p-island.

[0014] Figures 5A-5B yes Figure 4Electrical diagram of an integrated MOSFET-JFET device with on-resistance trimmed p-islands.

[0015] Figure 6 Highlighting the gradation of the P-island in the integrated MOSFET-JFET device.

[0016] Figure 7 Highlighting the depletion and drift regions in saturation mode.

[0017] Figure 8 Highlighting the current flow in the drift region in saturation mode.

[0018] Figure 9 Highlighting the depletion and drift regions in linear mode.

[0019] Figure 10 Highlighting the current flow in linear mode.

[0020] Figure 11 Sure Figure 12-14 The location of the horizontal cross section.

[0021] Figure 12 is a horizontal cross-section through the source of a SiC MOSFET.

[0022] Figure 13 is a horizontal cross-section through a JFET.

[0023] Figure 14 is a horizontal cross-section through island P. DETAILED DESCRIPTION

[0024] The present invention relates to an improvement in a high-voltage device. The following description is intended to enable one skilled in the art to make and use the invention in the context of a specific application and its requirements. Various modifications to the preferred embodiment will be readily apparent to those skilled in the art, and the general principles defined herein may also be applied to other embodiments. Therefore, the present invention is not intended to be limited to the specific embodiments shown and described but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0025] Figure 4 This figure shows a cross-sectional view of an integrated MOSFET-JFET device with a P-island for on-resistance trimming. The vertical MOSFET is formed by N+ source 32, P region 30, upper N region 56, and polysilicon gate 22. The JFET is formed by P+ tap 36 and N substrate 50. P-island 44 acts as an extension of the JFET, forming the IV curve.

[0026] A highly doped N+ SiC wafer substrate forms the N+ drain 52, with drain metal 28 formed on the backside. The N+ drain 52 is very thick, for example, 150-350 μm, supporting other thin layers (less than 20 μm) as a mechanical substrate or wafer. A lightly doped N substrate 50 is grown on the N+ drain 52 along with the P island 44 as one or more epitaxial layers.

[0027] The P islands 44 are centered in the trenches 20. The P islands 44 that are deeper in the N substrate 50 have narrower widths than the wider P islands 44 that are closer to the top surface. In addition, the vertical spacing between the P islands 44 increases for the deeper P islands 44. As will be discussed later in Figure 10 As shown in FIG, this gradual change in width and spacing of the P island 44 provides a lower on-resistance R for the linear region of lower drain-source voltage. DSON , while reducing the saturation current I for the higher drain-source voltage in the saturation region DSAT Therefore, the P island 44 better shapes or modifies the IV curve.

[0028] P region 30 is connected to source metal 26 via P+ tap 36, while N+ source 32 is also in contact with source metal 26. N+ source 32, P+ tap 36, P region 30, N substrate 50, P island 44, upper N region 56, and N+ drain 52 are all silicon carbide (SiC).

[0029] The upper N region 56 is formed on the top of the N substrate 50, for example, by epitaxial growth. The upper N region 56 has a slightly higher doping level than the N substrate 50 and provides better conductivity.

[0030] Epitaxial growth or implantation may be used to form P region 30 above upper N region 56 and to form N+ source 32 above upper N region 56. A vertical NPN structure of the vertical MOSFET is created by N+ source 32, P region 30, and upper N region 56.

[0031] The P region 30 forms a MOS channel controlled by the polysilicon gate 22. The N+ source 32 is the source and is connected to the source metal 26. The upper N region 56 is the drain and is connected to the drain metal 28 through the N substrate 50 and the N+ drain 52.

[0032] Gate oxide 25 is grown on the P region 30, N+ source 32, and upper N region 56 on three sides of the polysilicon gate 22. The gate oxide 25 may be formed in trenches cut into the N+ source 32, the P region 30, and the upper N region 56. The gate oxide 25 separates the P region 30, the N+ source 32, and the upper N region 56 from the polysilicon gate 22. The insulator 24 separates the source metal 26 from the polysilicon gate 22.

[0033] Trench 20 is formed in N-substrate 50. Trench 20 is centered around P-island 44 but does not contact P-island 44. P+ tap 36 is formed on the bottom and sidewalls of trench 20, for example, by ion implantation. P+ tap 36 has a higher doping level than P-region 30 and merges with P-region 30 below N+ source 32. Source metal 26 is deposited on the walls of trench 20 and above N+ source 32. Source metal 26 forms an ohmic contact or a Schottky contact with P+ tap 36 and N+ source 32.

[0034] P+ tap 36 and N substrate 50 form a JFET device. As the drain-source voltage increases, the depletion region under P+ tap 36 increases and contacts the uppermost P island 44, expanding the depletion region in the shape of the uppermost P island 44. The uppermost P island 44 extends beyond the corner of the trench 20 to shield the JFET of P+ tap 36 in the trench 20 and prevent current crowding in the JFET channel.

[0035] The lower P islands 44 achieve a higher drain-source voltage due to the expanded depletion region. These lower P islands 44 gradually narrow, providing a gradually widening current path through the N substrate 50. This wider current path results in lower on-resistance in the linear region and lower Idsat in the saturation region.

[0036] Figures 5A-5B yes Figure 4 Electrical diagram of an integrated MOSFET-JFET device with on-resistance trimmed p-islands.

[0037] exist Figure 5A In FIG, the integrated MOSFET-JFET device 100 has a SiC MOSFET formed by an N+ source 32, a P region 30, and an upper N region 56 as a drain, with its gate terminal G controlling a polysilicon gate 22 separated by a gate oxide 25. The drain of the MOSFET, the upper N region 56, is connected to the drain terminal D through the N substrate 50 and the N+ drain 52.

[0038] The integrated MOSFET-JFET device 100 also has a SiC JFET formed by a P+ tap 36 (which is connected to the source terminal S) and an N substrate 50 (which is connected to the drain terminal D through an N+ drain 52 ).

[0039] exist Figure 5BIn FIG. 1 , the integrated MOSFET-JFET device 100 includes a SiC MOSFET 504 and a SiC JFET 506 connected in series between terminals S and D. The source terminal S is connected to the source of the SiC MOSFET 504 and the junction gate terminal of the SiC JFET 506. When the gate G of the SiC MOSFET 504 is low, current does not flow through the SiC MOSFET 504 to the SiC JFET 506, thus cutting off the current between the terminals S and D. The SiC MOSFET 504 is an n-channel transistor (NMOS device).

[0040] Figure 6 The figure highlights the gradual transition of the P islands in the integrated MOSFET-JFET device. The widths W1, W2, and W3 of each P island 44 beneath trench 20 become progressively narrower as the P island 44 penetrates deeper into N substrate 50. Furthermore, the vertical spacings G1, G2, and G3 between P islands 44 increase with depth within N substrate 50. The spacing G1 between the topmost P island 44 and P+ tap 36 is smaller than the spacings G2 and G3.

[0041] For example, widths W1, W2, and W3 may be 6 μm, 2 μm, and 1 μm, while widths G1, G2, and G3 may be 2 μm, 3 μm, and 4 μm, respectively. The depth of trench 20 may be 3 μm, and the depth of the polysilicon gate may be 1 μm, including N+ source 32 and P region 30.

[0042] Figure 7 The depletion and drift regions in saturation mode are highlighted. Saturation mode occurs at high drain-source voltages. The JFET device has a reverse-biased pn junction between P+ tap 36 and N substrate 50, forming a depletion region depleted of carriers. Electrons in depletion region 72 decrease in density as they are drawn into P+ tap 36 by the electric field. During depletion, electrons deeper in N substrate 50 can be drawn into P island 44.

[0043] The shape of depletion region 72 is controlled by the taper of the width of P island 44 and the drain-source voltage. The electric field extends a short distance laterally to the sides of P island 44, giving depletion region 72 a tapered shape. As the drain-source voltage increases further, depletion region 72 becomes deeper as it becomes further depleted, and the taper tends to a more rectangular shape.

[0044] The drift region 70 is formed between the depletion regions 72. The drift region 70 also has a tapered or conical shape, narrow at the top and wide at the bottom. The drift region 70 is not depleted of carriers, but the relatively low doping of the N substrate 50 limits the current flow.

[0045] Figure 8The current flow in the drift region during saturation mode is highlighted. Saturation mode occurs at high drain-source voltages. The JFET device has a reverse-biased pn junction between the P+ tap 36 and the N substrate 50, forming a depletion region 72. The tapered shape of the depletion region 72 is due to the tapered width of the P island 44. At higher Vds voltages, the JFET device effect is squeezed or reduced as the width of the drift region 70 between adjacent P+ taps 36 and P islands 44 increases. This squeezing of the drift region 70 reduces the current as Vds increases, producing the JFET effect.

[0046] During saturation mode, high Vds causes depletion region 72 to extend all the way down to N+ drain 52. Current flowing through the MOSFET device, originating from N+ source 32, P region 30, and N substrate 50, must flow through drift region 70 at the drain in N substrate 50 to reach N+ drain 52 and drain metal 28. Current crowding occurs near the top of drift region 70, where P island 44 is widest. Current crowding is less frequent near the bottom of drift region 70, where P island 44 is smaller. Therefore, current flows more easily and with less resistance at the bottom of drift region 70, while current is more confined and with greater resistance at the top of drift region 70, where P island 44 is wide, thus squeezing drift region 70. At higher drain-source voltages, the bottom of depletion region 72 depletes further, further increasing the resistance at the bottom of drift region 70. Consequently, the saturation current is limited by the JFET effect, which pinches off the current corridor near the top of drift region 70.

[0047] Figure 9 The depletion and drift regions in linear mode are highlighted. Linear mode occurs at a lower drain-source voltage than saturation mode. The JFET device has a reverse-biased pn junction between P+ tap 36 and N substrate 50, forming a depletion region depleted of carriers. Electrons in depletion region 72 are pulled into P+ tap 36 by the electric field, causing their density to decrease.

[0048] In contrast to saturation mode, in linear mode, the voltage is not high enough for depletion region 72 to reach all the way down to N+ drain 52. Instead, depletion region 72 terminates midway through N substrate 50. During linear mode, the depth of depletion region 72 varies with changes in drain voltage Vds. As Vds increases, depletion region 72 moves deeper into N substrate 50. However, when depletion region 72 first contacts the top of a new P island 44, the entire P island 44 becomes charged, and depletion region 72 extends around that P island 44. Therefore, P island 44 causes depletion region 72 to jump to a deeper depth as Vds increases. The shape and position of P island 44 can be used to control the shape of depletion region 72.

[0049] Figure 10The current flow in linear mode is highlighted. The width of the top depletion region 72 between the topmost P islands 44 is narrower in linear mode than in saturation mode because the depletion region 72 extends less laterally from the P islands 44 and the Vds in the linear region is lower. This allows current to flow more easily and the resistance is lower.

[0050] Furthermore, the depletion region 72 does not extend all the way down to the N+ drain 52, so in the linear mode the drift region 70 extends below the depletion region 72. Current can flow laterally through the drift region 70, around or between P islands 44 that are not part of the depletion region 72. These additional current paths reduce the on-resistance in the linear mode.

[0051] The wider spacing between the deeper P islands 44 provides a wider lateral current path than that of the upper P islands 44. This causes the Ids-Vds curve in the linear region to become steeper. This steeper IV curve means that the drain-source resistance is lower than otherwise because the deeper P islands 44 are spaced further apart. In addition, the wider spacing of the P islands 44 further reduces Idsat in saturation mode.

[0052] Thus, the integrated MOSFET-JFET device provides a lower on-resistance in the linear region, which improves device efficiency. In addition, in the saturation region, the saturation current is limited and reduced, thereby providing better short-circuit protection. The geometry of the P island 44 can be adjusted, for example by using circuit simulation, to provide an optimal trade-off. In particular, increasing the width of the drift region 70 can increase the current, while reducing the width of the depletion region 72 can increase the on-resistance Rdson. The P island 44 causes the width of the depletion region 72 to vary for different depths and Vds, thereby reducing the saturation current and reducing the Rdson in the linear region. Therefore, the tapered P island 44 allows for a better trade-off between saturation current and Rdson.

[0053] Figure 11 Determined on the vertical cross-section Figure 12-14 The position of the horizontal cross-section. Figure 11 and Figure 4 Same, but with deeper grooves 20. Section 62 is as Figure 12 As shown, the cross section 64 passes through the N+ source 32, the source metal 26 in the trench 20, the gate oxide 25 and the polysilicon gate 22. Figure 13 As shown, the cross section 66 passes through the upper N region 56, the P+ tap 36 and the source metal 26 in the trench 20. Figure 14 As shown, it passes through the N substrate 50 and the P island 44.

[0054] Figure 12 is a horizontal cross section through the source of a SiC MOSFET. Figure 12 Shows Figure 11A cross section 62 is shown, which passes through the N+ source 32 , the source metal 26 in the trench 20 , the gate oxide 25 , and the polysilicon gate 22 .

[0055] The N+ source 32 can form a ring or annulus around the trench 20, and the trench 20 is filled with source metal 26. The gate oxide 25 separates the N+ source 32 from the polysilicon gate 22. The polysilicon gates 22 are connected together to form a grid surrounding the ring-shaped N+ source 32, which in turn surrounds the trench 20.

[0056] Figure 13 is a horizontal cross section through the JFET. Figure 13 A cross section 64 is shown through the upper N region 56, the P+ taps 36, and the source metal 26 in the trench 20. The P+ taps 36 form an array of rings around the trench 20. Outside of these rings of P+ taps 36 is the upper N region 56.

[0057] The center of the groove 20 and the P+ tap 36 ring can be aligned with the center of the P island 44, which is located below the cross section 64 and is later Figure 14 This placement of P+ tap 36 helps direct the JFET and MOSFET channel current injection into upper N region 56, passing between an adjacent pair of P islands 44, rather than near P islands 44 (not shown, but below trench 20). This alignment improves current spreading and reduces on-resistance.

[0058] Figure 14 is a horizontal section through island P. Figure 14 A cross section 66 through the N substrate 50 and the P island 44 is shown.

[0059] One central P island 44 is surrounded by eight P islands 44. Current passes through the interface between the P region 30 and the gate oxide 25, flows into the upper N region 56, and then passes through the N substrate 50 between the P island 44 and the periphery (away from the central P island 44).

[0060] Alternative Embodiments

[0061] The inventors have added several other embodiments. For example, the upper N region 56 provides a dual drift region with a dual doping profile. The drift region 70 includes a higher-doped upper N region 56 with lower resistance, and a lower drift region with lower doping and higher resistance in the N substrate 50. This dual drift region using the upper N region 56 can increase forward current and reduce Rdson.

[0062] Although three P islands 44 are shown below each trench 20, there may also be four P islands 44 below each trench 20, or some other number of P islands 44. Different tapers may be used, such as a linear decrease in width, or a nonlinear decrease. The vertical spacing between the P islands 44 may increase as the depth in the substrate increases, or may be the same vertical spacing, or may decrease as the depth increases. A more complex vertical spacing distribution may be used, one that both increases and decreases with depth, such as with two or more inflection points, particularly when the number of P islands 44 is three or more. The spacing and width may be determined or adjusted based on circuit simulation results. The width and spacing may have different tapers.

[0063] Different sizes, shapes, layouts, and distributions can be used. The thickness of each layer can be adjusted depending on the specific process used. Doping levels and dopant densities can be varied. Various structural combinations can be used. Trench 20 can be partially or completely filled with source metal 26 or some other material. The thickness of source metal 26 can be thicker, filling trench 20 completely, or very thin at the walls and bottom of trench 20.

[0064] P+ tap 36 can be a buried layer that contacts source metal 26 on the sidewalls of trench 20 but not the bottom of trench 20. P+ tap 36 does not necessarily contact N+ source 32, but there can be another layer in between. P+ tap 36 can be formed by doping the bottom and sidewalls of trench 20.

[0065] The transistor threshold voltage VTH may be greater than zero for an enhancement mode device or less than zero for a depletion mode device. The doping levels of the P region 30 and the N substrate 50 or upper N region 56 may be adjusted to adjust the threshold.

[0066] As an example of doping level, the N substrate 50 may be 10 14 to 10 18 , P region 30 can be 10 14 to 10 18 , P+ island 44, P+ tap 36, N+ source 32 and N+ drain 52 can be 10 17 to 10 21 , the upper N region 56 can be 10 15 to 10 19 .

[0067] The center of the P region 30 and trench 20 can be aligned with the center of the P island 44, as shown, or other alignments are possible. The transition from the P+ tap 36 to the P region 30 can be shifted to the right or left. The P region 30 can be deeper or thicker than the P+ tap 36, or shallower than the P+ tap 36, as long as the P region 30 contacts the P+ tap 36. Other areas can have thicker field oxides below the polysilicon gate 22, and the contact to the metal layer can be made to the polysilicon gate 22 at these field oxide areas, or directly at the gate oxide 25 in some processes.

[0068] Charge balance is improved when the overall positive and negative charges are balanced, which occurs when the overall doping level of the N substrate 50 is approximately the same as the overall doping level of the P island 44, integrated over the length of the island.

[0069] The P island 44 can be arranged as follows Figure 14 (8+1) shown N Pattern, where one central P island 44 is surrounded by 8 P islands 44, or other patterns such as (3+1) N ,(4+1) N ,…(M+1) N pattern. N represents the number of unit repetitions in the device in two dimensions. For a real device, N may be large, for example, >100. P island 44 may be centered on the center of trench 20 or offset from the center and may be symmetrical or asymmetrical.

[0070] There are many possible IC semiconductor manufacturing processes. Photomasks can be made using a variety of specialized machines and processes, including direct write to burn away metallization layers instead of photoresist. Diffusion, oxide growth, etching, deposition, ion implantation, and other manufacturing steps can be combined in various ways so that the final pattern they create on the IC is controlled by the photomask. Although circuit simulation or modeling of transistors, particularly drain current, has been described, other currents (e.g., diode current, substrate leakage current, etc.) can be modeled, as can other devices (e.g., capacitors, resistors, etc.).

[0071] Some etching steps may be dry trench etching to obtain sharper edges. The order of the process steps, as well as variations in the process steps themselves, can be varied. When power transistors are integrated into larger devices, additional process steps may be added, for example, for cleaning or for additional metal layers or for other transistor types, such as standard complementary metal oxide semiconductor (CMOS) transistors.

[0072] The polysilicon gate 22 may be covered on top by a dielectric, which may be covered by a metal such as tungsten to provide better adhesion for the source metal 26 while insulating the polysilicon gate 22. Other composite layers may be used.

[0073] Although trench 20 has been shown as being deeper than a MOSFET, the trench can be shallower and upper N region 56 can be deeper. The exact location of P region 30 in the channel can be adjusted.

[0074] P+ or N+ taps can be added and can be combined into strips or even rings. The P+ taps can surround the integrated MOSFET-JFET device 100 on all four sides or just one side. These devices can be arranged or replicated, for example by repeating the MOSFET or JFET structure.

[0075] The device can be simplified by deleting the upper N region 56 and replacing it with the N substrate 50. The upper N region 56 can be considered as a more highly doped portion of the N substrate 50. The device can be further simplified by having only one polysilicon gate 22 and two trenches 20. The trenches 20 can form a ring around the polysilicon gate 22.

[0076] The spacing between regions and their thickness can vary, depending on process design rules, and can be adjusted for the desired characteristics of the integrated MOSFET-JFET device 100. Diffusion regions of varying horizontal widths, such as the N+ source 32, can be used. Different channel lengths of the gate can be used to adjust the threshold voltage and DC leakage. Various parasitic capacitances may be present. The layout and geometry of the integrated MOSFET-JFET device 100 can affect its performance.

[0077] Terms such as up, down, above, below, horizontal, vertical, inside, and outside are relative and dependent on the viewing angle and are not meant to limit the present invention to a particular viewing angle. A device can be rotated so that vertical is horizontal and horizontal is vertical, so these terms are observer-dependent. A line or direction is considered vertical and the other horizontal as long as the two directions are substantially perpendicular to each other.

[0078] The polysilicon gate 22 is shown as a small rectangle, but can have a variety of shapes and can be interconnected on the gate or polysilicon layer or through contacts with metal layers. The polysilicon gate 22 can be connected to control signals through these metal contacts, not shown in the figure. The polysilicon gate 22 can also be floating or can be capacitively coupled to a control or power node. The polysilicon gate 22 can be standard polysilicon or a variety of other gate materials. The gate oxide 25 below the polysilicon gate 22 can be a gate oxide, a thicker field or isolation oxide, or a combination of the two, such as a thick oxide below the polysilicon gate 22, but a thin gate oxide on the sidewalls near the P and N source, channel, and drain regions.

[0079] A variety of materials can be used. Although the doping concentration tends to vary within a region, it can still be considered relatively constant compared to the rapid changes in doping concentration near region boundaries.

[0080] The substrate, N-substrate 50, is substantially planar, although there may be variations in its top surface due to features being etched into the top surface. The MOSFET structure is substantially perpendicular to the planar surface of the substrate. The sidewalls of the polysilicon gate 22 may be slightly tilted, perhaps within 20 degrees of perpendicular to the generally planar surface of the substrate. The centerline between the two sidewalls of the polysilicon gate 22 may be nearly vertical, with an angle of no more than 20 degrees from perpendicular to the plane of the substrate.

[0081] There are several variations possible in the semiconductor process used to manufacture the integrated MOSFET-JFET device 100. The alternatives can be combined in various ways, or used alone or in other combinations.

[0082] Although an N substrate 50 has been described, the P substrate can be replaced with a deep N well in a p-type substrate or a dual or multi-well process. All P and N types can be swapped, using a P substrate instead of the N substrate 50. Various alternative transistor technologies can be added, such as bipolar or BiCMOS.

[0083] While descriptions of how current flows and behaves have been presented, these are theoretical, and these theories may be incomplete or even incorrect. Especially for small devices, current may flow in unusual ways and use mechanisms that have not been thoroughly studied and understood.

[0084] The current itself may spread out or gather at various locations, so the current may not flow in a straight line, or part of the current may flow in a straight line, but the edge of the current flow may bend or curve around obstacles (such as the edge of the diffusion region). Therefore, the current flow direction is simplified and averaged, and end connections, such as contacts with external metal lines, as well as edge and boundary effects can be ignored.

[0085] Cutouts in diffusion and other areas can be used. Other shapes and physical layouts can be substituted, such as mixed fingers. Areas can be merged together, such as forming a ring or donut shape when the layout is viewed from above.

[0086] The device can be implemented using n-channel, p-channel, or bipolar transistors, or junctions within these transistors. The gate length can be increased to provide better protection from damage.

[0087] Different transistor, capacitor, resistor, and other device sizes can be used, and various layout arrangements can be used, such as multi-pin, ring, donut, or irregularly shaped transistors. Additional taps, guard rings, transistors, and other components can be added.

[0088] The final profile and shape of each layer can vary depending on the process used. In particular, deeper layers may shift relative to the mask layout. Additionally, the mask edges and the final processed boundaries may vary depending on the process step.

[0089] The shape of the integrated MOSFET-JFET device 100 may be different, such as having a more rounded bottom or field oxide border.

[0090] The background section of the present invention may contain background information about the problem or environment of the present invention rather than describing the prior art of others. Therefore, the material included in the background section is not an admission by the applicant that the prior art is available.

[0091] Any method or process described herein is machine-implemented or computer-implemented, intended to be performed by a machine, computer, or other device, and is not intended to be performed solely by humans without machine assistance. Tangible results produced may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio generation devices, and related media devices, and may include hard copy printouts that are also machine-generated. Computer control of other machines is another tangible result.

[0092] Any advantages and benefits described do not necessarily apply to all embodiments of the invention. When the word "means" appears in a claim element, applicant intends that the claim element fall within 35 USC § 112(f). Typically, the word "means" is preceded by a label of one or more words. The word or words preceding the word "means" is a label for the purpose of facilitating reference to the claim element and is not intended to express a structural limitation. Such a means-plus-function claim is intended to cover not only the structure described herein for performing the function and its structural equivalents, but also equivalent structures. For example, although a nail and a screw have different constructions, they are equivalent structures because they both perform the function of fastening. Claims that do not use the word "means" do not fall within 35 USC § 112(f). Signals are typically electronic signals, but can also be optical signals, such as those that can be transmitted over fiber optic lines.

[0093] The foregoing description of the embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the present invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

1. An integrated metal oxide semiconductor field effect transistor (MOSFET)-junction field effect transistor (JFET) device comprising: a drain contact formed on a back side of a highly doped semiconductor substrate having a high concentration of a first doping type; a substrate formed on a top surface of the highly doped semiconductor substrate, the substrate having a low concentration of the first doping type; a buried island formed in the substrate and located above the highly doped semiconductor substrate, the buried island having a second doping type having a polarity opposite to the first doping type, the buried island being separated from the top surface by the substrate and from the back surface by the substrate; a trench formed from the top surface into the substrate, wherein the sidewalls and bottom of the trench are doped with the second doping type to form a JFET tap contacting the substrate; wherein the trench is formed above one of the buried islands, wherein a JFET is formed by the JFET tap and the substrate; wherein the buried island further comprises: an uppermost buried island spaced apart from the JFET tap by a first spacing and having a first width; an intermediate buried island spaced apart from the uppermost buried island by a second spacing and having a second width; and a lower buried island spaced apart from the intermediate buried island by a third spacing and having a third width; the uppermost buried island, the intermediate buried island, and the lower buried island are all centered on the trench but do not contact the trench; the first width is wider than the second width, and the second width is wider than the third width; wherein the uppermost buried island, the intermediate buried island, and the lower buried island form a tapered structure; the first spacing is smaller than the second spacing, and the second spacing is smaller than the third spacing; wherein the vertical spacing between the buried islands increases for buried islands deeper in the substrate; wherein during a linear mode, the on-resistance of the drift region in the substrate is reduced by increasing the vertical spacing between buried islands deep in the substrate; wherein the buried islands are all within a depletion region generated during a saturation mode, wherein a lower buried island among the buried islands is not within the depletion region during a linear mode; a polysilicon gate formed between the trench and another trench; a source electrode formed near a top surface of the polysilicon gate, the source electrode having a high concentration of the first doping type; a body region formed below the source near the polysilicon gate, the body region being connected to the JFET tap; wherein the body region forms a channel of a MOSFET when biased by the polysilicon gate, the channel being used to conduct current between the source and the substrate; wherein the body region has a low concentration of the second doping type, wherein the low concentration is at least one order of magnitude lower than the high concentration; and A gate oxide isolates the polysilicon gate from the source, the body region, and the substrate.

2. The integrated MOSFET-JFET device of claim 1 , further comprising: a source metal located above the top surface and connected to the first terminal; a contact from the source metal to the source; a contact from the source metal to the JFET tap; A back metal forming a back contact, wherein the back metal is used to connect to the second terminal.

3. The integrated MOSFET-JFET device according to claim 2, wherein: The MOSFET is a vertical device in which current flows through the channel formed in the body region, and the channel is substantially orthogonal to the plane of the highly doped semiconductor substrate.

4. The integrated MOSFET-JFET device according to claim 3, wherein: The JFET tap has a higher concentration of the second doping type than the body region; The substrate further includes an upper drain region formed on the top of the substrate, adjacent to the polysilicon gate, and below the body region; wherein the concentration of the first doping type in the upper drain region is higher than the low concentration of the first doping type in the substrate; The upper drain region and the substrate form a double drift region with reduced on-resistance.

5. The integrated MOSFET-JFET device of claim 1 , further comprising: a plurality of trenches, each of the plurality of trenches having a JFET, and a plurality of the buried islands below the trenches; A plurality of MOSFETs are provided, each MOSFET having a polysilicon gate separated from the source, the body region and the substrate by a gate oxide.

6. The integrated MOSFET-JFET device of claim 1 , wherein: The substrate, buried islands and highly doped semiconductor substrate are all formed of silicon carbide (SiC).

7. The integrated MOSFET-JFET device according to claim 6, wherein: The body region has a low concentration of the second doping type, and the substrate has a low concentration of the first doping type; wherein the transistor electron current through the MOSFET flows from the source metal to the source, through the channel formed in the body region, through the substrate, and between the buried islands to the highly doped semiconductor substrate, and to the drain contact; wherein the transistor electron current is modulated by a gate voltage applied to the polysilicon gate, the gate voltage being controlled independently of a drain-source voltage applied between the source metal and the drain contact; wherein the transistor electron current through the MOSFET is also modulated by the JFET, which increases the depletion region between the buried islands according to the higher drain-source voltage, wherein the increase in the depletion region reduces the drift region in the substrate, wherein the transistor electron current flowing through the MOSFET flows through the substrate.

8. The integrated MOSFET-JFET device according to claim 7, wherein: The first doping type is n-type, and the second doping type is p-type.

9. An integrated device comprising: a semiconductor substrate forming an N+ drain; a drain metal formed on the back side of the semiconductor substrate to contact the N+ drain; An N substrate formed on a surface of the semiconductor substrate opposite to the back surface; a trench formed in the N substrate, the trench being on a top surface opposite to the back surface; P+ taps formed on the sides and bottom of the trench; An N+ source formed on the top surface; A P-body diode formed between the N+ source and the N-substrate and in contact with the P+ tap; gate; a gate oxide separating the gate from the N+ source, the P body diode, and the N substrate; a channel layer formed in the P-body diode adjacent to the gate oxide in response to a bias voltage applied to the gate, the channel layer conducting between the N+ source and the N substrate; a source metal formed on the top surface, the source metal being in contact with the N+ source and the P+ tap; a first buried P island formed in and surrounded by the N substrate, the first buried P island being located below the trench and separated from the P+ tap by the N substrate by a first vertical distance, the first buried P island having a first width; a second buried P island formed in and surrounded by the N substrate, the second buried P island being located below the trench and separated from the first buried P island by the N substrate by a second vertical spacing, the second buried P island having a second width; a third buried P island formed in and surrounded by the N substrate, the third buried P island being located below the trench and separated from the second buried P island by the N substrate by a third vertical spacing, and having a third width; wherein the first buried P island, the second buried P island, and the third buried P island are all centered on the trench but do not contact the trench; wherein the third vertical spacing is greater than the second vertical spacing; wherein the second vertical spacing is greater than the first vertical spacing, wherein the vertical spacing of the buried P islands increases as the depth of the buried P islands in the N substrate increases; wherein the first width is greater than the second width; wherein the second width is greater than the third width; The width of the buried P island decreases as the depth of the buried P island in the N substrate increases.

10. The integrated device of claim 9, wherein the N substrate, the first, second, and third buried P islands, the P body diode, the P+ tap, and the N+ source are formed of a silicon carbide (SiC) layer above the semiconductor substrate, which is also silicon carbide (SiC).

11. The integrated device according to claim 10, wherein: The P-body diode has a low doping concentration, which is lower than the doping concentration of the N+ source.

12. A tapered depletion region device, comprising: a highly doped semiconductor substrate having a high concentration of a first dopant type; a drain contact formed on the back side of the highly doped semiconductor substrate; a substrate formed on a top surface of the highly doped semiconductor substrate, the substrate having a low concentration of the first doping type; a plurality of trenches, sidewalls and a bottom of each of the plurality of trenches being doped with a second dopant type to form a junction field effect transistor (JFET) tap contacting the substrate; A plurality of rows of buried islands, each row of buried islands being located below one of the plurality of trenches, each row of buried islands comprising: a first buried island formed in and surrounded by the substrate, the first buried island being located below a trench and separated from the JFET tap by the substrate by a first vertical spacing, the first buried island having a first width; a second buried island formed in and surrounded by the substrate, the second buried island being located below the trench and separated from the first buried island by the substrate by a second vertical spacing, the second buried island having a second width; a third buried island formed in and surrounded by the substrate, the third buried island being located below the trench and separated from the second buried island by the substrate by a third vertical spacing, the third buried island having a third width; wherein the first buried island, the second buried island, and the third buried island are all centered on the trench but do not contact the trench; wherein the first width is greater than the second width; wherein the second width is greater than the third width; wherein the width of the buried island decreases as the depth of the buried island in the substrate increases; wherein the third vertical spacing is greater than the second vertical spacing; wherein the second vertical spacing is greater than the first vertical spacing, wherein the vertical spacing between the buried islands increases as the depth of the buried islands in the substrate increases; a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET in the plurality of MOSFETs comprising: a polysilicon gate formed between the plurality of trenches; a source electrode formed on a top surface close to the polysilicon gate, the source electrode having a high concentration of the first doping type; a body region formed below the source near the polysilicon gate, the body region connected to the JFET tap; wherein, when biased by the polysilicon gate, the body region forms a channel of the MOSFET, the channel being used to conduct current between the source and the substrate; wherein the body region has a low concentration of the second doping type, wherein the low concentration is at least one order of magnitude lower than the high concentration; and A gate oxide separates the polysilicon gate from the source, the body region, and the substrate.

13. The tapered depletion region device according to claim 12, further comprising: a source metal located on the top surface and configured to connect to the first terminal; a contact from the source metal to the source; a contact from the source metal to the JFET tap; A back metal forming a back contact, wherein the back metal is used to connect to the second terminal.

14. The tapered depletion region device according to claim 12, wherein: The MOSFET is a vertical device, wherein current flows through a channel formed in the body region, the channel being substantially orthogonal to the plane of the highly doped semiconductor substrate; The buried islands are all within the depletion region generated by the JFET within the substrate during saturation mode, wherein the upper buried island is within the depletion region during linear mode, and the upper buried island is above the lower buried island, wherein the lower buried island is not within the depletion region during the linear mode.

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