Method for improving optical proximity effect correction processing efficiency

Abstract

The present invention provides a method for improving the efficiency of optical proximity effect correction processing. The method comprises providing an original layout, obtaining an error mark pattern in the original layout, forming a first regional pattern covering each error mark pattern, the first regional pattern being the area covering each error mark pattern, and the position difference between the first regional pattern and the error mark pattern being less than or equal to a first design value; enlarging the first regional pattern to a second design value; forming a third regional pattern covering the second regional pattern, the position difference between the third regional pattern and the second regional pattern being less than or equal to the third design value, and being a rectangular area with the smallest area that can cover the second pattern; using the third regional pattern as a calculation area, and modifying a recipe to remove the error mark patterns in the calculation area. The present invention improves the OPC operation speed and can comprehensively and accurately eliminate all layout problems indicated by the error mark patterns.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for improving optical proximity effect correction processing efficiency. Background Art

[0002] During the OPC (Optical Proximity Correction) image retouching process, it's often necessary to modify the layout highlighted by specific error markers. Typically, the number of error markers can reach hundreds or even thousands, and they may include a variety of layout types. Currently, the layout is typically extracted using a layout window or clip to identify one to three error marker areas, and then modified using a recipe. After the modifications are complete, the entire layout is calculated to determine whether the recipe changes have eliminated all the issues highlighted by the error markers.

[0003] However, if the areas highlighted by error markers have inconsistent graphical features, modifying the recipe for that specific error marker may not completely eliminate the issues highlighted by the error marker. In this case, you need to select the specific error marker again, modify the recipe accordingly, and recalculate the entire layout. This process may need to be repeated multiple times, making full layout calculation very time-consuming.

[0004] For example, Figure 1 It shows a schematic diagram of layout calculation area compression, layout graphics in the original layout 101 and error mark graphics 102; Figure 2 It shows that the calculation area 103 is selected in the original layout.

[0005] Therefore, a method is needed to quickly calculate the layout near all error markers to improve the efficiency of the OPC modification recipe. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a method for improving the efficiency of optical proximity effect correction processing, so as to address the problem in the prior art that when the graphic features of the portion highlighted by the error marker are inconsistent, the recipe modified for the specific error marker portion may not completely eliminate the problems indicated by the error marker. In this case, it is necessary to select the specific error marker again, modify the recipe accordingly, and recalculate the entire layout. The above process may be repeated multiple times, and the calculation of the entire layout will consume a lot of time.

[0007] To achieve the above and other related objectives, the present invention provides a method for improving the efficiency of optical proximity effect correction processing, comprising:

[0008] Step 1: providing an original layout and obtaining an error mark pattern in the original layout;

[0009] Step 2: forming a first area pattern covering each of the error mark patterns, wherein the first area pattern is an area covering each of the error mark patterns, and a position difference between the first area pattern and the error mark pattern is less than or equal to a first design value;

[0010] Step 3: Enlarging the first regional pattern to a second design value to form a second regional pattern consisting of one or more enlarged first regional patterns;

[0011] Step 4: forming a third area pattern covering the second area pattern, wherein the position difference between the third area pattern and the second area pattern is less than or equal to a third design value; and forming a rectangular area with the smallest area that can cover the second pattern;

[0012] Step 5: Using the third region graphic as the calculation region, modify the recipe to remove the error mark graphic in the calculation region.

[0013] Preferably, in step 1, the error mark graphic in the layout is extracted using a layout window or clip method.

[0014] Preferably, some of the error mark graphics in step 1 have inconsistent shapes.

[0015] Preferably, the third rectangle in step 4 covers at least one shape of the error mark graphic.

[0016] Preferably, in step 2, the first rectangle is a rectangular area that can cover the smallest area of ​​the error mark graphic.

[0017] Preferably, in step three, the first rectangle is enlarged to a second design value based on the center point of the first rectangle.

[0018] Preferably, in step three, the distance between each edge of the second area graphic and the first area graphic is the second design value.

[0019] Preferably, in step three, the second design value is 8 to 12 nanometers.

[0020] Preferably, the third area pattern in step 4 is a rectangular area with the smallest area that can cover the second area pattern.

[0021] Preferably, the shapes of the first to third area graphics are all rectangular.

[0022] As described above, the method of improving the efficiency of optical proximity effect correction processing of the present invention has the following beneficial effects:

[0023] The present invention generates a layout calculation area near the areas marked by all error markers. When modifying a recipe, calculations are performed only in this layout calculation area. This greatly improves the OPC calculation speed and can comprehensively and accurately eliminate all layout problems marked by error markers. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Shown is a schematic diagram of layout calculation area compression in the prior art;

[0025] Figure 2 Shown is a schematic diagram of selecting a calculation area in the original layout of the prior art;

[0026] Figure 3 Shown is a schematic diagram of the area that needs to be calculated after graphics compression according to the present invention;

[0027] Figure 4 Shown is a schematic diagram of an error mark graphic in the original layout obtained according to the present invention;

[0028] Figure 5 Shown is a schematic diagram of a compressed area obtained by generating a minimum rectangular area using the original highlight marker of the present invention;

[0029] Figure 6 The present invention will be shown Figure 5 Schematic diagram of the compressed area generated by expanding the middle rectangular area by 10 μm in all directions;

[0030] Figure 7 Shown is the minimum recipe detection rectangular area generated by the present invention;

[0031] Figure 8 Schematic diagram of the method for improving optical proximity effect correction processing efficiency according to the present invention. DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] See also Figure 8The present invention provides a method for improving the efficiency of optical proximity effect correction processing, comprising:

[0034] Step 1: Provide the original layout 101 and obtain Figure 4 The error mark pattern 102 in the original layout 101 is shown;

[0035] In an embodiment of the present invention, in step 1, the error mark graphic 102 in the layout is extracted using a layout window or clip method.

[0036] In this embodiment of the present invention, if the shapes of some error markers 102 in step 1 are inconsistent, the modified recipe for that specific portion of error marker 102 may not completely eliminate the issues indicated by that portion. In this case, it is necessary to reselect that specific error marker 102, modify the recipe accordingly, and recalculate the entire layout. This process may be repeated multiple times, and calculating the entire layout can be very time-consuming.

[0037] Step 2, please refer to Figure 5 , forming a first area pattern 105 covering each error mark pattern 102, the first area pattern 105 being an area covering each error mark pattern, and a position difference between the first area pattern 105 and the error mark pattern 102 being less than or equal to a first design value;

[0038] In the embodiment of the present invention, the first rectangle in step 2 is a rectangular area with the smallest area that can cover the error mark pattern 102 , that is, the first design value is zero.

[0039] Step 3, please refer to Figure 6 , enlarging the first region pattern 105 to a second design value to form a second region pattern 104 consisting of one or more enlarged first region patterns 105;

[0040] In an embodiment of the present invention, in step three, the first rectangle is enlarged to the second design value based on the center point of the first rectangle.

[0041] In an embodiment of the present invention, in step three, the distance between each edge of the second region pattern 104 and the first region pattern 105 is the second design value.

[0042] In an embodiment of the present invention, the second design value in step three is 8 to 12 nanometers, and the distance between each edge of the second region pattern 104 and the first region pattern 105 in step three is 8 to 12 nanometers, preferably 10 nanometers.

[0043] Step 4, please refer to Figure 7, forming a third area pattern 103 covering the second area pattern 104, wherein the position difference between the third area pattern 103 and the second area pattern 104 is less than or equal to the third design value; and being a rectangular area with the smallest area that can cover the second pattern;

[0044] In an embodiment of the present invention, the third rectangle in step 4 covers at least one shape of error mark graphic 102, and can cover multiple types of error mark graphics 102, so that the recipe modified by a specifically selected portion of the error mark graphic 102 can completely clear all problems indicated by the error mark graphic 102.

[0045] In the embodiment of the present invention, the third area pattern 103 in step 4 is a rectangular area with the smallest area that can cover the second area pattern 104 , that is, the third design value is zero.

[0046] Step 5, please refer to Figure 3 , using the third area graphic 103 as the calculation area, modify the recipe to remove the error mark graphic 102 in the calculation area.

[0047] In an embodiment of the present invention, the shapes of the first to third region graphics are all rectangular.

[0048] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0049] In summary, the present invention generates a layout calculation area near the areas marked by all error markers. When modifying a recipe, calculations are performed only within this layout calculation area. This significantly improves OPC computation speed while comprehensively and accurately eliminating all layout issues indicated by error markers. Therefore, the present invention effectively overcomes the shortcomings of the prior art and possesses high industrial value.

[0050] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for improving the efficiency of optical proximity effect correction processing, characterized in that: At least: Step 1: providing an original layout and obtaining an error mark pattern in the original layout; Step 2: forming a first area pattern covering each of the error mark patterns, wherein the first area pattern is rectangular and covers each of the error mark patterns, and a position difference between the first area pattern and the error mark pattern is less than or equal to a first design value; Step 3: Enlarging the first regional pattern to a second design value to form a second regional pattern composed of one or more enlarged first regional patterns, wherein the second regional pattern is in a rectangular shape; Step 4: forming a third area pattern covering the second area pattern, wherein the third area pattern is rectangular, and the position difference between the third area pattern and the second area pattern is less than or equal to a third design value; the third area pattern is a rectangular area with the smallest area that can cover the second area pattern; Step 5: Using the third region graphic as the calculation region, modify the recipe to remove the error mark graphic in the calculation region.

2. The method for improving optical proximity effect correction processing efficiency according to claim 1, wherein: In step 1, the error mark graphic in the layout is extracted using a layout window or clip method.

3. The method for improving optical proximity effect correction processing efficiency according to claim 1, wherein: Some of the error marker graphics in step 1 have inconsistent shapes.

4. The method for improving optical proximity effect correction processing efficiency according to claim 3, wherein: The third rectangle in step 4 covers at least one shape of the error mark graphic.

5. The method for improving optical proximity effect correction processing efficiency according to claim 1, wherein: In step 2, the first rectangle is a rectangular area that can cover the smallest area of ​​the error mark graphic.

6. The method for improving optical proximity effect correction processing efficiency according to claim 1, wherein: In step three, the first rectangle is enlarged to a second design value based on the center point of the first rectangle.

7. The method for improving optical proximity effect correction processing efficiency according to claim 1, wherein: In step three, the distance between each edge of the second area pattern and the first area pattern is the second design value.

8. The method for improving optical proximity effect correction processing efficiency according to claim 7, wherein: In step three, the second design value is 8 to 12 nanometers.

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