Method, system, device and medium for reducing load rate of vehicle controller main chip

Abstract

The present application provides a method, system, device, and medium for reducing the load rate of a vehicle controller main chip, including: configuring a storage unit for each controller local area network signal, the storage unit including a first storage block for storing received signals, a second storage block for storing transmitted signals, and a third storage block for storing signals other than received and transmitted signals, the first storage block, the second storage block, and the third storage block each containing multiple caches; and multiplexing the caches in the first storage block, the second storage block, and the third storage block for signal processing based on the signal period, signal identification code, or signal source in each controller local area network signal. The present application can effectively improve processing resource utilization through cache multiplexing.

Description

Technical Field

[0001] The present application relates to the field of smart cars, and in particular to a method, system, device and medium for reducing the load rate of a main chip of a vehicle controller. Background Art

[0002] With the rapid development of the new energy industry, the market share of new energy vehicles continues to expand. Vehicle controllers, as the "brains" of new energy vehicles, play a crucial role. As new energy vehicles become increasingly information-based and intelligent, the requirements for vehicle controllers are also increasing. Given the long vehicle development cycle and the fixed core processor model, effectively improving the utilization of limited processor resources has become a major challenge. Summary of the Invention

[0003] In view of the above problems existing in the prior art, the present application proposes a method, system, device and medium for reducing the load rate of the main chip of the vehicle controller, which mainly solves the problem of low processor resource utilization in the existing method.

[0004] In order to achieve the above-mentioned objectives and other objectives, the technical solutions adopted in this application are as follows.

[0005] The present application provides a method for reducing the load rate of a vehicle controller main chip, comprising:

[0006] A storage unit is configured for each controller area network signal, the storage unit including a first storage block for storing received signals, a second storage block for storing transmitted signals, and a third storage block for storing signals other than received and transmitted signals, wherein the first storage block, the second storage block, and the third storage block each include a plurality of caches;

[0007] The buffers in the first storage block, the second storage block and the third storage block are multiplexed according to the signal period, the signal identification code or the signal source in each channel of the CAN signal to perform signal processing.

[0008] In one embodiment of the present application, after configuring a storage unit for each CAN signal, the method includes:

[0009] Get the byte length of each signal in each controller area network signal;

[0010] determining the amount of cache in the first storage block according to the byte length of the received signal in each controller area network signal;

[0011] determining the amount of cache in the second storage block according to the byte length of the sending signal in each controller area network signal; and

[0012] The amount of the buffer in the third storage block is determined according to the byte length of the signals other than the received signal and the sent signal in each controller area network signal.

[0013] In one embodiment of the present application, determining the amount of cache in the first storage block according to the byte length of the received signal in each controller area network signal includes:

[0014] comparing the byte length of each received signal with a preset first target byte length; if each received signal includes a signal of the preset first target byte length, using the cache quantity corresponding to the first target byte length as the cache quantity in the first storage block according to a preset mapping relationship between signal byte length and cache quantity;

[0015] If the received signals do not include a signal of the preset first target byte length, the amount of cache in the first storage block is determined according to the longest byte length in the received signals and the mapping relationship between the signal byte length and the amount of cache.

[0016] In one embodiment of the present application, determining the amount of cache in the second storage block according to the byte length of the transmitted signal in each controller area network signal includes:

[0017] comparing the byte length of each of the transmitted signals with a preset second target byte length; if each of the transmitted signals includes a signal of the preset second target byte length, using the cache quantity corresponding to the second target byte length as the cache quantity in the first storage block according to a preset mapping relationship between signal byte length and cache quantity;

[0018] If each of the transmitted signals does not include a signal of the preset second target byte length, the amount of cache in the second storage block is determined according to the longest byte length in each of the transmitted signals and the mapping relationship between the signal byte length and the amount of cache.

[0019] In one embodiment of the present application, multiplexing the caches in the first storage block, the second storage block, and the third storage block according to a signal period in each controller area network signal includes:

[0020] Acquire a signal in the controller area network signal whose signal period is less than a preset period threshold as a small period signal;

[0021] Allocating the short-cycle signal to different caches in the corresponding storage blocks according to the signal types stored in the first storage block, the second storage block, and the third storage block;

[0022] A signal whose signal period is greater than the preset period threshold is used as a large-period signal, and a small-period signal and a large-period signal are used to send the multiplexed sending signal in the second storage block. When the two signal periods used in the second storage block are the same, a sending offset is configured for the corresponding signal to complete the corresponding signal sending according to the sending offset.

[0023] In one embodiment of the present application, multiplexing the cache in the first storage block according to the signal identification code in each of the controller area network signals includes:

[0024] Obtaining received signals whose signal identification code deviation values ​​are within a preset range and recording them as adjacent signals;

[0025] The adjacent signals are multiplexed in a same buffer of the first storage block.

[0026] In one embodiment of the present application, multiplexing the caches in the first storage block, the second storage block, and the third storage block according to the signal source in each of the controller area network signals includes:

[0027] Obtaining a signal source of each signal in the controller area network signal;

[0028] The signals whose sources belong to the same controller or the same network segment are multiplexed in the same cache of the first storage block, the second storage block or the third storage block.

[0029] The present application also provides a system for reducing the load rate of a vehicle controller main chip, comprising:

[0030] a storage configuration module, configured to configure a storage unit for each controller area network signal, the storage unit comprising a first storage block for storing received signals, a second storage block for storing transmitted signals, and a third storage block for storing signals other than received and transmitted signals, the first storage block, the second storage block, and the third storage block each comprising a plurality of caches;

[0031] A signal multiplexing module is used to multiplex the caches in the first storage block, the second storage block and the third storage block according to the signal period, signal identification code or signal source in each CAN signal to perform signal processing.

[0032] The present application also provides a computer device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the method for reducing the load rate of the main chip of the vehicle controller are implemented.

[0033] The present application also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the method for reducing the load rate of the main chip of the vehicle controller are implemented.

[0034] As described above, the present application provides a method, system, device and medium for reducing the load rate of a vehicle controller main chip, which has the following beneficial effects.

[0035] This application increases the number of controller local area network signals that can be accommodated through caching, predefines storage blocks based on signal types, and multiplexes based on cycles, identification codes, and signal sources to effectively reduce signal cycle instability and frame loss caused by data conflicts. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a flow chart of a method for reducing the load rate of the main chip of the vehicle controller in one embodiment of the present application.

[0037] Figure 2 This is a module diagram of a system for reducing the load rate of a vehicle controller main chip in one embodiment of the present application.

[0038] Figure 3 This is a schematic structural diagram of a device in one embodiment of the present application. DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0040] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. Therefore, the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0041] See also Figure 1 The present application provides a method for reducing the load rate of a vehicle controller main chip, which includes the following steps.

[0042] Step S100: configuring a storage unit for each controller area network signal, wherein the storage unit includes a first storage block for storing received signals, a second storage block for storing transmitted signals, and a third storage block for storing signals other than received and transmitted signals, wherein the first storage block, the second storage block, and the third storage block each include a plurality of caches.

[0043] In one embodiment, taking the 32-bit processor MPC5748G (hereinafter referred to as this chip) as an example, this chip has three RAM blocks (hereinafter referred to as blocks) for each controller area network (hereinafter referred to as CAN) signal channel. Each block can process the following CAN signals: if the CAN signal is 8 bytes, it can accommodate 32 such buffers; if the CAN signal is 16 bytes, it can accommodate 21 such buffers; if the CAN signal is 32 bytes, it can accommodate 12 such buffers; if the CAN signal is 64 bytes, it can accommodate 7 such buffers. Therefore, each CAN channel can normally process a maximum of 21 64-byte CAN signals. And when this block is used to store high-byte CAN signals, its capacity will be fixed to the corresponding number of BUFFERs. For example, if this block stores 64-byte CAN signals, it can only store 6 more CAN signals (with a length less than or equal to 64 bytes); if it stores 32-byte CAN signals, it can only store 12 more CAN signals (with a length less than or equal to 32 bytes).

[0044] In actual engineering applications, the length of each CAN signal is often not uniform. There are some 8-byte signals and many 64-byte signals. If each block is selected to store 64 bytes, there will be a situation where the corresponding BUFFER number is insufficient. The embodiment of the present application proposes to increase the number of CAN signals that can be accommodated by reasonably selecting the storage type of each block and adopting BUFFER multiplexing. However, there is a problem with BUFFER multiplexing. This is equivalent to multiple signals occupying a hardware BUFFER for data transmission, which will cause data conflicts and lead to unstable signal cycle or frame loss. The embodiment of the present application proposes the following method to reduce cycle instability and avoid frame loss.

[0045] In one embodiment, three blocks are defined as BLOCK_0 (i.e., the first storage block), BLOCK_1 (i.e., the third storage block), and BLOCK_2 (i.e., the second storage block). First, the received and transmitted signals are separated, the received signal is placed in BLOCK_0, the transmitted signal is placed in BLOCK_2, and the remaining received and transmitted signals are placed in BLOCK_1.

[0046] In one embodiment, after configuring a storage unit for each CAN signal, the method includes:

[0047] Get the byte length of each signal in each controller area network signal;

[0048] determining the amount of cache in the first storage block according to the byte length of the received signal in each controller area network signal;

[0049] determining the amount of cache in the second storage block according to the byte length of the sending signal in each controller area network signal; and

[0050] The amount of the buffer in the third storage block is determined according to the byte length of the signals other than the received signal and the sent signal in each controller area network signal.

[0051] In one embodiment, determining the amount of cache in the first storage block according to the byte length of the received signal in each controller area network signal includes:

[0052] comparing the byte length of each received signal with a preset first target byte length; if each received signal includes a signal of the preset first target byte length, using the cache quantity corresponding to the first target byte length as the cache quantity in the first storage block according to a preset mapping relationship between signal byte length and cache quantity;

[0053] If the received signals do not include a signal of the preset first target byte length, the amount of cache in the first storage block is determined according to the longest byte length in the received signals and the mapping relationship between the signal byte length and the amount of cache.

[0054] Specifically, the first target byte length can be configured as 64 bytes. If the received signal has 64 bytes, the corresponding BLOCK is defined as a 64-byte BUFFER. If the first target byte length is not included, the type of the first storage block is determined by the longest byte.

[0055] In one embodiment, determining the amount of cache in the second storage block according to the byte length of the transmitted signal in each controller area network signal includes:

[0056] comparing the byte length of each of the transmitted signals with a preset second target byte length; if each of the transmitted signals includes a signal of the preset second target byte length, using the cache quantity corresponding to the second target byte length as the cache quantity in the first storage block according to a preset mapping relationship between signal byte length and cache quantity;

[0057] If each of the transmitted signals does not include a signal of the preset second target byte length, the amount of cache in the second storage block is determined according to the longest byte length in each of the transmitted signals and the mapping relationship between the signal byte length and the amount of cache.

[0058] Specifically, the second target byte length can be configured as 64 bytes. If the transmitted signal has 64 bytes, the corresponding BLOCK is defined as a 64-byte BUFFER. If the second target byte length is not included, the type of the first storage block is determined by the longest byte.

[0059] In one embodiment, the remaining signal BLOCK_1 may also be defined according to the above method.

[0060] Step S110 : multiplexing the buffers in the first storage block, the second storage block, and the third storage block according to the signal period, signal identification code, or signal source in each CAN signal to perform signal processing.

[0061] In one embodiment, multiplexing the caches in the first storage block, the second storage block, and the third storage block according to a signal period in each of the controller area network signals includes:

[0062] Acquire a signal in the controller area network signal whose signal period is less than a preset period threshold as a small period signal;

[0063] Allocating the short-cycle signal to different caches in the corresponding storage blocks according to the signal types stored in the first storage block, the second storage block, and the third storage block;

[0064] A signal whose signal period is greater than the preset period threshold is used as a large-period signal, and a small-period signal and a large-period signal are used to send the multiplexed sending signal in the second storage block. When the two signal periods used in the second storage block are the same, a sending offset is configured for the corresponding signal to complete the corresponding signal sending according to the sending offset.

[0065] Specifically, because shorter-period CAN signals have a greater impact on processor load, shorter-period signals cannot be multiplexed in the same BUFFER during multiplexing. Multiplexing involves assigning each BUFFER a small-period signal so that signals with small periods are not multiplexed in the same BUFFER. For signals sent by BLOCK_2, a combination of a small period and a large period is used, leveraging the difference in their transmission intervals to reduce period instability. If two IDs multiplexed in BLOCK_2 have the same period, an offset must be configured between the two IDs to create a transmission interval between the two signals. Otherwise, frame loss may occur.

[0066] In one embodiment, multiplexing the cache in the first storage block according to the signal identification code in each of the controller area network signals includes:

[0067] Obtaining received signals whose signal identification code deviation values ​​are within a preset range and recording them as adjacent signals;

[0068] The adjacent signals are multiplexed in a same buffer of the first storage block.

[0069] Specifically, for signals received in BLOCK_0, signals with similar IDs (signal identification codes) are multiplexed into one BUFFER. Signals with similar IDs can be identified based on the code value deviation between the signal representation codes of the signals.

[0070] In one embodiment, multiplexing the caches in the first storage block, the second storage block, and the third storage block according to the signal source in each of the controller area network signals includes:

[0071] Obtaining a signal source of each signal in the controller area network signal;

[0072] The signals whose sources belong to the same controller or the same network segment are multiplexed in the same cache of the first storage block, the second storage block or the third storage block.

[0073] Specifically, signals from the same controller or the same network segment are multiplexed in one BUFFER.

[0074] See also Figure 2 This embodiment provides a system for reducing the load rate of a vehicle controller main chip, configured to implement the method for reducing the load rate of a vehicle controller main chip described in the aforementioned method embodiment. Because the technical principles of the system embodiment are similar to those of the aforementioned method embodiment, the same technical details will not be reiterated.

[0075] In one embodiment, a system for reducing the load rate of a vehicle controller main chip includes: a storage configuration module 10, which is used to configure a storage unit for each controller local area network signal, the storage unit including a first storage block for storing a received signal, a second storage block for storing a transmitted signal, and a third storage for storing signals other than the received and transmitted signals, and the first storage block, the second storage block, and the third storage block respectively contain multiple caches; a signal multiplexing module 11, which is used to multiplex the caches in the first storage block, the second storage block, and the third storage block according to the signal period, signal identification code, or signal source in each controller local area network signal to perform signal processing.

[0076] The embodiment of the present application also provides a device for reducing the load rate of a vehicle controller main chip, which may include: one or more processors; and one or more machine-readable media having instructions stored thereon, which, when executed by the one or more processors, enable the device to perform Figure 1 In practical applications, the device can be used as a terminal device or as a server. Examples of terminal devices may include: smart phones, tablet computers, e-book readers, MP3 (Moving Picture Experts Group Audio Layer III) players, MP4 (Moving Picture Experts Group Audio Layer IV) players, laptop computers, car computers, desktop computers, set-top boxes, smart TVs, wearable devices, etc. The embodiments of this application do not limit the specific devices.

[0077] The embodiment of the present application further provides a machine-readable medium in which one or more modules (programs) are stored. When the one or more modules are applied to a device, the device can execute the embodiment of the present application. Figure 1 Instructions for the steps involved in a method for reducing the load rate of a vehicle controller main chip. The machine-readable medium can be any available medium capable of computer storage, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, hard disk, or tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0078] See Figure 3 This embodiment provides a device 80, which can be a desktop computer, a portable computer, a smartphone, or other device. Specifically, device 80 includes at least a memory 82 and a processor 83 connected via a bus 81. The memory 82 is configured to store computer programs, and the processor 83 is configured to execute the computer programs stored in the memory 82 to perform all or part of the steps in the aforementioned method embodiment.

[0079] The system bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The system bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus. The communication interface is used to realize communication between the database access device and other devices (such as clients, read-write libraries, and read-only libraries). The memory may include random access memory (RAM), and may also include non-volatile memory, such as at least one disk storage.

[0080] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.

[0081] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A method for reducing the load rate of a vehicle controller main chip, characterized in that: include: A storage unit is configured for each controller area network signal, the storage unit including a first storage block for storing received signals, a second storage block for storing transmitted signals, and a third storage block for storing signals other than transmitted and received signals, wherein the first storage block, the second storage block, and the third storage block each include a plurality of caches; multiplexing the caches in the first storage block, the second storage block, and the third storage block for signal processing according to a signal period, a signal identification code, or a signal source in each channel of the CAN signal; Multiplexing the caches in the first storage block, the second storage block, and the third storage block according to the signal period in each of the controller area network signals, comprising: acquiring a signal in the controller area network signal with a signal period less than a preset period threshold as a small-period signal; The small-period signal is allocated to different caches in the corresponding storage blocks according to the signal types stored in the first storage block, the second storage block and the third storage block; the signal whose signal period is greater than the preset period threshold is used as a large-period signal, and the signal is sent by combining the small-period signal and the large-period signal interval for the multiplexed sending signal in the second storage block. When the two signal periods used in the second storage block are the same, a sending offset is configured for the corresponding signal to complete the corresponding signal sending according to the sending offset.

2. The method for reducing the load rate of the vehicle controller main chip according to claim 1, characterized in that: After configuring the storage unit for each CAN signal, including: Get the byte length of each signal in each controller area network signal; determining the amount of cache in the first storage block according to the byte length of the received signal in each controller area network signal; determining the amount of cache in the second storage block according to the byte length of the sending signal in each controller area network signal; and The amount of the buffer in the third storage block is determined according to the byte length of the signals other than the received signal and the sent signal in each controller area network signal.

3. The method for reducing the load rate of the vehicle controller main chip according to claim 2, characterized in that: Determining the amount of cache in the first storage block according to the byte length of the received signal in each controller area network signal includes: comparing the byte length of each received signal with a preset first target byte length; if each received signal includes a signal of the preset first target byte length, using the cache quantity corresponding to the first target byte length as the cache quantity in the first storage block according to a preset mapping relationship between signal byte length and cache quantity; If the received signals do not include a signal of the preset first target byte length, the amount of cache in the first storage block is determined according to the longest byte length in the received signals and the mapping relationship between the signal byte length and the amount of cache.

4. The method for reducing the load rate of the vehicle controller main chip according to claim 2, characterized in that: Determining the amount of cache in the second storage block according to the byte length of the sending signal in each controller area network signal includes: comparing the byte length of each of the transmitted signals with a preset second target byte length; if each of the transmitted signals includes a signal of the preset second target byte length, using the cache quantity corresponding to the second target byte length as the cache quantity in the first storage block according to a preset mapping relationship between signal byte length and cache quantity; If each of the transmitted signals does not include a signal of the preset second target byte length, the amount of cache in the second storage block is determined according to the longest byte length in each of the transmitted signals and the mapping relationship between the signal byte length and the amount of cache.

5. The method for reducing the load rate of the vehicle controller main chip according to claim 1, characterized in that: Multiplexing the cache in the first storage block according to the signal identification code in each of the controller area network signals includes: Obtaining received signals whose signal identification code deviation values ​​are within a preset range and recording them as adjacent signals; The adjacent signals are multiplexed in a same buffer of the first storage block.

6. The method for reducing the load rate of the vehicle controller main chip according to claim 1, characterized in that: Multiplexing the caches in the first storage block, the second storage block, and the third storage block according to the signal source in each channel of the controller area network signal, comprising: Obtaining a signal source of each signal in the controller area network signal; The signals whose sources belong to the same controller or the same network segment are multiplexed in the same cache of the first storage block, the second storage block or the third storage block.

7. A system for reducing the load rate of a vehicle controller main chip, characterized in that: include: a storage configuration module, configured to configure a storage unit for each controller area network signal, the storage unit comprising a first storage block for storing received signals, a second storage block for storing transmitted signals, and a third storage block for storing signals other than transmitted and received signals, the first storage block, the second storage block, and the third storage block each comprising a plurality of caches; a signal multiplexing module, configured to multiplex the buffers in the first storage block, the second storage block, and the third storage block for signal processing according to a signal period, a signal identification code, or a signal source in each channel of the CAN signal; Multiplexing the caches in the first storage block, the second storage block, and the third storage block according to the signal period in each of the controller area network signals, comprising: acquiring a signal in the controller area network signal with a signal period less than a preset period threshold as a small-period signal; The small-period signal is allocated to different caches in the corresponding storage blocks according to the signal types stored in the first storage block, the second storage block and the third storage block; the signal whose signal period is greater than the preset period threshold is used as a large-period signal, and the signal is sent by combining the small-period signal and the large-period signal interval for the multiplexed sending signal in the second storage block. When the two signal periods used in the second storage block are the same, a sending offset is configured for the corresponding signal to complete the corresponding signal sending according to the sending offset.

8. A computer device comprising: A memory, a processor, and a computer program stored in the memory and runnable on the processor, characterized in that when the processor executes the computer program, the steps of the method for reducing the load rate of the main chip of the vehicle controller according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for reducing the load rate of the main chip of the vehicle controller according to any one of claims 1 to 6 are implemented.

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