Semiconductor structure and method of forming the same

Abstract

A semiconductor structure includes a fin extending from a base and longitudinally oriented along a first direction, wherein the fin includes a semiconductor layer stack, an isolation feature disposed on the base and longitudinally oriented along a second direction perpendicular to the first direction, wherein the isolation feature is disposed adjacent to the fin, and a metal gate structure having a top portion disposed on the semiconductor layer stack and a bottom portion interleaved with the semiconductor layer stack. Further, sidewalls of the bottom portion of the metal gate structure are defined by first sidewalls of the isolation feature, and the top portion of the metal gate structure laterally extends to a top surface of the isolation feature.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure and a method for forming the same, and particularly to a semiconductor structure for a multi-gate field-effect transistor and a method for forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of ICs, each generation smaller and more complex than the last. In the evolution of ICs, functional density (i.e., the number of interconnects per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has shrunk. This scaling down process typically provides benefits through increased production efficiency and reduced associated costs. This scaling down also increases the complexity of processing and manufacturing ICs, and similar advancements in IC processing and manufacturing are needed to achieve these advancements.

[0003] A nanosheet field-effect transistor (NS FET, or alternatively, a fully wound gate field-effect transistor GAA FET), as a type of multi-gate transistor, typically comprises a stack of channel layers (e.g., Si layers) disposed on an active region (e.g., fins), source / drain (S / D) components formed on or in the active region, and a metal gate stack interleaved with the channel layer stack and inserted between the S / D components. While existing methods for forming NS FETs are generally sufficient, they are not entirely satisfactory in all respects. For example, unintentional overlay offsets during the patterning of the dummy gate stack can lead to structural defects, resulting in degraded device performance. Summary of the Invention

[0004] One embodiment of this disclosure is a method for forming a semiconductor structure. The method includes forming fins protruding from a semiconductor substrate, wherein the fins are longitudinally oriented along a first direction and wherein the fins comprise alternating stacks of first and second semiconductor layers; forming trenches to separate the fins, wherein the trenches are longitudinally oriented along a second direction perpendicular to the first direction; forming an isolation structure in the trenches; forming a dielectric helmet on the isolation structure; forming a dummy gate structure on the dielectric helmet, wherein a first portion of the dummy gate structure is disposed on the fins and longitudinally oriented along the second direction, wherein a second portion of the dummy gate structure is parallel to the first portion and disposed adjacent to the sidewall of the isolation structure, and wherein a third portion of the dummy gate structure extends from the second portion to the top surface of the dielectric helmet; forming a plurality of source / drain components in the fins; and forming a metal gate structure in place of the dummy gate structure and the second semiconductor layer.

[0005] Another embodiment of this disclosure is a method for forming a semiconductor structure, the method comprising forming a plurality of fins protruding from a substrate and separated by a first trench, wherein each fin comprises an alternating stack of a plurality of channel layers and a plurality of non-channel layers; patterning the fins to form a second trench perpendicular to the longitudinal orientation of the fins; forming a cladding layer along the sidewalls of each fin exposed in the first and second trenches; forming an isolation structure on the cladding layer to fill the first and second trenches; forming a dielectric component on the isolation structure, wherein the dielectric component protrudes from the fins; forming a dummy gate structure comprising: a first portion formed on the cladding layer and disposed adjacent to a first sidewall of the dielectric component; and forming a second portion connected to the first portion and disposed on a top surface of the dielectric component; forming a source / drain component adjacent to the first portion of the dummy gate structure; and replacing the dummy gate structure, the non-channel layers, and the cladding layer with a metal gate structure.

[0006] Another embodiment of this disclosure is a semiconductor structure comprising fins extending from a substrate and longitudinally oriented along a first direction, wherein the fins comprise a semiconductor layer stack; an isolation member disposed on the substrate and longitudinally oriented along a second direction perpendicular to the first direction, wherein the isolation member is disposed adjacent to the fins; and a metal gate structure having a top disposed on the semiconductor layer stack and a bottom intersecting with the semiconductor layer stack, wherein the bottom sidewall of the metal gate structure is defined by a first sidewall of the isolation member, and wherein the top of the metal gate structure extends laterally to the top surface of the isolation member. Attached Figure Description

[0007] The following detailed description, along with the accompanying drawings, provides a complete explanation. It should be noted that, in accordance with industry practice, the various components are not necessarily drawn to scale. In fact, the dimensions of various components may be arbitrarily enlarged or reduced for clarity.

[0008] Figure 1A and 1B A flowchart illustrating example methods for manufacturing semiconductor structures according to various embodiments of the present disclosure is shown.

[0009] Figure 2A , 3A 1, 4A, 5A, 6A, 7A, 8A, 9A-1, 9A-2, 10A, 11A-1, 11A-2, 12, 15A and 16A are plan view top views of example semiconductor structures according to various embodiments of the present disclosure.

[0010] Figure 2B , 3B 4B, 5B, 6B, 7C, 8C, 9B, 10B, 11B, 15C, and 16C are respectively the intermediate stages of the methods shown in FIG1 and / or 2 according to various embodiments of the present disclosure. Figure 2A ,3A Cross-sectional views of the semiconductor structure of line AA' shown in 1, 4A, 5A, 6A, 7A, 8A, 9A-1, 10A, 11A-1, 15A and 16A.

[0011] Figure 2C , 3C 4C, 5C, 6C, 7D, 8D, 15D, and 16D are respectively the intermediate stages of the method shown in Figures 1 and / or 2 according to various embodiments of the present disclosure. Figure 2A , 3A Cross-sectional views of the semiconductor structure of line BB' shown in 4A, 5A, 6A, 7A, 8A, 9A-1, 10A, 11A-1, 15A and 16A.

[0012] Figure 8E , 9C 10C and 11C are respectively the intermediate stages of the methods shown in FIG1 and / or 2 according to various embodiments of the present disclosure. Figure 8A , 9A-1 Cross-sectional views of the semiconductor structure of line CC' shown in 10A and 11A-1.

[0013] Figure 8F , 9D 10D and 11D are respectively the intermediate stages of the methods shown in FIG1 and / or 2 according to various embodiments of the present disclosure. Figure 8A , 9A-1 Cross-sectional views of the semiconductor structure of line DD' shown in 10A and 11A-1.

[0014] Figure 7B , 8B 15B and 16B are respectively, according to various embodiments of the present disclosure, in... Figure 7A , 8A Three-dimensional perspective views of a portion of the semiconductor structure shown in 15A and 16A.

[0015] Figure 13 and 14 This is a cross-sectional view of an example semiconductor structure according to various embodiments of the present disclosure.

[0016] Explanation of reference numerals in the attached figures:

[0017] 100: Method

[0018] 102, 104, 106, 108, 110, 112, 114, 116, 118, 120: Operations

[0019] 200: Structure

[0020] 202: Base

[0021] 203a, 203b: Trench

[0022] 204: Fins

[0023] 205: Non-channel layer

[0024] 206: Channel Layer

[0025] 207: Hard mask layer

[0026] 208: Isolation component

[0027] 209: Covering layer

[0028] 211: Dielectric Structure

[0029] 211a, 211b: Sub-layers

[0030] 214: Dielectric Helmet

[0031] 220: Dummy gate structure

[0032] 220a, 220a': Dummy gate stack

[0033] 220b: Virtual bridge structure

[0034] 220c: False protrusion

[0035] 222a: Top gate separator

[0036] 230: Etching Stop Layer

[0037] 232: Interlayer dielectric layer

[0038] 260: Metal gate structure

[0039] 260a, 260a': Metal gate stack

[0040] 260b: Metal bridge structure

[0041] 260c: Metal protrusion

[0042] 262: Gate dielectric layer

[0043] 264: Metal gate electrode

[0044] 272: Dielectric layer

[0045] ML: Multilayer structure

[0046] AA', BB', CC': lines

[0047] CD,S: Width

[0048] P: Spacing

[0049] S1, S2: Lateral distance

[0050] W, W1, W2, W3, W5, W6: Width Detailed Implementation

[0051] The following disclosure provides numerous different embodiments or examples for implementing various components of this disclosure. The following disclosure describes specific examples of the various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, in the following disclosure, a component formed on, connected to, and / or coupled to another component may include embodiments where these components are formed in direct contact, and may also include embodiments where additional components are formed between them such that the features are not in direct contact. Furthermore, spatially related terms such as “below,” “under,” “down,” “above,” “on,” and similar terms are used to facilitate the description of the relationship between one element or component and another element(s) in the drawings. In addition to the orientations shown in the drawings, these spatially related terms are intended to encompass different orientations of the device in use or operation.

[0052] Furthermore, when terms such as "about," "approximately," etc., are used to describe numbers or ranges of numbers, this term is intended to cover numbers within a reasonable range that includes the described number, such as within + / - 10% of said number or other values ​​understood by one of ordinary skill in the art to which this invention pertains. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm. Moreover, reference numbers and / or letters may be repeated in various paradigms in this disclosure. This repetition is for simplicity and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0053] This disclosure relates substantially to semiconductor devices, and more particularly to FETs, such as three-dimensional NS FETs, in memory and / or standard logic cells of an IC structure. Typically, an NS FET comprises multiple vertically stacked sheets (e.g., nanosheets), wires (e.g., nanowires), or rods (e.g., nanorods) in the channel region of the FET. This disclosure includes multiple embodiments. Different embodiments may have different advantages, and no particular embodiment necessarily requires a specific advantage.

[0054] Now let's refer to it together. Figure 1A and 1BThe flowchart illustrates a method 100 for forming a semiconductor structure (hereinafter referred to as the structure) 200 according to various aspects of this disclosure. Method 100 is merely exemplary and is not intended to limit the scope of this disclosure beyond what is expressly stated in the claims. Additional operations may be provided before, during, and after method 100, and some described operations may be substituted, eliminated, or moved for additional embodiments of the method. The following is in conjunction with… Figure 2A and 16D Description method 100, where Figure 2A , 3A 1, 4A, 5A, 6A, 7A, 8A, 9A-1, 9A-2, 10A, 11A-1, 11A-2, 12, 15A and 16A are plan view top views of structure 200 according to some embodiments; Figure 2B , 3B 4B, 5B, 6B, 7C, 8C, 9B, 10B, 11B, 15C, and 16C are respectively based on some embodiments along... Figure 2A , 3A A cross-sectional view of the structure 200 of line AA' shown in 4A, 5A, 6A, 7A, 8A, 9A-1, 10A, 11A-1, 15A and 16A; Figure 2C , 3C 4C, 5C, 6C, 7D, 8D, 15D, and 16D are respectively based on some embodiments along... Figure 2A , 3A Cross-sectional views of the structure 200 of line BB' shown in 4A, 5A, 6A, 7A, 8A, 9A-1, 10A, 11A-1, 15A and 16A; Figure 8E , 9C 10C and 11C are respectively based on some embodiments along the... Figure 8A , 9A-1 A cross-sectional view of the structure 200 of line CC' shown in 10A and 11A-1; Figure 8F , 9D 10D and 11D are respectively based on some embodiments along... Figure 8A , 9A-1 A cross-sectional view of the structure 200 of line DD' shown in 10A and 11A-1; Figure 7B , 8B 15B and 16B are respectively based on some embodiments in Figure 7A , 8A A three-dimensional perspective view of a portion of structure 200 shown in 15A and 16A; and Figure 13 and 14This is a cross-sectional view of structure 200 according to some embodiments of the present disclosure. In these embodiments, lines AA' and DD' pass through the active three-dimensional device region (e.g., fin 204) along the X-axis; line BB' passes through the channel region of the fin along the Y-axis; and line CC' passes through the cladding layer (e.g., cladding layer 209) along the X-axis.

[0055] Structure 200 may be an intermediate device or part thereof manufactured during IC fabrication. The intermediate device may include static random-access memory (SRAM) and / or logic circuitry, passive elements such as resistors, capacitors, and inductors, and active elements such as NSFETs, FinFETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other transistors. In these embodiments, structure 200 includes one or more NSFETs. This disclosure is not limited to any particular number of devices or device regions, or any particular device configuration. Additional components may be added to structure 200, and some components described below may be replaced, modified, or eliminated in other embodiments of structure 200.

[0056] For operation 102, please refer to... Figures 2A to 2C Method 100 forms a structure 200 comprising a plurality of active three-dimensional device regions 204 (hereinafter referred to as fins 204) protruding from a semiconductor substrate 202 (hereinafter referred to as substrate 202), wherein adjacent fins 204 are separated by a trench 203a having a width S defined along the Y-axis.

[0057] Substrate 202 may comprise elemental (single-element) semiconductors, such as silicon (Si), germanium (Ge), and / or other suitable materials; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. Substrate 202 may be a monolayer material with a uniform composition. Alternatively, substrate 202 may comprise multiple material layers with similar or different compositions suitable for manufacturing IC devices.

[0058] In these embodiments, see Figure 2B and 2C Each fin 204 comprises an alternating non-channel layer (or sacrificial layer) 205 and channel layer 206 vertically stacked on a protrusion of substrate 202 in a multi-layer structure (ML), and a hard mask layer 207 on the ML. In these embodiments, the non-channel layer 205 is a sacrificial layer configured to be removed in subsequent process steps, thereby providing openings between the channel layers 206 for forming a metal gate stack therein. Each channel layer 206 may comprise a semiconductor material, such as Si, Ge, SiC, SiGe, GeSn, SiGeSn, SiGeCSn, other suitable semiconductor materials, or combinations thereof, while each non-channel layer 205 has a different composition than the channel layer 206. In one such example, the channel layer 206 may comprise element Si and the non-channel layer 205 may comprise SiGe. In another example, the channel layer 206 may comprise element Si and the non-channel layer 205 may comprise element Ge. In some examples, each fin 204 may contain a total of three to ten pairs of alternating non-channel layers 205 and channel layers 206. Other configurations may also be applied depending on specific design requirements.

[0059] In these embodiments, the hard mask layer 207 is a sacrificial layer configured to facilitate the formation of a gate isolation component (discussed in detail below) and subsequently removed from structure 200. Therefore, the thickness of the hard mask layer 207 can be adjusted based on the desired thickness of the gate isolation component. In some embodiments, the thickness of the hard mask layer 207 is greater than the thicknesses of the non-channel layer 205 and the channel layer 206. The hard mask layer 207 may comprise any suitable material, such as a semiconductor material, as long as its composition differs from that of the subsequently formed gate isolation component and the channel layer 206 disposed beneath it, to allow selective removal by an etching process. In some embodiments, the hard mask layer 207 has a composition similar to or the same as that of the non-channel layer 205 and comprises, for example, SiGe.

[0060] In these embodiments, forming the ML involves alternating growth of non-channel layers 205 and channel layers 206 in a series of epitaxial processes. The epitaxial processes can be performed using chemical vapor deposition (CVD) techniques (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure CVD (LP-CVD), and / or plasma-enhanced CVD (PE-CVD)), molecular beam epitaxy, other suitable selective epitaxial growth (SEG) processes, or combinations thereof. The epitaxial processes can use gaseous and / or liquid precursors containing suitable materials (e.g., Ge for the non-channel layer 205) that interact with the composition of the underlying substrate (e.g., substrate 202). In some examples, the non-channel layers 205 and channel layers 206 can be formed as nanosheets, nanowires, or nanorods. A wafer (or wire) release process can then be performed to remove the non-channel layer 205 to form openings between the channel layers 206, and subsequently form a metal gate stack layer in the openings to provide an NS FET. For embodiments where the hard mask layer 207 has the same composition as the non-channel layer 205, the hard mask layer 207 can also be formed by a similar epitaxial process as discussed herein.

[0061] In these embodiments, fins 204 are fabricated from the matrix (ML) (and the hard mask layer 207 disposed thereon) using a series of photolithography and etching processes. For example, the photolithography process may include forming a photoresist layer covering the ML, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the exposed photoresist layer to form a patterned mask element (not shown). The patterned mask element is then used as an etching mask to etch the ML, thereby causing the fins 204 to protrude from the substrate 202. The etching process may include dry etching, wet etching, reactive ion etching (RIE), other suitable processes, or combinations thereof. The patterned mask element is then removed from the ML using any suitable process, such as ashing and / or photoresist stripping.

[0062] Many other embodiments of the method for forming fin 204 may be suitable. For example, dual-patterning or multi-patterning processes can be used to pattern fin 204. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on substrate 202 and patterned using a photolithography process. Using a self-alignment process, spacers are formed next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern fin 204.

[0063] For operation 104, please refer to... Figures 3A to 3CAs shown, method 100 patterns fins 204 to form trenches 203b spanning fins 204. The trenches 203b extend through multiple fins 204 in a direction substantially perpendicular to the longitudinal direction (e.g., the X-axis) of the fins 204 (e.g., the Y-axis), thereby cutting (or separating) the fins 204. Method 100 may implement a series of photolithography and etching processes in operation 104 similar to those performed to form the fins 204. For example, a patterned photoresist layer (not shown) may be formed on the fins 204 first by a photolithography patterning process, and the patterned photoresist layer (and any subsequently patterned hard mask disposed thereunder) may be used as an etching mask to apply an etching process to the fins 204 to form the trenches 203b. After the trenches 203b are formed, the patterned photoresist layer is removed from the structure 200 by photoresist stripping or plasma ashing. In these embodiments, the trenches 203b are defined by a width W measured along the X-axis. In these embodiments, the width W is related to the pitch P between two adjacent dummy gate stacks (e.g., dummy gate stacks 220a / 220a'), as discussed in detail below. Because the dielectric components (e.g., dielectric structure 211 and dielectric helmet 214) formed in the trench 203b connect the ends of two adjacent fins 204 together and serve as part of the substrate of the dummy gate stacks (and subsequently metal gate stacks) formed thereon through a series of photolithography and etching processes, the width of the trench 203b is configured to maintain an ordered arrangement of the dummy gate stacks. In this regard, the width W is generally configured as a multiple of the pitch P or W ~ nP, where n is a positive integer, such as 1, 2, 3, etc. In this disclosure, the symbol "~" indicates that the two quantities are substantially the same, i.e., within + / - 10% of each other. In some embodiments, the width W is greater than the width S; although these embodiments are not limited thereto.

[0064] Then refer to Figures 4A to 4CIn method 100, an isolation component 208 is formed in operation 104, thereby partially filling trenches 203a and 203b, wherein the top surface of the isolation component 208 is below the bottommost non-channel layer 205. The isolation component 208 may comprise silicon oxide (SiO and / or SiO2), tetraethyl orthosilicate (TEOS), doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), etc.), a low-k dielectric material (with a dielectric constant less than that of silicon oxide, approximately 3.9), other suitable materials, or combinations thereof. The isolation component 208 may comprise a shallow trench isolation (STI) component. In some embodiments, the isolation component 208 is formed by filling the trenches separating the fins 204 with the dielectric material described above using any of the suitable methods described above, such as CVD, flowable CVD (FCVD), spin-on-glass (SOG), other suitable methods, or combinations thereof. Subsequently, the dielectric material is planarized and selectively etched back using a chemical-mechanical planarization / polishing (CMP) process to form the isolation component 208. The isolation component 208 may comprise a single-layer structure or a multi-layer structure.

[0065] For operation 106, please refer to... Figures 5A to 5CIn method 100, a cladding layer 209 is formed along the sidewalls of fin 204 and on the isolation members 208 in trenches 203a and 203b. In these embodiments, the cladding layer 209 and the non-channel layer 205 are sacrificial layers configured to be replaced by a metal gate stack in the channel region of fin 204. In these embodiments, the cladding layer 209 has the same composition as the non-channel layer 205 and contains SiGe. In some embodiments, the cladding layer 209 is epitaxially grown using the suitable methods discussed above for forming ML. In some embodiments, the cladding layer 209 is compliantly deposited on the surface of structure 200 as a blanket amorphous layer, rather than being epitaxially grown. In some examples, the cladding layer 209 may be formed to a thickness of about 5 nm to about 10 nm. Subsequently, method 100 performs an etching process to selectively remove portions of the cladding layer 209, thereby exposing portions of the isolation members 208 and the top surface of the hard mask layer 207. Etching processes may include dry etching, wet etching, RIE, or a combination thereof.

[0066] For operation 108, please refer to... Figures 6A to 6C In method 100, a dielectric structure 211 is formed on the isolation component 208 to completely fill trenches 203a and 203b. The dielectric structure 211 is configured to isolate adjacent fins 204 and provides a substrate on which a dielectric helmet 214 can be formed prior to the formation of the dummy gate structure. The dielectric structure 211 may comprise any suitable material, such as SiO and / or SiO2, silicon nitride (SiN), silicon carbide (SiC), oxygen-containing silicon nitride (SiON), oxygen-containing silicon carbide (SiOC), carbon-containing silicon nitride (SiCN), FSG, low-k dielectric materials, other suitable materials, or combinations thereof. The dielectric structure 211 may comprise a single-layer structure or a multilayer structure as shown herein, wherein the dielectric structure 211 includes a sublayer 211b disposed on a sublayer 211a. In some embodiments, sublayer 211a comprises a nitrogen-containing dielectric material, such as SiN and / or SiCN, and sublayer 211b comprises an oxygen-containing dielectric material, such as SiO and / or SiO2. In some embodiments, the compositions of the dielectric structure 211 and the isolation component 208 are different. The dielectric structure 211 (or each of its sublayers) can be deposited by any suitable method, such as CVD, FCVD, SOG, other suitable methods, or combinations thereof, and subsequently planarized by one or more CMP processes such that the top surface of the dielectric structure 211 is substantially coplanar with the top surface of the hard mask layer 207.

[0067] Subsequently, in operation 110, see reference. Figures 7A to 7DMethod 100 forms a dielectric helmet 214 on a dielectric structure 211. The dielectric helmet 214 may comprise SiN, SiC, SiON, SiOC, SiCN, Al2O3, SiO and / or SiO2, a high-k dielectric material (having a k value greater than that of silicon oxide, approximately 3.9), other suitable materials, or combinations thereof. In these embodiments, the dielectric helmet 214 includes a high-k dielectric material used during subsequent processing steps to enhance the etch resistance of the dielectric helmet 214. The dielectric helmet 214 may comprise a single-layer or multi-layer structure. In some embodiments, the dielectric constant of the dielectric helmet 214 is greater than the dielectric constant of the dielectric structure 211 and the isolation member 208. In these embodiments, the width W1 of the dielectric helmet 214 is smaller than the width W of the trench 203b due to the presence of the cladding layers 209. In this respect, the width W is approximately the sum of the width W1 and the thickness T of each cladding layer 209, or W ~ (W1 + 2T).

[0068] Method 100 forms a dielectric helmet 214 by first recessing the top of the dielectric structure 211 to form trenches, such that the top surface of the recessed dielectric structure 211 is substantially coplanar with the topmost channel layer 206. In other words, each of the resulting trenches (not shown) formed on the recessed dielectric structure 211 has a thickness corresponding to the thickness up to the hard mask layer 207. The etching process may include any suitable process, such as dry etching, wet etching, RIE, other suitable processes, or combinations thereof. Method 100 then proceeds to deposit one or more dielectric materials in the trenches and performs a CMP process to form the dielectric helmet 214. One or more dielectric materials may be deposited by any suitable method, such as CVD, FCVD, ALD, other suitable methods, or combinations thereof. Subsequently, method 100 removes the hard mask layer 207 from the structure 200 to expose the topmost channel layer 206 of the ML. Thus, the dielectric helmet 214 protrudes from the top surface of the fin 204. In these embodiments, method 100 selectively removes the hard mask layer 207 without removing or substantially removing the dielectric helmet 214 and the topmost channel layer 206 of ML.

[0069] In these embodiments, the dielectric helmet 214 is configured to provide isolation between the metal gate stack subsequently formed on the fins 204. In other words, a portion of the dielectric helmet 214 may be configured to truncate the metal gate stack into multiple sections. In this respect, the dielectric helmet 214 may be patterned to form one or more gate isolation features (or gate cleaving features) that are self-aligned with the underlying dielectric structure 211 and between the fins 204.

[0070] Now refer to Figures 8A to 8FIn method 100, dummy gate structure 220 is formed on substrate 202 in operation 112. In these embodiments, dummy gate structure 220 includes dummy gate stacks 220a, each dummy gate stack 220a disposed on a channel region of fin 204 to form an NS FET, dummy gate stacks 220a' disposed along the edge of fin 204 and on a portion of cladding layer 209, wherein dummy gate stacks 220a and 220a' are substantially longitudinally oriented along the Y-axis, i.e., substantially perpendicular to the longitudinal direction of fin 204, and a dummy bridge structure 220b connecting two adjacent dummy gate stacks 220a', wherein the dummy bridge structure 220b is substantially longitudinally oriented along the X-axis, i.e., substantially parallel to the longitudinal direction of fin 204. In other words, the dummy bridge structure 220b laterally (i.e., along the X-axis) spans the top surface of the dielectric helmet 214 disposed between the ends of two fins 204 separated along the X-axis, thereby physically or directly connecting one dummy gate stack 220a' to an adjacent dummy gate stack 220a'. In one aspect, the dummy bridge structure 220b can be considered as a "jog structure" of the dummy gate stack 220a'. In some embodiments, see [reference needed]. Figure 8A and 8F Except for the portion connected by the dummy bridge structure 220b, adjacent dummy gate stacks 220a' are separated from each other by dielectric helmets 214.

[0071] See Figure 8A and 8C In these embodiments, the spacing (i.e., separation distance) between two adjacent dummy gate stacks 220a and between a dummy gate stack 220a and an adjacent dummy gate stack 220a' is defined by P, the width (or gate length) of each dummy gate stack 220a and 220a' is defined by CD (i.e., critical dimension), and the distance between the two outer walls of the dummy gate stack 220a' is defined by W2, which is greater than the width W1 of the dielectric helmet 214 on which the dummy bridge structure 220b is formed. In other words, see [reference] Figure 8C The dummy bridge structure 220b is formed to cover the top and sidewalls of the dielectric helmet 214, and is defined by a width W1 along the X-axis. Figures 8A to 8F In the embodiments depicted, the width W defined in operation 104 is approximately twice the spacing P, or W ~ 2P, and the width W2 is greater than the width W. In some embodiments, the width W2 is approximately the sum of the width W and the width CD, or W2 ~ (W + CD). Furthermore, the widths W1, W2, and CD can be related by the following equation: W2 ~ (W1 + 2CD). In some examples, which are not limited in this disclosure, the width CD can be from about 6 nm to about 11 nm and the spacing P can be from about 39 nm to about 81 nm.

[0072] In some embodiments, see Figure 8A and 8E The dummy bridge structure 220b extends along the Y-axis to cover a portion of the covering layer 209. In some embodiments, the dummy bridge structure 220b does not extend along the Y-axis to the covering layer 209 of the covered portion. In some embodiments, see... Figure 8F In this configuration, the dummy bridge structure 220b is not formed along the length of each dummy gate stack 220a'. In other words, compared to... Figure 8C and 8F The dummy bridge structure 220b is not formed on the top surface of the dielectric helmet 214, as can be seen along line DD', which is offset from line CC' along the Y-axis.

[0073] In some embodiments, see Figure 9A-1 and 9A-2 The dummy gate structure 220 does not include a dummy bridge structure 220b for connecting two adjacent dummy gate stacks 220a', but instead includes dummy protrusions 220c that project from the dummy gate stacks 220a' and extend laterally toward each other to the top surface of the dielectric helmet 214 without merging to connect the dummy gate stacks 220a'. Similar to the dummy bridge structure 220b, each dummy protrusion 220c is considered a "bump and groove structure" of the dummy gate stacks 220a' because it extends laterally to contact the top surface of the dielectric helmet 214. In some embodiments, see [reference]. Figure 9A-1 The dummy protrusions 220c are configured to have sharp corners and edges, so that each is formed in a substantially rectangular shape. In some embodiments, see [reference needed]. Figure 9A-2 The dummy protrusions 220c are formed with rounded corners, which may be produced by the etching process used to define the dummy gate structure 220. In these embodiments, the opposing dummy protrusions 220c are positioned substantially symmetrically around the dielectric helmet 214, i.e., their widths are substantially equal.

[0074] use Figure 9A-1 For example and reference Figure 9B In this embodiment, the dummy protrusion 220c disposed on the top surface of the dielectric helmet 214 is defined by a width W3, which is smaller than the width CD of the previously defined dummy gate stack 220a'. In some embodiments, the ratio of width W3 to width CD is from about 0.1 to about 0.5. For example, if the width CD is about 11 nm, then the width W3 may be from about 1 nm to about 5 nm. The width W3 is not limited as defined in these embodiments, as long as the two dummy protrusions 220c are separated from each other and the separation distance allows for the removal of dummy gate structure material during the patterning process of forming the dummy protrusions 220c, the aforementioned separation distance being the difference between twice the width W1 and width W3 of the dielectric helmet 214 (i.e., W1-2W3).

[0075] In some embodiments, see Figure 9A-1 (Or 9A-2) and 9C, each dummy protrusion 220c extends along the Y-axis to cover the covering layer 209 of the portion. In some embodiments, the dummy protrusion 220c does not extend along the Y-axis to cover the covering layer 209 of the portion. In some embodiments, see... Figure 9D The dummy bridge structure 220b is not formed along the length of each dummy gate stack 220a'. In other words, compared to Figure 9B and 9D The dummy protrusion 220c is not formed on the top surface of the dielectric helmet 214, as seen along line DD', which is offset from line CC' along the Y-axis.

[0076] Figures 8A to 9D The embodiment of the dummy gate structure 220 described herein is discussed with reference to the trench 203b, where the width W is approximately twice the pitch P, or W ~ 2P. As provided herein, the width W can be any multiple of the pitch P, or W ~ nP, where n is a positive integer. In this regard, see also... Figures 10A to 11D Further example embodiments are provided, in which the width W is approximately a pitch P, or W ~ P. Therefore, the dielectric helmet 214 formed between the ends of the fins 204 has a reduced width, as discussed in detail below. It is worth noting that these embodiments do not limit the dimension of the width W, which can vary depending on specific IC layout design rules.

[0077] See Figures 10A to 10D The dummy gate structure 220 includes a dummy bridge structure 220b formed on the dielectric helmet 214 to connect the dummy gate stack 220a', wherein Figure 10A Corresponding to Figure 8A , Figure 10B Corresponding to Figure 8C , Figure 10C Corresponding to Figure 8E ,and Figure 10D Corresponding to Figure 8F .

[0078] Similar to Figure 8C The described embodiments, Figure 10B The width W5 of the dielectric helmet 214 is substantially the same as the width of the dielectric helmet 214 along the X-axis, and the width W6 is approximately the sum of width W5 and width CD, or W6 ~ (W5 + 2CD), where the aforementioned width W6 is the distance between the two outer sidewalls of the dummy bridge structure 220b. Furthermore, the width W6 is approximately the sum of width W and width CD, or W6 ~ (W + CD). Figure 10C A dummy bridge structure 220b is shown, which extends along the Y-axis to cover the portion of the cladding layer 209, as shown. Figure 8E As shown, and Figure 10D The dummy bridge structure 220b is depicted not as formed along the length of each dummy gate stack 220a', similar to Figure 8F The example shown.

[0079] See Figure 11A-1 , 11A-2 And 11B to 11D, the dummy gate structure 220 includes a dummy protrusion 220c formed on the dielectric helmet 214 without connecting adjacent dummy gate stacks 220a', wherein Figure 11A-1 Corresponding to Figure 9A-1 , Figure 11A-2 Corresponding to Figure 9A-2 , Figure 11B Corresponding to Figure 9B , Figure 11C Corresponding to Figure 9C ,and Figure 11D Corresponding to Figure 9D . Figure 11A-1 and 11A-2 The dummy protrusion 220c is depicted as being formed into a basically rectangular shape, each with sharp edges and corners. Figure 11A-1 ) or a structure with rounded corners ( Figure 11A-2 Examples of ).

[0080] Similar to Figure 9B The illustrated embodiment, Figure 11B A dummy protrusion 220c, defined by a width W3, is depicted on the top surface of the dielectric helmet 214. This width W3 is smaller than the width CD of the dummy gate stack 220a', and the opposing dummy protrusions 220c are separated by a distance of approximately (W5 - 2W3). Since the width W5 is smaller than the width W1, and assuming the width CD is fixed, therefore... Figure 11B The dummy protrusion 220c shown is compared to Figure 9B Those in the middle are set closer to each other. As mentioned above, the ratio of width W3 to width CD is about 0.1 to about 0.5, but this ratio is not limiting, as long as the separation distance of (W5-2W3) can be adapted to the patterning process used to form the dummy protrusion 220c. Figure 11C Each dummy protrusion 220c extends along the Y-axis to cover, as shown Figure 9C The portion shown is covered by layer 209, while Figure 11D The dummy protrusion 220c is depicted not being formed along the length of each dummy gate stack 220a', similar to Figure 9D The embodiment shown.

[0081] In some embodiments, see Figure 12 The dummy gate structure 220 combines embodiments of the dummy bridge structure 220b and the dummy protrusion 220c, collectively referred to as a bump-concave structure, such as... Figures 8A to 11DAs shown in the illustration. In some embodiments, the width of one or more convex and concave structures varies independently along the X-axis to accommodate different design requirements. For illustrative purposes, a dummy bridge structure 220b is formed on a dielectric helmet 214 having a width W1 (i.e., W ~ 2P), and a dummy protrusion 220c is configured with rounded corners and formed on a dielectric helmet 214 having a width W5 (i.e., W ~ P). Although not depicted, convex and concave structures of other sizes are also applicable to this disclosure.

[0082] When forming a dummy gate stack along the edge of a fin, it is generally desirable that the centerline of the dummy gate stack be aligned with the edge of the fin. However, see [link to relevant documentation]. Figure 13 As an example, overlay misalignment of the photolithography mask can cause the centerline to move away from the edge of the fin during photolithography, resulting in excessive gate stack material (e.g., polysilicon) remaining between the dummy gate stack and the dielectric helmet. This residue, in Figure 13 The lateral distance S1, denoted by R, can span a distance much smaller than the width CD of the dummy gate stack. This distance is too small to be effectively removed during the etching process that forms the dummy gate stack after the photolithography process. In some examples, the lateral distance S1 can be less than about half the width CD. When subsequent manufacturing processes are performed, such as forming S / D recesses, the residual R may be exposed and provide a substrate on which epitaxial material can grow, resulting in epitaxial mushroom defects. This unintentional growth can negatively impact device performance. In one such example, the epitaxial mushroom defect may not be properly insulated from the subsequently formed metal gate stack (MG), resulting in an electrical short circuit. See also... Figure 14 An offset in the opposite direction (e.g., shifting the centerline toward the dielectric helmet) causes the lateral distance S2 to be greater than about half the width CD, and may cause pits (or voids) to form within the epitaxial S / D component and / or reduce the width of the channel layer of the adjacent epitaxial S / D component, resulting in an electrical short circuit between the subsequently formed MG and S / D contacts (MD).

[0083] These embodiments provide methods for reducing or eliminating the growth of epitaxial mushroom defects, avoiding MG-MD short circuits, and / or pitting in epitaxial S / D components by forming a bump structure extending from a dummy gate stack (e.g., dummy gate stack 220a') disposed at the edge of the fin. Whether the bump structure is configured as a bridge structure connecting two dummy gates (e.g., dummy bridge structure 220b) or as separate protrusions (e.g., dummy protrusion 220c), these embodiments ensure that at least a portion of the dielectric helmet (e.g., dielectric helmet 214) is covered by the bump structure to eliminate the formation of residual R, thereby eliminating mushroom defects on the dummy gate stack and reducing the occurrence of pitting and / or MG-MD short circuits.

[0084] See also Figures 8A to 12 Each portion of the dummy gate structure 220 (i.e., dummy gate stacks 220a, 220a', dummy bridge structure 220b, and dummy protrusion 220c) may include a dummy gate electrode disposed on an optional dummy gate dielectric layer and / or interface layer (not depicted). In these embodiments, the dummy gate structure 220 is configured to be replaced with a metal gate structure. The dummy gate structure 220 can be formed by a series of deposition and patterning processes. For example, the dummy gate structure 220 can be formed by depositing a polysilicon (poly-Si) layer on a substrate 202 and subsequently patterning the polysilicon layer via a series of photolithography and etching processes (e.g., dry etching processes). In these embodiments, the photolithography process is configured to form bump structures (i.e., dummy bridge structures 220b and / or dummy protrusions 220c) in the dummy gate structure 220. This can be achieved by designing a photomask having one or more bump structures with dimensions relative to the gate stack as discussed in detail above. To accommodate the patterning process and protect the dummy gate structure 220 during subsequent manufacturing processes, one or more hard mask layers (not depicted) may be formed on the dummy gate structure 220.

[0085] See also Figures 8A to 12 In method 100, operation 112 subsequently forms a top gate separator 222a on the sidewall of each portion of the dummy gate structure 220. The top gate separator 222a may comprise a single-layer or multi-layer structure and may comprise SiO and / or SiO2, SiN, SiC, SiON, SiOC, SiCN, air, low-k dielectric materials, high-k dielectric materials (e.g., hafnium oxide (HfO2), lanthanum oxide (La2O3), etc.), other suitable materials, or combinations thereof. The top gate separator 222a can be left on the sidewall of each dummy gate structure 220 by first depositing a dielectric layer on the dummy gate structure 220 via a suitable deposition method (e.g., CVD and / or ALD) and then removing portions of the dielectric layer in an anisotropic (e.g., oriented) etching process (e.g., dry etching).

[0086] Follow-up operations for Method 100 Figures 15A to 16D Discussion, in which, for illustrative purposes, Figures 15A to 15D against Figures 8A to 8E The embodiments described herein Figures 16A to 16D against Figure 11A-1 , 11A-2 The embodiments depicted in 11B-11D.

[0087] See Figure 15B , 15CMethods 100, 16B and 16C, form an epitaxial S / D component 224 in operation 114 within fins 204 adjacent to dummy gate stacks 220a and 220a'. In these embodiments, method 100 forms an S / D recess (not depicted) in the S / D region of fin 204, forms an inner gate separator 222b on the sidewall of non-channel layer 205 exposed in the S / D recess, and forms the epitaxial S / D component 224 within the S / D recess.

[0088] In these embodiments, method 100 forms the S / D recess by performing an etching process that selectively removes portions of the fins 204 in the S / D region. In some embodiments, the etching process is a dry etching process using a suitable etchant capable of removing the channel layer 206 (e.g., Si) and the non-channel layer 205 (e.g., SiGe) of the ML. In some examples, the dry etchant may be a chlorine-containing etchant comprising Cl2, SiCl4, BCl3, other chlorine-containing gases, or combinations thereof. A cleaning process may then be performed to clean the S / D recess with a hydrofluoric acid (HF) solution or other suitable solution.

[0089] The inner gate spacer 222b may be a single-layer or multi-layer structure and may comprise silicon oxide, SiN, SiCN, SiOC, SiON, SiOCN, low-k dielectric materials, air, high-k dielectric materials (e.g., HfO2, La2O3, etc.), other suitable dielectric materials, or combinations thereof. In some embodiments, the inner gate spacer 222b has a different composition from the top gate spacer 222a. Forming the inner gate spacer 222b may involve selectively removing portions of the non-channel layer 205 exposed in the S / D recess, while not removing or substantially removing portions of the channel layer 206 to form a trench (not depicted). The non-channel layer 205 may be etched using a dry etching process. Subsequently, one or more dielectric layers are formed in the trench, followed by one or more etching processes to remove (i.e., etch back) excess dielectric layer deposited on the surface of the channel layer 206, thereby forming the inner gate spacer 222b. One or more dielectric layers can be deposited by any suitable method, such as ALD, CVD, physical vapor deposition (PVD), other suitable methods, or a combination thereof.

[0090] Each epitaxial S / D component 224 may be adapted to form a p-type FET device (i.e., comprising p-type epitaxial material) or, alternatively, an n-type FET device (i.e., comprising n-type epitaxial material). The p-type epitaxial material may comprise one or more silicon-germanium epitaxial (epiSiGe) layers, each doped with a p-type dopant such as boron, germanium, indium, gallium, other p-type dopants, or combinations thereof. The n-type epitaxial material may comprise one or more silicon (epiSi) or silicon-carbon (epiSiC) epitaxial layers, each doped with an n-type dopant such as arsenic, phosphorus, other n-type dopants, or combinations thereof. In some embodiments, one or more epitaxial growth processes are performed to grow epitaxial material in each S / D recess and on the inner gate spacer 222b. For example, method 100 may implement an epitaxial growth process similar to that discussed above regarding the formation of the ML. In some embodiments, the epitaxial material is doped in situ by adding dopants to the source material during the epitaxial growth process. In some embodiments, the epitaxial material is doped by an ion implantation process after a deposition process. In some embodiments, an annealing process is then performed to activate the dopants in the epitaxial S / D component 224.

[0091] Subsequently, in operation 114, method 100 forms an etch-stop layer (ESL) 230 on structure 200 to protect underlying components, such as epitaxial S / D components 224, during subsequent manufacturing processes. ESL 230 may comprise any suitable dielectric material such as SiN, SiCN, Al2O3, other suitable materials, or combinations thereof, and may be formed by CVD, ALD, PVD, other suitable methods, or combinations thereof. In these embodiments, ESL 230 provides etch selectivity relative to the surrounding dielectric elements to ensure protection against accidental damage to those elements. Method 100 then forms an interlayer dielectric (ILD) layer 232 on ESL 230 to fill the spaces between portions of the dummy gate structure 220. The ILD layer 232 may comprise SiO and / or SiO2, a low-k dielectric material, TEOS, doped silicon oxide (e.g., BPSG, FSG, PSG, BSG, etc.), other suitable dielectric materials, or combinations thereof, and may be formed by any suitable method, such as CVD, FCVD, SOG, other suitable methods, or combinations thereof. Method 100 then performs one or more CMP processes to expose the top surface of the dummy gate structure 220.

[0092] In some embodiments, method 100 patterns the dielectric helmet 214 in operation 116 such that some portions of the dielectric helmet 214 are retained as gate isolation components for separating the subsequently formed metal gate structure, and other portions of the dielectric helmet 214 are removed from structure 200. For example... Figures 15A to 15DAn embodiment is shown in which a portion of the dielectric helmet 214 under the dummy bridge structure 220b is removed during the patterning process of operation 116, while Figures 16A to 16D An embodiment is shown in which a portion of the dielectric helmet 214 formed under the dummy protrusion 220c is not removed and is retained as a gate isolation component of the subsequently formed metal gate structure.

[0093] In some embodiments, method 100 patterns the dielectric helmet 214 by forming a patterned mask element (not depicted) to expose the portion of the dummy gate structure 220 that engages with the portion of the dielectric helmet 214 to be removed. The patterned mask element comprises at least a photoresist layer that can be patterned by a series of photolithography and etching processes discussed in detail above for patterning the fin 204. Subsequently, method 100 removes the exposed portion of the patterned mask element of the dummy gate structure 220 in an etching process (e.g., a dry etching process) to expose the portion of the dielectric helmet 214. In some embodiments, the etching process does not need to completely remove the exposed portion of the dummy gate stack 220, and the extent of this removal is controlled by adjusting the duration of the etching process. After the etching process is performed, the patterned mask element is removed from the structure 200 by any suitable method, such as photoresist stripping and / or plasma ashing. Then, in a suitable etching process (e.g., a dry etching process), the exposed portions of the dielectric helmet 214 are selectively removed relative to the dummy gate stack 220 to form a patterned dielectric helmet 214. In some embodiments, operation 116 is optional and the dielectric helmet 214 is patterned in a subsequent operation.

[0094] See also Figures 15A to 16D In method 100, at operation 118, a metal gate structure 260 replaces the dummy gate structure 220, the non-channel layer 205, and the cladding layer 209. The metal gate structure 260 includes a metal gate stack 260a, a metal gate stack 260a', a metal bridge structure 260b, and a metal protrusion 260c, corresponding to the dummy gate stack 220a, dummy gate stack 220a', dummy bridge structure 220b, and dummy protrusion 220c, respectively. In these embodiments, a portion of the metal gate stack 260a' extends along the sidewalls of the fin 204 and along the sidewalls of the dielectric structure 211. To clearly show the metal gate structure 260 in a planar top view, in Figure 15A and 16A The additional components formed on the metal gate structure 260 are omitted.

[0095] In these embodiments, method 100 first performs an etching process to remove the dummy gate structure 220 (or the remaining portion after the dielectric helmet 214 has been patterned), thereby forming a gate trench (not depicted) between the top gate spacers 222a. The etching process may be a dry etching process, a wet etching process, a RIE process, other suitable processes, or a combination thereof. In some embodiments, removing the dummy gate structure 220 removes a portion of the dielectric helmet 214 disposed under the dummy gate structure 220, for example, under the dummy bridge structure 220b and / or the dummy protrusion 220c.

[0096] Subsequently, method 100 removes the cladding layer 209 and the non-channel layer 205 to form openings that intersect with and along the sidewalls of the channel layer 206. In some embodiments, method 100 performs separate etching processes to remove the cladding layer 209 and the non-channel layer 205. For example, method 100 may perform a first etching process to remove the cladding layer 209, creating vertical openings along the sidewalls of each fin 204, and then perform a second etching process to remove the non-channel layer 205, creating horizontal openings that intersect with the channel layer 206. For embodiments where the non-channel layer 205 and the cladding layer 209 have the same composition (e.g., SiGe), the same etchant can be used to perform the first and second etching processes, such as a fluorinated etchant containing hydrofluoric acid (HF), F-2, other fluorinated etchants (e.g., CF4, CHF3, CH3F, etc.), or combinations thereof.

[0097] See also Figures 15A to 16D Then, method 100 forms a metal gate structure 260 in the gate trench, vertical opening, and horizontal opening. Thus, portions of the metal gate structure 260 surround (or interleave) each channel layer 206 and extend along the sidewalls of the fin 204. For embodiments in which portions of the dielectric helmet 214 are removed, for example by patterning the dielectric helmet 214 in operation 116 and / or by recessing the dummy gate structure 220 in operation 118, the metal gate structure 260 is formed to directly contact the top surface of the dielectric structure 211 (see [reference]). Figure 15C Metal bridge structure 260b and Figure 16C The protruding metal portion 260c).

[0098] In some embodiments, see Figure 15D and 16DThe metal gate structure 260 includes a gate dielectric layer 262 and a metal gate electrode 264 on the gate dielectric layer. The gate dielectric layer 262 may contain a high-k dielectric material, such as HfO2, La2O3, other suitable materials, or combinations thereof. The metal gate electrode 264 includes at least one work function metal layer and a bulk conductive layer disposed thereon. The work function metal layer may be a p-type or n-type work function metal layer. Example work function metals include TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable work function metals, or combinations thereof. The bulk conductive layer may contain Co, W, Ru, Cu, Al, Ti, Ni, Au, Pt, Pd, other suitable materials, or combinations thereof. The metal gate structure 260 may further include other material layers (not depicted), such as interface layers, capping layers, barrier layers, other suitable layers, or combinations thereof disposed on the surface of the channel layer 206. The various layers of the metal gate structure 260 may be formed by various methods, including, for example, ALD, CVD, PVD, electroplating, other suitable methods, or combinations thereof. After the main conductive layer is formed, one or more CMP processes are performed to remove excess material formed on the top surface of the ILD layer 232, thereby planarizing the structure 200.

[0099] In some embodiments, see still Figures 15A to 16D Method 100 then recesses the metal gate structure 260 to form a trench (not depicted) such that any remaining portion of the dielectric helmet 214 protrudes from the recessed metal gate structure 260 and separates (or cuts) the recessed metal gate structure 260 into multiple portions. Subsequently, method 100 deposits a dielectric layer 272 on the structure 200 to fill the trench. In some embodiments, the dielectric layer 272 is configured to include, for example, patterning the ILD layer 232 to form S / D contact openings (not depicted) on the epitaxial S / D components during subsequent fabrication processes, providing self-alignment capability and etch selectivity. Therefore, in these embodiments, the dielectric layer 272 has a different composition than the ILD layer 232. In some embodiments, the dielectric layer 272 comprises SiN, SiCN, SiOC, SiON, SiOCN, SiO and / or SiO2, other suitable materials, or combinations thereof. Subsequently, method 100 removes portions of dielectric layer 272 formed on ILD layer 232 in one or more CMP processes, thereby planarizing the top surface of structure 200.

[0100] Subsequently, method 100 performs additional fabrication processes on structure 200 in operation 120, such as forming a multi-layer interconnect (MLI) structure (not depicted) thereon. The MLI may include various interconnect components, such as vias and conductors, disposed in dielectric layers, such as ESL and ILD layers. In some embodiments, vias are vertical interconnect components configured to interconnect device-level contacts, such as S / D contacts (not depicted) or gate contacts (not depicted), with conductors, or vias interconnect different conductors, which are horizontal interconnect components. The ESL and ILD layers of the MLI may each have substantially the same composition as discussed above regarding the composition of ESL 230 and ILD layer 232. Vias and conductors may each contain any suitable conductive material, such as Co, W, Ru, Cu, Al, Ti, Ni, Au, Pt, Pd, metal silicides, other suitable conductive materials, or combinations thereof, and are formed by a series of patterning and deposition processes. Furthermore, each via and conductor may additionally include a barrier layer comprising TiN and / or TaN.

[0101] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits for semiconductor devices and their formation. For example, this disclosure provides methods for reducing or eliminating the growth of epitaxial mushroom defects, avoiding MG-MD short circuits, and / or pitting in epitaxial S / D components by forming a bump structure extending from a dummy gate stack disposed on the edge of a semiconductor fin. In some embodiments, the bump structure bridges two adjacent dummy gate stacks on a dielectric helmet disposed along the edge of the semiconductor fin. In some embodiments, the bump structure includes two protrusions, each extending in opposite directions from the two adjacent dummy gate stacks, without coalescing together to completely cover the dielectric helmet. In these embodiments, after a gate replacement process is performed, the bump structure remains at least partially on the semiconductor fin as a portion of the metal gate structure. Embodiments of this disclosure ensure that at least a portion of the dielectric helmet is covered by the bump structure to counteract the adverse effects of unintentional cover offset during patterning of the dummy gate stacks.

[0102] In one aspect, this disclosure provides a method for forming a semiconductor structure. The method includes forming fins protruding from a semiconductor substrate, wherein the fins are longitudinally oriented along a first direction and include alternating stacks of first and second semiconductor layers; forming trenches to separate the fins, wherein the trenches are longitudinally oriented along a second direction perpendicular to the first direction; forming an isolation structure in the trenches; forming a dielectric helmet on the isolation structure; forming a dummy gate structure on the dielectric helmet; forming source / drain components in the fins; and forming a metal gate structure replacing the dummy gate structure and the second semiconductor layers. In these embodiments, the dummy gate structure includes a first portion, a second portion, and a third portion, the first portion being disposed on the fins and longitudinally oriented along the second direction, the second portion being parallel to the first portion and disposed adjacent to the sidewall of the isolation structure, and the third portion extending from the second portion to the top surface of the dielectric helmet.

[0103] In some embodiments, the first and second portions of the dummy gate structure are separated by a spacing P, and the trench is formed to have a width W of approximately nP, where n is a positive integer.

[0104] In some embodiments, a third portion of the dummy gate structure extends to completely cover the top surface of the dielectric helmet.

[0105] In some embodiments, a third portion of the dummy gate structure extends to partially cover the top surface of the dielectric helmet.

[0106] In some embodiments, each of the first and second portions of the dummy gate structure is formed to have a width CD, and the third portion is formed to have a width W1 that is smaller than the width CD.

[0107] In some embodiments, the isolation structure is a first isolation structure, and the method of forming the semiconductor structure further includes forming a second isolation structure to partially fill the trench before forming the first isolation structure, and forming a coating layer along the sidewalls of the fins exposed in the trench and on the second isolation structure, such that the first isolation structure is formed on the coating layer.

[0108] In some embodiments, the fin is a first fin and the groove is a first groove, wherein forming the first fin also forms a second fin, the second fin is longitudinally oriented along a first direction and separated from the first fin by a second groove oriented along the first direction, and an isolation structure is formed in both the first groove and the second groove.

[0109] In another aspect, this disclosure provides a method for forming a semiconductor structure, the method comprising forming fins protruding from a substrate and separated by a first trench, wherein each fin comprises an alternating stack of channel layers and non-channel layers; patterning the fins to form a second trench perpendicular to the longitudinal orientation of the fins; forming a cladding layer along the sidewalls of each fin exposed in the first and second trenches; forming an isolation structure on the cladding layer to fill the first and second trenches; forming a dielectric component on the isolation structure, wherein the dielectric component protrudes from the fins; forming a dummy gate structure; forming a source / drain component adjacent to a first portion of the dummy gate structure; and replacing the dummy gate structure, the non-channel layer, and the cladding layer with a metal gate structure. In these embodiments, forming the dummy gate structure includes forming a first portion disposed on the cladding layer and adjacent to a first sidewall of the dielectric component, and forming a second portion connected to the first portion and disposed on the top surface of the dielectric component.

[0110] In some embodiments, the isolation structure is a first isolation structure, and the method of forming the semiconductor structure further includes forming a second isolation structure before forming a cladding layer to partially fill the first isolation structure and the second isolation structure.

[0111] In some embodiments, the dielectric component has a first width and the second portion of the dummy gate structure has a second width, and the second width is the same as the first width.

[0112] In some embodiments, the dummy gate structure includes a third portion adjacent to a second sidewall of the dielectric component opposite to the first sidewall, and the second portion extends onto the dielectric component to connect the third portion of the dummy gate structure.

[0113] In some embodiments, the dielectric component has a first width and the second portion of the dummy gate structure has a second width, wherein the first width is greater than the second width.

[0114] In some embodiments, the first portion of the dummy gate structure has a third width, and the second width is smaller than the third width.

[0115] In some embodiments, the second portion is formed to have multiple rounded corners in a planar top view.

[0116] In another aspect, this disclosure provides a semiconductor structure including fins, an isolation member, and a metal gate structure. The fins extend from a substrate and are longitudinally oriented along a first direction, wherein the fins comprise a stack of semiconductor layers. The isolation member is disposed on the substrate and is longitudinally oriented along a second direction perpendicular to the first direction, wherein the isolation member is disposed adjacent to the fins. The metal gate structure has a top disposed on the semiconductor layer stack and a bottom intersecting with the semiconductor layer stack. In these embodiments, the sidewall of the bottom of the metal gate structure is defined by a first sidewall of the isolation member, and the top of the metal gate structure extends laterally to the top surface of the isolation member.

[0117] In some embodiments, the semiconductor structure further includes a dielectric helmet disposed on the isolation member. The dielectric helmet defines a sidewall at the top of the metal gate structure.

[0118] In some embodiments, the dielectric constant of the isolation component is less than that of the dielectric helmet.

[0119] In some embodiments, the metal gate structure is a first metal gate structure, and the semiconductor structure further includes a second metal gate structure having a sidewall defined by a second sidewall of the isolation member opposite to the first sidewall. The top of the first metal gate structure extends completely to the top surface of the isolation structure to connect to the top of the second metal gate structure.

[0120] In some embodiments, the insulating member includes a bottom and a top, with the bottom embedded in a substrate and the top disposed on the bottom. The top and bottom have different compositions.

[0121] In some embodiments, the top of the isolation component comprises two sub-layers with different compositions.

[0122] The foregoing description outlines components of numerous embodiments, enabling those skilled in the art to better understand this disclosure from various perspectives. Those skilled in the art will understand that other processes and structures can be readily designed or modified based on this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive concept and scope of this disclosure. Various changes, substitutions, or modifications can be made to this disclosure without departing from the inventive concept and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure: A fin protruding from a semiconductor substrate is formed, wherein the fin is longitudinally oriented along a first direction, and wherein the fin comprises an alternating stack of first and second semiconductor layers; Grooves are formed to separate the fins, wherein the grooves are longitudinally oriented along a second direction perpendicular to the first direction; An isolation structure is formed in the trench; A gate isolation component is formed on the isolation structure; A dummy gate structure is formed on the gate isolation member, wherein a first portion of the dummy gate structure is disposed on the fin and longitudinally oriented along the second direction, wherein a second portion of the dummy gate structure is parallel to the first portion and disposed adjacent to the sidewall of the isolation structure, and wherein a third portion of the dummy gate structure extends from the second portion to the top surface of the gate isolation member; Multiple source / drain components are formed in the fins; as well as The dummy gate structure and the plurality of second semiconductor layers are removed, and a metal gate structure is formed in the space where the dummy gate structure and the plurality of second semiconductor layers are removed.

2. The method for forming a semiconductor structure as claimed in claim 1, wherein the first portion and the second portion of the dummy gate structure are separated by a spacing P, and wherein the trench is formed with a width W of nP, where n is a positive integer.

3. The method of forming a semiconductor structure as claimed in claim 1, wherein the third portion of the dummy gate structure extends to completely cover the top surface of the gate isolation member.

4. The method of forming a semiconductor structure as claimed in claim 1, wherein the third portion of the dummy gate structure extends to partially cover the top surface of the gate isolation member.

5. The method of forming a semiconductor structure as claimed in claim 4, wherein each of the first portion and the second portion of the dummy gate structure is formed to have a width CD, and wherein the third portion is formed to have a width W1 that is smaller than the width CD.

6. The method for forming a semiconductor structure as claimed in claim 1, wherein the isolation structure is a first isolation structure, and the method for forming the semiconductor structure further comprises, before forming the first isolation structure: A second isolation structure is formed to partially fill the trench; as well as A coating layer is formed along the sidewall of the fin exposed in the groove and on the second isolation structure, such that the first isolation structure is formed on the coating layer.

7. The method of forming a semiconductor structure as claimed in claim 1, wherein the fin is a first fin and the trench is a first trench, wherein forming the first fin also forms a second fin, the second fin is longitudinally oriented along the first direction and separated from the first fin by a second trench oriented along the first direction, and wherein the isolation structure is formed in both the first trench and the second trench.

8. A method for forming a semiconductor structure, comprising: Multiple fins are formed that protrude from the substrate and are separated by a first groove, wherein each fin contains an alternating stack of multiple channel layers and multiple non-channel layers. The plurality of fins are patterned to form a second groove perpendicular to the longitudinal direction of the plurality of fins; A coating layer is formed along the sidewall of each fin exposed in the first and second grooves; An isolation structure is formed on the coating layer to fill the first trench and the second trench; A dielectric component is formed on the isolation structure, wherein the dielectric component protrudes from the plurality of fins; The dummy gate structure includes: A first portion formed on the coating layer and disposed adjacent to the first sidewall of the dielectric component; as well as A second portion is formed, connected to the first portion and disposed on the top surface of the dielectric component; The first portion adjacent to the dummy gate structure forms a source / drain component; as well as The dummy gate structure, the plurality of non-channel layers, and the cladding layer are removed, and a metal gate structure is formed in the space where the dummy gate structure, the plurality of non-channel layers, and the cladding layer are removed.

9. The method for forming a semiconductor structure as claimed in claim 8, wherein the isolation structure is a first isolation structure, and the method for forming the semiconductor structure further includes forming a second isolation structure before forming the cladding layer to partially fill the first isolation structure and the second isolation structure.

10. The method of forming a semiconductor structure as claimed in claim 8, wherein the dielectric component has a first width and the second portion of the dummy gate structure has a second width, and wherein the second width is the same as the first width.

11. The method of forming a semiconductor structure as claimed in claim 10, wherein the dummy gate structure includes a third portion adjacent to a second sidewall of the dielectric member opposite to the first sidewall, and wherein the second portion extends onto the dielectric member to connect the third portion of the dummy gate structure.

12. The method of forming a semiconductor structure as claimed in claim 8, wherein the dielectric component has a first width and the second portion of the dummy gate structure has a second width, and wherein the first width is greater than the second width.

13. The method of forming a semiconductor structure as claimed in claim 12, wherein the first portion of the dummy gate structure has a third width, and wherein the second width is smaller than the third width.

14. The method of forming a semiconductor structure as claimed in claim 8, wherein the second portion is formed to have a plurality of rounded corners in a planar top view.

15. A semiconductor structure comprising: Fins extending from a substrate and longitudinally oriented along a first direction, wherein the fins comprise a stack of semiconductor layers; An isolation member is disposed on the substrate and oriented longitudinally along a second direction perpendicular to the first direction, wherein the isolation member is disposed adjacent to the fin; as well as A metal gate structure having a top disposed on the semiconductor layer stack and a bottom interposed with the semiconductor layer stack, wherein a first sidewall of the isolation member defines the boundary of the sidewall of the bottom of the metal gate structure, and wherein the top of the metal gate structure extends laterally to the top surface of the isolation member.

16. The semiconductor structure of claim 15, further comprising: A gate isolation member is disposed on the isolation member, wherein the gate isolation member defines the boundary of the sidewall of the top of the metal gate structure.

17. The semiconductor structure of claim 16, wherein the dielectric constant of the isolation component is less than the dielectric constant of the gate isolation component.

18. The semiconductor structure of claim 15, wherein the metal gate structure is a first metal gate structure, the semiconductor structure further comprising a second metal gate structure having a sidewall defined by a second sidewall of the isolation member opposite to the first sidewall, and wherein the top of the first metal gate structure extends completely to the top surface of the isolation structure to connect the top of the second metal gate structure.

19. The semiconductor structure of claim 15, wherein the isolation member comprises a bottom and a top, the bottom being embedded in the substrate, the top being disposed on the bottom, and wherein the top surface has a different composition from the bottom surface.

20. The semiconductor structure of claim 19, wherein the top of the isolation component comprises two sublayers with different compositions.

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