Method for forming flash memory structure

Abstract

A method for forming a flash memory structure comprises: providing control gate openings between initial control gates, providing sacrificial openings exposing the control gate openings between sacrificial layers, and forming first sidewalls on the sidewalls of the sacrificial openings; forming a first dielectric layer, an initial second sidewall located on the sidewalls of the first dielectric layer, and a second dielectric layer located on the sidewalls of the initial second sidewalls on the sidewalls of the initial control gate structure exposed by the control gate openings and the sacrificial openings, wherein the material of the initial second sidewalls is different from that of the first dielectric layer and the second dielectric layer; etching the initial second sidewalls until the top surface of the initial second sidewalls is lower than the top surface of the initial control gate structure to form the second sidewalls; after forming the second sidewalls, etching the floating gate material layer until the substrate is exposed to form transition floating gates, wherein the transition floating gates have floating gate openings; and forming an erase gate structure within the control gate openings, the sacrificial openings, and the floating gate openings to improve the process window and the stability of device performance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a flash memory structure. Background Art

[0002] Flash memory is a type of non-volatile memory that can retain data even without a current supply, meaning it persists even during power outages. Based on their structure, flash memory can be divided into two types: NOR Flash and NAND Flash. NAND Flash, due to its direct code execution, high reliability, and fast read speed, has become the mainstream non-volatile memory in flash memory technology. It is widely used in applications such as mobile phones and motherboards that require system code storage.

[0003] With the continuous development of semiconductor technology, it is imperative to reduce the size of NOR flash memory cells. However, this size reduction may bring more and more problems to NOR flash memory, such as reliability failure and low programming efficiency.

[0004] Therefore, the performance of the NOR-type flash memory structure formed by the prior art needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a flash memory structure to improve the performance of the formed flash memory structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a flash memory structure, comprising: providing a substrate; forming a floating gate material layer on the surface of the substrate, and two initial control gate structures separated from each other on the surface of the floating gate material layer, each initial control gate structure comprising an initial control gate, a sacrificial layer located on the initial control gate, and a first sidewall; a control gate opening is provided between the initial control gates, a sacrificial opening is provided between the sacrificial layers to expose the control gate opening, and the first sidewall is located on the sidewall of the sacrificial opening; forming a first sidewall between the control gate opening and the sidewall of the initial control gate structure exposed by the sacrificial opening; A dielectric layer, an initial second spacer located on the sidewall of the first dielectric layer, and a second dielectric layer located on the sidewall of the initial second spacer, wherein the material of the initial second spacer is different from that of the first dielectric layer and the second dielectric layer; etching the initial second spacer until the top surface of the initial second spacer is lower than the top surface of the initial control gate structure to form a second spacer; after forming the second spacer, etching the floating gate material layer until the substrate is exposed to form a transition floating gate, wherein a floating gate opening is provided between the transition floating gates; and forming an erase gate structure within the control gate opening, the sacrificial opening, and the floating gate opening.

[0007] Optionally, the method for forming the first dielectric layer, the initial second sidewall spacer and the second dielectric layer includes: forming a first dielectric material layer, a second sidewall spacer layer located on the surface of the floating gate material layer and the surfaces of the two initial control gate structures, and a second dielectric material layer located on the surface of the second sidewall spacer layer; etching back the first dielectric material layer, the second sidewall spacer layer and the second dielectric material layer until the surface of the floating gate material layer is exposed, forming the first dielectric layer with the first dielectric material layer, forming the initial second sidewall spacer with the second sidewall spacer layer, and forming the second dielectric layer with the second dielectric material layer.

[0008] Optionally, the process of etching back the first dielectric material layer, the second spacer material layer and the second dielectric material layer includes a dry etching process.

[0009] Optionally, the process of etching the initial second sidewall spacer includes a wet etching process.

[0010] Optionally, the process parameters of the wet etching process include: the etching solution includes a phosphoric acid solution, the etching temperature ranges from 120° C. to 180° C., and the etching solution concentration ranges from 80% to 90%.

[0011] Optionally, after forming the floating gate opening and before forming the erase gate structure, the second dielectric layer is further removed.

[0012] Optionally, after forming the erase gate structure, it further includes: removing the sacrificial layer; after removing the sacrificial layer, using the first side wall as a mask, etching the initial control gate and the transition floating gate until the substrate surface is exposed, forming two separate storage gate structures on the substrate, each storage gate structure including a floating gate and a control gate structure located on the floating gate, the control gate structure including a control gate and the first side wall, the floating gate is formed by the transition floating gate, and the control gate is formed by the initial control gate.

[0013] Optionally, the control gate structure also includes a floating gate oxide layer located between the floating gate and the substrate; the method for forming the floating gate oxide layer includes: before forming the floating gate material layer, forming a floating gate oxide material layer on the surface of the substrate; the floating gate oxide material layer is etched to form the floating gate oxide layer.

[0014] Optionally, the method for forming the two initial control gate structures includes: forming a control gate material layer on the floating gate material layer; forming a sacrificial material layer on a portion of the control gate material layer; etching the sacrificial material layer to form the sacrificial layer and the sacrificial opening; forming the first side wall on the side wall of the sacrificial opening; after forming the first side wall, etching the control gate material layer exposed at the bottom of the sacrificial opening to form two initial control gates.

[0015] Optionally, the control gate structure also includes a control gate dielectric layer located between the floating gate and the control gate; the method for forming the control gate dielectric layer includes: before forming the control gate material layer, forming a control gate dielectric material layer on the floating gate material layer; the control gate dielectric material layer is etched to form the control gate dielectric layer.

[0016] Optionally, the erase gate structure includes an erase gate layer; the method for forming the erase gate structure includes: forming an erase gate material layer within the control gate opening, the sacrificial opening and the floating gate opening, and on the surface of the initial control gate structure; flattening the erase gate material layer until the top surface of the initial control gate structure is exposed, and forming the erase gate layer with the erase gate material layer.

[0017] Optionally, the erase gate structure further includes an erase gate dielectric layer, and the erase gate layer is located on a surface of the erase gate dielectric layer.

[0018] Optionally, a depth of the second spacer top surface below the initial control gate structure top surface ranges from 500 Å to 1000 Å.

[0019] Optionally, the material of the second sidewall includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride; the material of the first dielectric layer includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride; the material of the second dielectric layer includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0020] Optionally, the material of the first dielectric layer is the same as the material of the second dielectric layer.

[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0022] In a method for forming a flash memory structure provided by the technical solution of the present invention, an initial second sidewall spacer is located between a first dielectric layer and a second dielectric layer. During etching of the initial second sidewall spacer to form the second sidewall spacer, an etching process is selected that has a large etching selectivity ratio between the initial second sidewall spacer and the first dielectric layer, and a large etching selectivity ratio between the initial second sidewall spacer and the second dielectric layer. By controlling etching process parameters (such as time), the top surface of the initial second sidewall spacer can be made lower than the top of the initial control gate structure while reducing etching damage to the initial second sidewall spacer of the initial control gate sidewall due to the protective effect of the second dielectric layer. During the planarization process of forming the erase gate structure, the top surface of the initial control gate structure is exposed. Since the top surface of the second sidewall spacer is lower than the top surface of the initial control gate structure, the top surface of the second sidewall spacer will not be exposed. Therefore, in the subsequent etching process, the situation where the etching of the second sidewall spacer affects the device performance can be avoided, thereby improving the process window and the stability of the device performance.

[0023] Furthermore, after forming the floating gate opening and before forming the erase gate structure, the second dielectric layer is removed. Since the initial second sidewall spacer under the second dielectric layer is also laterally etched during the etching of the initial second sidewall spacer, after removing the second dielectric layer, the portion of the floating gate extending deep into the erase gate structure in the formed storage structure is increased. The wrapping structure between the floating gate and the erase gate structure is conducive to the tunneling of electrons in the floating gate into the erase gate, thereby improving the erasure efficiency of the formed flash memory structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figures 1 to 4 It is a structural diagram of the formation process of a flash memory structure;

[0025] Figures 5 to 14 It is a structural schematic diagram of each step of the method for forming a flash memory structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0027] As described in the background art, the performance of the NOR-type flash memory structure formed using existing technology needs to be further improved. The following describes the formation process of a flash memory structure.

[0028] Figures 1 to 4 The present invention is a structural diagram of the formation process of a flash memory structure.

[0029] Please refer to Figure 1, providing a substrate 100; forming a floating gate oxide material layer 101 on the surface of the substrate 100, a floating gate material layer 102 on the surface of the floating gate oxide material layer 101, two initial control gate structures separated from each other on the surface of the floating gate material layer 102, and an initial opening 107 between the two initial control gate structures, each initial control gate structure including an initial gate dielectric layer 103, an initial control gate 104 located on the initial gate dielectric layer 103, a sacrificial layer 105 and a first sidewall 106 located on the initial control gate 104, the first sidewall 106 also being located on the sidewall of the sacrificial layer 105, and the initial opening 107 exposing the first sidewall 106; forming a protective material layer 108 on the surfaces of the two initial control gate structures and a second sidewall material layer 109 located on the surface of the protective material layer 108.

[0030] Please refer to Figure 2 , the protective material layer 108 and the second sidewall material layer 109 are etched back until the surface of the floating gate material layer 102 is exposed, and a protective layer 110 is formed with the protective material layer 108, and a second sidewall 111 is formed with the second sidewall material layer 109; after the second sidewall 111 is formed, the floating gate material layer 102 and the floating gate oxide material layer 101 are etched until the surface of the substrate 100 is exposed, and a transition floating gate layer 112 is formed with the floating gate material layer 102, a transition floating gate oxide layer 113 is formed with the floating gate oxide material layer 101, and an opening 114 is formed with the initial opening 107.

[0031] Please refer to Figure 3 , forming an erase gate dielectric material layer (not shown in the figure) and an erase gate material layer (not shown in the figure) located on the erase gate dielectric material layer within the opening 114 and on the surface of the initial control gate structure; planarizing the erase gate material layer and the erase gate dielectric material layer until the top surface of the initial control gate structure is exposed, and forming an erase gate 115 with the erase gate material layer and the erase gate dielectric material layer.

[0032] Please refer to Figure 4 After forming the erase gate 115, the sacrificial layer 105 is removed; after removing the sacrificial layer 105, the initial control gate 104, the initial gate dielectric layer 103, the transition floating gate layer 112, and the transition floating gate oxide layer 113 are etched using the first sidewall 106 as a mask to form a control gate 116 from the initial control gate 104, a gate dielectric layer 117 from the initial gate dielectric layer 103, a floating gate layer 118 from the transition floating gate layer 112, and a floating gate oxide layer 119 from the transition floating gate oxide layer 113.

[0033] The above method is used to form a NOR-type flash memory structure. The second sidewall spacer 111 is used to isolate the erase gate 115 from the control gate 116. The sacrificial layer 105 and the second sidewall spacer 111 are both made of silicon nitride. The second sidewall spacer 111 is formed by etching back the second sidewall material layer 109, and the etching back process is a dry etching process.

[0034] There are two situations in the formation process of the second sidewall spacer 111. In one situation, the amount of etching back of the second sidewall spacer material layer 109 is small: after the erase gate material layer is planarized, the top surface of the second sidewall spacer 111 is exposed (such as Figure 3 As shown), the process of removing the sacrificial layer 105 is etched by a phosphoric acid solution. Since the top surface of the second sidewall 111 is exposed and the material is the same as the sacrificial layer 105, it is easy to cause the second sidewall 111 to be etched at the same time to form a groove A (as shown). Figure 4 As shown), it may even cause the etching solution to enter the flash memory structure along the groove A, affecting the device performance and even causing the device to fail. In another case, the amount of back etching of the second sidewall material layer 109 is relatively large: due to the presence of a corner B on the initial control gate 104, the second sidewall material layer 109 on the surface of the corner B tends to protrude relative to other positions. In the case of over-etching, it is easy to cause the formed second sidewall 111 to be disconnected from this point, thereby generating leakage and even causing the performance failure of the formed flash memory device. In short, the formation process window of the second sidewall 111 is relatively small, which is not conducive to the stability of device performance.

[0035] To solve the above-mentioned problem, the present invention provides a method for forming a flash memory structure, wherein an initial second sidewall spacer is located between a first dielectric layer and a second dielectric layer. During etching of the initial second sidewall spacer to form the second sidewall spacer, an etching process is selected that has a large etching selectivity ratio between the initial second sidewall spacer and the first dielectric layer, and a large etching selectivity ratio between the initial second sidewall spacer and the second dielectric layer. By controlling etching process parameters (such as time), etching damage to the initial second sidewall spacer on the initial control gate sidewall can be reduced while making the top surface of the initial second sidewall spacer lower than the top of the initial control gate structure. During the planarization process of forming the erase gate structure, the top surface of the initial control gate structure is exposed. Since the top surface of the second sidewall spacer is lower than the top surface of the initial control gate structure, the top surface of the second sidewall spacer will not be exposed. Therefore, in the subsequent etching process, the situation where the etching of the second sidewall spacer affects the device performance can be avoided, thereby improving the process window and the stability of the device performance.

[0036] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 5 to 14 It is a structural schematic diagram of each step of the method for forming a flash memory structure in an embodiment of the present invention.

[0038] Please refer to Figure 5 , providing a substrate 200.

[0039] In this embodiment, the material of the substrate 200 includes silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0040] Subsequently, a floating gate material layer and two initial control gate structures separated from each other are formed on the surface of the floating gate material layer. Each initial control gate structure includes an initial control gate, a sacrificial layer located on the initial control gate, and a first side wall. There is a control gate opening between the initial control gates, and there is a sacrificial opening between the sacrificial layers that exposes the control gate opening. The first side wall is located on the side wall of the sacrificial opening.

[0041] The method for forming the floating gate material layer and the two initial control gate structures can be found in Figures 6 and 7 .

[0042] Please refer to Figure 6 , forming a floating gate material layer 202 on the surface of the substrate 200; forming a control gate material layer 204 on the floating gate material layer 202; forming a sacrificial material layer (not shown in the figure) on a portion of the control gate material layer 204; etching the sacrificial material layer to form the sacrificial layer 205 and the sacrificial opening 207; and forming the first sidewall 206 on the sidewall of the sacrificial opening 207.

[0043] In this embodiment, before forming the floating gate material layer 202, a floating gate oxide material layer 201 is formed on the surface of the substrate 200. The floating gate oxide material layer 201 is used to form a floating gate oxide layer.

[0044] In this embodiment, before forming the control gate material layer 204, a control gate dielectric material layer 203 is formed on the floating gate material layer 202. The control gate dielectric material layer 203 is used to form a control gate dielectric layer.

[0045] In this embodiment, the control gate dielectric material layer 203 includes a first gate dielectric material layer (not shown in the figure), a second gate dielectric material layer (not shown in the figure) located on the first gate dielectric material layer, and a third gate dielectric material layer (not shown in the figure) located on the second gate dielectric material layer. Specifically, the first gate dielectric material layer is made of silicon oxide; the second gate dielectric material layer is made of silicon nitride; and the third gate dielectric material layer is made of silicon oxide.

[0046] Please refer to Figure 7 After forming the first sidewall spacer 206 , the control gate material layer 204 exposed at the bottom of the sacrificial opening 207 is etched to form the two initial control gates 208 .

[0047] Each initial control gate structure includes an initial control gate 208 , a sacrificial layer 205 and a first spacer 206 located on the initial control gate 208 , and a control gate opening 209 is defined between the initial control gates 208 .

[0048] In this embodiment, the control gate opening 209 is also located in the control gate dielectric material layer 203 .

[0049] Subsequently, a first dielectric layer, an initial second sidewall spacer located on the sidewall of the first dielectric layer, and a second dielectric layer located on the sidewall of the initial second sidewall spacer are formed on the sidewall of the initial control gate structure exposed by the control gate opening 209 and the sacrificial opening 207. The material of the initial second sidewall spacer is different from that of the first dielectric layer and the second dielectric layer.

[0050] In this embodiment, the formation method of the first dielectric layer, the initial second sidewall spacer and the second dielectric layer can be found in Figures 8 and 9 .

[0051] Please refer to Figure 8 A first dielectric material layer 210, a second spacer material layer 211 located on the surface of the first dielectric material layer 210, and a second dielectric material layer 212 located on the surface of the second spacer material layer 211 are formed on the surface of the floating gate material layer 202 and the surfaces of the two initial control gate structures.

[0052] The first dielectric material layer 210 is used to form a first dielectric layer; the second spacer material layer 211 is used to form an initial second spacer and further form a second spacer; and the second dielectric material layer 212 is used to form a second dielectric layer.

[0053] The material of the first dielectric material layer 210 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride; the material of the second sidewall material layer 211 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride; the material of the second dielectric material layer 212 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0054] The material of the second spacer material layer 211 is different from the material of the first dielectric material layer 210 and the second dielectric material layer 212 .

[0055] In this embodiment, the material of the second spacer material layer 211 is silicon nitride; the materials of the first dielectric material layer 210 and the second dielectric material layer 212 are both silicon oxide.

[0056] The first dielectric material layer 210 plays a role in protecting the floating gate material layer 202 and the initial control gate 208 when etching the second spacer material layer 211 .

[0057] Please refer to Figure 9 , the first dielectric material layer 210, the second spacer material layer 211 and the second dielectric material layer 212 are etched back until the surface of the floating gate material layer 202 is exposed, and the first dielectric layer 213 is formed by the first dielectric material layer 210, the initial second spacer 214 is formed by the second spacer material layer 211, and the second dielectric layer 215 is formed by the second dielectric material layer 212.

[0058] The process of etching back the first dielectric material layer 210 , the second spacer material layer 211 and the second dielectric material layer 212 includes a dry etching process.

[0059] Controlling the etching back process time of the second spacer material layer 211 to prevent over-etching can reduce etching damage to the initially formed second spacer 214, thereby improving the isolation capability of the subsequently formed second spacer between the control gate and erase gate structures.

[0060] The second dielectric layer 215 is used as a mask to etch the floating gate material layer 202 to form a floating gate opening in the floating gate material layer 202 .

[0061] Please refer to Figure 10 , the initial second spacer 214 is etched until the top surface of the initial second spacer 214 is lower than the top surface of the initial control gate structure to form a second spacer 216 .

[0062] The sidewalls of the initial second sidewall spacer 214 have a second dielectric layer 215. During the process of etching the initial second sidewall spacer 214 to form the second sidewall spacer 216, an etching process with a large etching selectivity ratio between the initial second sidewall spacer 214 and the second dielectric layer 215 is selected, and etching process parameters (such as time) are controlled. This can reduce etching damage to the initial control gate structure and the sidewalls of the initial control gate structure caused by the initial second sidewall spacer 214 due to the protective effect of the second dielectric layer.

[0063] In addition, during the etching process of the initial second sidewall 214, the initial second sidewall 214 under the second dielectric layer 215 is also laterally etched (as shown in the dotted line area A), which is beneficial for forming a structure in which the floating gate is wrapped by the erase gate structure after the second dielectric layer 215 is removed.

[0064] The process of etching the initial second spacer 214 includes a wet etching process.

[0065] The process parameters of the wet etching process include: the etching solution includes a phosphoric acid solution, the etching temperature ranges from 120° C. to 180° C., and the etching solution concentration ranges from 80% to 90%.

[0066] The depth of the top surface of the second spacer 216 below the top surface of the initial control gate structure is in a range of 500 Å to 1000 Å.

[0067] The material of the second sidewall spacer 216 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the second sidewall spacer 216 is silicon nitride.

[0068] Please refer to Figure 11 After forming the second sidewall spacer 216 , the floating gate material layer 202 is etched until the substrate 200 is exposed to form transition floating gates 217 , with floating gate openings 218 between the transition floating gates 217 .

[0069] In this embodiment, the floating gate opening 218 is also located in the floating gate oxide material layer 201 .

[0070] Subsequently, an erase gate structure is formed in the control gate opening 209 , the sacrificial opening 207 , and the floating gate opening 218 .

[0071] In this embodiment, after forming the floating gate opening 218 and before forming the erase gate structure, please refer to Figure 12 .

[0072] Please refer to Figure 12 After forming the floating gate opening 218 and before forming the erase gate structure, the second dielectric layer 215 is removed.

[0073] The process of removing the second dielectric layer 215 includes a wet etching process.

[0074] In this embodiment, the first dielectric layer 213 and the second dielectric layer 215 are made of the same material, silicon oxide. After removing the second dielectric layer 215, the first dielectric layer 213 beneath the second sidewall spacer 216 is also laterally etched to expose the top corner of the transition floating gate 217 (as indicated by the dotted line A). This allows the portion of the floating gate extending deeper into the erase gate structure to be increased in the subsequently formed erase gate structure. The wrapping structure between the floating gate and the erase gate structure facilitates tunneling of electrons from the floating gate into the erase gate, thereby improving the erase efficiency of the resulting flash memory structure.

[0075] Please refer to Figure 13 An erase gate structure is formed in the control gate opening 209 , the sacrificial opening 207 and the floating gate opening 218 .

[0076] In this embodiment, the erase gate structure includes an erase gate layer 219 .

[0077] In this embodiment, the top of the erase gate structure located between the transition floating gates 217 has a first size, and the bottom of the erase gate structure located between the control gate structures has a second size, where the first size is smaller than the second size. Specifically, this allows a larger portion of the subsequently formed floating gate to extend deeper into the erase gate structure. The wrapping structure between the floating gate and erase gate structures facilitates tunneling of electrons in the floating gate into the erase gate, thereby improving the erase efficiency of the resulting flash memory structure.

[0078] The method for forming the erase gate structure includes: forming an erase gate material layer (not shown in the figure) within the control gate opening 209, the sacrificial opening 207 and the floating gate opening 218, and on the surface of the initial control gate structure; flattening the erase gate material layer until the top surface of the initial control gate structure is exposed, and forming the erase gate layer 219 with the erase gate material layer.

[0079] During the planarization process of forming the erase gate structure, the top surface of the initial control gate structure is exposed. Since the top surface of the second sidewall 216 is lower than the top surface of the initial control gate structure, the top surface of the second sidewall 216 will not be exposed. Therefore, in the subsequent etching process, the situation where the device performance is affected by etching the second sidewall 216 can be avoided, thereby improving the process window and the stability of the device performance.

[0080] The erase gate structure further includes an erase gate dielectric layer 220 , and the erase gate layer 219 is located on a surface of the erase gate dielectric layer 220 .

[0081] Please refer to Figure 14 After forming the erase gate structure, the sacrificial layer 205 is also removed; after removing the sacrificial layer 205, the initial control gate 208 and the transition floating gate 217 are etched using the first sidewall 206 as a mask until the surface of the substrate 200 is exposed, thereby forming two separate storage gate structures on the substrate 200, each storage gate structure including a floating gate 221 and a control gate structure located on the floating gate 221, the control gate structure including a control gate 222 and the first sidewall 206, the floating gate 221 is formed using the transition floating gate 217, and the control gate 222 is formed using the initial control gate 208.

[0082] In the etching process for removing the sacrificial layer 205, since the top surface of the second side wall 216 is lower than the top surface of the initial control gate structure, the top surface of the second side wall 216 will not be exposed, which can avoid affecting the device performance by etching the second side wall 216, thereby improving the process window and the stability of the device performance.

[0083] The control gate structure further includes a floating gate oxide layer 223 located between the floating gate 221 and the substrate 200. Specifically, the floating gate oxide material layer 201 is etched to form the floating gate oxide layer 223.

[0084] In this embodiment, the control gate structure further includes a control gate dielectric layer 224 located between the floating gate 221 and the control gate 222. Specifically, the control gate dielectric material layer 203 is etched to form the transition control gate dielectric layer 224.

[0085] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a flash memory structure, characterized in that: include: providing a substrate; forming a floating gate material layer on the surface of the substrate and two initial control gate structures separated from each other on the surface of the floating gate material layer, each initial control gate structure comprising an initial control gate, a sacrificial layer on the initial control gate, and a first sidewall spacer, a control gate opening being defined between the initial control gates, a sacrificial opening exposing the control gate opening being defined between the sacrificial layers, and the first sidewall spacer being located on a sidewall of the sacrificial opening; forming a first dielectric material layer, a second spacer material layer located on the surface of the first dielectric material layer, and a second dielectric material layer located on the surface of the second spacer material layer on the surface of the floating gate material layer and the surfaces of the two initial control gate structures; The first dielectric material layer, the second spacer material layer, and the second dielectric material layer are etched back until the surface of the floating gate material layer is exposed, and a first dielectric layer, an initial second spacer located on the sidewall of the first dielectric layer, and a second dielectric layer located on the sidewall of the initial second spacer are formed on the sidewall of the initial control gate structure exposed by the control gate opening and the sacrificial opening, wherein the material of the initial second spacer is different from that of the first dielectric layer and the second dielectric layer, the first dielectric layer is formed by the first dielectric material layer, the initial second spacer is formed by the second spacer material layer, and the second dielectric layer is formed by the second dielectric material layer; Etching the initial second spacer until the top surface of the initial second spacer is lower than the top surface of the initial control gate structure, and the initial second spacer under the second dielectric layer is also laterally etched to form a second spacer; After forming the second sidewall spacer, etching the floating gate material layer until the substrate is exposed to form transition floating gates, with floating gate openings between the transition floating gates; An erase gate structure is formed in the control gate opening, the sacrificial opening, and the floating gate opening.

2. The method for forming a flash memory structure according to claim 1, wherein: The process of etching back the first dielectric material layer, the second spacer material layer and the second dielectric material layer includes a dry etching process.

3. The method for forming a flash memory structure according to claim 1, wherein: The process of etching the initial second sidewall spacer includes a wet etching process.

4. The method for forming a flash memory structure according to claim 3, wherein: The process parameters of the wet etching process include: the etching solution includes a phosphoric acid solution, the etching temperature ranges from 120° C. to 180° C., and the etching solution concentration ranges from 80% to 90%.

5. The method for forming a flash memory structure according to claim 1, wherein: After forming the floating gate opening and before forming the erase gate structure, the second dielectric layer is removed.

6. The method for forming a flash memory structure according to claim 1, wherein: After forming the erase gate structure, the method further includes: removing the sacrificial layer; after removing the sacrificial layer, etching the initial control gate and the transition floating gate using the first sidewall as a mask until the substrate surface is exposed, thereby forming two separate storage gate structures on the substrate, each storage gate structure including a floating gate and a control gate structure located on the floating gate, the control gate structure including a control gate and the first sidewall, forming the floating gate with the transition floating gate, and forming the control gate with the initial control gate.

7. The method for forming a flash memory structure according to claim 6, wherein: The control gate structure also includes a floating gate oxide layer located between the floating gate and the substrate; the method for forming the floating gate oxide layer includes: forming a floating gate oxide material layer on the surface of the substrate before forming the floating gate material layer; and etching the floating gate oxide material layer to form the floating gate oxide layer.

8. The method for forming a flash memory structure according to claim 6, wherein: The method for forming the two initial control gate structures includes: forming a control gate material layer on the floating gate material layer; forming a sacrificial material layer on a portion of the control gate material layer; etching the sacrificial material layer to form the sacrificial layer and the sacrificial opening; forming the first sidewall on the sidewall of the sacrificial opening; after forming the first sidewall, etching the control gate material layer exposed at the bottom of the sacrificial opening to form two initial control gates.

9. The method for forming a flash memory structure according to claim 8, wherein: The control gate structure also includes a control gate dielectric layer located between the floating gate and the control gate; the method for forming the control gate dielectric layer includes: before forming the control gate material layer, forming a control gate dielectric material layer on the floating gate material layer; the control gate dielectric material layer is etched to form the control gate dielectric layer.

10. The method for forming a flash memory structure according to claim 1, wherein: The erase gate structure includes an erase gate layer; The method for forming the erase gate structure includes: forming an erase gate material layer within the control gate opening, the sacrificial opening and the floating gate opening, and on the surface of the initial control gate structure; flattening the erase gate material layer until the top surface of the initial control gate structure is exposed, and forming the erase gate layer with the erase gate material layer.

11. The method for forming a flash memory structure according to claim 10, wherein: The erase gate structure further includes an erase gate dielectric layer, and the erase gate layer is located on a surface of the erase gate dielectric layer.

12. The method for forming a flash memory structure according to claim 1, wherein: The depth of the top surface of the second spacer below the top surface of the initial control gate structure is in a range of 500 Å to 1000 Å.

13. The method for forming a flash memory structure according to claim 1, wherein: The material of the second sidewall spacer includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride; The material of the first dielectric layer includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride; The material of the second dielectric layer includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

14. The method for forming a flash memory structure according to claim 13, wherein: The material of the first dielectric layer is the same as that of the second dielectric layer.

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