Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display, and comprises a display area, a first non-display area and a second non-display area, the first non-display area and the second non-display area are arranged along a first direction, and the display area at least partially surrounds the first non-display area and the second non-display area; the display area comprises a plurality of first signal lines extending along the first direction, at least part of the first signal lines comprises a first line segment and at least one second line segment, the first line segment is located between the first non-display area and the second non-display area, the second line segment is located on a side of the first non-display area away from the second non-display area along the first direction, and / or the second line segment is located on a side of the second non-display area away from the first non-display area along the first direction; in the same first signal line, the first line segment and the second line segment are electrically connected through a first cross-line. In this way, the first non-display area and the second non-display area can be used to reduce the width of the corresponding frame, and the screen-to-body ratio can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, more particularly, to a display panel and a display device. BACKGROUND

[0002] From the CRT (Cathode Ray Tube) era to the LCD (Liquid Crystal Display) era, to the OLED (Organic Light-Emitting Diode) era and the LED (Light Emitting Diode) display era, the display industry has undergone decades of development and has become increasingly sophisticated. The display industry has become closely related to our lives, from traditional mobile phones, tablets, televisions and PCs, to current smart wearable devices, VR, vehicle displays and other electronic devices, all of which cannot do without display technology.

[0003] In order to meet the light sensing needs of display products such as photographing, a through hole is usually introduced in the display product to place a camera and other light sensing elements. However, the introduction of the through hole will disconnect the wires originally arranged in the display product, and the connection of the disconnected wires is usually achieved by winding around the through hole in the prior art. This method increases the width of the non-display area around the hole, which is not conducive to the design of narrow frame around the hole, resulting in a decrease in the screen ratio of the display product. SUMMARY

[0004] Therefore, the present application provides a display panel and a display device, aiming to achieve narrow frame design around the hole in the product and improve the screen ratio of the display product.

[0005] In a first aspect, the present application provides a display panel, comprising a display area and at least two non-display areas, the non-display areas comprising at least a first non-display area and a second non-display area arranged adjacently, the first non-display area and the second non-display area being arranged along a first direction, and the display area at least partially surrounding the non-display areas.

[0006] The display area comprises a plurality of first signal lines extending along the first direction, at least part of the first signal lines comprising a first line segment and at least one second line segment, the first line segment being located between two adjacent non-display areas, at least part of the second line segment being located on a side of the first non-display area away from the second non-display area along the first direction, and / or at least part of the second line segment being located on a side of the second non-display area away from the first non-display area along the first direction; the first line segment and the second line segment in the same first signal line are electrically connected by a first cross-line.

[0007] In a second aspect, the present application provides a display device comprising the display panel provided in the first aspect of the present application.

[0008] Compared with the related art, the display panel and the display device provided by the present application at least achieve the following beneficial effects:

[0009] The display panel and the display device provided by the embodiment of the present application are provided with at least two non-display areas, and the display area at least partially surrounds the aforementioned non-display areas. The non-display area at least includes a first non-display area and a second non-display area arranged along a first direction. The display area includes a plurality of first signal lines extending along the first direction. Along the first direction, part of the first signal lines overlap with the first non-display area and the second non-display area. This part of the first signal lines includes a first line segment and at least one second line segment. The first line segment is located between the adjacent two non-display areas. At least part of the second line segment is located on the side of the first non-display area away from the second non-display area, and / or at least part of the second line segment is located on the side of the second non-display area away from the first non-display area. In order to realize the electrical connection of the first line segment and the second line segment in the first signal line, the present application introduces a first cross line in the display panel. The first cross line is arranged in a different layer from the first line segment and the second line segment in the first signal line. When the first line segment and the second line segment are connected through the first cross line, there is no need to wind the line in the frame area of the first non-display area or the second non-display area, which can reduce the number of lines corresponding to the frame area of the first non-display area and the second non-display area, provide compression space for the frame of the first non-display area and the second non-display area, and thus be beneficial to realize the narrow frame design of the hole circumference corresponding to the first non-display area and the second non-display area, and be beneficial to improve the screen-to-body ratio of the display panel and the display device.

[0010] Of course, any product implementing the present application does not necessarily need to achieve all the technical effects described above.

[0011] Other features of the present application and its advantages will become apparent from the following detailed description of exemplary embodiments thereof, with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0013] Figure 1 Fig. 1 shows a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0014] Figure 2 Fig. 2 shows another structural schematic diagram of a display panel provided by an embodiment of the present application;

[0015] Figure 3 Fig. 3 shows a wiring schematic diagram of the first signal line arranged around the first non-display area and the second non-display area;

[0016] Figure 4 The diagram shown is another structural schematic of the display panel provided in an embodiment of the present invention;

[0017] Figure 5 The diagram shown is a schematic diagram of the connection between the pixel driving circuit and the light-emitting element in a display panel provided in an embodiment of the present invention;

[0018] Figure 6 The diagram shown is another structural schematic of the display panel provided in an embodiment of the present invention;

[0019] Figure 7 The diagram shows a connection diagram of a shift register and a control line corresponding to a control line in a pixel driving circuit.

[0020] Figure 8 The diagram shows a possible connection of the fourth control line corresponding to the positions of the first and second non-display areas.

[0021] Figure 9 The diagram shown illustrates a correspondence between control lines and pixel rows in a display panel provided by an embodiment of the present invention.

[0022] Figure 10 The image shown is a schematic diagram of a film layer of a display panel provided in an embodiment of the present invention;

[0023] Figure 11 The diagram shown is a layout diagram between the first non-display area and the second non-display area in a display panel provided by an embodiment of the present invention;

[0024] Figure 12 As shown Figure 11 A magnified view of a portion of region A1 in the middle;

[0025] Figure 13 As shown Figure 12 A magnified view of a portion of region A2 in the middle;

[0026] Figure 14 The diagram shows another connection diagram of the fourth control line corresponding to the positions of the first and second non-display areas;

[0027] Figure 15 The diagram shows another connection diagram of the fourth control line corresponding to the positions of the first and second non-display areas;

[0028] Figure 16 The diagram shown is another structural schematic of the display panel provided in an embodiment of the present invention;

[0029] Figure 17 The diagram shows a wiring schematic of a first signal line and a second signal line disposed around a first non-display area and a second non-display area;

[0030] Figure 18 Fig. 2 shows a panel layout corresponding to region A3 in Fig. 1 ; Figure 17

[0031] Figure 19 Fig. 3 shows a panel layout corresponding to region A4 in Fig. 1 ; Figure 17

[0032] Figure 20 Fig. 4 shows a panel layout corresponding to region A5 in Fig. 1 ; Figure 17

[0033] Figure 21 Fig. 5 shows another layout of the first and second signal lines arranged around the first and second non-display areas;

[0034] Figure 22 Fig. 6 shows a schematic diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0035] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of the components and steps, numerical expressions, and numerical values set forth in these embodiments are not limiting to the scope of the present application unless otherwise specifically stated.

[0036] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way limiting to the scope of the application and its applications or uses.

[0037] Techniques, methods, and apparatus known to those of ordinary skill in the relevant art can not be discussed in detail herein. However, where appropriate, such techniques, methods, and apparatus should be considered as falling within the scope of the disclosure.

[0038] In all of the examples shown and discussed herein, any specific values should be interpreted as merely illustrative and not as a limitation. Thus, other examples of the exemplary embodiments can have different values.

[0039] Various modifications and changes can be made to the present application in light of the above disclosure without departing from the spirit or scope of the present application. Accordingly, the present application is not limited to the above examples, but intended to cover all modifications and equivalents falling within the scope of the claims (the technical solutions claimed in the application) and their equivalents. It should be noted that the embodiments provided by the present application can be combined with each other without contradiction.

[0040] It should be noted that like numbers and letters refer to like items throughout the drawings, and that, once an item is defined in one drawing, it need not be discussed further in subsequent drawings. It should be noted that like numbers and letters refer to like items throughout the drawings, and that, once an item is defined in one drawing, it need not be discussed further in subsequent drawings.​​

[0041] In the related art, when a through hole for placing a photosensitive element such as a camera is introduced in a display panel, signal lines originally arranged at the position of the through hole need to be routed around the through hole. When the number of the signal lines routed is large, the width of the frame around the hole is large, which is not conducive to realizing narrow frame design around the hole, and reduces the screen ratio of the display product.

[0042] To this end, the display panel provided by the present application includes a display area and at least two non-display areas, the non-display areas at least including first and second non-display areas arranged adjacent to each other, the first and second non-display areas arranged along a first direction, and the display area at least partially surrounding the non-display areas; the display area includes a plurality of first signal lines extending along the first direction, at least part of the first signal lines including first line segments and at least one second line segment, the first line segments being located between the adjacent two non-display areas, and at least part of the second line segments being located on a side of the first non-display area away from the second non-display area along the first direction, and / or at least part of the second line segments being located on a side of the second non-display area away from the first non-display area along the first direction; the first line segments and the second line segments in the same first signal line are electrically connected through a first cross-line. The electrical connection of the first line segments and the second line segments in the first signal line is realized by introducing the first cross-line, which is conducive to avoiding routing around the first and second non-display areas, thereby providing a space for the compression of the frame area corresponding to the first and second non-display areas, and facilitating the narrowing of the frame corresponding to the first and second non-display areas, and improving the screen ratio of the display panel and the display device.

[0043] The above is the core idea of the present application, and the technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the embodiments of the present application.

[0044] Figure 1 Fig. 1 shows a structural schematic diagram of a display panel provided by an embodiment of the present application, Figure 2 Fig. 2 shows another structural schematic diagram of a display panel provided by an embodiment of the present application, Figure 3 Fig. 3 shows a wiring schematic diagram of the first signal line L1 arranged around the first non-display area NA1 and the second non-display area NA2, wherein, Figure 1 Fig. 4 shows a scheme in which the display area fully surrounds the first non-display area NA1 and the second non-display area NA2, Figure 2 Fig. 5 shows a scheme in which the display area AA semi-surrounds the first display area NA1 and the second display area NA2.

[0045] Please refer to Figures 1 to 3The display panel 100 provided by the embodiment of the present application comprises a display area AA and at least two non-display areas NA, the non-display areas NA at least comprise a first non-display area NA1 and a second non-display area NA2 arranged adjacently, the first non-display area NA1 and the second non-display area NA2 are arranged along a first direction D1, and the display area AA at least partially surrounds the first non-display area NA1 and the second non-display area NA2.

[0046] The display area AA comprises a plurality of first signal lines L1 extending along the first direction D1, at least part of the first signal lines L1 comprises a first line segment L11 and at least one second line segment L12, the first line segment L11 is located between two adjacent non-display areas AA, and at least part of the second line segment L12 is located on a side of the first non-display area NA1 away from the second non-display area NA2 along the first direction D1, and / or at least part of the second line segment L12 is located on a side of the second non-display area NA2 away from the first non-display area NA1 along the first direction D1; in the same first signal line L1, the first line segment L11 and the second line segment L12 are electrically connected through a first cross-line 10, and in an embodiment, the first cross-line 10 is arranged in a layer different from the first signal line L1.

[0047] Optionally, when the display panel provided by the embodiment of the present application is applied to a display device, the first non-display area NA1 and the second non-display area NA2 comprise an optical device area for placing an optical device such as a camera. In a picture shooting stage, the optical device area is used for transmitting light.

[0048] Specifically, please refer to the following description Figures 1 to 3 In the display panel provided by the embodiment of the present application, at least two non-display areas NA are arranged, and the display area AA at least partially surrounds the non-display area AA. Among them, the non-display area AA at least comprises a first non-display area NA1 and a second non-display area NA2 arranged along a first direction D1. The display area AA comprises a plurality of first signal lines L1 extending along the first direction D1, and part of the first signal lines L1 overlaps with the first non-display area NA1 and the second non-display area NA2 along the first direction D1, this part of the first signal lines L1 comprises a first line segment L11 and at least one second line segment L12, wherein the first line segment L11 is located between two adjacent non-display areas AA, and at least part of the second line segment L12 is located on a side of the first non-display area NA1 away from the second non-display area NA2, and / or at least part of the second line segment L12 is located on a side of the second non-display area NA2 away from the first non-display area NA1. Figures 1 to 3With the scheme that the display panel only includes the first non-display area NA1 and the second non-display area NA2, the second line segment L12 is arranged on the side of the first non-display area NA1 away from the second non-display area NA2 and on the side of the second non-display area NA2 away from the first non-display area NA1. To realize the electrical connection of the first line segment L11 and the second line segment L12 in the first signal line L1, the application introduces the first cross line 10 in the display panel. In one embodiment, the first cross line 10 is arranged in a different layer from the first line segment L11 and the second line segment L12 in the first signal line L1. When the first line segment L11 and the second line segment L12 are connected through the first cross line 10, there is no need to perform wire winding in the frame area of the first non-display area NA1 or the second non-display area NA2, the number of wires corresponding to the frame area of the first non-display area NA1 and the second non-display area NA2 can be reduced, the compression space of the frame of the first non-display area NA1 and the second non-display area NA2 is provided, and thus the narrow frame design of the hole corresponding to the first non-display area NA1 and the second non-display area NA2 is facilitated, and the screen-to-body ratio of the display panel and the display device is improved.

[0049] It should be noted that the Figure 1 and Figure 2 are only exemplary drawings of the structure of the display panel, and in actual implementation, the structure of the display panel includes but is not limited to the above, and can also include other structures, such as the film layer structure, the pixel circuit, the driving circuit and the like of the display panel, which are not described herein in detail, and can be understood by referring to the structure of the display panel in the related art. Moreover, Figure 1 and Figure 2 The embodiment is described by taking the display panel in a rectangular shape as an example, and in some other embodiments of the application, the shape of the display panel can also be other shapes, such as a rounded rectangle, a circle, an ellipse or any other feasible shape. The number of the first signal lines L1 overlapping with the first display area AA and the second non-display area NA2 in the first direction D1 in the embodiment is also only illustrative and does not represent the actual number.

[0050] In addition, Figure 1 The embodiment is described by taking the display panel including two non-display areas AA as an example, and in some other embodiments of the application, the number of the non-display areas AA included in the display panel can also be three or more, for example, please refer to Figure 4 , Figure 4 Another structure of the display panel provided by the embodiment of the application is shown in FIG. 6. When the display panel includes three non-display areas NA (for example, the first non-display area NA1, the second non-display area NA2 and the third non-display area NA3), the three non-display areas NA are arranged in the first direction D1, and the first line segment L11 is arranged between any two adjacent non-display areas NA.

[0051] Optionally, the display panel provided by the embodiment can be a display panel adopting an organic light-emitting diode display technology, i.e., an OLED (Organic Light-Emitting Diode) display panel. The basic structure of the light-emitting layer of the OLED display panel generally includes an anode, a light-emitting material layer, and a cathode. When a power supply supplies a proper voltage, the holes of the anode and the electrons of the cathode will combine in the light-emitting material layer to generate bright light. Compared with a thin-film field-effect transistor liquid crystal display, the OLED display device has the characteristics of high visuality and high brightness, and is more power-saving, light in weight, and thin in thickness. Of course, in some other embodiments of the application, the display panel can also be a display panel adopting an inorganic light-emitting diode display technology, for example, a Micro LED display panel, or a Mini LED display panel, etc.

[0052] Figure 5 Fig. 1 shows a connection diagram of a pixel driving circuit and a light-emitting element in a display panel provided by an embodiment of the application, Figure 6 Fig. 2 shows another structural diagram of a display panel provided by an embodiment of the application. Please refer to Figure 5 and Figure 6 In an optional embodiment of the application, the display panel includes a plurality of pixel driving circuits located in the display area AA and light-emitting elements electrically connected with the pixel driving circuits. The pixel driving circuits are electrically connected with a plurality of control lines X, and the first signal line L1 includes the control lines X.

[0053] The display panel 100 includes a first frame area B1 and a second frame area B2 opposite along a first direction D1. The first frame area B1 and the second frame area B2 both include a plurality of shift registers 30. At least part of the control lines X are electrically connected with the shift registers 30 located in the first frame area B1, and at least part of the control lines X are electrically connected with the shift registers 30 located in the second frame area B2. The first cross-line 10 corresponding to at least part of the control lines X is routed from the first non-display area NA1 and the second non-display area NA2 along a first side of a second direction D2, and the first cross-line 10 corresponding to at least part of the control lines X is routed from the first non-display area NA1 and the second non-display area NA2 along a second side of the second direction D2. The first side and the second side are opposite along the second direction D2, and the second direction D2 intersects the first direction D1.

[0054] It should be noted that, Figure 5 Only the structure of one pixel driving circuit electrically connected with the light-emitting element is shown, which is taken as an example of a pixel driving circuit with an 8T1C (8 transistors and 1 capacitor) structure for illustration, and the actual structure of the pixel driving circuit is not limited. In some other embodiments of the application, the pixel driving circuit can also be in a 7T1C structure, which is not limited in the application. Figure 5The pixel driving circuit in the illustrated embodiment includes one driving transistor M0 and eight switching transistors M0-M7. Except for the driving transistor M0, the rest are switching transistors. The gate of each switching transistor is electrically connected to a control line X, and the driving signal is provided to the switching transistor through the control line X to control the on or off of the switching transistor. Optionally, the control line X connected to the switching transistor is routed on the display panel in a manner of extending along the first direction D1. When the control line X overlaps the first non-display area NA1 and the second non-display area NA2 along the first direction D1, the control line X forms a first line segment L11 between the first non-display area NA1 and the second non-display area NA2 and a second line segment L12 on the side of the first non-display area NA1 or the second non-display area NA2 away from the first line segment L11. The first signal line L1 mentioned in the foregoing embodiment includes these control lines X, and the first line segment L11 and the second line segment L12 in the control line X are electrically connected through the first cross line 10, thereby avoiding the problem of excessive frame width of the first non-display area NA1 and the second non-display area NA2 caused by the wiring around the first non-display area NA1 and the second non-display area NA2 when there are more control lines X.

[0055] With reference to the foregoing Figure 5 Optionally, the control line X corresponding to the pixel driving circuit is connected to the shift register 30 located in the frame area of the display panel, and the control signal is provided to the control line X through the shift register 30 to control the on or off of the switching transistor in the driving circuit. Specifically, the non-display area AA of the display panel includes the first frame area B1 and the second frame area B2 oppositely arranged along the first direction D1, and the shift register 30 is arranged in the first frame area B1 and the second frame area B2. Among the plurality of control lines X corresponding to the same pixel driving circuit, part of the control lines X are electrically connected to the shift register 30 located in the first frame area B1, and part of the control lines X are electrically connected to the shift register 30 located in the second frame area B2. In this way, it is beneficial to avoid the problem of excessive single-side frame width of the display panel caused by the concentration of the shift register 30 in the same frame area of the display panel, thereby balancing the width of the first frame area B1 and the second frame area B2 and improving the overall aesthetics of the display panel.

[0056] In addition, please refer to Figure 3 , Figure 5 and Figure 6The first cross line 10 corresponding to the partial control line X is routed from the first non-display area NA1 and the second non-display area NA2 on the first side (for example, the upper side) of the second direction D2, and is routed from the first non-display area NA1 and the second display area AA on the second side (for example, the lower side) of the second direction D2. In this way, the space on the upper and lower sides of the first non-display area NA1 and the second non-display area NA2 along the second direction D2 is fully utilized, and the uniformity of the routing of the first cross line 10 around the first non-display area NA1 and the second non-display area NA2 is improved.

[0057] It should be noted that when the lengths of the first cross lines 10 on the same side of the first non-display area NA1 and the second non-display area NA2 are different, the loadings of the first signal lines L1 corresponding to the first cross lines 10 of different lengths may be different. In order to balance the impedance difference between the first signal lines L1, the cross-sectional areas of the first cross lines 10 of different lengths can be changed. For example, the cross-sectional area of the first cross line 10 of a longer length is set to be smaller than the cross-sectional area of the first cross line 10 of a shorter length; or at least part of the line segments of the first cross line 10 closer to the first non-display area NA1 and the second non-display area NA2 are set as broken lines or curves, and the line segments of the first cross line 10 farther from the first non-display area NA1 and the second non-display area NA2 are all set as straight lines, so that the lengths of the different first cross lines 10 are close or the same, which is also conducive to balancing the impedance difference between the different first signal lines L1.

[0058] Continuing to refer to Figure 3 In an optional embodiment of the present application, the number of first cross lines 10 routed from the first non-display area NA1 and the second non-display area NA2 on the first side of the second direction D2 is the same as the number of first cross lines 10 routed from the first non-display area NA1 and the second non-display area NA2 on the second side of the second direction D2.

[0059] It should be noted that the number of first cross lines 10 above and below the first non-display area NA1 and the second non-display area NA2 referred to in the embodiments of the present application means that the numbers are the same within an error tolerance range. For example, when the number of first cross lines 10 above and below the first non-display area NA1 and the second non-display area NA2 differs by 1, the condition of the present application is still met.

[0060] When the first cross-line 10 is used to realize the electrical connection between the first line segment L11 and the second line segment L12 in the first signal line L1, the first cross-line 10 is routed above or below the first non-display area NA1 and the second non-display area NA2 along the second direction D2, and the number of the first cross-line 10 located above and below the first non-display area NA1 and the second non-display area NA2 is substantially the same. In this way, the first cross-line 10 is arranged as evenly as possible on the upper and lower sides of the first non-display area NA1 and the second non-display area NA2. On the one hand, the peripheral space of the first non-display area NA1 and the second non-display area NA2 can be reasonably utilized. On the other hand, it is also beneficial to improve the screen mura phenomenon caused by the uneven distribution of the first cross-line 10 on the upper and lower sides of the first non-display area NA1 and the second non-display area NA2.

[0061] Please refer to Figures 4 to 7 , Figure 7 The figure shows a connection diagram of the shift register 30 corresponding to the control line X in the pixel driving circuit and the control line X. In an optional embodiment of the present application, the pixel driving circuit includes a data writing module 61, a compensation module 62, a first reset module 63, a second reset module 64, a light-emitting control module 65, and a voltage adjustment module 66. The control line X includes a first control line S1N connected to the control end of the first reset module 63, a second control line S2N connected to the control end of the compensation module 62, a third control line SP* connected to the control end of the second reset module 64 and the voltage adjustment module 66, a fourth control line SP connected to the control end of the data writing module 61, and a light-emitting control line EMIT connected to the light-emitting control module 65.

[0062] Two of the first control line S1N, the second control line S2N, the third control line SP*, and the light-emitting control line EMIT are connected to the shift register 30 in the first frame area B1, and the other two are connected to the shift register 30 in the second frame area B2.

[0063] Optionally, the gate of the driving transistor M0 is connected to the first node N1, the source is connected to the second node N2, and the drain is connected to the third node N3. The light emitting element is coupled to the third node N3 through the fourth node N4. The first reset module 63 is connected to the first node N1 and is configured to reset the first node N1. The second reset module 64 is connected to the fourth node N4 and is configured to reset the fourth node N4. The data writing module 61 and the voltage adjusting module 66 are connected to the second node N2. The voltage adjusting module 66 is configured to adjust the threshold voltage of the driving transistor M0. The compensation module 62 is connected between the second node N2 and the third node N3. Optionally, the first reset module 63, the second reset module 64, the data writing module 61, the compensation module 62, and the voltage adjusting module 66 each include one transistor, but the number of transistors actually included in each module is not limited. In some other embodiments of the present application, the number of transistors included in these modules can also be embodied as other. In the present embodiment, the control line X connected to the control end of the first reset module 63 and the second reset module 64 is the first control line S1N. The control line X connected to the control end of the compensation module 62 is the second control line S2N. The control line X connected to the control end of the voltage adjusting module 66 is the third control line SP*. The control line X connected to the control end of the data writing module 61 is the fourth control line SP. The control line X connected to the light emitting control module 65 is the light emitting control line EMIT. Optionally, the first control line S1N, the second control line S2N, the third control line SP*, and the light emitting control line EMIT are all single-side driven, that is, each of these control lines X is connected to only one shift register 30. Specifically, two of the first control line S1N, the second control line S2N, the third control line SP*, and the light emitting control line EMIT are connected to the shift register 30 in the first border area B1, and the other two are connected to the shift register 30 in the second border area B2. In this way, in the areas corresponding to the first non-display area NA1 and the second non-display area NA2, two of the above four control lines X are led out from the shift register 30 in the first border area B1, extend to the left side of the first non-display area NA1, are connected to the first line segment L11 between the first non-display area NA1 and the second non-display area NA2 through the first cross line 10, and then are connected to the second line segment L12 on the right side of the second non-display area NA2 through the first cross line 10. In this way, the second line segment L12 on the left side of the first non-display area NA1, the first line segment L11 between the first non-display area NA1 and the second non-display area NA2, and the second line segment L12 on the right side of the second non-display area NA2 in the first signal line L1 can all receive the signal transmitted by the same shift register 30, ensuring the normal display function of the sub-pixels connected to these line segments.Similarly, the other two of the four control lines X are led out from the shift register 30 in the second border area B2, extend to the right side of the second non-display area NA2, are connected to the first line segment L11 between the second non-display area NA2 and the first non-display area NA1 through the first cross line 10, and are then connected to the second line segment L12 on the right side of the first non-display area NA1 through the first cross line 10, so that the second line segment L12 on the right side of the second non-display area NA2, the first line segment L11 between the second non-display area NA2 and the first non-display area NA1, and the second line segment L12 on the left side of the first non-display area NA1 in the first signal line L1 can all receive signals transmitted by the same shift register 30, ensuring the normal display function of the sub-pixels connected to these line segments.

[0064] When the first control line S1N, the second control line S2N, the third control line SP*, and the light-emitting control line EMIT are all single-side driven, the shift registers 30 connected to these control lines X are uniformly distributed in the first border area B1 and the second border area B2, which is conducive to the rational use of the space of the first border area B1 and the second border area B2 and the consistency of the border width of the first border area B1 and the second border area B2.

[0065] Figure 8 The fourth control line SP is shown in a connection diagram corresponding to the positions of the first non-display area NA1 and the second non-display area NA2. It should be noted that Figure 8 Only the part of the fourth control line SP that is truncated by the first non-display area NA1 and the second non-display area NA2 is shown, and other control lines that are truncated by the first non-display area NA1 and the second non-display area NA2 are not shown.

[0066] Continuing to refer to Figures 4 to 7 and combining Figure 8 In an optional embodiment of the present application, at least part of the fourth control line SP connected to the first cross line 10 is connected to the shift register 30 in the first border area B1, and the remaining fourth control line SP connected to the first cross line 10 is connected to the shift register 30 in the second border area B2.

[0067] Specifically, the control line X connected to the control end of the data writing module 61 in the pixel driving circuit is the fourth control line SP. Optionally, when the fourth control line SP does not overlap with the first non-display area NA1 and the second non-display area NA2 along the first direction D1, this part of the fourth control line SP is double-side driven, that is, one end of the same fourth control line SP is electrically connected to the shift register 30 located in the first border area B1, and the other end is electrically connected to the shift register 30 located in the second border area B2, so as to improve the driving capability of the fourth control line SP on the pixel driving circuit connected thereto.

[0068] Please refer to Figure 8 When the fourth control line SP overlaps with the first non-display area NA1 and the second non-display area NA2 along the first direction D1, optionally, this part of the fourth control line SP adopts single-side driving, that is, in the first line segment L11 corresponding to the fourth control line SP, part of the first line segment L11 is only electrically connected with the second line segment L12 on the left side of the first non-display area NA1 through the first cross-line 10, and then is electrically connected with the shift register 30 in the first bezel area B1 through the second line segment L12, at this time, the shift register 30 in the first bezel area B1 is used to provide signals to the second line segment L12 and the first line segment L11; another part of the first line segment L11 is only electrically connected with the second line segment L12 on the right side of the second non-display area NA2 through the first cross-line 10, and then is electrically connected with the shift register 30 in the second bezel area B2 through the second line segment L12, at this time, the shift register 30 in the second bezel area B2 is used to provide signals to the second line segment L12 and the first line segment L11. In this way, the number of shift registers 30 in the first bezel area B1 and the second bezel area B2 will not be increased, the normal display of the sub-pixels at the positions corresponding to the first line segment L11 and the second line segment L12 is ensured, and the number of the first cross-lines 10 in the display panel is also reduced, thus the wiring complexity of the display panel is simplified.

[0069] Please refer to Figures 4 to 8 , and refer to Figure 9 , Figure 9 Fig. 1 shows a corresponding relationship diagram between a control line X and a pixel row 40 in a display panel provided by an embodiment of the present application. In an optional embodiment of the present application, the display panel includes a plurality of pixel rows 40, each of which includes a plurality of light emitting elements; at least one of a first control line S1N, a second control line S2N, a third control line SP* and a light emitting control line EMIT is electrically connected with a pixel driving circuit corresponding to a light emitting element in each of the N pixel rows 40, N≥2; and a fourth control line SP is electrically connected with a pixel driving circuit corresponding to a light emitting element in the same pixel row 40. It should be noted that Figure 9 For example, only the first control line S1N, the second control line S2N, the third control line SP* and the light emitting control line EMIT are electrically connected with the pixel driving circuits corresponding to the light emitting elements in two pixel rows 50, that is, one of the above control lines drives two pixel rows, in some other embodiments of the present application, one of the above control lines can also drive three or more than three pixel rows, which is not limited in the present application. Please refer to Figure 9The same shift register 30 is connected with the first reset module 63 in the pixel driving circuit of the two pixel rows 40, and the reset of the first node N1 of the pixel driving circuit in the two pixel rows 40 is realized through the control of the first control line S1N; the same shift register 30 is connected with the second reset module 64 in the pixel driving circuit of the two pixel rows 40, and the reset of the fourth node of the pixel driving circuit in the two pixel rows 40 is realized through the control of the first control line S1N; the same shift register 30 is connected with the voltage adjustment module 66 in the pixel driving circuit of the two pixel rows 40, and the threshold compensation of the driving transistor of the pixel driving circuit in the two pixel rows 40 is realized through the control of the third control line SP*; the same shift register 30 is connected with the compensation module 62 in the pixel driving circuit of the two pixel rows 40, and the threshold compensation of the two pixel driving circuits is realized through the control of the second control line S2N. In this way, the same shift register 30 can provide signals to the pixel driving circuits in the two pixel rows 40, which greatly reduces the number of shift registers 30 contained in the display panel compared with the mode that one shift register 30 corresponds to the pixel driving circuit in one pixel row 40, so that the space occupied by the shift register 30 in the first frame area B1 and the second frame area B2 is reduced, and the narrow frame design of the display panel is realized.

[0070] Please refer to Figures 5 to 8 When the pixel driving circuit adopts the 8T1C circuit as shown in Figure 5 , optionally, the same first control line S1N drives the pixel driving circuits corresponding to the two pixel rows 40, the same emission control line EMIT drives the pixel driving circuits corresponding to the two pixel rows 40, and the shift register 30 connected with the first control line S1N and the emission control line EMIT is located in the first frame area B1; the same second control line S2N drives the pixel driving circuits corresponding to the two pixel rows 40, the same third control line SP* drives the pixel driving circuits corresponding to the two pixel rows 40, and the shift register 30 connected with the second control line S2N and the fourth control line SP is located in the second frame area B2.

[0071] Please refer to Figure 7 and Figure 9The same fourth control line SP is only electrically connected to the corresponding pixel driving circuit in the same pixel row 40. The area between the first non-display area NA1 and the second non-display area NA2 needs to be displayed. The same fourth control line SP only needs to be wound from one side, for example, it can be connected to the shift register 30 in the first border area B1. After the fourth control line SP extends to the side of the first non-display area NA1 away from the second non-display area NA2, it is connected to the first line segment L11 between the first non-display area NA1 and the second non-display area NA2 through the first crossover line 10. Therefore, in the pixel row 40 overlapping with the first non-display area NA1 along the first direction D1, each two rows and one column of pixel driving circuits requires 6 first crossover lines 10 vertically and horizontally. In the pixel row 40 overlapping with the second non-display area NA2 along the first direction D1, each two rows and one column of pixel driving circuits only requires 4 first crossover lines 10 vertically and horizontally. Assume that the total number of pixel rows 40 overlapping with the first non-display area NA1 along the first direction D1 is N. The first cross lines 10 corresponding to the first signal line L1 in these pixel rows 40 are N / 2 groups above and below the first non-display area NA1 and the second non-display area NA2. Each group has 6 first cross lines 10 at the position corresponding to the first non-display area NA1 (assuming the line width of each first cross line 10 is x, the limit between two adjacent first cross lines 10 is y, x+y=D, then the space occupied by each group is 6D. Optionally, if X≤3um, Y≤3um, then D≤6um). 4 first cross lines 10 are set at the position corresponding to the second non-display area NA2. The number of first cross lines 10 to be set above and below the first non-display area is 3N (N / 2*6=3N above and below). The number of first cross lines 10 to be set above and below the second non-display area NA2 is 2N (N / 2*4=2N above and below). Assuming the distance along the first direction D1 between the first non-display area NA1 and the second non-display area NA2 is A, if distance A < 5N*D, the occupied bezel space is (5N*DA) / 2. Since the first line segment L11 at the position corresponding to distance A is connected by the first crossover line 10, the proportion of space occupied by the bezel is greatly reduced. Conversely, if distance A ≥ 5N*D, the entire space between the first non-display area NA1 and the second non-display area NA2 can be used to complete the wiring of the first crossover line 10, without occupying the bezel space of the first non-display area NA1 and the second non-display area NA2. The routing space of the first crossover line 10 above or below the first non-display area NA1 is N / 2*6*D. By connecting the first line segment L11 and the second line segment L12 through this U-shaped first crossover line 10, a total of 3N*D bezel space in the top, bottom, left, and right of the non-display area AA can be saved. Therefore, it is beneficial to realize the narrow bezel design of the non-display area AA and improve the screen ratio of the display panel.

[0072] Figure 10 The diagram shown is a schematic diagram of a film layer of a display panel provided in an embodiment of the present invention. It should be noted that... Figure 10Only part of the film layers of the display panel is shown, which does not represent the actual number and size of the film layers contained in the display panel. Among them, Figure 10 The display panel shown in the embodiment shows two types of transistors, the first type of transistor is a low-temperature polysilicon transistor, which includes an active layer poly; the second type of transistor is a metal oxide transistor, which includes an active layer IGZO. Please refer to Figure 10 , the display panel is a multi-film layer stack structure, including metal layer, active layer, electrode layer and insulating layer, etc., also including anode layer RE and light-emitting layer 50 above the anode layer RE.

[0073] Figure 11 The layout between the first non-display area and the second non-display area in the display panel provided by the embodiment of the application is shown, Figure 12 The layout between the first non-display area and the second non-display area in the display panel provided by the embodiment of the application is shown, Figure 11 A partial enlarged view of the area A1 in the embodiment of the application is shown, Figure 11 The embodiment shown shows the connection relationship between the two pixel rows corresponding to the first non-display area and the second non-display area, wherein the first cross line 10-S1N corresponds to the part of the first cross line along the second direction D2 electrically connected with the first control line S1N, the first cross line 10-SP corresponds to the part of the first cross line along the second direction D2 electrically connected with the fourth control line SP, the first cross line 10-EMIT corresponds to the part of the first cross line along the second direction D2 electrically connected with the light-emitting control line EMIT, the first cross line 10-S2N corresponds to the part of the first cross line along the second direction D2 electrically connected with the second control line S2N, and the first cross line 10-SP* corresponds to the part of the first cross line along the second direction D2 electrically connected with the third control line SP*; the first line segment L11-S1N corresponds to the first line segment corresponding to the first control line S1N, the first line segment L11-EMIT corresponds to the first line segment corresponding to the light-emitting control line, the first line segment L11-S2N corresponds to the first line segment corresponding to the second control line, and the first line segment L11-SP* corresponds to the first line segment corresponding to the third control line.

[0074] Please refer to Figure 7 , Figure 11 and Figure 12 In an optional embodiment of the application, the first line segment L11 includes a first end adjacent to the first non-display area NA1 and a second end adjacent to the second non-display area NA2; the first end of the N first line segments L11 corresponding to at least one of the first control line S1N, the second control line S2N, the third control line SP* and the light-emitting control line EMIT in the adjacent N pixel rows is electrically connected, or the second end is electrically connected.

[0075] Figure 11and Figure 12 The illustrated embodiment shows that, taking a one-drive-two design in a pixel circuit as an example, in two pixel rows between the first non-display area and the second non-display area, the first ends of the first line segments corresponding to the two adjacent first control lines S1N are electrically connected; the first ends of the first line segments corresponding to the two adjacent light-emitting control lines EMIT are electrically connected; the second ends of the first line segments corresponding to the two adjacent second control lines S2N are electrically connected, and the second ends of the first line segments corresponding to the two adjacent third control lines SP* are electrically connected. In some other embodiments of the present application, the first ends or the second ends of the above-mentioned control lines located in three or more pixel rows can also be electrically connected to receive the same signal, and the present application does not make specific limitations in this regard.

[0076] In this way, the control lines that are electrically connected to each other only need to be connected to one shift register, and the control signals can be provided to the mutually connected control lines through the same shift register, effectively reducing the number of shift registers actually contained in the display panel, thereby being conducive to reducing the frame.

[0077] Figure 13 The illustrated is Figure 12 A partial enlarged view of the middle area A2, which shows a connection relationship of two gates of a metal oxide transistor. Please refer to Figure 5 、 Figure 10 and Figure 13 In an optional embodiment of the present application, at least one of the first reset module 63 and the compensation module 62 includes a metal oxide transistor, which includes an active layer IGZO and a first gate s1 and a second gate s2 located on both sides of the active layer IGZO along the thickness direction of the display panel between the first non-display area NA1 and the second non-display area NA2, and the ends of the first gate s1 and the second gate s2 in the same metal oxide transistor are electrically connected.

[0078] The metal oxide transistor belongs to the second transistor M02, wherein the first gate s1 is located at the gate metal layer MG, the second gate s2 is located at the capacitor metal layer MC, and the first gate s1 and the second gate s2 are located at the upper and lower sides of the active layer IGZO respectively. In the embodiment of the application, the first gate s1 and the second gate s2 of the metal oxide transistor between the first non-display area and the second non-display area are electrically connected, so that the first gate s1 and the second gate s2 of the metal oxide transistor receive the same signal, and thus the first gate s1 and the second gate s2 of the same metal oxide transistor can share the same control line, thereby being beneficial to reducing the leakage current of the metal oxide transistor, improving the stability of the device, and more beneficial to avoiding or reducing the influence of the leakage current of the metal oxide transistor on the first node. In addition, the second gate s2 in the metal oxide transistor can also play a certain shielding effect on the influence of the H particles on the active layer IGZO in the metal oxide transistor, and connecting the first gate s1 and the second gate s2 is also beneficial to improving the mobility of the device.

[0079] Optionally, the first gate s1 and the second gate s2 can be electrically connected by means of other conductive film layers in the display panel, for example, please refer to Figure 10 and Figure 13 The connecting part 90 located at the second metal layer M2 can be provided, the first gate s1 is electrically connected with the connecting part 90 through punching, and the second gate s2 is electrically connected with the connecting part 90 through punching, so as to realize the electrical connection between the first gate s1 and the second gate s2. Of course, the film layer where the connecting part 90 is located is not limited, and the connecting part 90 is also only illustrative in the second metal layer M2. In some other embodiments of the application, the connecting part 90 can also be arranged in other film layers.

[0080] Please refer to Figures 5 to 10 In an optional embodiment of the application, the first control line S1N, the second control line S2N, the third control line SP*, the fourth control line SP and the light-emitting control line EMIT are distributed in at least two different film layers.

[0081] Figure 10 The film layer structure corresponding to the embodiment shown includes the first metal layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4, the capacitor metal layer MC, the gate metal layer MG and the like. Optionally, the first cross line 10 in the embodiment of the application is arranged in the fourth metal layer M4, and the control line X contained in the first signal line L1 can be arranged in at least two of the other metal layers.

[0082] Since the pixel driving circuit corresponding to the sub-pixel in the display panel is connected with the first control line S1N, the second control line S2N, the third control line SP*, the fourth control line SP and the light-emitting control line EMIT respectively to obtain the control signal, in the display panel, the first control line S1N, the second control line S2N, the third control line SP*, the fourth control line SP and the light-emitting control line EMIT all extend along the first direction D1, when these control lines X are distributed in the same film layer, the small interval between adjacent wires may cause signal interference. Thus, it is beneficial to improve the screen ratio of the display panel, and also beneficial to increase the distance between adjacent wires to avoid signal interference between wires.

[0083] For reference Figure 7 In an optional embodiment of the present application, the first cross-line 10 corresponding to the first control line S1N, the second control line S2N, the third control line SP* and the light-emitting control line EMIT respectively includes a first sub-first cross-line 101 and a second sub-first cross-line 102; the first end of the first line segment L11 in the first control line S1N, the second control line S2N, the third control line SP* and the light-emitting control line EMIT is connected with the second line segment L12 located on the side of the first non-display area NA1 away from the second non-display area NA2 through the first sub-first cross-line 10, and the second end is connected with the second line segment L12 located on the side of the second display area AA away from the first non-display area NA1 through the second sub-first cross-line 102.

[0084] Optionally, in the display panel provided by the embodiment of the present application, the first control line S1N, the second control line S2N, the third control line SP* and the light-emitting control line EMIT connected with the pixel driving circuit are all single-side driven, that is, each of the control lines X is connected with only one shift register 30, when the control lines X include the first line segment L11 located between the first non-display area NA1 and the second non-display area NA2, the second line segment L12 located on the side of the first non-display area NA1 away from the second non-display area NA2, and the second line segment L12 located on the side of the second non-display area NA2 away from the first non-display area NA1, and the first line segment L11 and the two second line segments L12 all receive the signal of the same shift register 30, the first sub-first cross-line 10 is used to electrically connect the first line segment L11 and the second line segment L12 located on the left side of the first non-display area NA1, and the second sub-first cross-line 102 is used to electrically connect the first line segment L11 and the second line segment L12 located on the right side of the first non-display area NA1, in this way, the electrical connection of the first line segment L11 and the two second line segments L12 is realized by using the first sub-first cross-line 10 and the second sub-first cross-line 102, and the corresponding sub-pixel of the first line segment L11 and the two second line segments L12 can all receive the signal sent by the shift register 30, thereby being beneficial to guarantee the normal display function of the corresponding sub-pixel.

[0085] Please refer to Figure 7 , Figure 11 and Figure 12 , in an optional embodiment of the present application, at least three pixel columns are arranged between the first non-display area NA1 and the second non-display area NA2, at least part of the first line segment L11 is electrically connected with a first cross-line 10 through a first hole K01 and electrically connected with another first cross-line 10 through a second hole K02; along the first direction D1, the distance between the first hole K01 and the second hole K02 is greater than or equal to the total width of the three continuous pixel columns between the first non-display area NA1 and the second non-display area NA2.

[0086] At least part of the first line segment L11 arranged between the first non-display area NA1 and the second non-display area NA2 needs to be electrically connected with the second line segment L12 located on both sides through two first cross-lines 10, for example Figure 7 The first line segment L11 corresponding to the first control line S1N, the second control line S2N, the third control line SP* and the light-emitting control line EMIT in the embodiment shown. In this embodiment, the distance between the first hole K01 and the second hole K02 connected with the same first line segment L11 along the first direction D1 is greater than or equal to the total width of the three continuous pixel columns between the first non-display area NA1 and the second non-display area NA2, which is beneficial to ensure the spacing between the first hole K01 and the second hole K02, avoid the phenomenon of interference or short circuit between the two holes due to too small distance between the first hole K01 and the second hole K02, and also beneficial to reduce the difficulty of manufacturing the first hole K01 and the second hole K02.

[0087] Figure 14 The other connection diagram of the fourth control line SP corresponding to the positions of the first non-display area NA1 and the second non-display area NA2 is shown, it should be noted that Figure 14 Only the part of the fourth control line SP truncated by the first non-display area NA1 and the second non-display area NA2 is shown, and other control lines X truncated by the first non-display area NA1 and the second non-display area NA2 are not shown.

[0088] Please refer to Figure 14 , in an optional embodiment of the present application, the first line segment L11 in the fourth control line SP is electrically connected with the second line segment L12 located on one side of the first line segment L11 along the first direction D1 through the first cross-line 10.

[0089] Optionally, in the display panel provided by the embodiment of the present application, in the fourth control line SP connected with the data writing module 61 in the pixel driving circuit, the fourth control line SP not overlapping with the first non-display area NA1 and the second non-display area NA2 along the first direction D1 is double-side driven, that is, the two ends of the fourth control line SP are connected with different shift registers 30 respectively. In the fourth control line SP overlapping with the first non-display area NA1 and the second non-display area NA2 along the first direction D1, two control lines X correspond to the same pixel row 40, the same first line segment L11 is only electrically connected with the second line segment L12 on the left side of the first non-display area NA1 through the first cross line 10, at this time, the first line segment L11 obtains the signal through the shift register 30 in the first border area B1 electrically connected with the second line segment L12 on the left side of the first non-display area NA1, the second line segment L12 on the right side of the second non-display area NA2 does not need to be electrically connected with the first line segment L11, and obtains the control signal through the shift register 30 in the second border area B2. Alternatively, the same first line segment L11 is only electrically connected with the second line segment L12 on the right side of the second non-display area NA2 through the first cross line 10, at this time, the first line segment L11 obtains the control signal through the shift register 30 in the second border area B2 electrically connected with the second line segment L12 on the right side of the second non-display area NA2, the second line segment L12 on the left side of the first non-display area NA1 does not need to be electrically connected with the first line segment L11, and obtains the control signal through the shift register 30 in the first border area B1. The connection relationship between the fourth control line SP and the shift register 30 reduces the number of the first cross line 10, thereby facilitating the simplification of the overall wiring difficulty of the display panel.

[0090] It should be noted that in the fourth control line SP overlapping with the first non-display area NA1 and the second non-display area NA2 along the first direction D1, if the corresponding first line segment L11 is connected with the second line segment L12 through one first cross line 10, the above embodiment shows the case that the first cross line 10 is distributed around the first non-display area NA1 and the second non-display area NA2, in some other embodiments of the present application, the first cross line 10 in this part can also be distributed only around the second non-display area NA2, for example, please refer to Figure 15 , wherein Figure 15 , which is another connection diagram of the fourth control line SP corresponding to the positions of the first non-display area NA1 and the second non-display area NA2. Of course, in some other embodiments of the present application, the above-mentioned first cross line corresponding to the fourth control line can also be located only around the first non-display area, which is not limited in the present application.

[0091] Please refer to Figure 7 , Figure 8 and Figure 11 and Figure 12In an optional embodiment of the present application, in the first cross-line 10 connected with the fourth control line SP, at least part of the first cross-line 10 is located on the first side of the first line segment L11 along the second direction D2, and at least part of the first cross-line 10 is located on the second side of the first line segment L11 along the second direction D2; in the first cross-line 10 connected with at least one of the first control line S1N, the second control line S2N, the third control line SP* and the light-emitting control line EMIT, at least part of the first cross-line 10 is located on at least one side of the first line segment L11 along the second direction D2.

[0092] Specifically, as the space between the first non-display area NA1 and the second non-display area NA2 is limited, when the first line segment L11 in the first non-display area NA1 and the second non-display area NA2 is electrically connected with the second line segment L12 through the first cross-line 10, at least part of the first cross-line 10 must be led out from the area between the first non-display area NA1 and the second non-display area NA2. In the embodiment of the present application, in the first cross-line 10 connected with the fourth control line SP, part of the first cross-line 10 is arranged above the first line segment L11, and another part of the first cross-line 10 is arranged below the first line segment L11; in the cross-line connected with other control lines, at least part of the first cross-line 10 is located on at least one side of the first line segment L11 along the second direction. In this way, the first cross-line 10 around the first non-display area NA1 and the second non-display area NA2 can be distributed as evenly as possible above and below the first line segment L11, which can not only reasonably utilize the space around the first non-display area NA1 and the second non-display area NA2, but also be conducive to improving the screen mura phenomenon caused by uneven distribution of the first cross-line 10 on the upper and lower sides of the first non-display area NA1 and the second non-display area NA2.

[0093] Please refer to Figure 7 , Figure 11 and Figure 12 In an optional embodiment of the present application, at least three pixel columns are arranged between the first non-display area NA1 and the second non-display area NA2; in the first cross-line 10 corresponding to the first control line S1N, the second control line S2N, the third control line SP*, the fourth control line SP and the light-emitting control line EMIT between the first non-display area NA1 and the second non-display area NA2, the line segment extending along the second direction D2 is located within the range defined by the three continuous pixel columns. In this way, the space between the first non-display area NA1 and the second non-display area NA2 can be reasonably utilized, and the phenomenon of occupying the frame space of the first non-display area NA1 or the second non-display area NA2 due to the too large space occupied by the above-mentioned line segment extending along the second direction D2 can be avoided, thereby being conducive to reducing the frame width of the first non-display area NA2 and the second non-display area NA2.

[0094] Please refer to Figure 2In an optional embodiment of the present application, the display panel 100 further comprises a frame region B at least partially surrounding the display region AA, and at least part of the first cross-line 10 is located in the frame region B.

[0095] Specifically, Figure 2 The illustrated embodiment takes the first non-display region NA1 and the second non-display region NA2 close to the upper frame region of the display panel as an example. When the first non-display region NA1 and the second non-display region NA2 are close to the upper frame of the display panel, in the first cross-line 10 connecting the first line segment L11 and the second line segment L12 in the first signal line L1, at least part of the first cross-line 10 is routed from above the first non-display region NA1 and the second non-display region NA2, and in this embodiment, at least part of the line segment in the first cross-line 10 is arranged in the upper frame region B. In this way, the overlapping area of the first cross-line 10 and the display region AA is reduced, which is conducive to reducing the coupling interference caused by the overlapping of the first cross-line 10 and other lines in the display region AA, and thus is conducive to improving the accuracy and stability of the signal transmitted on the first cross-line 10.

[0096] Figure 16 Another structural schematic diagram of the display panel provided by the embodiment of the present application is shown, Figure 17 A wiring schematic diagram of the first signal line L1 and the second signal line L2 arranged around the first non-display region NA1 and the second non-display region NA2 is shown, and the embodiment shows a scheme in which the display panel comprises the second signal line L2 extending along the second direction D2.

[0097] Please refer to Figure 16 and Figure 17 In an optional embodiment of the present application, the display region AA further comprises a plurality of second signal lines L2 extending along the second direction D2, and at least part of the second signal lines L2 comprises a third line segment L23 and a fourth line segment L24 arranged along the second direction D2; along the second direction D2, the third line segment L23 and the fourth line segment L24 are located on both sides of the first non-display region NA1 or on both sides of the second non-display region NA2, and in the same second signal line L2, the third line segment L23 and the fourth line segment L24 are electrically connected by a second cross-line 20; at least part of the second cross-line 20 is arranged in the same layer as the first cross-line 10, and the second direction D2 intersects the first direction D1.

[0098] Specifically, when the first non-display area NA1 and the second non-display area NA2 are introduced in the display panel 100, in the second signal lines L2 extending along the second direction D2 in the display panel 100, at least part of the second signal lines L2 overlap with the first non-display area NA1 or the second non-display area NA2 along the second direction D2, and the part of the second signal lines L2 includes the third line segment L23 and the fourth line segment L24 respectively located on both sides of the non-display area AA along the second direction D2, wherein the third line segment L23 and the fourth line segment L24 in the same second signal line L2 are electrically connected through the second cross-line 20, optionally, the second cross-line 20 is arranged in a layer different from the second signal line L2, and at least part of the second cross-line 20 is arranged in the same layer as the first cross-line 10. By using the second cross-line 20 arranged in a layer different from the second signal line L2 to connect the third line segment L23 and the fourth line segment L24 in the second signal line L2, there is no need to perform wire winding in the frame area of the first non-display area NA1 or the second non-display area NA2, so that the number of wires corresponding to the frame area of the first non-display area NA1 and the second non-display area NA2 can also be reduced, the compression space of the frame of the first non-display area NA1 and the second non-display area NA2 is provided, and thus the narrow frame design of the hole circumference corresponding to the first non-display area NA1 and the second non-display area NA2 is facilitated, and the screen-to-body ratio of the display panel is improved.

[0099] With reference to the foregoing Figure 16 and Figure 17 In an optional embodiment of the present application, the first cross-line 10 and the second cross-line 20 are arranged in the same layer.

[0100] When the first cross-line 10 connecting the first line segment L11 and the second line segment L12 and the second cross-line 20 connecting the third line segment L23 and the fourth line segment L24 are arranged in the same layer in the display panel, it is equivalent to that a single additional film layer is newly added in the display panel to arrange the first cross-line 10 and the second cross-line 20, and there is no need to introduce different film layer structures for the first cross-line 10 and the second cross-line 20, so that while the first non-display area NA1 and the second non-display area NA2 and other non-display areas AA in the display panel are reduced in frame width by using the first cross-line 10 and the second cross-line 20, the film layer complexity of the whole display panel is also facilitated to be simplified.

[0101] With reference to the foregoing Figure 10 and Figure 17 In an optional embodiment of the present application, the first cross-line 10 is connected with the first signal line L1 through the first connection hole K1, and the second cross-line 20 is electrically connected with the second signal line L2 through the second connection hole K2; the display panel further includes a plurality of third connection holes K3, and the first connection hole K1, the second connection hole K2 and the third connection hole K3 do not overlap with each other in the thickness direction of the display panel.

[0102] It should be noted that in order to control the normal display of the display panel, a driving layer is usually set in the display panel. The driving layer is a multi-film layer stacked structure. When structures located in two different film layers need to be electrically connected, a connection hole is usually formed in the insulating layer between the two film layers. The electrical connection between the two is achieved through the connection hole. For example, the anode of the light-emitting element can be electrically connected to the transistor on the driving layer through the connection hole. Let's assume that this part of the connection hole is the third connection hole K3.

[0103] When a first crossover 10 connecting the first line segment L11 and the second line segment L12 is introduced into the display panel, the first crossover 10 is disposed on a different layer from the first line segment L11 and the second line segment L12. At this time, the first crossover 10 is electrically connected to the first line segment L11 and the second line segment L12 through the first connecting hole K1. When a second crossover 20 connecting the third line segment L23 and the fourth line segment L24 is introduced into the display panel, the second crossover 20 is disposed on a different layer from the third line segment L23 and the fourth line segment L24. At this time, the second crossover 20 is electrically connected to the third line segment L23 and the fourth line segment L24 through the second connecting hole K2. When the first crossover 10 and the second crossover 20 are introduced, the first connecting hole K1 and the second connecting hole K2 in this embodiment are essentially new connecting holes added on the basis of the existing third connecting hole K3 in the display panel. At this time, the embodiment of the present invention limits the first connecting hole K1, the second connecting hole K2 and the third connecting hole K3 to not overlap in the thickness direction of the display panel. That is to say, the first connecting hole K1, the second connecting hole K2 and the third connecting hole K3 in the display panel are staggered and do not interfere with each other. Therefore, it is beneficial to avoid the introduction of the first connecting hole K1 and the second connecting hole K2 from affecting the third connecting hole K3 on the display panel, and to improve the stability and accuracy of the signal transmission corresponding to each connecting hole.

[0104] Figure 18 The image shown is related to Figure 17 The panel layout diagram corresponding to area A3 in the diagram. Figure 19 The image shown is related to Figure 17 The panel layout diagram corresponding to area A4 in the diagram. Figure 20 The image shown is related to Figure 17The panel layout diagram corresponding to the region A5 in FIG. 1C, which shows three data lines data1, data2 and data3 and corresponding partial second cross lines 20 overlapping with the first non-display area NA1 along the second direction D2, wherein second cross line 20-data1 represents the second cross line connected with the data line data1, second cross line 20-data2 represents the first cross line connected with the data line data2, second cross line 20-data3 represents the first cross line connected with the data line data3, first cross line 10-SP represents the first cross line connected with the fourth control line SP, first cross line 10-S1N represents the first cross line connected with the first control line S1N, and first cross line 10-EMIT represents the first cross line connected with the light emitting control line EMIT.

[0105] Please refer to Figures 17 to 20 In an optional embodiment of the present application, the second cross line 20 includes a line segment 24 extending along the second direction D2, and the line segment 24 extending along the second direction D2 does not overlap with other second signal lines L2 in the thickness direction of the display panel.

[0106] In the display panel provided by the embodiment of the present application, the second signal line L2 extending along the second direction D2 may be, for example, a data signal line connected with a pixel driving circuit, used to provide a data signal to the pixel driving circuit, and at least part of the data lines do not transmit data signals at the same time. When the line segment extending along the second direction D2 in the second cross line 20 overlaps with other second signal lines L2, if the second signal line L2 connected with the second cross line 20 and the second signal line L2 overlapping with the line segment extending along the second direction D2 in the second cross line 20 do not transmit data signals at the same time or do not transmit data signals at the same time, the signals between the two may interfere with each other, affecting the accuracy and stability of signal transmission. Therefore, in the embodiment of the present application, the line segment extending along the second direction D2 in the second cross line 20 is arranged not to overlap with other second signal lines L2 in the thickness direction of the display panel, which is beneficial to reduce or avoid signal interference between different second signal lines L2, and improve the accuracy and stability of signal transmission.

[0107] In an optional embodiment of the present application, the display panel includes a fixed voltage signal line located in the display area AA, and the fixed voltage signal line includes a first fixed voltage signal line extending along the first direction D1 and a second fixed voltage signal line extending along the second direction D2; in the first cross line 10 and the second cross line 20, at least part of the line segments extending along the first direction D1 overlap with the first fixed voltage signal line in the thickness direction of the display panel, and at least part of the line segments extending along the second direction D2 overlap with the second fixed voltage signal line.

[0108] Specifically, the display panel has some fixed voltage signal lines, and the voltage on these fixed voltage signal lines is always constant, for example... Figure 5 Taking the pixel driving circuit shown as an example, the signal lines connected to the first power supply terminal VDD, the signal lines connected to the second power supply terminal VEE, the signal lines connected to the reset signal terminals VREF1 and VREF2, and the signal lines connected to the substrate receiving the fixed potential of the storage capacitor Cst are all fixed voltage signal lines, and the potential on these signal lines is constant. Some of these signal lines include segments extending along the first direction D1; these segments are assumed to be the first fixed voltage signal lines. Other signal lines include segments extending along the second direction D2; these segments are assumed to be the second fixed voltage signal lines. When a first crossover line 10 and a second crossover line 20 are introduced into the display panel, at least a portion of the line segments extending along the first direction D1 of these two crossover lines overlap with the first fixed voltage signal line, and at least a portion of the line segments extending along the second direction D2 overlap with the second fixed voltage signal line. In this way, the orthographic projection of the first crossover line 10 and the second crossover line 20 in the first signal line L1 onto the display panel overlaps with the fixed voltage signal line in the display panel. Since the signal on the fixed voltage signal line is constant, it will not interfere with the signal in the first crossover line 10. Moreover, it can also improve the screen-off mura phenomenon that may occur in the display panel when the first crossover line 10 and the second crossover line 20 are introduced into the display panel to a certain extent.

[0109] Optionally, the line segments extending along the first direction D1 in the first cross line 10 and the second cross line 20 are projected onto the display panel within the range of the first fixed voltage signal line projected onto the display panel, and the line segments extending along the second direction D2 in the first cross line 10 and the second cross line 20 are projected onto the display panel within the range of the second fixed voltage signal line projected onto the display panel. In this way, it is equivalent to using the fixed voltage signal line to block the first cross line 10 and the second cross line 20, which is more conducive to improving the screen-off mura phenomenon.

[0110] Please refer to Figure 18 In an optional embodiment of the present invention, in the first crossover 10 and the second crossover 20, at least a portion of the line segment 23 extending along the first direction D1 in the thickness direction of the display panel overlaps with the first signal line L1. Considering that the display panel is provided with multiple first signal lines L1 extending along the first direction D1, when the first crossover 10 and the second crossover 20 are introduced into the display panel, at least a portion of the line segments extending along the first direction D1 in the first crossover 10 and the second crossover 20 overlap with the first signal line L1, which helps to simplify the wiring difficulty of the first crossover 10 and the second crossover 20.

[0111] Please refer to Figure 17In an optional embodiment of the present application, the first crossing wire 10 comprises a first sub-wire segment 11 extending along the first direction D1 and a second sub-wire segment 12 extending along the second direction D2, and the second crossing wire 20 comprises a third sub-wire segment 23 extending along the first direction D1 and a fourth sub-wire segment 24 extending along the second direction D2; along the thickness direction of the display panel, the first sub-wire segment 11 and the third sub-wire segment 23 do not overlap with each other, and the second sub-wire segment 12 and the fourth sub-wire segment 24 do not overlap with each other.

[0112] Specifically, when the first crossing wire 10 is used to connect the first wire segment L11 and the second wire segment L12 in the first signal line L1, and the second crossing wire 20 is used to connect the third wire segment L23 and the fourth wire segment L24 in the second signal line L2, the same first crossing wire 10 comprises the first sub-wire segment 11 extending along the first direction D1 and the second sub-wire segment 12 extending along the second direction D2, and the same second crossing wire 20 comprises the third sub-wire segment 23 extending along the first direction D1 and the fourth sub-wire segment 24 extending along the second direction D2. Alternatively, the first sub-wire segment 11 and the third sub-wire segment 23 extending along the first direction D1 do not overlap with each other and will not be short-circuited with each other, and the second sub-wire segment 12 and the fourth sub-wire segment 24 extending along the second direction D2 do not overlap with each other and will not be short-circuited with each other. In this way, the first sub-wire segment 11 and the second sub-wire segment 12 in the first crossing wire 10 and the third sub-wire segment 23 and the fourth sub-wire segment 24 in the second crossing wire 20 can be arranged in the same film layer, thus being conducive to reducing the number of film layers in the display panel and simplifying the film layer structure of the display panel.

[0113] Please continue to refer to Figure 17 In an optional embodiment of the present application, at least part of the third sub-wire segment 23 is located between two adjacent first sub-wire segments 11, and at least part of the fourth sub-wire segment 24 is located between two adjacent second sub-wire segments 12.

[0114] Specifically, the first sub-wire segment 11 in the first crossing wire 10 and the third sub-wire segment 23 in the second crossing wire 20 both extend along the first direction D1. When arranging the first sub-wire segment 11 and the third sub-wire segment 23, at least part of the third sub-wire segment 23 is arranged between two adjacent first sub-wire segments 11 in a staggered design, which is conducive to reasonably utilizing the space around the non-display area AA and avoiding the problem of excessive wiring range of the first sub-wire segment 11 and the third sub-wire segment 23 when arranging multiple first sub-wire segments 11 and multiple third sub-wire segments 23 in two different spaces.

[0115] Similarly, the second sub-line segment 12 in the first cross-line 10 and the fourth sub-line segment 24 in the second cross-line 20 both extend along the second direction D2, and when the second sub-line segment 12 and the fourth sub-line segment 24 are arranged, at least part of the fourth sub-line segment 24 is arranged in an interleaved manner between two adjacent second sub-line segments 12, which is conducive to reasonably utilizing the space around the non-display area AA and avoiding the problem of excessive wiring range of the second sub-line segment 12 and the fourth sub-line segment 24 when the plurality of second sub-line segments 12 and the plurality of fourth sub-line segments 24 are arranged in two different spaces. Therefore, the interleaved arrangement of the first sub-line segment 11 and the second sub-line segment 12 and the interleaved arrangement of the third sub-line segment 23 and the fourth sub-line segment 24 are conducive to simplifying the wiring range of the first cross-line 10 and the second cross-line 20 on the display panel, avoiding the problem of insufficient wiring space on the display panel when the number of the first cross-line 10 and the second cross-line 20 is large, and thus conducive to ensuring the narrow frame design around the first non-display area NA1 and the second non-display area NA2.

[0116] Figure 21 Another wiring schematic diagram of the first signal line L1 and the second signal line L2 arranged around the first non-display area NA1 and the second non-display area NA2 is shown, and in an optional embodiment of the present application, along the first direction D1, the length of the first non-display area NA1 is greater than the length of the second non-display area NA2; at least part of the second cross-line 20 semi-encloses the first cross-line 10 on the side of the first non-display area NA1 away from the second non-display area NA2.

[0117] Please refer to Figure 21When the first non-display area NA1 and the second non-display area NA2 are introduced in the display panel, optionally, the first non-display area NA1 and the second non-display area NA2 are different in size along the first direction D1, specifically, the width of the first non-display area NA1 along the first direction D1 is greater than the width of the second non-display area NA2 along the second direction D2, optionally, the first non-display area NA1 includes two light transmission holes, and the second non-display area NA2 includes a single light transmission hole. At this time, the number of the second signal lines L2 overlapping the first non-display area along the second direction D2 will be greater than the number of the second signal lines L2 overlapping the second non-display area NA2 along the second direction D2, and thus the number of the second cross lines 20 corresponding to the first non-display area NA1 will be greater than the number of the second cross lines 20 corresponding to the second non-display area NA2. When at least part of the first cross lines 10 and the second cross lines 20 are designed in a staggered manner, due to the large number of the second cross lines 20, part of the second cross lines 20 will not be able to be designed in a staggered manner. At this time, the part of the second cross lines 20 is arranged on the side of the first non-display area NA1 away from the second non-display area NA2 and semi-surrounds the first cross lines 10 for design, thereby reasonably utilizing the space of the first non-display area NA1 and the second non-display area NA2. It should be noted that, due to the small size of the second non-display area along the first direction D1, the first cross lines 10 and the second cross lines 20 corresponding to the second non-display area NA2 can be arranged in a staggered manner. If the number of the second cross lines 20 corresponding to the second non-display area NA2 is greater than the number of the first cross lines 10, part of the second cross lines 20 can be arranged on the side of the second non-display area NA2 away from the first non-display area NA1 in a manner of at least partially including the first cross lines 10, which is not limited in the present application.

[0118] Please refer to Figure 10 , Figure 16 and Figure 17 , in an optional embodiment of the present application, the display panel includes a substrate 00 and a transistor layer arranged on the substrate, the transistor layer includes a first type of transistor M01 and a second type of transistor M02; the display panel includes a first metal layer M1, a second metal layer M2, a gate metal layer MG, a capacitor metal layer MC, a third metal layer M3, and a fourth metal layer M4, the gate of the first type of transistor M01 is located on the first metal layer M1, the gate of the second type of transistor M02 is located on the gate metal layer MG, the source and the drain of the first type of transistor M01 and the second type of transistor M02 are located on the second metal layer M2; the capacitor metal layer MC is located between the first metal layer M1 and the second metal layer M2, the third metal layer M3 is located on the side of the second metal layer M2 away from the substrate, and the fourth metal layer M4 is located on the side of the third metal layer M3 away from the substrate; at least part of the line segments in the first cross lines 10 are located on the fourth metal layer M4.

[0119] Specifically,Figure 10 The display panel shown in the embodiment includes two types of transistors, and optionally, the first type of transistor M01 is a low-temperature polysilicon transistor, and the second type of transistor M02 is an oxide transistor. Please refer to Figure 5 The driving transistor M0, the first transistor M1 in the data writing module 61, the fourth transistor M4 in the data writing module 61, the fourth transistor M4 and the fifth transistor M5 in the light-emitting control module 65, the sixth transistor M6 in the second reset module 64, and the seventh transistor M7 in the voltage adjustment module 66 are all the first type of transistor M01, and the second transistor M2 in the compensation module 62 and the third transistor M3 in the first reset module 63 are all the second type of transistor M02. Since the second transistor M2 and the third transistor M3 are both transistors directly connected to the first node N1, the drain current of the second transistor M2 and the third transistor M3 will directly affect the potential of the first node N1. When the second transistor M2 and the third transistor M3 are set as oxide transistors, since the drain current of the oxide transistor is small, it is beneficial to avoid or reduce the influence of the drain current of the second transistor M2 and the third transistor M3 on the potential of the first node N1, thereby improving the light-emitting stability of the light-emitting element.

[0120] Please refer to Figure 3 , Figure 5 , Figure 10 , Figure 16 and Figure 17 Optionally, the first control line S1N, the second control line S2N, the third control line SP*, the fourth control line SP, and the light-emitting control line EMIT in the embodiment of the present application can be located in any film layer of the first metal layer M1, the capacitor metal layer MC, the gate metal layer MG, and the third metal layer M3. The first line segment L11 and the second line segment L12 in the same control line can be located in the same metal layer or different metal layers, and the present application does not make specific limitations thereon. For example, the first control line S1N and the second control line S2N can be arranged in the gate metal layer MG, and the third control line SP*, the light-emitting control line EMIT, and the fourth control line SP can be arranged in the first metal layer. Of course, this is only an example, and in some other embodiments of the present application, the film layers where the first control line S1N, the second control line S2N, the third control line SP*, the fourth control line SP, and the light-emitting control line EMIT are actually located can also be adjusted according to actual conditions.

[0121] In the embodiment, at least part of the first cross-line 10 connecting the first line segment L11 and the second line segment L12 can be arranged in the fourth metal layer M4, and optionally, the first cross-line 10 is arranged in the fourth metal layer M4. Since the first cross-line 10 is arranged in a different layer from the first line segment L11 and the second line segment L12 in the first signal line L1, the first cross-line 10 is used to connect the first line segment L11 and the second line segment L12, which avoids the problem that the first line segment L11 and the second line segment L12 are wound around the non-display area AA, resulting in that the width of the frame around the non-display area AA is too large, thereby facilitating the narrow frame design around the non-display area AA.

[0122] It should be noted that, please refer to Figure 16 and Figure 17 When the second cross-line 20 is introduced in the display panel to realize the electrical connection between the third line segment L23 and the fourth line segment L24 in the second signal line L2, optionally, the third line segment L23 and the fourth line segment L24 in the second signal line L2 are arranged in the second metal layer M2, or arranged in the third metal layer M3, and can also be arranged in other film layers which do not interfere with the first signal line L1, and the present application does not make specific limitation on this. At this time, the second cross-line 20 can be arranged in the fourth metal layer M4 together with the first cross-line 10, so that two different film layers do not need to be introduced in the display panel to arrange the first cross-line 10 and the second cross-line 20, thereby facilitating the simplification of the film layer complexity of the display panel.

[0123] Based on the same inventive concept, the present application also provides a display device, please refer to Figure 22 , Figure 22 Fig. 1 shows a structure schematic diagram of a display device provided by an embodiment of the present application, and the display device 200 provided by the embodiment of the present application comprises the display panel 100 provided by any of the above embodiments of the present application.

[0124] It can be understood that the display device 200 provided by the embodiment of the present application can be a computer, a mobile phone, a tablet computer, or other display devices with display function, and the present application does not make specific limitation on this. The display device provided by the embodiment of the present application has the beneficial effects of the display panel provided by the embodiment of the present application, and specific description can be referred to the specific description of the display panel in the above embodiments, which will not be described here again.

[0125] In summary, the display panel and the display device provided by the present application at least achieve the following beneficial effects:

[0126] The display panel and the display device provided by the embodiment of the present application are provided with at least two non-display areas, and the display area at least partially surrounds the aforementioned non-display areas. The non-display area at least includes a first non-display area and a second non-display area arranged along a first direction. The display area includes a plurality of first signal lines extending along the first direction. Along the first direction, part of the first signal lines overlaps with the first non-display area and the second non-display area. The part of the first signal lines includes a first line segment and at least one second line segment. The first line segment is located between the two adjacent non-display areas. At least part of the second line segment is located on a side of the first non-display area away from the second non-display area, and / or at least part of the second line segment is located on a side of the second non-display area away from the first non-display area. In order to realize the electrical connection of the first line segment and the second line segment in the first signal line, the present application introduces a first cross line in the display panel. The first cross line is arranged in a layer different from the first line segment and the second line segment in the first signal line. When the first line segment and the second line segment are connected through the first cross line, there is no need to perform wire winding in the frame area of the first non-display area or the second non-display area. The number of wires corresponding to the frame area of the first non-display area and the second non-display area can be reduced, the compression space of the frame of the first non-display area and the second non-display area is provided, and thus the narrow frame design of the hole around the first non-display area and the second non-display area is facilitated, and the screen-to-body ratio of the display panel and the display device is improved.

[0127] Although some specific embodiments of the present application have been described in detail by examples, those skilled in the art should understand that the above examples are only for illustration, but not for limiting the scope of the present application. Those skilled in the art should understand that the above embodiments can be modified without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A display panel, characterized in that, It includes a display area and at least two non-display areas, wherein the non-display areas include at least a first non-display area and a second non-display area arranged adjacent to each other, the first non-display area and the second non-display area are arranged along a first direction, and the display area at least partially surrounds the non-display areas; The display area includes multiple first signal lines extending along the first direction. At least a portion of the first signal lines include a first segment and at least one second segment. The first segment is located between two adjacent non-display areas. At least a portion of the second segment is located on the side of the first non-display area away from the second non-display area along the first direction. And / or, at least a portion of the second segment is located on the side of the second non-display area away from the first non-display area along the first direction. In the same first signal line, the first segment and the second segment are electrically connected by a first crossover wire. The display panel includes multiple pixel driving circuits located in the display area and light-emitting elements electrically connected to the pixel driving circuits. The pixel driving circuits are electrically connected to multiple control lines, and the first signal line includes the control lines. The display panel includes a first border area and a second border area opposite to each other along a first direction. Both the first border area and the second border area include a plurality of shift registers. At least a portion of the control lines are electrically connected to the shift registers located in the first border area, and at least a portion of the control lines are electrically connected to the shift registers located in the second border area. The pixel driving circuit includes a data writing module, a compensation module, a first reset module, a second reset module, a light emission control module, and a voltage adjustment module. The control lines include a first control line connected to the control terminal of the first reset module, a second control line connected to the control terminal of the compensation module, a third control line connected to the control terminals of the second reset module and the voltage adjustment module, a fourth control line connected to the control terminal of the data writing module, and a light emission control line connected to the light emission control module. Two of the first control line, the second control line, the third control line, and the light emission control line are connected to the shift register in the first border area, and the other two are connected to the shift register in the second border area.

2. The display panel according to claim 1, characterized in that, At least a portion of the control lines correspond to the first cross line running from the first non-display area and the second non-display area along the first side of the second direction, and at least a portion of the control lines correspond to the first cross line running from the first non-display area and the second non-display area along the second side of the second direction, the first side and the second side being opposite to each other along the second direction, and the second direction intersecting the first direction.

3. The display panel according to claim 2, characterized in that, The number of first cross lines running from the first non-display area and the second non-display area along the second direction on the first side is the same as the number of first cross lines running from the first non-display area and the second non-display area along the second direction on the second side.

4. The display panel according to claim 1, characterized in that, At least a portion of the fourth control lines connected to the first crossover are connected to a shift register in the first border area, and the remaining fourth control lines connected to the first crossover are connected to a shift register in the second border area.

5. The display panel according to claim 1, characterized in that, It includes multiple pixel rows, and each pixel row includes multiple light-emitting elements; at least one of the first control line, the second control line, the third control line and the light-emitting control line is electrically connected to the pixel driving circuits corresponding to the light-emitting elements in N pixel rows, where N≥2; the fourth control line is electrically connected only to the pixel driving circuits corresponding to the light-emitting elements in the same pixel row.

6. The display panel according to claim 5, characterized in that, The first line segment includes a first end adjacent to the first non-display area and a second end adjacent to the second non-display area; The first end of the N first line segments corresponding to at least one of the first control line, the second control line, the third control line, and the light emission control line in the adjacent N pixel rows is electrically connected, or the second end is electrically connected.

7. The display panel according to claim 1, characterized in that, At least one of the first reset module and the compensation module includes a metal oxide transistor. Between the first non-display area and the second non-display area, along the thickness direction of the display panel, the metal oxide transistor includes an active layer and a first gate and a second gate located on both sides of the active layer. In the same metal oxide transistor, the ends of the first gate and the second gate are electrically connected.

8. The display panel according to claim 1, characterized in that, The first control line, the second control line, the third control line, the fourth control line, and the light emission control line are distributed in at least two different film layers.

9. The display panel according to claim 1, characterized in that, The first span line corresponding to the first control line, the second control line, the third control line, and the light emission control line respectively includes a first sub-first span line and a second sub-first span line; the first end of the first line segment in the first control line, the second control line, the third control line, and the light emission control line is connected to the second line segment located in the first non-display area along the first direction away from the second non-display area through the first sub-first span line, and the second end is connected to the second line segment located in the second display area along the first direction away from the first non-display area through the second sub-first span line.

10. The display panel according to claim 9, characterized in that, At least three pixel columns are provided between the first non-display area and the second non-display area. The first line segment is electrically connected to the first sub-first crossover line through a first hole, and the first line segment is electrically connected to the second sub-first crossover line through a second hole. Along the first direction, the distance between the first hole and the second hole is greater than or equal to the total width of the three consecutive pixel columns.

11. The display panel according to claim 1, characterized in that, The first segment of the fourth control line is electrically connected to the second segment located on one side of the first segment along the first direction via the first crossover.

12. The display panel according to claim 1, characterized in that, In the first cross line connected to the fourth control line, at least a portion of the first cross line is located on the first side of the first line segment along the second direction, and at least a portion of the first cross line is located on the second side of the first line segment along the second direction; In the first cross line connected to at least one of the first control line, the second control line, the third control line, and the light emission control line, at least a portion of the first cross line is located on at least one side of the first line segment along a second direction, the second direction intersecting the first direction.

13. The display panel according to claim 12, characterized in that, At least three pixel columns are provided between the first non-display area and the second non-display area; between the first non-display area and the second non-display area, in the first cross line corresponding to the first control line, the second control line, the third control line, the fourth control line and the light emission control line, the line segment extending along the second direction is located within the range defined by the three consecutive pixel columns.

14. The display panel according to claim 1, characterized in that, The display panel also includes a border area that surrounds the display area in at least a portion, and at least a portion of the first cross line is located in the border area.

15. The display panel according to claim 1, characterized in that, The display area further includes multiple second signal lines extending along a second direction, at least some of which include third and fourth segments arranged along the second direction; along the second direction, the third and fourth segments are located on both sides of the first non-display area or on both sides of the second non-display area, and in the same second signal line, the third and fourth segments are electrically connected by a second crossover line; at least some of the second crossover lines are arranged on the same layer as the first crossover line, and the second direction intersects the first direction.

16. The display panel according to claim 15, characterized in that, The first and second crossovers are set on the same layer.

17. The display panel according to claim 15, characterized in that, The first crossover line is connected to the first signal line through the first connecting hole, and the second crossover line is electrically connected to the second signal line through the second connecting hole; the display panel also includes a plurality of third connecting holes, and the first connecting hole, the second connecting hole, and the third connecting hole do not overlap in the thickness direction of the display panel.

18. The display panel according to claim 15, characterized in that, The second cross line includes a line segment extending along a second direction, which does not overlap with other second signal lines in the thickness direction of the display panel.

19. The display panel according to claim 15, characterized in that, The display panel includes fixed voltage signal lines located in the display area. The fixed voltage signal lines include a first fixed voltage signal line extending along the first direction and a second fixed voltage signal line extending along the second direction. Among the first and second cross lines, at least a portion of the line segment extending along the first direction overlaps with the first fixed voltage signal line along the thickness direction of the display panel, and at least a portion of the line segment extending along the second direction overlaps with the second fixed voltage signal line.

20. The display panel according to claim 15, characterized in that, In the first and second cross lines, at least a portion of the line segment extending along the first direction in the thickness direction of the display panel overlaps with the first signal line.

21. The display panel according to claim 15, characterized in that, The first cross line includes a first sub-segment extending along the first direction and a second sub-segment extending along the second direction; the second cross line includes a third sub-segment extending along the first direction and a fourth sub-segment extending along the second direction; along the thickness direction of the display panel, the first sub-segment and the third sub-segment do not overlap, and the second sub-segment and the fourth sub-segment do not overlap.

22. The display panel according to claim 21, characterized in that, At least a portion of the third sub-segment is located between two adjacent first sub-segments, and at least a portion of the fourth sub-segment is located between two adjacent second sub-segments.

23. The display panel according to claim 15, characterized in that, Along the first direction, the length of the first non-display area is greater than the length of the second non-display area; at least a portion of the second cross line partially surrounds the first cross line on the side of the first non-display area away from the second non-display area.

24. The display panel according to claim 1, characterized in that, The display panel includes a substrate and a transistor layer disposed on the substrate. The transistor layer includes a first type of transistor and a second type of transistor. The display panel includes a first metal layer, a second metal layer, a gate metal layer, a capacitor metal layer, a third metal layer, and a fourth metal layer. The gate of the first type of transistor is located on the first metal layer, the gate of the second type of transistor is located on the gate metal layer, and the source and drain of the first type of transistor and the second type of transistor are located on the second metal layer. The capacitor metal layer is located between the first metal layer and the second metal layer. The third metal layer is located on the side of the second metal layer facing away from the substrate, and the fourth metal layer is located on the side of the third metal layer facing away from the substrate. At least a portion of the line segment in the first cross line is located in the fourth metal layer.

25. A display device, characterized in that, Includes the display panel described in any one of claims 1 to 24.

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