Display substrate and its preparation method, display device

Abstract

A display substrate includes: a substrate, a circuit structure layer, a light-transmitting structure layer, and a light-emitting structure layer. The circuit structure layer is located in a second region and includes a plurality of first pixel circuits. The light-transmitting structure layer is located in a first region and includes a shielding layer and at least one connecting layer. The shielding layer and the at least one connecting layer at least partially overlap in their orthogonal projections onto the substrate. The at least one connecting layer includes a plurality of first connecting lines, at least one of which extends from the first region to the second region. The light-emitting structure layer includes a plurality of first light-emitting elements located in the first region. At least one first light-emitting element is electrically connected to at least one first pixel circuit via at least one first connecting line. The light-emitting structure layer includes a patterned cathode located in the first region. The shielding layer is configured to act as a shielding structure during cathode patterning processing, such that the orthogonal projection of the patterned cathode onto the substrate at least partially overlaps with the orthogonal projection of the shielding layer onto the substrate.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Under-display camera technology is a novel technology proposed to increase the screen-to-body ratio of display devices. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, a method for preparing the same, and a display device.

[0005] In one aspect, embodiments of this disclosure provide a display substrate, comprising: a substrate, a circuit structure layer, a light-transmitting structure layer, and a light-emitting structure layer. The substrate includes a first region and a second region located at least one side of the first region. The circuit structure layer is located in the second region and includes at least a plurality of first pixel circuits. The light-transmitting structure layer is located in the first region and includes a shielding layer and at least one connecting layer. The shielding layer and the at least one connecting layer at least partially overlap in their orthographic projections onto the substrate. The at least one connecting layer includes a plurality of first connecting lines, at least one of which extends from the first region to the second region. The light-emitting structure layer is located on the side of the circuit structure layer and the light-transmitting structure layer away from the substrate and includes at least a plurality of first light-emitting elements located in the first region. At least one of the plurality of first light-emitting elements in the first region is electrically connected to at least one of the plurality of first pixel circuits in the second region via at least one first connecting line. The light-emitting structure layer includes a patterned cathode located in the first region. The shielding layer is configured as a shielding structure in the cathode patterning process, such that the orthographic projection of the patterned cathode on the substrate at least partially overlaps with the orthographic projection of the shielding layer on the substrate.

[0006] In some exemplary embodiments, the shielding layer is located on the side of the at least one connecting layer close to the substrate.

[0007] In some exemplary embodiments, the material of the at least one connecting layer is a metallic material or an oxide material.

[0008] In some exemplary embodiments, the shielding layer includes: a shielding strip extending along a first direction, and a plurality of shielding blocks connected to the shielding strip. Within the first region, the orthographic projection of at least one first connecting line of the at least one connecting layer along the first direction onto the substrate lies within the range of the orthographic projection of the shielding strip onto the substrate.

[0009] In some exemplary embodiments, the first region includes a first sub-region and a second sub-region, the second sub-region being located on at least one side of the first sub-region. The shielding layer of the second sub-region includes a shielding strip extending along a first direction and a plurality of shielding blocks connected to the shielding strip; the shielding layer of the first sub-region includes a plurality of independently disposed shielding blocks.

[0010] In some exemplary embodiments, the material of the first connecting line electrically connected to at least one first light-emitting element in the second sub-region is different from the material of the first connecting line electrically connected to at least one first light-emitting element in the first sub-region.

[0011] In some exemplary embodiments, the shielding strip and the connected plurality of shielding blocks are an integral structure.

[0012] In some exemplary embodiments, the light-emitting structure layer further includes: a patterned anode located in the first region, wherein the orthographic projection of the anode in the first region onto the substrate is within the range of the orthographic projection of the shielding layer onto the substrate.

[0013] In some exemplary embodiments, the circuit structure layer includes: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on the substrate. The shielding layer is disposed in the same layer as one of the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer, and the at least one connecting layer is located in a different layer from the shielding layer.

[0014] In some exemplary embodiments, the circuit structure layer further includes: a first transparent conductive layer, a second transparent conductive layer, and a third transparent conductive layer located on the side of the fourth conductive layer away from the substrate. The at least one connection layer is disposed in the same layer as at least one of the first transparent conductive layer, the second transparent conductive layer, and the third transparent conductive layer.

[0015] In some exemplary embodiments, the plurality of first light-emitting elements in the first region include a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, a first light-emitting element emitting a third color light, and a first light-emitting element emitting a fourth color light. The shielding layer includes at least a first shielding block, a second shielding block, a third shielding block, and a fourth shielding block; the first shielding block, the second shielding block, the third shielding block, and the fourth shielding block are disposed along a first direction. The orthographic projection of the anode of the first light-emitting element emitting the first color light onto the substrate is located within the orthographic projection range of the first shielding block onto the substrate; the orthographic projection of the anode of the first light-emitting element emitting the second color light onto the substrate is located within the orthographic projection range of the second shielding block onto the substrate; the orthographic projection of the anode of the first light-emitting element emitting the third color light onto the substrate is located within the orthographic projection range of the third shielding block onto the substrate; and the orthographic projection of the anode of the first light-emitting element emitting the fourth color light onto the substrate is located within the orthographic projection range of the fourth shielding block onto the substrate.

[0016] In some exemplary embodiments, the shielding layer further includes a shielding strip connecting the first shielding block, the second shielding block, the third shielding block, and the fourth shielding block. The first shielding block, the second shielding block, and the third shielding block are located on one side of the shielding strip in a second direction, and the fourth shielding block is located on the other side of the shielding strip in the second direction; the second direction intersects the first direction.

[0017] In some exemplary embodiments, the shielding layer further includes a shielding strip connecting the first shielding block, the second shielding block, the third shielding block, and the fourth shielding block. The first shielding block and the third shielding block are located on one side of the shielding strip in a second direction, and the second shielding block and the fourth shielding block are located on the other side of the shielding strip in the second direction; the second direction intersects the first direction.

[0018] In some exemplary embodiments, the shielding layer is located on the side of the at least one connecting layer away from the substrate; the shielding layer includes a cutout portion, and the at least one first connecting line is electrically connected to the anode of the first light-emitting element through an anode connection via, wherein the orthogonal projection of the anode connection via on the substrate is located within the orthogonal projection range of the cutout portion.

[0019] On the other hand, this disclosure provides a display device, including: a display substrate as described above, and a sensor located on the non-display side of the display substrate, wherein the orthographic projection of the sensor onto the display substrate overlaps with a first region of the display substrate.

[0020] On the other hand, this disclosure provides a method for fabricating a display substrate, the display substrate including a first region and a second region located at least one side of the first region. The fabrication method includes: forming a light-transmitting structural layer on a substrate in the first region, and forming a circuit structural layer on a substrate in the second region; forming a light-emitting structural layer on the side of the circuit structural layer and the light-transmitting structural layer away from the substrate, the light-emitting structural layer including at least a plurality of first light-emitting elements located in the first region; and forming a patterned cathode of the light-emitting structural layer in the first region. The circuit structural layer includes at least a plurality of first pixel circuits; the light-transmitting structural layer includes: a shielding layer and at least one connecting layer, the at least one connecting layer including a plurality of first connecting lines, at least one of the plurality of first connecting lines extending from the first region to the second region; the shielding layer and the at least one connecting layer at least partially overlap in their orthographic projections onto the substrate. At least one of the plurality of first light-emitting elements in the first region is electrically connected to at least one of the plurality of first pixel circuits in the second region via the at least one first connecting line. The shielding layer is configured as a shielding structure in the cathode patterning process, such that the orthographic projection of the patterned cathode on the substrate at least partially overlaps with the orthographic projection of the shielding layer on the substrate.

[0021] In some exemplary embodiments, a light-transmitting structure layer is formed on a substrate in the first region, and a circuit structure layer is formed on a substrate in the second region. This includes: forming a semiconductor layer on the substrate in the second region, the semiconductor layer including at least an active layer of a transistor in a first pixel circuit; simultaneously forming a shielding layer in the first region and a second conductive layer in the second region, the second conductive layer including a gate electrode of a transistor in the first pixel circuit and a first electrode of a storage capacitor; simultaneously forming a connection layer in the first region and a third conductive layer in the second region, the third conductive layer including a second electrode of a storage capacitor in the first pixel circuit; and forming a fourth conductive layer in the second region, the fourth conductive layer including a first electrode and a second electrode of a transistor in the first pixel circuit.

[0022] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0023] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0024] Figure 1This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0025] Figure 2 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0026] Figure 3 This is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0027] Figure 4 This is a partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0028] Figure 5A and Figure 5B This is a plan view of the shielding layer of the first display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0029] Figure 6 This is a partial planar schematic diagram of the shielding layer according to at least one embodiment of the present disclosure;

[0030] Figure 7 This is a partial planar schematic diagram of the first display area after the connection layer is formed, according to at least one embodiment of the present disclosure;

[0031] Figure 8 This is a partial planar schematic diagram of the first display area after the formation of the anode layer according to at least one embodiment of the present disclosure;

[0032] Figure 9 This is a partial planar schematic diagram of the first display area after forming a pixel definition layer according to at least one embodiment of the present disclosure;

[0033] Figure 10 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0034] Figure 11 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0035] Figure 12 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0036] Figure 13 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0037] Figure 14 This is another partial plan view of the first display area after the formation of the anode layer according to at least one embodiment of the present disclosure;

[0038] Figure 15A and Figure 15B Another planar schematic diagram of the shielding layer of the first display area of ​​the display substrate of at least one embodiment of the present disclosure;

[0039] Figure 16 This is another partial planar schematic diagram of the shielding layer according to at least one embodiment of the present disclosure;

[0040] Figure 17 This is another partial planar schematic diagram of the shielding layer according to at least one embodiment of the present disclosure;

[0041] Figures 18A to 18D This is a partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0042] Figure 19 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0043] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0044] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0045] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0046] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0047] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0048] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0049] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0050] In this specification, to distinguish the two terminals of a transistor other than the gate, one electrode is referred to as the first terminal and the other as the second terminal. The first terminal can be either the source or the drain, and the second terminal can be either the drain or the source. The gate of the transistor is referred to as the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0051] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0052] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0053] In this disclosure, "light transmittance" refers to the ability of light to pass through a medium, and is the percentage of light flux passing through a transparent or translucent body relative to the incident light flux.

[0054] In this disclosure, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0055] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main part of A extends along direction B".

[0056] For products such as smart terminals, it is usually necessary to set up hardware such as front-facing cameras, fingerprint sensors or light sensors. In order to improve the screen ratio, full-screen or narrow-bezel products usually adopt under-display fingerprint or under-display camera technology.

[0057] This disclosure provides a display substrate, comprising: a substrate, a circuit structure layer, a light-transmitting structure layer, and a light-emitting structure layer. The substrate includes a first region and a second region located at least one side of the first region. The circuit structure layer is located in the second region and includes at least a plurality of first pixel circuits. The light-transmitting structure layer is located in the first region and includes a shielding layer and at least one connecting layer. The shielding layer and the at least one connecting layer at least partially overlap in their orthogonal projections onto the substrate. The at least one connecting layer includes a plurality of first connecting lines, at least one of which extends from the first region to the second region. The light-emitting structure layer is located on the side of the circuit structure layer and the light-transmitting structure layer away from the substrate and includes at least a plurality of first light-emitting elements located in the first region. At least one of the plurality of first light-emitting elements in the first region is electrically connected to at least one of the plurality of first pixel circuits in the second region via at least one first connecting line. The light-emitting structure layer includes a patterned cathode located in the first region. The shielding layer is configured as a shielding structure in the cathode patterning process, such that the orthogonal projection of the patterned cathode onto the substrate at least partially overlaps with the orthogonal projection of the shielding layer onto the substrate.

[0058] The display substrate provided in this embodiment uses a first connecting line provided with at least one connecting layer to electrically connect a first light-emitting element located in a first region and a first pixel circuit located in a second region. The shielding layer and the orthogonal projection of at least one connecting layer on the substrate at least partially overlap, which can improve the influence of the arrangement of the first connecting line on the light transmittance of the first region.

[0059] In some exemplary embodiments, the material of at least one interconnect layer can be a metallic material or an oxide material. For example, oxide materials may include indium tin oxide (ITO) and indium gallium zinc oxide (IGZO).

[0060] In some examples, the display substrate may include one or more interconnect layers made of a metallic material. Electrical connections between the plurality of first pixel circuits and the plurality of first light-emitting elements can be achieved entirely through first interconnect lines made of a metallic material. In other examples, the display substrate may include multiple interconnect layers made of an oxide material. Electrical connections between the plurality of first pixel circuits and the plurality of first light-emitting elements can be achieved entirely through transparent first interconnect lines made of an oxide material. In still other examples, the display substrate may include at least one interconnect layer made of a metallic material and at least one interconnect layer made of an oxide material. Electrical connections between a portion of the first pixel circuits and a portion of the first light-emitting elements can be achieved through first interconnect lines made of a metallic material, while electrical connections between another portion of the first pixel circuits and another portion of the first light-emitting elements can be achieved through transparent first interconnect lines made of an oxide material. This embodiment is not limited in this respect.

[0061] In some examples, the display substrate includes one or more interconnect layers made of a metallic material, which can reduce the use of transparent conductive layers, thereby reducing the fabrication process and improving production capacity. Furthermore, by using one or more interconnect layers made of a metallic material, it is possible to increase the number of interconnect lines between the first light-emitting element and the first pixel circuit, which helps to increase the size of the first region.

[0062] In some exemplary embodiments, the shielding layer may be located on the side of at least one interconnecting layer closer to the substrate. For example, the circuit structure layer may include at least: a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on the substrate. The shielding layer may be disposed on the same layer as one of the first, second, third, fourth, and fifth conductive layers and formed simultaneously in the same patterning process. The interconnecting layer may be located on a different layer than the shielding layer. For example, the shielding layer may be disposed on the same layer as the first conductive layer, and the interconnecting layer may be disposed on the same layer as any one of the second to fifth conductive layers. Alternatively, the shielding layer may be disposed on the same layer as the second conductive layer, and the interconnecting layer may be disposed on the same layer as any one of the third to fifth conductive layers. However, this embodiment is not limited to this. In other examples, the shielding layer may be located on the side of the interconnecting layer away from the substrate. For example, the shielding layer can be disposed on the same layer as the fifth conductive layer and formed simultaneously through the same patterning process, and the connecting layer can be disposed on the same layer as any of the first to fourth conductive layers and formed simultaneously through the same patterning process.

[0063] In some exemplary embodiments, the shielding layer may include: a shielding strip extending along a first direction, and a plurality of shielding blocks connected to the shielding strip. Within the first region, the orthographic projection of the extension portion of at least one first connecting line of at least one connecting layer along the first direction onto the substrate may fall within the range of the orthographic projection of the shielding strip onto the substrate. This example uses the shielding strip of the shielding layer to at least partially shield the first connecting line of the connecting layer, which can prevent the connecting layer from affecting the light transmittance of the first region and can fully utilize space for wiring arrangement.

[0064] In some exemplary embodiments, the first region may include a first sub-region and a second sub-region, the second sub-region being located at least one side of the first sub-region. The shielding layer of the second sub-region may include a shielding strip extending along a first direction and a plurality of shielding blocks connected to the shielding strip; the shielding layer of the first sub-region may include a plurality of independently disposed shielding blocks. In this example, removing the shielding strip from the shielding layer of a local area within the first region can help improve the diffraction caused by numerous shielding strips. In some examples, the material of the first connecting line electrically connecting at least one first light-emitting element in the second sub-region may be different from the material of the first connecting line electrically connecting at least one first light-emitting element in the first sub-region. For example, at least one first light-emitting element in the second sub-region can be electrically connected to at least one first pixel circuit in the second region via a first connecting line made of a metallic material, or at least one first light-emitting element in the first sub-region can be electrically connected to at least one first pixel circuit in the second region via a first connecting line made of an oxide material. This can improve the light transmittance of the first region and improve the diffraction situation. However, this embodiment is not limited to this. In other examples, at least one first light-emitting element in the first sub-region can also be electrically connected to at least one first pixel circuit in the second region via a first connecting line made of a metallic material.

[0065] In some exemplary embodiments, the light-emitting structure layer may further include: a patterned anode located in a first region, wherein the orthographic projection of the anode in the first region onto the substrate lies within the range of the orthographic projection of the shielding layer onto the substrate. This example, by covering the anode in the first region with the shielding layer, can protect the anode in the first region and ensure the light transmittance of the first region, and can also prevent the cathode patterning process from affecting the anode.

[0066] The following examples illustrate the solution of this embodiment.

[0067] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, such as Figure 1As shown, the display substrate may include a display area AA and a peripheral area BB surrounding the display area AA. The display area AA of the display substrate may include a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. In this example, the second display area A2 may surround the perimeter of the first display area A1. In this example, the aforementioned first area may be the first display area A1, and the aforementioned second area may be the second display area A2. In other examples, the aforementioned second area may be the peripheral area BB.

[0068] In some examples, such as Figure 1 As shown, the first display area A1 can be a light-transmitting display area, also known as an under-display camera (FDC) area, configured for image display and light transmission; the second display area A2 can be a normal display area, configured for image display. For example, the orthographic projection of a sensor (such as a camera) onto the display substrate can be located within the first display area A1 of the display substrate. In some examples, such as... Figure 1 As shown, the first display area A1 can be circular, and the size of the sensor's orthographic projection on the display substrate can be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 can be rectangular, and the size of the sensor's orthographic projection on the display substrate can be less than or equal to the size of the inscribed circle of the first display area A1.

[0069] In some examples, such as Figure 1 As shown, the ratio of the resolution of the second display area A2 to the resolution of the first display area A1 can be approximately 0.8 to 1.2. Alternatively, the resolution of the second display area A2 can be approximately the same as the resolution of the first display area A1. The resolution of the first display area A1 can, for example, be greater than 400.

[0070] In some examples, such as Figure 1 As shown, the first display area A1 can be located at the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 can be located at other positions such as the upper left or upper right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0071] In some examples, such as Figure 1 As shown, the display area AA can be rectangular, such as a rounded rectangle. The first display area A1 can be circular or elliptical. However, this embodiment is not limited to this. For example, the first display area A1 can be other shapes such as rectangle, semicircle, pentagon, etc.

[0072] In some examples, the display area AA can be provided with multiple sub-pixels. At least one sub-pixel can include pixel circuitry and a light-emitting element. The pixel circuitry can be configured to drive the connected light-emitting element. For example, the pixel circuitry is configured to provide drive current to drive the light-emitting element to emit light. The pixel circuitry can include multiple transistors and at least one capacitor; for example, the pixel circuitry can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Here, in the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0073] In some examples, the multiple transistors in the pixel circuit can be either P-type or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the manufacturing process, reduces the complexity of the display substrate manufacturing, and improves product yield. In other examples, the multiple transistors in the pixel circuit can include both P-type and N-type transistors.

[0074] In some examples, the multiple transistors in the pixel circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate—an LTPS+Oxide (LTPO) display substrate—leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0075] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0076] In some examples, a pixel unit of the display area AA may include three sub-pixels, which may be red, green, and blue sub-pixels respectively. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, which may be red, green, blue, and white sub-pixels respectively.

[0077] In some examples, the shape of the light-emitting element can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement. When a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0078] Figure 2 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of this exemplary embodiment is described using a 7T1C structure as an example. However, this embodiment is not limited thereto.

[0079] In some examples, such as Figure 2 As shown, the pixel circuit of this example may include six switching transistors (T1, T2, T4 to T7), a driving transistor T3, and a storage capacitor Cst. The six switching transistors are a data write transistor T4, a threshold compensation transistor T2, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, and a second reset transistor T7. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0080] In some examples, such as Figure 2As shown, the display substrate may include: a scan line GL, a data line DL, a first power line PL1, a second power line PL2, a light emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. In some examples, the first power line PL1 may be configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 may be configured to provide a constant second voltage signal VSS to the pixel circuit, wherein the first voltage signal VDD is greater than the second voltage signal VSS. The scan line GL may be configured to provide a scan signal SCAN to the pixel circuit, the data line DL may be configured to provide a data signal DATA to the pixel circuit, the light emission control line EML may be configured to provide a light emission control signal EM to the pixel circuit, the first reset control line RST1 may be configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 may be configured to provide a second reset control signal RESET2 to the pixel circuit. In some examples, in the nth row pixel circuit, the first reset control line RST1 can be electrically connected to the scan line GL of the (n-1)th row pixel circuit to be input to the scan signal SCAN(n-1), i.e., the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). The second reset control line RST2 can be electrically connected to the scan line GL of the nth row pixel circuit to be input to the scan signal SCAN(n), i.e., the second reset control signal RESET2(n) is the same as the scan signal SCAN(n). In some examples, the second reset control line RST2 electrically connected to the nth row pixel circuit and the first reset control line RST1 electrically connected to the (n+1)th row pixel circuit can be a single structure. Here, n is an integer greater than 0. In this way, the signal lines of the display substrate can be reduced, realizing a narrow bezel design of the display substrate. However, this embodiment is not limited to this.

[0081] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. The first and second initial signals can be constant voltage signals, the magnitude of which may be, for example, between a first voltage signal VDD and a second voltage signal VSS, but are not limited thereto. In other examples, the first and second initial signals may be the same, and only the first initial signal line may be configured to provide the first initial signal.

[0082] In some examples, such as Figure 2As shown, the driving transistor T3 is electrically connected to the light-emitting element EL, and outputs a driving current to drive the light-emitting element EL to emit light under the control of signals such as the scan signal SCAN, data signal DATA, first voltage signal VDD, and second voltage signal VSS. The gate of the data writing transistor T4 is electrically connected to the scan line GL, the first terminal of the data writing transistor T4 is electrically connected to the data line DL, and the second terminal of the data writing transistor T4 is electrically connected to the first terminal of the driving transistor T3. The gate of the threshold compensation transistor T2 is electrically connected to the scan line GL, the first terminal of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second terminal of the threshold compensation transistor T2 is electrically connected to the second terminal of the driving transistor T3. The gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control line EML, the first terminal of the first light-emitting control transistor T5 is electrically connected to the first power supply line PL1, and the second terminal of the first light-emitting control transistor T5 is electrically connected to the first terminal of the driving transistor T3. The gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control line EML. The first terminal of the second light-emitting control transistor T6 is electrically connected to the second terminal of the driving transistor T3. The second terminal of the second light-emitting control transistor T6 is electrically connected to the anode of the light-emitting element EL. The first reset transistor T1 is electrically connected to the gate of the driving transistor T3 and is configured to reset the gate of the driving transistor T3. The second reset transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the anode of the light-emitting element EL. The gate of the first reset transistor T1 is electrically connected to the first reset control line RST1. The first terminal of the first reset transistor T1 is electrically connected to the first initial signal line INIT1. The second terminal of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3. The gate of the second reset transistor T7 is electrically connected to the second reset control line RST2. The first terminal of the second reset transistor T7 is electrically connected to the second initial signal line INIT2. The second terminal of the second reset transistor T7 is electrically connected to the anode of the light-emitting element EL. The first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and the second capacitor plate of the storage capacitor Cst is electrically connected to the first power supply line PL1.

[0083] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3, and the threshold compensation transistor T2; the second node N2 is the connection point of the first light-emitting control transistor T5, the data writing transistor T4, and the driving transistor T3; the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2, and the second light-emitting control transistor T6; and the fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7, and the light-emitting element EL. The fourth node N4 is the anode connection node.

[0084] The following is about Figure 2 The working process of the pixel circuit is illustrated below. Figure 2 The pixel circuit shown is illustrated using P-type transistors as an example.

[0085] In some exemplary embodiments, the operation of the pixel circuit during a frame display period may include a first stage, a second stage, and a third stage.

[0086] The first stage is called the reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first reset transistor T1. The first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize the first node N1 and clear the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is a high-level signal, and the light emission control signal EM provided by the light emission control line EML is a high-level signal, turning off the data writing transistor T4, the threshold compensation transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7. During this stage, the light-emitting element EL does not emit light.

[0087] The second stage is called the data writing stage or threshold compensation stage. The scan signal SCAN provided by the scan line GL is a low-level signal, while the first reset control signal RESET1 provided by the first reset control line RST1 and the light emission control signal EM provided by the light emission control line EML are both high-level signals. The data line DL outputs the data signal DATA. During this stage, because the first capacitor plate of the storage capacitor Cst is low, the driving transistor T3 is turned on. The low-level scan signal SCAN turns on the threshold compensation transistor T2, the data writing transistor T4, and the second reset transistor T7. Threshold compensation transistor T2 and data write transistor T4 are turned on, allowing the data voltage Vdata output from data line DL to be supplied to first node N1 via second node N2, the turned-on drive transistor T3, third node N3, and the turned-on threshold compensation transistor T2. The difference between the data voltage Vdata output from data line DL and the threshold voltage of drive transistor T3 is charged into storage capacitor Cst. The voltage at the first capacitor plate of storage capacitor Cst (i.e., first node N1) is Vdata - |Vth|, where Vdata is the data voltage output from data line DL and Vth is the threshold voltage of drive transistor T3. Second reset transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the anode of light-emitting element EL, initializing (resetting) the anode of light-emitting element EL, clearing its internal pre-stored voltage, completing the initialization, and ensuring that light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, causing the first reset transistor T1 to turn off. The light emission control signal EM provided by the light emission control signal line EML is a high-level signal, which disconnects the first light emission control transistor T5 and the second light emission control transistor T6.

[0088] The third stage is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, while the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. When the light-emitting control signal EM provided by the light-emitting control signal line EML is low, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on. The first voltage signal VDD output from the first power supply line PL1 provides a driving voltage to the anode of the light-emitting element EL through the turned-on first light-emitting control transistor T5, driving transistor T3, and second light-emitting control transistor T6, driving the light-emitting element EL to emit light.

[0089] During the pixel circuit driving process, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and first terminal. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the driving transistor T3 is:

[0090] I = K × (Vgs - Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 .

[0091] Where I is the driving current flowing through the driving transistor T3, which is also the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0092] As can be seen from the above formula, the current flowing through the light-emitting element EL is independent of the threshold voltage of the driving transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the driving transistor T3.

[0093] Figure 3 This is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, such as... Figure 3 As shown, the second display area A2 of the display substrate may include a transition area A2a and a non-transition area A2b. The transition area A2a may be located on at least one side outside the first display area A1 (e.g., one side; or, the left and right sides; or, the four sides, i.e., including the top and bottom sides and the left and right sides).

[0094] In some examples, such as Figure 3As shown, the first display area A1 may include a plurality of first light-emitting elements 10 arranged in an array. The transition area A2a of the second display area A2 may include a plurality of first pixel circuits 41 and a plurality of second pixel circuits 42 arranged in an array, and may also include a plurality of second light-emitting elements (not shown). At least one first pixel circuit 41 in the transition area A2a may be electrically connected to at least one first light-emitting element 10 via a connecting line L, and is configured to drive the at least one first light-emitting element 10 to emit light. For example, one first pixel circuit 41 may be configured to drive two, three, or four first light-emitting elements 10 emitting the same color light to emit light. The orthographic projection of the first light-emitting element 10 onto the substrate and the orthographic projection of the electrically connected first pixel circuit 41 onto the substrate may not overlap. At least one second pixel circuit 42 in the transition area A2a may be electrically connected to at least one second light-emitting element, and is configured to drive the at least one second light-emitting element to emit light. For example, one second pixel circuit 42 may be configured to drive one second light-emitting element to emit light. The orthographic projection of the second pixel circuit 42 onto the substrate and the orthographic projection of the electrically connected second light-emitting element onto the substrate may at least partially overlap. In this example, by placing the first pixel circuit 41 that drives the first light-emitting element in the transition region A2a, the occlusion of light by the pixel circuit can be reduced, thereby increasing the light transmittance of the first display area A1.

[0095] In some examples, such as Figure 3 As shown, the non-transition region A2b may include an array of multiple second pixel circuits 42 and multiple invalid pixel circuits 43, and may also include multiple second light-emitting elements. The transition region A2a may also include multiple invalid pixel circuits 43. By setting invalid pixel circuits 43, the uniformity of components in multiple film layers during the etching process can be improved. For example, the structure of invalid pixel circuit 43 may be substantially the same as that of the first pixel circuit 41 and the second pixel circuit 42 in the same row or column, except that it is not electrically connected to any light-emitting element.

[0096] In some examples, since the second display area A2 is provided with not only a second pixel circuit 42 electrically connected to the second light-emitting element, but also a first pixel circuit 41 electrically connected to the first light-emitting element 10, the number of pixel circuits in the second display area A2 can be greater than the number of second light-emitting elements. In some examples, such as... Figure 3 As shown, the area for setting the new pixel circuit (including the first pixel circuit and the invalid pixel circuit) can be obtained by reducing the size of the second pixel circuit in the first direction D1. For example, the size of the pixel circuit in the first direction D1 can be smaller than the size of the second light-emitting element in the first direction D1. In this example, as... Figure 3As shown, the original 'a' column pixel circuits can be compressed along the first direction D1, thereby adding space for one more column of pixel circuits. The space occupied by the 'a' column pixel circuits before compression and the 'a+1' column pixel circuits after compression can be the same. Here, 'a' can be an integer greater than 1. In some examples, 'a' can be equal to 4. However, this embodiment is not limited to this. For example, 'a' can be equal to 2 or 3.

[0097] In other examples, the original b rows of pixel circuits can be compressed along the second direction D2 to add space for a new row of pixel circuits, and the space occupied by the original b rows of pixel circuits and the compressed b+1 rows of pixel circuits is the same. Here, b can be an integer greater than 1. Alternatively, the area for setting the new pixel circuits can be obtained by reducing the size of the second pixel circuits along the first direction D1 and the second direction D2.

[0098] In this embodiment of the disclosure, a row of pixel circuits may include a plurality of pixel circuits arranged sequentially along a first direction D1. Each row of pixel circuits may be adjacent to the same gate line (e.g., a scan line). A row of light-emitting elements may include a plurality of first light-emitting elements and a plurality of second light-emitting elements arranged along the first direction D1.

[0099] Figure 4 This is a partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 4 The diagram illustrates the structure of four first light-emitting elements (e.g., a first light-emitting element 311 emitting a first color light, a first light-emitting element 312 emitting a second color light, a first light-emitting element 313 emitting a third color light, and a first light-emitting element 314 emitting a fourth color light) in the first display area A1 and a sub-pixel in the second display area A2.

[0100] In some examples, in the direction perpendicular to the display substrate, such as Figure 4 As shown, the first display area A1 may include a light-transmitting structure layer 201 disposed on the substrate 100 and a light-emitting structure layer 202 located on the side of the light-transmitting structure layer 201 away from the substrate 100; the second display area A2 may include a circuit structure layer 203 disposed on the substrate 100 and a light-emitting structure layer 202 located on the side of the circuit structure layer 203 away from the substrate 100.

[0101] In some examples, such as Figure 4As shown, the light-emitting structure layer 202 of the first display area A1 and the second display area A2 may include: an anode layer, a pixel definition layer 36, an organic light-emitting layer 37, and a cathode layer 38. The organic light-emitting layer 37 can emit light under the drive of the anode layer and the cathode layer 38. The anode layer of the first display area A1 may include: the anode of the first light-emitting element (e.g., including: the first anode 31 of the first light-emitting element 311 emitting first color light, the second anode 32 of the first light-emitting element 312 emitting second color light, the third anode 33 of the first light-emitting element 313 emitting third color light, and the fourth anode 34 of the first light-emitting element 314 emitting fourth color light); the anode layer of the second display area A2 may include: the anode of the second light-emitting element (e.g., the fifth anode 35 of the second light-emitting element of a sub-pixel). The cathode layer 38 of the first display area A1 may include: a patterned first cathode layer 381. The cathode layer 38 of the second display area A2 may include a second cathode layer 382, ​​which may be a full-surface structure.

[0102] In some examples, such as Figure 4 As shown, the circuit structure layer 203 of the second display area A2 may include: a plurality of transistors and storage capacitors constituting pixel circuits. Figure 4 This example uses only one transistor and one storage capacitor from a pixel circuit. The circuit structure layer 203 of the second display area A2 may include: a semiconductor layer, a first insulating layer 101, a second conductive layer (also referred to as a first gate metal layer), a second insulating layer 102, a third conductive layer (also referred to as a second gate metal layer), a third insulating layer 103, a fourth conductive layer (also referred to as a first source / drain metal layer), a fourth insulating layer 104, a fifth conductive layer (also referred to as a second source / drain metal layer), and a fifth insulating layer 105, sequentially disposed on the substrate 100. The semiconductor layer may include: the active layer of the transistor in the pixel circuit of the second display area A2. The second conductive layer may include: the gate electrode of the transistor in the pixel circuit and the first electrode of the storage capacitor. The third conductive layer may include: the second electrode of the storage capacitor in the pixel circuit. The fourth conductive layer may include: the first and second electrodes of the transistor in the pixel circuit. The fifth conductive layer may include: a first anode connection electrode 301, configured to electrically connect the anode of the second light-emitting element and the second pixel circuit.

[0103] In some examples, such as Figure 4As shown, the light-transmitting structure layer 201 of the first display area A1 may include: a first insulating layer 101, a shielding layer 51, a second insulating layer 102, a connecting layer 52, a third insulating layer 103, a fourth insulating layer 104, and a fifth insulating layer 105 sequentially disposed on the substrate 100. This example uses a connecting layer as an example. The connecting layer 52 and the third conductive layer of the circuit structure layer 203 can be disposed on the same layer. The connecting layer 52 may include multiple first connecting lines, which can extend from the first display area A1 to the second display area A2, so as to electrically connect the first light-emitting element of the first display area A1 and the first pixel circuit of the second display area A2. The shielding layer 51 can be disposed on the same layer as the second conductive layer of the circuit structure layer 203. The shielding layer 51 can be configured as a mask structure in subsequent cathode patterning processing, so that the orthographic projection of the patterned cathode on the substrate 100 and the orthographic projection of the shielding layer 51 on the substrate 100 can substantially completely overlap. The orthographic projections of the shielding layer 51 and the connecting layer 52 onto the substrate 100 may at least partially overlap. For example, within the first display area A1, the orthographic projection of the connecting layer 52 onto the substrate 100 may be located within the orthographic projection range of the shielding layer 51 onto the substrate 100. In other examples, the display substrate may be provided with two or three connecting layers. For instance, two connecting layers may be disposed co-layered with the third conductive layer and the fourth conductive layer, respectively, and three connecting layers may be disposed co-layered with the third conductive layer, the fourth conductive layer, and the fifth conductive layer, respectively. In this example, the use of connecting layers to provide the first connecting lines electrically connecting the first pixel circuit and the first light-emitting element is advantageous in increasing the number of first connecting lines, thereby facilitating an increase in the size of the first display area. Moreover, by using connecting layers disposed co-layered with at least one conductive layer in the circuit structure layer of the second display area, the number of process fabrication steps can be reduced, which is beneficial for increasing production capacity.

[0104] The structure and fabrication process of the display substrate are described below by way of example. The "patterning process" described in the embodiments of this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." In this embodiment of the disclosure, "A and B are in the same layer" or "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, or the surfaces of A and B closest to the substrate are substantially the same distance from the substrate, or the surfaces of A and B closest to the substrate are in direct contact with the same film layer. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0105] In some exemplary embodiments, the fabrication process of the display substrate may include the following operations.

[0106] (1) Providing a substrate. In some examples, the substrate 100 can be a flexible substrate or a rigid substrate. For example, a rigid substrate can be made of materials such as glass or quartz. A flexible substrate can be made of materials such as polyimide (PI), and the flexible substrate can be a single-layer structure or a stacked structure composed of inorganic material layers and flexible material layers. However, this embodiment is not limited in this respect.

[0107] (2) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on the substrate 100 of the second display area A2, and the semiconductor thin film is patterned by a patterning process to form a semiconductor layer in the second display area A2. For example, the semiconductor layer of the second display area may include: the active layer of the transistors of the pixel circuit.

[0108] In some examples, the material of the semiconductor layer may include, for example, polycrystalline silicon. The active layer may include at least one channel region and a first region and a second region located at both ends of the channel region. The channel region may be undoped and possess semiconductor properties. The first and second regions may be located on opposite sides of the channel region and are doped with impurities, thus becoming conductive. The impurities may vary depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as source or drain electrodes of the transistor. Portions of the active layer between transistors may be interpreted as doped wiring that can be used to electrically connect the transistors.

[0109] (3) Forming a second conductive layer and a shielding layer. In some examples, a first insulating film and a second conductive film are sequentially deposited on the substrate 100 on which the aforementioned structure is formed. The second conductive film is patterned by a patterning process to form a first insulating layer 101 covering the semiconductor layer, a second conductive layer disposed on the first insulating layer 101 of the second display area A2, and a shielding layer 51 disposed on the first insulating layer 101 of the first display area A1, such as... Figure 4 As shown. For example, the second conductive layer of the second display area A2 may include at least: the gate electrode of the transistor of the pixel circuit in the second display area and the first plate of the storage capacitor.

[0110] Figure 5A and Figure 5B This is a plan view of the shielding layer of the first display area of ​​a display substrate according to at least one embodiment of the present disclosure. Figure 6 This is a partial planar schematic diagram of the shielding layer according to at least one embodiment of the present disclosure. Figure 5A As shown, the first display area can be rectangular; for example... Figure 5B As shown, the first display area can be circular or elliptical. Figure 6 The diagram illustrates the structure of the shielding layer for two pixel units (including eight first light-emitting elements, the first pixel circuits corresponding to the eight first light-emitting elements being located in the second display area) in the first display area. Figure 6 The two pixel units corresponding to the illustrated occlusion layer can be sequentially arranged along the second direction D2. Each pixel unit includes four first light-emitting elements, and the four first light-emitting elements in each pixel unit can be sequentially arranged along the first direction D1. The first direction D1 intersects with the second direction D2. For example, the first direction D1 can be a horizontal direction, and the second direction D2 can be a vertical direction.

[0111] In some examples, such as Figure 6As shown, the shielding layer may include: a first shielding block 511, a second shielding block 512, a third shielding block 513, a fourth shielding block 514, and a shielding strip 510. The shielding strip 510 may be a strip-shaped structure extending along a first direction D1. The block-shaped first shielding block 511, second shielding block 512, third shielding block 513, and fourth shielding block 514 may be arranged along the first direction D1 and are all connected to the shielding strip 510 to form an interconnected integral structure. For example, the first shielding block 511 and the third shielding block 513 may be connected to the shielding strip 510 via connecting strips, and the second shielding block 512 and the fourth shielding block 514 may be directly connected to the shielding strip 510. The first blocking block 511, the second blocking block 512, and the third blocking block 513 can be located on one side of the connected blocking strip 510 along the second direction D2, and the fourth blocking block 514 can be located on the other side of the connected blocking strip 510 along the second direction D2.

[0112] In some examples, such as Figure 6 As shown, on a plane parallel to the substrate, the first shielding block 511 can be approximately elliptical in shape, while the second shielding block 512, the third shielding block 513, and the fourth shielding block 514 can be approximately circular in shape. However, this embodiment is not limited in this respect. For example, the shapes of the first to fourth shielding blocks can include any one or more of the following: rectangle, square, pentagon, and hexagon.

[0113] (4) Forming a third conductive layer and a connecting layer. In some examples, a second insulating film and a third conductive film are sequentially deposited on the substrate 100 on which the aforementioned structure is formed. The third conductive film is patterned using a patterning process to form a second insulating layer 102, a third conductive layer disposed on the second insulating layer 102 of the second display area A2, and a connecting layer 52 disposed on the second insulating layer 102 of the first display area A1, such as... Figure 4 As shown. For example, the third conductive layer may include the second plate of the storage capacitor of the pixel circuit. The orthographic projection of the second plate of the storage capacitor onto the substrate 100 may at least partially overlap with the orthographic projection of the first plate of the storage capacitor onto the substrate 100.

[0114] In some examples, the connection layer 52 may include a plurality of first connection lines. At least one first connection line may extend from the first display area A1 to the second display area A2 to electrically connect the anode of the first light-emitting element in the first display area A1 and the first pixel circuit of the second display area A2.

[0115] Figure 7 This is a partial planar schematic diagram of the first display area after the formation of the connection layer according to at least one embodiment of the present disclosure. In some examples, such as Figure 6 and Figure 7As shown, the first connecting line 521 may include an extension along the first direction D1. Within the first display area, the orthographic projection of the extension of the first connecting line 521 along the first direction D1 onto the substrate may overlap with the orthographic projection of the shielding strip 510 of the shielding layer 51 onto the substrate. For example, within the first display area, the orthographic projection of one shielding strip 510 onto the substrate may cover the orthographic projections of the extensions of three first connecting lines 521 along the first direction D1 onto the substrate. In other examples, the orthographic projection of one shielding strip within the first display area may cover the orthographic projections of four or more first connecting lines along the first direction D1 onto the substrate.

[0116] (5) Forming a third insulating layer and a fourth conductive layer. In some examples, a third insulating film is deposited on the substrate 100 on which the aforementioned structure is formed, and a third insulating layer 103 is formed by a patterning process. A plurality of active vias are formed on the third insulating layer 103 of the second display area A2, the plurality of active vias including at least two active vias located in the second display area A2, the two active vias exposing the two ends of the active layer of a transistor respectively. Subsequently, a fourth conductive film is deposited, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer disposed in the second display area A2, such as... Figure 4 As shown. For example, the fourth conductive layer may include: the first and second terminals of the transistors of the pixel circuit located in the second display area A2, wherein the first and second terminals of the transistors may be connected to the two ends of the active layer through active vias, respectively.

[0117] At this point, the pixel circuit for the second display area A2 can be fabricated. For example, transistor 300A may include an active layer, a gate electrode, a first electrode, and a second electrode. Storage capacitor 300B may include a first electrode plate and a second electrode plate. At this time, the light-transmitting structure layer 201 of the first display area A1 may include: a first insulating layer 101, a shielding layer 51, a second insulating layer 102, a connecting layer 52, and a third insulating layer 103 sequentially disposed on the substrate 100.

[0118] In some examples, the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer 101 and the second insulating layer 102 can be referred to as gate insulating (GI) layers, and the third insulating layer 103 can be referred to as interlayer insulating (ILD) layers. The second conductive layer, the third conductive layer, the fourth conductive layer, the shielding layer 51, and the connecting layer 52 can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The semiconductor layer can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), and polycrystalline silicon (p-Si). In other words, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0119] (6) Forming a fifth conductive layer. In some examples, a fourth insulating film is deposited on the substrate 100 on which the aforementioned structure is formed, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer 104. The fourth insulating layer 104 has a plurality of vias formed in the second display area A2, the plurality of vias including at least a first connection hole located in the second display area A2. The fourth insulating layer 104 in the first connection hole of each sub-pixel can be removed to expose the first electrode of the transistor of the pixel circuit of the sub-pixel. In some examples, the fourth insulating layer 104 can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer. The fourth insulating layer 104 can be referred to as a passivation (PVX) layer.

[0120] Subsequently, a fifth conductive thin film is deposited, and then patterned using a patterning process to form the fifth conductive layer. For example... Figure 4As shown, the fifth conductive layer includes at least a first anode connection electrode 301 located in the second display area A2. The first anode connection electrode 301 can be electrically connected to the transistor of the second pixel circuit through a first connection via, and the first anode connection electrode 301 can be configured to be electrically connected to the anode of the subsequently formed second light-emitting element. In some examples, the fifth conductive layer may also include a second anode connection electrode (not shown) located in the second display area A2. The second anode connection electrode can be electrically connected to a first connection line extending to the second display area A2 through a second connection hole opened in the fourth insulating layer 104, and can also be electrically connected to the first pixel circuit through the first connection hole. The fourth insulating layer 104 and the third insulating layer 103 in the second connection hole can be removed to expose the surface of the first connection line. However, this embodiment is not limited to this. In other examples, the first electrode of the transistor of the first pixel circuit located in the fourth conductive layer can be electrically connected to the first connection line through a via opened in the third insulating layer, so as to be electrically connected to the anode of the first light-emitting element through the first connection line.

[0121] In some examples, the fifth conductive layer can be a multilayer composite structure, such as Ti / Al / Ti. However, this embodiment is not limited to this.

[0122] (7) Forming the fifth insulating layer. In some examples, a fifth insulating film is coated on the substrate 100 on which the aforementioned structure is formed, and the fifth insulating layer 105 is formed by a patterning process, such as... Figure 4 As shown. The fifth insulating layer 105 may have multiple vias, such as a third connection via located in the second display area A2 and a fourth connection via located in the first display area A1. The fifth insulating layer 105 within the third connection via can be removed to expose the surface of the first anode connection electrode 301. The fifth insulating layer 105, the fourth insulating layer 104, and the third insulating layer 103 within the fourth connection via can be removed to expose the surface of the first connection line. In some examples, the fifth insulating layer 105 may be made of an organic material, such as resin. The fifth insulating layer 105 may also be referred to as a planarization layer.

[0123] Thus, the light-transmitting structure layer 201 of the first display area A1 and the circuit structure layer 203 of the second display area A2 are fabricated. The light-transmitting structure layer 201 of the first display area A1 may include: a first insulating layer 101, a shielding layer 51, a second insulating layer 102, a connecting layer 52, a third insulating layer 103, a fourth insulating layer 104, and a fifth insulating layer 105 sequentially disposed on the substrate 100. The circuit structure layer 203 of the second display area A2 may include: a semiconductor layer, a first insulating layer 101, a second conductive layer, a second insulating layer 102, a third conductive layer, a third insulating layer 103, a fourth conductive layer, a fourth insulating layer 104, a fifth conductive layer, and a fifth insulating layer 105 sequentially disposed on the substrate 100.

[0124] (8) Forming the anode layer. In some examples, an anode conductive film is deposited on the substrate 100 where the aforementioned structure is formed, and the anode conductive film is patterned using a patterning process to form the anode layer. For example... Figure 4 As shown, the anode layer may include: a first anode 31 of a first light-emitting element 311 emitting a first color light located in the first display area A1; a second anode 32 of a first light-emitting element 312 emitting a second color light; a third anode 33 of a first light-emitting element 313 emitting a third color light; a fourth anode 34 of a first light-emitting element 314 emitting a fourth color light; and a fifth anode 35 of a second light-emitting element located in the second display area A2. The fifth anode 35 can be electrically connected to the first anode connection electrode 301 through a third connection via. In some examples, the first color light can be red light, the second and fourth color light can be green light, and the third color light can be blue light. However, this embodiment is not limited to this.

[0125] Figure 8 This is a partial planar schematic diagram of the first display area after the formation of the anode layer according to at least one embodiment of the present disclosure. Figure 8 The diagram illustrates the anode structure of two pixel units (including eight first light-emitting elements, the first pixel circuits corresponding to the eight first light-emitting elements being located in the second display area) in the first display area. Figure 8 The two pixel units shown can be arranged sequentially along the second direction D2. Each pixel unit includes four first light-emitting elements, and the four first light-emitting elements of each pixel unit can be arranged along the first direction D1.

[0126] In some examples, such as Figure 8 As shown, the first anode 31 may include a first body 31a and a first connecting portion 31b. The first body 31a may be generally elliptical. The first connecting portion 31b is connected to the first body 31a and extends to be electrically connected to a first connecting line 521. The second anode 32 may include a second body 32a and a second connecting portion 32b. The second body 32a may be generally circular. The second connecting portion 32b is connected to the second body 32a and extends to be electrically connected to a first connecting line 521. The third anode 33 may include a third body 33a and a third extension 33b. The third body 33a may be generally circular. The third extension 33b is connected to the third body 33a and extends to be electrically connected to a first connecting line 521. The fourth anode 34 may include a fourth body 34a and a fourth extension 34b. The fourth body 34a may be generally circular. The fourth extension 34b is connected to the fourth body 34a and extends to be electrically connected to a first connecting line 521. In other examples, the shapes of the first body 31a, the second body 32a, the third body 33a, and the fourth body 34a can be quadrilaterals, pentagons, or hexagons.

[0127] In some examples, such as Figures 6 to 8 As shown, within at least one pixel unit, the orthographic projections of the first extension 31b of the first anode 31, the second extension 32b of the second anode 32, the third extension 33b of the third anode 33, and the fourth extension 34b of the fourth anode 34 onto the substrate may overlap with the orthographic projection of the shielding strip 510 of the shielding layer 51 onto the substrate. The orthographic projections of the first anode 31, the second anode 32, the third anode 33, and the fourth anode 34 onto the substrate may be located within the orthographic projection range of the shielding layer 51 onto the substrate. The position and shape of the first shielding block 511 may be substantially similar to the position and shape of the first body 31a of the first anode 31, and the orthographic projection of the first body 31a of the first anode 31 onto the substrate may be located within the orthographic projection range of the first shielding block 511 of the shielding layer 51 onto the substrate, so that during subsequent cathode patterning processing, the first shielding block 511 can shield the first anode 31, preventing damage to the first anode 31. The position and shape of the second shielding block 512 can be substantially similar to the position and shape of the second body 32a of the second anode 32. The orthographic projection of the second body 32a of the second anode 32 onto the substrate can be located within the orthographic projection range of the second shielding block 512 onto the substrate, so that during subsequent cathode patterning processing, the second shielding block 512 can shield the second anode 32 and prevent damage to the second anode 32. The position and shape of the third shielding block 513 can be substantially similar to the position and shape of the third body 33a of the third anode 33. The orthographic projection of the third body 33a of the third anode 33 onto the substrate can be located within the orthographic projection range of the third shielding block 513 onto the substrate, so that during subsequent cathode patterning processing, the third shielding block 513 can shield the third anode 33 and prevent damage to the third anode 33. The position and shape of the fourth shielding block 514 can be basically similar to the position and shape of the fourth body 34a of the fourth anode 34. The orthographic projection of the fourth body 34a of the fourth anode 34 onto the substrate can be located within the orthographic projection range of the fourth shielding block 514 onto the substrate, so that the fourth shielding block 514 can shield the fourth anode 34 during subsequent cathode patterning processing to prevent damage to the fourth anode 34.

[0128] In some examples, the anode conductive film can be made of a metallic material or a transparent conductive material. The metallic material can include any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals. The transparent conductive material can include indium tin oxide (ITO) or indium zinc oxide (IZO). In some examples, the anode conductive film can be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO.

[0129] (9) Forming a pixel definition layer. In some examples, a pixel definition film is coated on the substrate 100 on which the aforementioned pattern is formed, and the pixel definition film is patterned by a patterning process to form a pixel definition layer (PDL) 36, such as... Figure 4 As shown, the pixel definition layer 36 has multiple pixel openings that expose the anode layer. The pixel definition layer 36 within the pixel openings can be removed to expose the surface of the anode of the corresponding sub-pixel. In some examples, the material of the pixel definition layer 36 may include polyimide or acrylic, etc.

[0130] Figure 9 This is a partial planar schematic diagram of the first display area after forming a pixel definition layer, according to at least one embodiment of the present disclosure. Figure 9 The diagram illustrates the pixel openings of two adjacent pixel units (including eight first light-emitting elements, the eight first light-emitting elements being electrically connected to a first pixel circuit located in the second display area) along the second direction D2. Figure 4 ,as well as Figures 6 to 9 As shown, the first pixel opening OP1 is located in the first light-emitting element 311 that emits the first color light, and can expose part of the surface of the first body 31a of the first anode 31; the second pixel opening OP2 is located in the first light-emitting element 312 that emits the second color light, and can expose part of the surface of the second body 32a of the second anode 32; the third pixel opening OP3 is located in the first light-emitting element 313 that emits the third color light, and can expose part of the surface of the third body 33a of the third anode 33; the fourth pixel opening OP4 is located in the first light-emitting element 314 that emits the fourth color light, and can expose part of the surface of the fourth body 34a of the fourth anode 34.

[0131] In some examples, a half-tone mask patterning process can be used to form a spacer pillar pattern when forming the pixel definition layer. The spacer pillars can be located outside the pixel openings and can be configured to support a fine metal mask in subsequent vapor deposition processes. However, this embodiment is not limited to this.

[0132] In some examples, the pixel opening shape can be rectangular, square, pentagonal, hexagonal, circular, or elliptical in the direction parallel to the display substrate. In the direction perpendicular to the display substrate, the cross-sectional shape of the pixel opening can be rectangular or trapezoidal. The inner sidewall of the pixel opening can be planar or curved. However, this embodiment is not limited in this respect.

[0133] (10) Forming an organic light-emitting layer. In some examples, an organic light-emitting layer 37 is formed on the substrate 100 on which the aforementioned structure is formed, by vapor deposition or inkjet printing, such as... Figure 4As shown. In some examples, the organic light-emitting layer 37 can be located within each sub-pixel of the first display area A1 and the second display area A2, and connected to the anode of the sub-pixel through the pixel opening of the sub-pixel. For example, the organic light-emitting layer 37 of the first light-emitting element 311 can be configured to emit red light, the organic light-emitting layer of the first light-emitting element 312 can be configured to emit green light, the organic light-emitting layer of the first light-emitting element 313 can be configured to emit blue light, and the organic light-emitting layer of the first light-emitting element 314 can be configured to emit green light. The organic light-emitting layer 37 of the second display area A2 can be configured to emit monochromatic light or emit white light. This embodiment is not limited in this respect.

[0134] In some examples, the organic light-emitting layer may include: a light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0135] In some examples, the organic light-emitting layer can be fabricated as follows: First, a hole injection layer, a hole transport layer, and an electron blocking layer are sequentially formed on the display substrate using an open-mask evaporation process or an inkjet printing process, forming a common layer of the hole injection layer, hole transport layer, and electron blocking layer. Then, a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer are formed in the corresponding sub-pixels using a fine metal mask evaporation process or an inkjet printing process. The light-emitting layers of adjacent sub-pixels may have a small amount of overlap (e.g., the overlapping portion occupies less than 10% of the area of ​​their respective light-emitting layer patterns) or may be isolated. Subsequently, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially formed on the display substrate using an open-mask evaporation process or an inkjet printing process, forming a common layer of the hole blocking layer, electron transport layer, and electron injection layer.

[0136] In some examples, the organic light-emitting layer may include a microcavity conditioning layer such that the thickness of the organic light-emitting layer between the cathode and anode meets the design of the microcavity length. For example, a hole transport layer, an electron blocking layer, or an electron transport layer may be used as the microcavity conditioning layer. This embodiment is not limited in this respect.

[0137] In some examples, the emissive layer may include a host material and a guest material doped in the host material. The doping ratio of the guest material in the emissive layer can be approximately 1% to 20%. Within this doping ratio range, on the one hand, the host material of the emissive layer can effectively transfer exciton energy to the guest material to excite the guest material to emit light; on the other hand, the host material "dilutes" the guest material, effectively improving the quenching caused by collisions between molecules of the guest material and collisions between energies, thereby improving luminous efficiency and device lifetime. The doping ratio can be the ratio of the mass of the guest material to the mass of the emissive layer, i.e., a mass percentage. For example, the thickness of the emissive layer can be approximately 10 nm to 50 nm.

[0138] (11) Forming a cathode layer. In some examples, a cathode layer pattern is formed on the substrate on which the aforementioned structure is formed by vapor deposition using an open mask. For example, the cathode layer pattern located in the first display area and the second display area can be a full-surface structure.

[0139] In some examples, the cathode layer can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the aforementioned metals. For example, the cathode layer can be made of Mg and Ag, which have good electrical conductivity.

[0140] In some examples, an optical coupling layer can be formed after the cathode layer pattern is formed. The optical coupling layer is disposed on the cathode, and its refractive index can be greater than that of the cathode layer, which is beneficial for light extraction and increases light extraction efficiency. The material of the optical coupling layer can be organic, inorganic, or a combination of organic and inorganic materials, and it can be a single layer, multiple layers, or a composite layer.

[0141] (12) Perform cathode patterning. In some examples, on the substrate forming the aforementioned structure, an exposure machine is used to irradiate the substrate from the side away from the light-transmitting structure layer, forming a patterned first cathode layer 381 in the first display area A1, such as... Figure 4 As shown. The second cathode layer 382 of the second display area A2 can be a full-surface structure. The exposure machine can be an infrared laser device. The patterned first cathode layer 381 selectively removes part of the cathode, leaving only the cathode pattern necessary for light emission. The position and shape of the patterned first cathode layer 381 are substantially the same as the position and shape of the shielding layer 51, and the orthographic projection of the patterned first cathode layer 381 on the substrate can at least partially overlap with the orthographic projection of the shielding layer 51 on the substrate, for example, they can completely coincide.

[0142] In this example, since the multiple anodes and cathodes of the first display area A1 are located on the side of the shielding layer 51 away from the substrate 100, when the infrared laser device irradiates from the back of the display substrate (the side of the substrate away from the light-transmitting structure layer), the shielding layer 51 can act as a protective layer. It can not only protect the multiple anodes from being irradiated by the infrared laser, but also protect the cathodes that have overlapping areas with the shielding layer 51. This allows the cathodes with overlapping areas to be retained without being irradiated by the infrared laser, while the cathodes that do not overlap with the shielding layer 51 are removed by the infrared laser irradiation, forming a patterned cathode.

[0143] Subsequent fabrication processes may include forming encapsulation structure layers. For example, a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer may be formed sequentially. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The encapsulation structure employs a stacked structure of inorganic, organic, and inorganic materials, which ensures encapsulation integrity and effectively isolates external water and oxygen.

[0144] The structure and fabrication process of the display substrate in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and patterning processes can be modified and added or reduced according to actual needs. The fabrication process of this exemplary embodiment can be implemented using currently mature fabrication equipment, is well compatible with existing fabrication processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0145] The display substrate provided in this embodiment, by having the shielding layer of the first display area and the second conductive layer of the second display area co-layered, and the connection layer of the first display area and the third conductive layer of the second display area co-layered, can reduce the number of transparent conductive layers, thereby reducing fabrication steps and lowering costs. Furthermore, using at least one connection layer to set the first connecting line electrically connecting the first pixel circuit and the first light-emitting element is beneficial for increasing the number of first connecting lines, thus increasing the size of the first display area. For example, if the line width and adjacent line spacing of the first connecting line are both designed to be 1.5 / 1.5, then the display substrate using three transparent conductive layers can achieve the connecting line arrangement using only two transparent conductive layers, reducing the fabrication process of two transparent conductive layers and significantly lowering costs. Additionally, taking a circular first display area as an example, using one connection layer to arrange the connecting lines can increase the radius of the first display area by approximately 127 micrometers, which is beneficial for increasing the aperture of the first display area.

[0146] Figure 10 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, such as Figure 10As shown, the shielding layer 51 of the light-transmitting structure layer 201 of the first display area A1 can be disposed on the same layer as the second conductive layer of the circuit structure layer 203 of the second display area A2, and the connecting layer 52 of the light-transmitting structure layer 201 of the first display area A1 can be disposed on the same layer as the fourth conductive layer of the circuit structure layer 203 of the second display area A2. However, this embodiment is not limited to this. For example, the connecting layer 52 of the first display area A1 can be disposed on the same layer as the fifth conductive layer of the second display area A2. The remaining structure of the display substrate of this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0147] Figure 11 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, such as Figure 11 As shown, the circuit structure layer 203 of the second display area A2 may include: a first conductive layer, a sixth insulating layer 106, a semiconductor layer, a first insulating layer 101, a second conductive layer, a second insulating layer 102, a third conductive layer, a third insulating layer 103, a fourth conductive layer, a fourth insulating layer 104, a fifth conductive layer, and a fifth insulating layer 105 sequentially disposed on the substrate 100. For example, the first conductive layer may include: a shielding electrode (not shown), configured to shield the channel region of the active layer of the transistor in the pixel circuit. The first conductive layer may be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, Ti / Al / Ti, etc.

[0148] In this example, such as Figure 11 As shown, the shielding layer 51 of the light-transmitting structure layer 201 of the first display area A1 can be disposed on the same layer as the first conductive layer of the second display area A2. The connecting layer 52 of the first display area A1 can be disposed on the same layer as the fourth conductive layer of the second display area A2. However, this embodiment is not limited to this. For example, the connecting layer 52 of the first display area A1 can be disposed on the same layer as the second conductive layer, the third conductive layer, or the fifth conductive layer. The remaining structure of the display substrate of this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0149] Figure 12 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, such as Figure 12As shown, the circuit structure layer 203 of the second display area A2 may include: a semiconductor layer, a first insulating layer 101, a second conductive layer, a second insulating layer 102, a third conductive layer, a third insulating layer 103, a fourth conductive layer, a fourth insulating layer 104, a fifth conductive layer, a fifth insulating layer 105, a first transparent conductive layer, a seventh insulating layer 107, a second transparent conductive layer, an eighth insulating layer 108, a third transparent conductive layer, and a ninth insulating layer 109, sequentially disposed on the substrate 100. The first transparent conductive layer may include a third anode connection electrode 302, the second transparent conductive layer may include a fourth anode connection electrode 303, and the third transparent conductive layer may include a fifth anode connection electrode 304. The anode of the second light-emitting element (e.g., the fifth anode 35) may be electrically connected to the second pixel circuit sequentially through the fifth anode connection electrode 304, the fourth anode connection electrode 303, the third anode connection electrode 302, and the first anode connection electrode 301. The first transparent conductive layer, the second transparent conductive layer, and the third transparent conductive layer may be made of a transparent conductive material, such as ITO. The shielding layer 51 of the first display area A1 can be disposed on the same layer as the second conductive layer of the second display area A2, and the connecting layer 52 of the first display area A1 can be disposed on the same layer as the second transparent conductive layer of the second display area A2. However, this embodiment is not limited to this. For example, the display substrate may include three connecting layers, disposed on the same layer as the first transparent conductive layer, the second transparent conductive layer and the third transparent conductive layer, respectively, and the first connecting lines of the three connecting layers can extend from the first display area A1 to the second display area A2 to realize the electrical connection between the first light-emitting element and the first pixel circuit. The remaining structure of the display substrate of this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0150] In other examples, such as when the shielding layer is co-layered with the first conductive layer, the display substrate includes multiple interconnect layers, one of which may be co-layered with one of the second to fifth conductive layers, and the remaining interconnect layers may be co-layered with at least one of the first and third transparent conductive layers.

[0151] Figure 13 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, such as Figure 13As shown, the circuit structure layer 203 of the second display area A2 may include: a semiconductor layer, a first insulating layer 101, a second conductive layer, a second insulating layer 102, a third conductive layer, a third insulating layer 103, a fourth conductive layer, a fourth insulating layer 104, a fifth conductive layer, and a fifth insulating layer 105 sequentially disposed on the substrate 100. The shielding layer 51 of the first display area A1 may be located on the side of the connecting layer 52 away from the substrate 100. For example, the shielding layer 51 may be disposed in the same layer as the fourth conductive layer of the second display area A2, and the connecting layer 52 may be disposed in the same layer as the second conductive layer of the second display area A2. The shielding layer 51 may include a cutout portion 500. Taking the connection between the fourth anode 34 of the first light-emitting element 314 and the first connecting line 521 as an example, the fourth anode 34 may be electrically connected to the first connecting line 521 through an anode connection via. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, and the second insulating layer 102 inside the anode connection via may be removed, exposing the surface of the first connecting line 521. The orthographic projection of the anode connection via onto the substrate can be located within the orthographic projection range of the cutout portion 500 of the shielding layer 51 onto the substrate. For example, the cutout portion 500 corresponding to the anode connection via connecting the fourth anode 34 to the first connection line 521 can be located in the area of ​​the fourth shielding block or the shielding strip adjacent to the fourth shielding block. In some examples, the orthographic projection of the cutout portion 500 onto the substrate can be rectangular, circular, pentagonal, or hexagonal. However, this embodiment is not limited to this. In this example, when the shielding layer is located on the side of the connection layer away from the substrate and close to the light-emitting structure layer, the electrical connection between the first light-emitting element and the first connection line of the connection layer is achieved by setting the cutout portion in the shielding layer. In some examples, the orthographic projection of the cutout portion of the shielding layer onto the substrate can be located within the orthographic projection range of the connection layer onto the substrate, thereby ensuring the effect of cathode patterning. The remaining structure of the display substrate of this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0152] Figure 14 This is another partial planar schematic diagram of the first display area after the formation of the anode layer, according to at least one embodiment of the present disclosure. Figure 14 The diagram illustrates the anode structure of two adjacent pixel units (including eight first light-emitting elements, with the first pixel circuits corresponding to the eight first light-emitting elements located in the second display area) along the second direction D2. In some examples, such as Figure 14As shown, the first anode 31 of the first light-emitting element emitting the first color light can be approximately elliptical, the second anode 32 of the first light-emitting element emitting the second color light can be approximately circular, the third anode 33 of the first light-emitting element emitting the third color light can be approximately circular, and the fourth anode 34 of the first light-emitting element emitting the fourth color light can be approximately circular. The orthographic projection of the first anode 31 onto the substrate can be located within the orthographic projection range of the first shielding block of the shielding layer 51 onto the substrate. The orthographic projection of the second anode 32 onto the substrate can be located within the orthographic projection range of the second shielding block of the shielding layer 51 onto the substrate. The orthographic projection of the third anode 33 onto the substrate can be located within the orthographic projection range of the third shielding block of the shielding layer 51 onto the substrate. The orthographic projection of the fourth anode 34 onto the substrate can be located within the orthographic projection range of the fourth shielding block of the shielding layer 51 onto the substrate. The remaining structures of the display substrate in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0153] Figure 15A and Figure 15B This is another planar schematic diagram of the shielding layer of the first display area of ​​a display substrate according to at least one embodiment of the present disclosure. In some examples, such as Figure 15A As shown, the aforementioned first region can be a rectangular first display area. The first region may include a first sub-region A11 and a second sub-region A12 surrounding the first sub-region A11. The obscuring layer within the second sub-region A12 may include an obscuring strip 510 and a plurality of obscuring blocks connected to the obscuring strip 510 (e.g., the aforementioned first to fourth obscuring blocks). The obscuring layer within the first sub-region A11 may include a plurality of independently disposed obscuring blocks.

[0154] In some examples, such as Figure 15B As shown, the aforementioned first region can be a circular first display area. The first sub-region of the first region can be a central region, and the masking layer of the first sub-region can include a masking strip and multiple masking blocks connected to the masking strip; the second sub-region can be a peripheral region surrounding the central region, and the masking layer in the second sub-region can include multiple independently set masking blocks.

[0155] Figure 16 This is another partial planar schematic diagram of the shielding layer according to at least one embodiment of the present disclosure. Figure 16 for Figure 15A and Figure 15B A partial schematic diagram of the shading layer in the first sub-region. Figure 16 The diagram illustrates the structure of the masking layer corresponding to two adjacent pixel units (including eight first light-emitting elements, the first pixel circuits corresponding to the eight first light-emitting elements being located in the second display area) along the second direction D2.

[0156] In some examples, such as Figure 16As shown, the shielding layer of the first sub-region may include: a fifth shielding block 515, a sixth shielding block 516, a seventh shielding block 517, and an eighth shielding block 518, all independently configured. The fifth shielding block 515 to the eighth shielding block 518 may be configured along a first direction D1. The position and shape of the fifth shielding block 515 may be similar to the position and shape of the first anode of the first light-emitting element emitting the first color light; the position and shape of the sixth shielding block 516 may be similar to the position and shape of the second anode of the first light-emitting element emitting the second color light; the position and shape of the seventh shielding block 517 may be similar to the position and shape of the third anode of the first light-emitting element emitting the third color light; and the position and shape of the eighth shielding block 518 may be similar to the position and shape of the fourth anode of the first light-emitting element emitting the fourth color light.

[0157] In some examples, such as Figures 15A to 16 As shown, the first light-emitting element in the first sub-region A11 can be electrically connected to the first pixel circuit of the second display area via a first connecting line made of transparent conductive material, and the first light-emitting element in the second sub-region A12 can be electrically connected to the first pixel circuit of the second display area via a first connecting line made of metallic material. For example, the connecting layer containing the first connecting line electrically connected to the first light-emitting element in the first sub-region A11 can be disposed in the same layer as the first transparent conductive layer, the second transparent conductive layer, or the third transparent conductive layer in the second display area; the connecting layer containing the first connecting line electrically connected to the first light-emitting element in the second sub-region A12 can be disposed in the same layer as one of the first to fifth conductive layers in the second display area. However, this embodiment is not limited to this. In other examples, all the first light-emitting elements in the first region can be electrically connected to the first pixel circuit of the second display area via a first connecting line made of metallic material. This example improves the diffraction problem caused by the shielding strip by setting a shielding layer in part of the first region to remove the shielding strip extending along the first direction.

[0158] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0159] Figure 17 This is another partial planar schematic diagram of the shielding layer according to at least one embodiment of the present disclosure. In some examples, such as Figure 17As shown, the shielding layer of the first display area may include: a first shielding strip 510a, a second shielding strip 510b, a plurality of shielding blocks connected to the first shielding strip 510a (e.g., an eleventh shielding block 531 and a thirteenth shielding block 533), and a plurality of shielding blocks connected to the second shielding strip 510b (e.g., a twelfth shielding block 532, a thirteenth shielding block 533, and a fourteenth shielding block 534). The first shielding strip 510a and the second shielding strip 510b may each extend approximately along the second direction D2, and the first shielding strip 510a and the second shielding strip 510b may be arranged at intervals along the first direction D1.

[0160] In some examples, such as Figure 17 As shown, the position and shape of the eleventh blocking block 531 can be similar to the position and shape of the first anode of the first light-emitting element emitting the first color light. The position and shape of the twelfth blocking block 532 can be similar to the position and shape of the second anode of the first light-emitting element emitting the second color light. The position and shape of the thirteenth blocking block 533 can be similar to the position and shape of the third anode of the first light-emitting element emitting the third color light. The position and shape of the fourteenth blocking block 534 can be similar to the position and shape of the fourth anode of the first light-emitting element emitting the fourth color light.

[0161] In some examples, the orthographic projection of the extension portion of at least one first connecting line of the connecting layer along the second direction D2 onto the substrate may lie within the orthographic projection range of the first or second shielding strip of the shielding layer onto the substrate. The pattern of the shielding layer may match the orientation of the first connecting line. The extension direction of the shielding strip of the shielding layer is parallel to the first direction D1 or the second direction D2, or may intersect both the first direction D1 and the second direction D2. The shielding strip may be straight or curved. However, this embodiment is not limited in this respect. The remaining structure of the display substrate of this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0162] Figures 18A to 18D This is a partial schematic diagram of the first display area according to at least one embodiment of the present disclosure. Figure 18A The diagram illustrates the structure of two pixel units (including eight first light-emitting elements, wherein the eight first light-emitting elements are electrically connected to a first pixel circuit located in the second display area) arranged along the second direction D2 in the first display area. Each pixel unit may include four first light-emitting elements, which may be arranged along the first direction D1. Figure 18A The diagram illustrates the local structure of the first display area after the pixel definition layer is formed. Figure 18B The diagram illustrates a partial structure of the first display area after the anode layer is formed. Figure 18C The diagram illustrates the partial structure of the first display area after the connection layer is formed. Figure 18D The diagram illustrates a portion of the structure of the first display area after the shielding layer is formed.

[0163] In some examples, such as Figures 18A to 18D As shown, the shielding layer may include a shielding strip 510 extending along a first direction D1 and a first shielding block 511, a second shielding block 512, a third shielding block 513, and a fourth shielding block 514 connected to the shielding strip 510. For example, the first shielding block 511 may be approximately teardrop-shaped, the third shielding block 513 may be approximately circular, and the second shielding block 512 and the fourth shielding block 514 may be approximately elliptical. The first shielding block 511 and the third shielding block 513 may be located on one side of the shielding strip 510 along a second direction D2, and the second shielding block 512 and the fourth shielding block 514 may be located on the other side of the shielding strip 510 along the second direction D2.

[0164] In some examples, such as Figures 18A to 18D As shown, the shielding layer can be located on the side of the connecting layer closer to the substrate. The connecting layer includes multiple first connecting lines 521. The orthographic projection of the extension portion of the first connecting line 521 along the first direction D1 onto the substrate is located within the orthographic projection range of the shielding strip 510 onto the substrate. The position and shape of the first anode 31 of the first light-emitting element 311 emitting the first color light can correspond to the first shielding block 511, the position and shape of the second anode 32 of the first light-emitting element 312 emitting the second color light can correspond to the second shielding block 512, the position and shape of the third anode 33 of the first light-emitting element 313 emitting the third color light can correspond to the third shielding block 513, and the position and shape of the fourth anode 34 of the first light-emitting element 314 emitting the fourth color light can correspond to the fourth shielding block 514.

[0165] In this example, the arrangement of the first to fourth light-emitting elements differs from that in the previous embodiments. The remaining structure of the display substrate in this embodiment can be found in the description of the previous embodiments, and therefore will not be repeated here.

[0166] This embodiment also provides a method for fabricating a display substrate, the display substrate including a first region and a second region located at least one side of the first region. The fabrication method includes: forming a light-transmitting structure layer on a substrate of the first region, and forming a circuit structure layer on a substrate of the second region; forming a light-emitting structure layer on the side of the circuit structure layer and the light-transmitting structure layer away from the substrate, the light-emitting structure layer including at least a plurality of first light-emitting elements located in the first region; and forming a patterned cathode of the light-emitting structure layer in the first region. The circuit structure layer includes at least a plurality of first pixel circuits; the light-transmitting structure layer includes: a shielding layer and at least one connecting layer, the at least one connecting layer including a plurality of first connecting lines, at least one of the plurality of first connecting lines extending from the first region to the second region. The orthographic projections of the shielding layer and the at least one connecting layer on the substrate at least partially overlap. At least one of the plurality of first light-emitting elements in the first region is electrically connected to at least one of the plurality of first pixel circuits in the second region via at least one first connecting line. The shielding layer is configured as a shielding structure in the cathode patterning process, such that the orthographic projection of the patterned cathode on the substrate at least partially overlaps with the orthographic projection of the shielding layer on the substrate.

[0167] In some exemplary embodiments, a light-transmitting structure layer is formed on a substrate in a first region, and a circuit structure layer is formed on a substrate in a second region. This includes: forming a semiconductor layer on the substrate in the second region, the semiconductor layer including at least an active layer of a transistor in a first pixel circuit; simultaneously forming a shielding layer in the first region and a second conductive layer in the second region, the second conductive layer including a gate electrode of a transistor in the first pixel circuit and a first electrode of a storage capacitor; simultaneously forming a connection layer in the first region and a third conductive layer in the second region, the third conductive layer including a second electrode of a storage capacitor in the first pixel circuit; and forming a fourth conductive layer in the second region, the fourth conductive layer including a first electrode and a second electrode of a transistor in the first pixel circuit.

[0168] The fabrication process of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0169] This disclosure also provides a display device, including the display substrate described above.

[0170] Figure 19 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 19 As shown, this embodiment provides a display device, including a display substrate 91 and a sensor 92 located on the non-display side away from the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 overlaps with the first display area A1.

[0171] In some examples, the display substrate 91 can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device can be any product or component with display function, such as an OLED display, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments disclosed herein are not limited thereto.

[0172] The accompanying drawings in this disclosure only illustrate the structures involved in this disclosure; other structures can be referred to with common design. Unless otherwise specified, the embodiments and features described in these embodiments can be combined to obtain new embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this disclosure without departing from the spirit and scope of this disclosure, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, characterized by, The application relates to a display panel, comprising: a substrate, comprising a first region and a second region located on at least one side of the first region; a circuit structure layer, located on the second region, and comprising at least a plurality of first pixel circuits; a light-transmitting structure layer, located on the first region, comprising a shielding layer and at least one connecting layer; the at least one connecting layer comprises a plurality of first connecting lines, at least one first connecting line of the plurality of first connecting lines extending from the first region to the second region; the shielding layer and the at least one connecting layer at least partially overlap in the orthographic projection on the substrate; a light-emitting structure layer, located on the side of the circuit structure layer and the light-transmitting structure layer away from the substrate, and comprising at least a plurality of first light-emitting elements located in the first region; at least one first light-emitting element of the plurality of first light-emitting elements in the first region is electrically connected to at least one first pixel circuit of the plurality of first pixel circuits in the second region through the at least one first connecting line; the light-emitting structure layer comprises a patterned cathode located in the first region; the shielding layer is configured as a shielding structure in the cathode patterning process, so that the orthographic projection of the patterned cathode on the substrate at least partially overlaps with the orthographic projection of the shielding layer on the substrate; the first region comprises a first sub-region and a second sub-region, the second sub-region being located on at least one side of the first sub-region; the shielding layer of the second sub-region comprises a shielding strip extending along a first direction and a plurality of shielding blocks connected to the shielding strip; the shielding layer of the first sub-region comprises a plurality of shielding blocks independently arranged; the material of the first connecting line electrically connected to at least one first light-emitting element in the second sub-region is a metal material, and the material of the first connecting line electrically connected to at least one first light-emitting element in the first sub-region is an oxide material.

2. The display substrate of claim 1, wherein, The shielding layer is located on the side of the at least one connecting layer close to the substrate.

3. The display substrate of claim 1, wherein, The material of the at least one connecting layer is a metal material or an oxide material.

4. The display substrate of claim 1, wherein, The shielding layer comprises a shielding strip extending along a first direction and a plurality of shielding blocks connected to the shielding strip; In the first region, the orthographic projection of the extension part of at least one first connecting line of the at least one connecting layer along the first direction on the substrate is located within the range of the orthographic projection of the shielding strip on the substrate. 5.The display substrate of claim 1, wherein, The shielding strip and the plurality of shielding blocks connected thereto are an integral structure. 6.The display substrate of claim 1, wherein, The light-emitting structure layer further comprises a patterned anode located in the first region, and the orthographic projection of the anode of the first region on the substrate is located within the range of the orthographic projection of the shielding layer on the substrate.

7. The display substrate of claim 1, wherein, The circuit structure layer comprises a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer arranged on the substrate; The shielding layer is arranged in the same layer as one of the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer, and the at least one connecting layer is arranged in a different layer from the shielding layer. 8.The display substrate of claim 7, wherein, The circuit structure layer further comprises a first transparent conductive layer, a second transparent conductive layer and a third transparent conductive layer located on the side of the fourth conductive layer away from the substrate; The at least one connecting layer is arranged in the same layer as at least one of the first transparent conductive layer, the second transparent conductive layer and the third transparent conductive layer. 9.The display substrate of claim 1, wherein, The first area comprises a plurality of first light emitting elements, including a first light emitting element emitting first color light, a first light emitting element emitting second color light, a first light emitting element emitting third color light and a first light emitting element emitting fourth color light. The shielding layer comprises at least a first shielding block, a second shielding block, a third shielding block and a fourth shielding block; the first shielding block, the second shielding block, the third shielding block and the fourth shielding block are arranged along a first direction. The anode of the first light emitting element emitting first color light is projected on the first shielding block in the substrate, the anode of the first light emitting element emitting second color light is projected on the second shielding block in the substrate, the anode of the first light emitting element emitting third color light is projected on the third shielding block in the substrate, and the anode of the first light emitting element emitting fourth color light is projected on the fourth shielding block in the substrate. 10.The display substrate of claim 9, wherein, The shielding layer further comprises a shielding strip connecting the first shielding block, the second shielding block, the third shielding block and the fourth shielding block; the first shielding block, the second shielding block and the third shielding block are located on one side of the shielding strip along a second direction, and the fourth shielding block is located on the other side of the shielding strip along the second direction; the second direction intersects the first direction. 11.The display substrate of claim 9, wherein, The shielding layer further comprises a shielding strip connecting the first shielding block, the second shielding block, the third shielding block and the fourth shielding block; the first shielding block and the third shielding block are located on one side of the shielding strip along a second direction, and the second shielding block and the fourth shielding block are located on the other side of the shielding strip along the second direction; the second direction intersects the first direction. 12.The display substrate of claim 1, wherein, The shielding layer is located on the side of the at least one connecting layer away from the substrate; the shielding layer comprises a hollow part, and the at least one first connecting line is electrically connected to the anode of the first light emitting element through an anode connection via hole; the anode connection via hole is projected on the projection range of the hollow part in the substrate.

13. A display device comprising: The display substrate comprises a first area and a second area located on at least one side of the first area, and the preparation method comprises:

14. A method for preparing a display substrate, characterized in that, The display substrate comprises a first area and a second area located on at least one side of the first area, and the preparation method comprises: Forming a light-transmitting structure layer on the substrate of the first region and forming a circuit structure layer on the substrate of the second region; the circuit structure layer at least includes a plurality of first pixel circuits; the light-transmitting structure layer includes: a shielding layer and at least one connecting layer, the at least one connecting layer includes a plurality of first connecting lines, at least one first connecting line in the plurality of first connecting lines extends from the first region to the second region; the shielding layer and the at least one connecting layer at least partially overlap in the orthographic projection of the substrate; wherein the first region includes: a first sub-region and a second sub-region, the second sub-region is located at least one side of the first sub-region; the shielding layer of the second sub-region includes: a shielding strip extending in a first direction and a plurality of shielding blocks connected with the shielding strip; the shielding layer of the first sub-region includes: a plurality of shielding blocks independently arranged; the material of the first connecting line electrically connected with at least one first light-emitting element in the second sub-region is a metal material, and the material of the first connecting line electrically connected with at least one first light-emitting element in the first sub-region is an oxide material; forming a light-emitting structure layer away from the substrate on the circuit structure layer and the light-transmitting structure layer, the light-emitting structure layer at least includes a plurality of first light-emitting elements located in the first region; at least one first light-emitting element in the plurality of first light-emitting elements in the first region is electrically connected with at least one first pixel circuit in the plurality of first pixel circuits in the second region through the at least one first connecting line; forming a patterned cathode of the light-emitting structure layer in the first region; the shielding layer is configured as a shielding structure in the cathode patterning process, so that the orthographic projection of the patterned cathode on the substrate at least partially overlaps with the orthographic projection of the shielding layer on the substrate.

15. The preparation method according to claim 14, characterized in that, forming a light-transmitting structure layer on the substrate of the first region and forming a circuit structure layer on the substrate of the second region, comprising: forming a semiconductor layer on the substrate of the second region, the semiconductor layer at least includes: an active layer of a transistor of a first pixel circuit; synchronously forming a shielding layer in the first region and forming a second conductive layer in the second region, the second conductive layer includes: a gate electrode of a transistor of the first pixel circuit and a first plate of a storage capacitor; synchronously forming a connecting layer in the first region and forming a third conductive layer in the second region, the third conductive layer includes: a second plate of a storage capacitor of the first pixel circuit; forming a fourth conductive layer in the second region, the fourth conductive layer includes: a first electrode and a second electrode of a transistor of the first pixel circuit.

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