High voltage isolation ring structure for gate drive circuit

Abstract

The application provides a high-voltage isolation ring structure of a gate driving circuit, which comprises a high-voltage field effect tube, a high-voltage isolation ring and a closed loop structure formed by a high-voltage transition zone between the high-voltage field effect tube and the high-voltage isolation ring; the inside of the closed loop structure is a high-end voltage area, and the outside is a low-end voltage area; a P-type shielding isolation ring is inserted between the high-voltage field effect tube and the high-end voltage area; a self-shielding isolation ring is nested on the P-type shielding isolation ring; a high-voltage interconnection parasitic resistance area is formed between the P-type shielding isolation rings, and the position of the self-shielding isolation ring embedded in the P-type shielding isolation ring and the distance between the two P-type shielding isolation rings can adjust the parasitic N-epi resistance of the high-voltage interconnection parasitic resistance area. The application realizes the complete isolation between the high-voltage field effect tube and the high-end voltage area by using the P-type shielding isolation ring, then nests the self-shielding isolation ring on the P-type shielding isolation ring, and realizes the semi-self-shielding isolation structure of the full-shielding isolation in part of the area and the self-shielding isolation in part of the area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit manufacturing, in particular to a high-voltage isolation ring structure of a gate drive circuit. BACKGROUND

[0002] In the design of high-voltage integrated circuits, in the application of a half-bridge drive circuit which requires high-end voltage circuits and low-end voltage circuits to be compatible on the same chip circuit, there are high-end voltage regions High-side and low-end voltage regions Low-side. Figure 1 Figure 1 A high-voltage self-shielding cross-sectional structure diagram in the prior art is shown. The high-voltage self-shielding structure is composed of three voltage-resistant structures: a high-voltage field effect tube, a high-voltage isolation ring (HVIR) and a high-voltage transition zone between the two, which are connected to each other to form a closed loop structure. The inside of the closed loop is the high-end voltage region, and the outside of the closed loop is the low-end voltage region. The high-voltage field effect tube is controlled to be turned on and off by an IC internal circuit logic control signal to realize the voltage level shift from low-end to high-end. The high-voltage isolation ring surrounds the entire high-end voltage circuit part to realize the voltage resistance to the low-end. The high-voltage transition zone between the high-voltage field effect tube and the high-voltage isolation ring (HVIR) realizes the voltage resistance transition from the high-voltage field effect tube to the high-voltage isolation ring structure.

[0003] Figure 2 is Figure 1 A cross-sectional view at AA. It can be seen from Figure 2 that the HVLDMOS is used to simultaneously satisfy the functions of the isolation ring and the circuit voltage level shift. In the prior art, there is a resistance and a Zener embedding protection between the power supply VB and the drain VD of the LDMOS in the high-end voltage region. The parasitic resistance between VB and VD is formed by the high-voltage self-depletion effect of the high-side in operation. In the high-voltage self-shielding structure in the prior art, the PTOP layer is implanted to realize the parasitic resistance. The small parasitic resistance leads to high leakage loss between the power supply VB and the drain VD of the LDMOS.

[0004] Therefore, a new structure is needed to reduce the leakage loss. SUMMARY

[0005] In order to solve the problems existing in the prior art, the present application provides a high-voltage isolation ring structure of a gate drive circuit, which is used to increase the parasitic resistance value by adjusting the distance of the two P-type shielding isolation rings, reduce the leakage loss of VB to VD, and meet the circuit design requirements.

[0006] The present application provides a high-voltage isolation ring structure of a gate drive circuit, which at least includes:

[0007] ​A closed loop structure formed by connecting a high-voltage field effect transistor, a high-voltage isolation ring and a high-voltage transition region between the two; the inside of the closed loop structure is a high-end voltage region, and the outside is a low-end voltage region;

[0008] A P-type shielding isolation ring inserted between the high-voltage field effect transistor and the high-end voltage region;

[0009] A self-shielding isolation ring nested on the P-type shielding isolation ring;

[0010] A high-voltage interconnection parasitic resistance region formed between the P-type shielding isolation rings, and the position of the self-shielding isolation ring embedded in the P-type shielding isolation ring and the distance between the two P-type shielding isolation rings can adjust the parasitic N-epi resistance of the high-voltage interconnection parasitic resistance region.

[0011] Preferably, the closed loop structure is a closed square ring, and the corners are treated with a circular arc.

[0012] Preferably, the high-voltage field effect transistor is an LDMOS, which includes a P-type substrate, an epitaxial layer on the P-type substrate, a source of the LDMOS close to the low-end voltage region, a drain of the LDMOS close to the P-type shielding isolation ring, and a gate between the source and the drain.

[0013] Preferably, a P-well is provided in the epitaxial layer below the source of the LDMOS, and the P-well has a P-type heavily doped region and an N-type heavily doped region; a field oxide region is provided on the surface of the epitaxial layer between the source and the drain of the LDMOS, and field plates connected to the gate and the drain cover both ends of the field oxide region, a P-type top implant layer is formed in the epitaxial layer below the field oxide region, and an N-type heavily doped region is provided in the epitaxial region below the drain of the LDMOS.

[0014] Preferably, a high-voltage P-well and a P-type buried layer on the high-voltage P-well are provided at the junction of the LDMOS part and the low-end voltage region, the high-voltage P-well is located in the epitaxial layer, and the P-type buried layer is located at the junction of the P-type substrate and the epitaxial layer.

[0015] Preferably, the high-end voltage region includes a P-type substrate, an epitaxial layer on the P-type substrate, an N-type buried layer at the junction of the P-type substrate and the epitaxial layer, an N-type heavily doped region on the surface of the epitaxial layer, and a power supply VB above the N-type heavily doped region.

[0016] Preferably, the P-type shielding isolation ring is formed by connecting a lower P-type buried layer and an upper high-voltage P-well, and is in communication with the P-type substrate, a field oxide region is formed above the high-voltage P-well, and full isolation of the epitaxial layer on both sides of the P-type shielding isolation ring is achieved.

[0017] Preferably, the P-type shield isolation ring is segmented, and the segmented empty parts are filled with the self-shield isolation ring.

[0018] Preferably, a first P-type shield isolation ring surrounding the high-voltage field effect tube is opened at a position close to the source on one side, and filled with a first self-shield isolation ring; a second P-type shield isolation ring surrounding the high-voltage field effect tube is also opened at a position on the other side, and filled with a second self-shield isolation ring.

[0019] Preferably, a first self-shield isolation ring is connected from the drain VD end to the N-epi region between the two P-type isolation rings, and then connected to the power supply VB end through a second self-shield isolation ring, to form the high-voltage interconnection parasitic resistance region.

[0020] The high-voltage isolation ring structure of the gate drive circuit of the present application completely isolates the high-voltage field effect tube and the high-voltage region by using a P-type shield isolation ring, and then nests a self-shield isolation ring in the P-type shield isolation ring, so as to increase the parasitic resistance value by adjusting the position of the self-shield isolation ring embedded in the P-type shield isolation ring and the distance between the two P-type shield isolation rings, and reduce the leakage loss from VB to VD. BRIEF DESCRIPTION OF DRAWINGS

[0021] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application, taken in conjunction with the accompanying drawings, in which:

[0022] Figure 1 A cross-sectional structure schematic diagram of a high-voltage self-shield structure in the prior art is shown;

[0023] Figure 2 A cross-sectional structure schematic diagram of a high-voltage isolation ring structure of an embodiment of the present application is shown; Figure 1 A cross-sectional structure schematic diagram of a high-voltage isolation ring structure of an embodiment of the present application is shown;

[0024] Figure 3 A cross-sectional structure schematic diagram of a high-voltage isolation ring structure of an embodiment of the present application is shown;

[0025] Figure 4 A cross-sectional structure schematic diagram of a high-voltage interconnection parasitic resistance region of a high-voltage isolation ring structure of an embodiment of the present application is shown;

[0026] Figure 5 A cross-sectional structure schematic diagram of a high-voltage isolation ring structure of an embodiment of the present application is shown; Figure 3 A cross-sectional structure schematic diagram of a high-voltage isolation ring structure of an embodiment of the present application is shown;

[0027] Figure 6 A cross-sectional structure schematic diagram of a high-voltage isolation ring structure of an embodiment of the present application is shown; Figure 4 A cross-sectional structure schematic diagram of a high-voltage isolation ring structure of an embodiment of the present application is shown; DETAILED DESCRIPTION

[0028] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0029] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0030] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0031] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0032] Gate drive circuits often need to drive both high-side and low-side power devices simultaneously, with a significant voltage difference between them, sometimes exceeding 600V. For example, in high-side applications for motor drives, a high-voltage isolation ring is required in the gate drive circuit to isolate the high-voltage and low-voltage sides, and a level shifting circuit is also needed to achieve level conversion between them. Existing structures typically utilize high-voltage LDMOS to simultaneously fulfill the functions of isolation ring and level shifting. This structure leverages the self-depletion effect of PTOP-N-epi-Psub in the high-voltage transition region during high-voltage operation, creating a parasitic high resistance between VB and VD. This low parasitic resistance leads to high leakage losses between the power supply VB and the LDMOS drain VD. Therefore, this invention proposes a high-voltage isolation ring structure for the gate drive circuit. The technical solution of this invention will be further illustrated below with reference to the accompanying drawings and specific embodiments.

[0033] like Figure 3 The diagram shown is a cross-sectional schematic of the high-voltage isolation ring structure of the gate drive circuit according to an embodiment of the present invention. The high-voltage isolation ring structure of this embodiment includes at least: a high-voltage field-effect transistor (FET), a high-voltage isolation ring, and a high-voltage transition region connecting the FET and the isolation ring. The FET, the transition region, and the isolation ring together form a closed-loop structure. Figure 3As shown, in the embodiment of the present application, the closed loop structure is a closed square ring, and the corners are treated with a circular arc. The inside of the closed loop structure is a high-end voltage area, and the outside is a low-end voltage area.

[0034] The high-voltage isolation ring structure of the embodiment of the present application further comprises: a P-type shielding isolation ring inserted between the high-voltage field effect tube and the high-end voltage area, a self-shielding isolation ring nested on the P-type shielding isolation ring, and a high-voltage interconnection parasitic resistance area formed between the P-type shielding isolation rings. Specifically, in the embodiment of the present application, two P-type shielding isolation rings are inserted between the high-voltage field effect tube and the high-end voltage area, and the corners are treated with a circular arc to improve the electric field on the corners. Here, the P-type shielding isolation ring is used to completely isolate the high-voltage field effect tube and the high-end voltage area. The high-voltage interconnection parasitic resistance area is formed between the two P-type shielding isolation rings.

[0035] Figure 5 As shown Figure 3 As shown Figure 5 As shown, in the embodiment of the present application, the high-voltage field effect tube is an LDMOS, which comprises: a P-type substrate, an epitaxial layer located on the P-type substrate, a source of the LDMOS close to the low-end voltage area, a drain of the LDMOS close to the P-type shielding isolation ring, and a gate located between the source and the drain. A high-voltage P-well is provided in the epitaxial layer below the source of the LDMOS, and the high-voltage P-well has a P-type heavily doped region and an N-type heavily doped region; the epitaxial layer surface between the source and the drain of the LDMOS has a field oxide region, and field plates connected to the gate and the drain cover both ends of the field oxide region, a P-type top implant layer is formed in the epitaxial layer below the field oxide region, and an N-type heavily doped region is provided in the epitaxial region below the drain of the LDMOS portion.

[0036] In the embodiment of the present application, a high-voltage P-well and a P-type buried layer located on the high-voltage P-well are provided at the junction of the LDMOS portion and the low-end voltage area, the high-voltage P-well is located in the epitaxial layer, and the P-type buried layer is located at the junction of the P-type substrate and the epitaxial layer.

[0037] In the embodiment of the present application, the high-end voltage area comprises: a P-type substrate, an epitaxial layer located on the P-type substrate, an N-type buried layer located at the junction of the P-type substrate and the epitaxial layer, an N-type heavily doped region located at the surface of the epitaxial layer, and a power supply VB located above the N-type heavily doped region.

[0038] In the embodiment of the present application, the P-type shielding isolation ring comprises: a P-type substrate, an epitaxial region located on the P-type substrate, and a field oxide region located on the surface of the epitaxial region, a high-voltage P-well, and a P-type buried layer located on the high-voltage P-well, the high-voltage P-well is located in the epitaxial layer, and the P-type buried layer is located at the junction of the P-type substrate and the epitaxial layer.

[0039] Figure 4Fig. 1 is a cross-sectional view of a high-voltage interconnection parasitic resistance region of a high-voltage isolation ring structure according to an embodiment of the present application; Figure 6 Fig. 2 is a cross-sectional view of a high-voltage interconnection parasitic resistance region of a high-voltage isolation ring structure according to another embodiment of the present application; Figure 4 Fig. 3 is a cross-sectional view of a high-voltage interconnection parasitic resistance region of a high-voltage isolation ring structure according to another embodiment of the present application; Figure 4 Fig. 4 is a cross-sectional view of a high-voltage interconnection parasitic resistance region of a high-voltage isolation ring structure according to another embodiment of the present application; Figure 6 As shown in Fig. 4, in an embodiment of the present application, a segment is opened on one side of the first P-type shielding isolation ring surrounding the high-voltage field effect tube, and a first self-shielding isolation ring is filled in the segment. A segment is also opened on the other side of the second P-type shielding isolation ring surrounding the high-voltage field effect tube, and a second self-shielding isolation ring is filled in the segment. Thus, a high-voltage interconnection parasitic resistance region is formed from the drain VD end through the first self-shielding isolation ring to the N-epi region between the two P-type shielding isolation rings and then through the second self-shielding isolation ring to the power supply VB end.

[0040] In an embodiment of the present application, before N-epi growth, two buried layers NBL / PBL are implanted, and the P-type shielding isolation ring and self-shielding isolation ring regions are implanted with PBL.

[0041] N-type epitaxy is grown, and high temperature during the growth process causes the PBL region to expand into the N-epi.

[0042] Subsequently, field oxidation region (LOCOS) growth is performed, and high-energy PTOP implantation (or implantation + push well) is performed at the P-type shielding isolation ring position, so that the PTOP and PBL are connected together, and the high-voltage Level-shift region and high-end voltage region are completely isolated. However, the PBL on the N-epi and the N-epi region between the two shielding isolation rings do not have PTOP implantation, and form a parasitic resistance region.

[0043] The high-voltage isolation ring structure of the present application uses a P-type shielding isolation ring to completely isolate the high-voltage field effect tube and the high-end voltage region, and then nests a P-type self-shielding isolation ring on the P-type shielding isolation ring. The self-shielding isolation ring is realized by a separate P-type buried layer (PBL). When the N-epi above the PBL is completely depleted to realize self-shielding isolation when the N-epi is applied with high voltage at the VB / VD end, the N-epi is connected through the P-type shielding isolation ring + self-shielding isolation ring at the VB / VD end when low voltage is applied, and thus a semi-self-shielding isolation structure is realized, in which a partial region is completely shielded and isolated, and a partial region is self-shielded and isolated. The structure increases the parasitic resistance value and reduces the leakage loss from VB to VD by adjusting the position of the self-shielding isolation ring embedded in the P-type shielding isolation ring and the distance between the two P-type shielding isolation rings.

[0044] The above merely illustrates the preferred embodiments of the present application, and is not used to limit the present application, and any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A high voltage isolation ring structure of a gate drive circuit, characterized by, At least comprising: A closed loop structure formed by a high-voltage field effect tube, a high-voltage isolation ring and a high-voltage transition zone between the two; Two P-type shield isolation rings arranged in an inner-outer nested manner inserted between the high-voltage field effect tube and the high-voltage area; A self-shield isolation ring nested on each of the inner and outer P-type shield isolation rings; A high-voltage interconnection parasitic resistance zone formed between the two P-type shield isolation rings, the position of the self-shield isolation ring embedded in the P-type shield isolation ring and the spacing between the two P-type shield isolation rings are adjusted to adjust the parasitic N-epi resistance of the high-voltage interconnection parasitic resistance zone.

2. The high voltage isolation ring structure of the gate driving circuit according to claim 1, wherein, The closed loop structure is a closed square ring, and the corners are treated with a circular arc.

3. The high voltage isolation ring structure of the gate driving circuit according to claim 1, wherein, The high-voltage field effect tube is an LDMOS, which comprises a P-type base, an epitaxial layer on the P-type base, a source of the LDMOS close to the low-voltage area, a drain of the LDMOS close to the P-type shield isolation ring, and a gate between the source and the drain.

4. The high voltage isolation ring structure of the gate driving circuit according to claim 3, wherein, A P-well is provided in the epitaxial layer below the source of the LDMOS, the P-well has a P-type heavily doped region and an N-type heavily doped region; a field oxide region is provided on the surface of the epitaxial layer between the source and the drain of the LDMOS, and a field plate connected to the gate and the drain covers both ends of the field oxide region, a P-type top implant layer is formed in the epitaxial layer below the field oxide region, and an N-type heavily doped region is provided in the epitaxial layer below the drain of the LDMOS.

5. The high voltage isolation ring structure of the gate driving circuit according to claim 4, wherein, A high-voltage P-well and a P-type buried layer on the high-voltage P-well are provided at the junction of the LDMOS part and the low-voltage area, the high-voltage P-well is located in the epitaxial layer, and the P-type buried layer is located at the junction of the P-type base and the epitaxial layer.

6. The high voltage isolation ring structure of the gate driving circuit according to claim 5, wherein, The high-voltage area comprises a P-type base, an epitaxial layer on the P-type base, an N-type buried layer at the junction of the P-type base and the epitaxial layer, an N-type heavily doped region on the surface of the epitaxial layer, and a power supply VB above the N-type heavily doped region.

7. The high voltage isolation ring structure of the gate driving circuit according to claim 6, wherein, The P-type shield isolation ring is formed by a lower P-type buried layer and an upper high-voltage P-well in communication, and is in communication with the P-type base, a field oxide region is formed above the high-voltage P-well, and full isolation of the epitaxial layer on both sides of the P-type shield isolation ring is achieved.

8. The high voltage isolation ring structure of the gate driving circuit according to claim 1, wherein, The P-type shield isolation ring is segmented, and the segmented spare part is embedded with the self-shield isolation ring.

9. The high voltage isolation ring structure of the gate driving circuit according to claim 8, wherein, A section is opened near the source position on one side of the first P-type shield isolation ring closest to the high-voltage field effect tube, and is filled with a first self-shield isolation ring; a section is also opened on the other side of the second P-type shield isolation ring closest to the high-voltage field effect tube, and is filled with a second self-shield isolation ring.

10. The high voltage isolation ring structure of the gate driving circuit according to claim 9, wherein, The high-voltage interconnection parasitic resistance zone is formed from the drain VD end through the first self-shield isolation ring to the N-epi area between the two P-type isolation rings and then through the second self-shield isolation ring to the power supply VB end.

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