LDMOS device and method of manufacturing the same

Abstract

The application provides an LDMOS device and a manufacturing method thereof. The device comprises a substrate, a well region structure and a connecting structure. The substrate comprises a substrate, an epitaxial layer, a body region, a drift region and a source region. The substrate and the epitaxial layer are stacked in sequence. The body region and the drift region are in contact and are both located in the epitaxial layer. The source region is located in the body region. The doping type of the substrate, the epitaxial layer and the body region is the same. The doping type of the drift region and the source region is the same and is different from the doping type of the epitaxial layer. The well region structure is located in the epitaxial layer. The well region structure is in contact with the body region and the drift region respectively. The doping type of the well region structure is the same as that of the epitaxial layer. The doping concentration of the well region structure is higher than that of the epitaxial layer. The connecting structure is located in the epitaxial layer. The connecting structure is in contact with the substrate, the source region and the well region structure respectively. The connecting structure is used for connecting the substrate and the well region structure. The avalanche withstand capability of the device is high. The reliability and stability of the device are good.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically, to an LDMOS device and a method for fabricating the same. Background Technology

[0002] For power or switching LDMOS (Laterally Diffused Metal Oxide Semiconductor) FETs, due to the presence of inductive load and stray inductance, the energy stored in the inductor is released through the device at the moment of device turn-off, forcing the device to undergo avalanche breakdown. The resulting high voltage and high current surge can easily cause device failure. For RF LDMOS FETs, impedance mismatch during operation can also cause the device to enter an avalanche state, and low withstand capability can also lead to device failure. Therefore, improving the survivability of LDMOS FETs in avalanche mode, i.e., the ability to withstand high avalanche breakdown energy, is beneficial to improving the reliability, stability, and application range of the device. The avalanche breakdown energy withstand capability of a device is generally evaluated by Energy Avalanche Single Pulse (EAS) or Energy Avalanche Repetitive Pulse (EAR). Improving the avalanche breakdown energy withstand capability means improving EAS or EAR.

[0003] Currently, the main methods to improve the high avalanche breakdown energy of LDMOS FET devices are to adopt reasonable layout, better cell design, and optimized epitaxial materials. However, these methods only optimize and improve the external conditions and cannot improve the internal factors affecting EAS capability. This is because there is an unchangeable parasitic NPN transistor inside the cell. The internal parasitic NPN transistor is formed by the N-type source region, the P-type body region, and the N-type drift region. Although mature layouts short-circuit the N-type drift region and the P-type body region during lead hole routing, theoretically the device will not have secondary breakdown characteristics. However, during instantaneous switching state changes, current will still flow through the body region. If the forward voltage drop generated by the lateral current flowing through the body region exceeds the forward turn-on voltage threshold of the parasitic NPN transistor, the parasitic NPN transistor will turn on. Once the parasitic NPN transistor turns on, it often enters a positive feedback state, thus causing secondary breakdown. Once secondary breakdown occurs, the device is prone to failure.

[0004] A higher avalanche withstand capability means better robustness. For switching devices, this translates to higher EAS (Electronic Avalanche Surcharge) and better Unclamped Inductive Switching (UIS) capability, resulting in better stability and a wider range of applications.

[0005] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0006] The main objective of this application is to provide an LDMOS device and its fabrication method to solve the problem of poor reliability and stability of the device due to its low avalanche withstand capability in the prior art.

[0007] According to one aspect of the present invention, an LDMOS device is provided, the LDMOS device comprising a substrate, a well structure, and a connection structure, wherein the substrate comprises a substrate, an epitaxial layer, a body region, a drift region, and a source region, the substrate and the epitaxial layer are stacked sequentially, the body region is in contact with the drift region and is located within the epitaxial layer, the source region is located within the body region, the substrate, the epitaxial layer, and the body region are doped with the same type, the drift region is doped with the same type as the source region but with a different type than the doping type of the epitaxial layer; the well structure is located within the body region. In the epitaxial layer, the well structure is located on the side of the body region and the drift region closer to the substrate. The well structure is in contact with the body region and the drift region, respectively. The doping type of the well structure is the same as that of the epitaxial layer, and the doping concentration of the well structure is higher than that of the epitaxial layer. The connection structure is located in the epitaxial layer and on the side of the body region away from the drift region. The connection structure is in contact with the substrate, the source region, and the well structure, respectively. The connection structure is used to connect the substrate and the well structure.

[0008] Optionally, the connection structure includes a first connection layer and a second connection layer stacked sequentially along a direction away from the substrate. The connection structure also includes a third connection layer. The surface of the second connection layer away from the substrate is flush with the surface of the epitaxial layer away from the substrate. The second connection layer contacts the source region and a portion of the well region structure. The first connection layer contacts a portion of the well region structure. The first connection layer, the second connection layer, and the epitaxial layer have the same doping type. The doping concentration of the first connection layer is lower than that of the second connection layer. The third connection layer is located among the first connection layer, the second connection layer, and the epitaxial layer, and is in contact with the substrate.

[0009] Optionally, the well region structure includes a plurality of well regions stacked sequentially along the thickness direction of the substrate, wherein the well region farthest from the substrate is in contact with the body region and the drift region, respectively.

[0010] Optionally, the epitaxial layer is P-type doped and the drift region is N-type doped.

[0011] According to another aspect of this application, a method for fabricating an LDMOS device is also provided. The method includes: providing a substrate; forming an epitaxial layer, a well structure, and a connection structure on the substrate, wherein a body region, a drift region, and a source region are formed in the epitaxial layer, wherein the body region is in contact with the drift region, the source region is located in the body region, the body region and the drift region are located on the side of the well structure away from the substrate, the well structure is in contact with the body region and the drift region respectively, the connection structure is located in the epitaxial layer and on the side of the body region away from the drift region, the connection structure is in contact with the substrate, the source region, and the well structure respectively, the well structure, the epitaxial layer, the body region, and the substrate have the same doping type, and the doping concentration of the well structure is higher than the doping concentration of the epitaxial layer, the drift region and the source region have the same doping type but different doping type from the epitaxial layer.

[0012] Optionally, forming an epitaxial layer, a well structure, and a connection structure on the substrate, and forming a body region, a drift region, and a source region in the epitaxial layer, includes: forming the epitaxial layer and a first oxide layer sequentially stacked on the exposed surface of the substrate, and performing ion implantation on the epitaxial layer to obtain the well structure; removing the first oxide layer, and performing ion implantation on the epitaxial layer with the well structure to form the body region and the drift region; performing ion implantation on the body region to obtain the source region, and performing ion implantation on the epitaxial layer with the source region to obtain a first preliminary connection layer; performing ion implantation on the first preliminary connection layer to obtain a second connection layer, with the remaining first preliminary connection layer forming the first connection layer and the second connection layer forming the second connection layer. The surface of the epitaxial layer away from the substrate is flush with the surface of the epitaxial layer away from the substrate. The second connecting layer is in contact with the source region and the well region structure, respectively. The first connecting layer is in contact with the well region structure. The first connecting layer, the second connecting layer and the epitaxial layer have the same doping type. The doping concentration of the first connecting layer is lower than that of the second connecting layer. A portion of the first connecting layer, a portion of the second connecting layer and a portion of the epitaxial layer are removed to obtain a first opening. The first opening penetrates the first connecting layer and the second connecting layer, exposing a portion of the substrate. A metal material is deposited in the first opening to obtain a third connecting layer. The first connecting layer, the second connecting layer and the third connecting layer constitute the connecting structure.

[0013] Optionally, after removing the first oxide layer, the method further includes: sequentially forming a pre-gate oxide layer and a pre-gate layer on the exposed surface of the epitaxial layer; removing a portion of the pre-gate oxide layer and a portion of the pre-gate layer to obtain a gate oxide layer and a gate.

[0014] Optionally, before removing a portion of the first interconnect layer, a portion of the second interconnect layer, and a portion of the epitaxial layer, and after forming the body region and the drift region, the method further includes: performing ion implantation on the drift region to obtain a buffer zone, wherein the surface of the buffer zone away from the substrate is flush with the surface of the drift region away from the substrate; and performing ion implantation on the buffer zone to obtain a drain region, wherein the surface of the drain region away from the substrate is flush with the surface of the drift region away from the substrate.

[0015] Optionally, forming an epitaxial layer, a well region structure, and a connection structure on the substrate includes: sequentially forming the epitaxial layer and a first oxide layer on the exposed surface of the substrate; performing ion implantation on the epitaxial layer to obtain a plurality of well regions sequentially stacked along the thickness direction of the substrate, the plurality of well regions forming the well region structure; performing ion implantation on the epitaxial layer with the well region structure to obtain a first pre-connection layer, the first pre-connection layer being in contact with the well region structure; performing ion implantation on the first pre-connection layer to obtain a second connection layer, the remaining first pre-connection layer forming the first connection layer; removing the first oxide layer; performing ion implantation on the epitaxial layer forming the first connection layer to obtain the body region and the drift region, performing ion implantation on the body region to obtain the source region; removing a portion of the first connection layer, a portion of the second connection layer, and a portion of the epitaxial layer to obtain a first opening, the first opening penetrating the first connection layer and the second connection layer, and exposing a portion of the substrate; depositing a metal material in the first opening to obtain a third connection layer, the first connection layer, the second connection layer, and the third connection layer constituting the connection structure.

[0016] Optionally, forming an epitaxial layer, a well region structure, and a connection structure on the substrate includes: sequentially forming a first pre-epitaxial layer and a second oxide layer on the exposed surface of the substrate; ion implanting the first pre-epitaxial layer to obtain a plurality of well regions sequentially stacked along the thickness direction of the substrate, the plurality of well regions forming the well region structure; ion implanting the first pre-epitaxial layer with the well region structure to obtain a second pre-connection layer, and ion implanting the second pre-connection layer to obtain a third pre-connection layer, the second and third pre-connection layers respectively contacting the well region structure, the remaining second pre-connection layer forming the first connection layer, the doping concentration of the third pre-connection layer being higher than that of the second pre-connection layer; removing the second oxide layer to expose the first pre-epitaxial layer; and forming a second pre-epitaxial layer on the exposed surface of the first pre-epitaxial layer. The first and second pre-epitaxial layers constitute the epitaxial layer; ion implantation is performed on the second pre-epitaxial layer to form a fourth pre-connection layer, the fourth pre-connection layer being in contact with the third pre-connection layer, the doping concentration of the fourth pre-connection layer being equal to the doping concentration of the third pre-connection layer, and the fourth and third pre-connection layers forming the second connection layer; ion implantation is performed on the epitaxial layer forming the second connection layer to obtain the body region and the drift region, and ion implantation is performed on the body region to obtain the source region; a portion of the first connection layer, a portion of the second connection layer, and a portion of the epitaxial layer are removed to obtain a first opening, the first opening penetrating the first connection layer and the second connection layer, and exposing a portion of the substrate; a metal material is deposited in the first opening to obtain a third connection layer, and the first, second, and third connection layers constitute the connection structure.

[0017] By applying the technical solution of this application, the well structure and the connection structure are provided in the epitaxial layer, and the well structure is in contact with the connection structure, the substrate, and the source region, respectively. The well structure is also in contact with the body region and the drift region. The well structure has the same doping type as the epitaxial layer, and the doping concentration of the well structure is higher than that of the epitaxial layer. When avalanche occurs in the source region, the drift region, and the body region, the well structure and the connection structure can guide the hole current generated by the avalanche from the well structure and the connection structure to the substrate and then leave, thereby mitigating the intensity of the avalanche current flowing through the body region and the source region. This ensures that the device has a high avalanche withstand capability, solving the problem of poor reliability and stability of the device due to the low avalanche withstand capability in the prior art, and ensuring that the device has good reliability and stability. Attached Figure Description

[0018] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0019] Figure 1 A schematic flowchart illustrating a method for fabricating an LDMOS device according to an embodiment of this application is shown.

[0020] Figures 2 to 13 The diagrams show the structural schematics obtained after each process step in the fabrication method of an LDMOS device according to an embodiment of this application.

[0021] Figures 14 to 17 The diagrams show the structural schematics obtained after each process step of the fabrication method of an LDMOS device according to another embodiment of this application.

[0022] Figures 18 to 23 The diagrams show the structural schematics obtained after each process step of a method for fabricating an LDMOS device according to another embodiment of this application.

[0023] The above figures include the following reference numerals:

[0024] 10. Substrate; 20. Well region structure; 30. Interconnection structure; 40. Gate oxide layer; 50. Gate; 60. Field plate; 70. Dielectric layer; 80. First opening; 90. Preparatory gate oxide layer; 100. Preparatory gate; 101. Substrate; 102. Epitaxial layer; 103. Body region; 104. Drift region; 105. Source region; 106. Buffer zone; 107. Drain region; 108. First preparatory epitaxial layer; 109. Second preparatory epitaxial layer; 110. First oxide layer; 120. Second oxide layer; 201. Well region; 301. First interconnection layer; 302. Second interconnection layer; 303. Third interconnection layer; 304. First preparatory interconnection layer; 305. Second preparatory interconnection layer; 306. Third preparatory interconnection layer; 307. Fourth preparatory interconnection layer. Detailed Implementation

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0029] As mentioned in the background section, the existing technology suffers from poor reliability and stability due to the low avalanche withstand capability of the devices. In order to solve the above problems, a typical embodiment of this application provides an LDMOS device and a method for fabricating the same.

[0030] According to a typical embodiment of this application, an LDMOS device is provided, such as... Figure 13As shown, the LDMOS device includes a substrate 10, a well structure 20, and a connection structure 30. The substrate 10 includes a substrate 101, an epitaxial layer 102, a body region 103, a drift region 104, and a source region 105. The substrate 101 and the epitaxial layer 102 are stacked sequentially. The body region 103 is in contact with the drift region 104 and is located within the epitaxial layer 102. The source region 105 is located within the body region 103. The substrate 101, the epitaxial layer 102, and the body region 103 have the same doping type. The drift region 104 has the same doping type as the source region 105 but a different doping type than the epitaxial layer 102. The well structure 20 is located within the epitaxial layer 102. The well structure 20 is located on the side of the body region 103 and the drift region 104 closer to the substrate 101. The well structure 20 is in contact with the body region 103 and the drift region 104, respectively. The doping type of the well structure 20 is the same as that of the epitaxial layer 102, and the doping concentration of the well structure 20 is higher than that of the epitaxial layer 102. The connection structure 30 is located in the epitaxial layer 102 and on the side of the body region 103 away from the drift region 104. The connection structure 30 is in contact with the substrate 101, the source region 105 and the well structure 20, respectively. The connection structure 30 is used to connect the substrate 101 and the well structure 20.

[0031] The aforementioned LDMOS device includes a substrate, a well structure, and a connection structure. The substrate comprises a substrate, an epitaxial layer, a body region, a drift region, and a source region. The substrate and the epitaxial layer are stacked sequentially. The body region is in contact with the drift region and is located within the epitaxial layer. The source region is located within the body region. The substrate, the epitaxial layer, and the body region have the same doping type. The drift region has the same doping type as the source region but a different doping type than the epitaxial layer. The well structure is located within the epitaxial layer and is situated on the side of the body region and the drift region closest to the substrate. The well structure is in contact with both the body region and the drift region. The well structure has the same doping type as the epitaxial layer, and its doping concentration is higher than that of the epitaxial layer. The connection structure is located within the epitaxial layer and is situated on the side of the body region furthest from the drift region. The connection structure is in contact with the substrate, the source region, and the well structure, and is used to connect the substrate and the well structure. Compared to existing technologies where low avalanche withstand capability leads to poor reliability and stability, the LDMOS device of this application addresses this issue by incorporating a well structure and a connection structure in the epitaxial layer. The well structure contacts the connection structure, the substrate, and the source region, and also contacts the body region and the drift region. The well structure shares the same doping type as the epitaxial layer, but its doping concentration is higher. This allows the well structure and connection structure to guide the hole current generated by avalanche from the well structure and connection structure to the substrate and then away when avalanche occurs in the source region, drift region, and body region. This mitigates the intensity of the avalanche current flowing through the body region and source region, ensuring high avalanche withstand capability and resolving the problem of poor reliability and stability caused by low avalanche withstand capability in existing technologies. This results in better reliability and stability for the device.

[0032] Specifically, the aforementioned well structure and connection structure mitigate the intensity of avalanche current flowing through the aforementioned body region and source region, thereby delaying the turn-on of the parasitic NPN transistor. In addition, the aforementioned well structure and connection structure make the current generated by avalanche charge exhibit a discrete distribution, which can reduce the local temperature rise caused by avalanche current, further ensuring that the aforementioned device has a high avalanche withstand capability, and further ensuring that the aforementioned LDMOS device has good reliability and stability.

[0033] In one specific embodiment, the well structure and the connection structure described above enable the LDMOS device to operate in a larger mismatch mode. For a switch-mode MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the device can withstand greater avalanche energy, ensuring better robustness and allowing it to be used under more severe conditions, thus expanding the application range of the device.

[0034] This further ensures the good reliability and stability of the aforementioned LDMOS device. According to a specific embodiment of this application, such as... Figure 13 As shown, the connection structure 30 includes a first connection layer 301 and a second connection layer 302 stacked sequentially along a direction away from the substrate 101. The connection structure 30 also includes a third connection layer 303. The surface of the second connection layer 302 away from the substrate 101 is flush with the surface of the epitaxial layer 102 away from the substrate 101. The second connection layer 302 is in contact with the source region 105 and a portion of the well region structure 20. The first connection layer 301 is in contact with a portion of the well region structure 20. The first connection layer 301, the second connection layer 302 and the epitaxial layer 102 have the same doping type. The doping concentration of the first connection layer 301 is lower than that of the second connection layer 302. The third connection layer 303 is located in the first connection layer 301, the second connection layer 302 and the epitaxial layer 102, and is in contact with the substrate 101. By setting the connection structure including the first connection layer, the second connection layer and the third connection layer, with the second connection layer in contact with the source region and the well region respectively, and the third connection layer in contact with the substrate, the grounding of the source region is achieved. Since the doping concentration of the first connection layer is lower than that of the second connection layer, the short circuit between the body region and the source region is achieved. The third connection layer ensures that the breakdown voltage of the device is high, further ensuring the reliability and stability of the device.

[0035] Specifically, the doping concentration of the second connection layer in the above connection structure is higher than that of the first connection layer, which better realizes the grounding of the source region and avoids setting the P-type contact region in the prior art.

[0036] According to another specific embodiment of this application, such as Figure 13As shown, the substrate 10 further includes a buffer zone 106 and a drain region 107. The buffer zone 106 is located within the drift region 104, and the surface of the buffer zone 106 away from the substrate 101 is flush with the surface of the drift region 104 away from the substrate 101. The drain region 107 is located within the buffer zone 106, and the surface of the drain region 107 away from the substrate 101 is flush with the surface of the drift region 104 away from the substrate 101. The buffer zone can alleviate the electric field concentration in the drain region, ensuring a high breakdown voltage for the device and further guaranteeing its reliability and stability.

[0037] Specifically, the aforementioned drift region is the pressure-bearing area of ​​the aforementioned device.

[0038] According to another specific embodiment of this application, such as Figure 13 As shown, the LDMOS device further includes a gate oxide layer 40, a gate 50, and a field plate 60. The gate oxide layer 40 is located on the surface of the epitaxial layer 102 away from the substrate 101, and covers a portion of the body region 103. The gate 50 is located on the surface of the gate oxide layer 40 away from the epitaxial layer 102. The field plate 60 is located on the side of the gate 50 away from the gate oxide layer 40, and its projection in the epitaxial layer 102 covers a portion of the body region 103 and a portion of the drift region 104. By forming the gate oxide layer, the gate, and the field plate, the LDMOS device achieves good performance.

[0039] According to a specific embodiment of this application, such as Figure 13 As shown, the LDMOS device further includes a dielectric layer 70, which covers the surface of the gate 50 away from the substrate and a portion of the surface of the epitaxial layer 102 away from the substrate 101. The dielectric layer exposes the source region, drain region and interconnection structure of the device away from the substrate. The field plate is located on the surface of the dielectric layer away from the gate.

[0040] The aforementioned LDMOS device may further include a metal lead-out structure located on the portion of the epitaxial layer away from the substrate, and in contact with the source region, drain region, and interconnection structure, respectively. The metal lead-out structure enables shorting and grounding of the source region and the interconnection structure.

[0041] According to another specific embodiment of this application, such as Figure 13As shown, the well structure 20 includes a plurality of well regions 201 stacked sequentially along the thickness direction d of the substrate 101. Among the plurality of well regions 201, the well region 201 farthest from the substrate 101 is in contact with the body region 103 and the drift region 104, respectively. By providing body regions that are in contact with the body region and the drift region, and because the body structure is in contact with the connection structure, the body structure and the connection structure can shunt the hole current in the body region and allow the hole current to be introduced into the substrate, thereby mitigating the avalanche current intensity flowing through the body region and the source region. This further ensures that the device has a high avalanche withstand capability, solving the problem of poor reliability and stability of the device due to low avalanche withstand capability in the prior art, and further ensuring that the LDMOS device has good reliability and stability.

[0042] Specifically, the aforementioned well region structure forms a PN junction with the aforementioned drift region. The multi-layered well region can be used as a side field plate, resulting in a lower surface electric field strength of the device. This draws the collisional ionization center of the device into the device body. The multiple well regions can also introduce hole currents generated by shunt collisional ionization into hole paths, thereby reducing the hole current intensity flowing through the aforementioned body region, delaying the turn-on of the parasitic NPN transistor, and improving the avalanche ionization tolerance of the device. This allows the device to operate in more demanding avalanche modes, further ensuring the device's good reliability and stability.

[0043] In one specific embodiment, in the prior art, the MOSFET is a unipolar device. When the device is operating, electrons generated by impact ionization can leave the device from the drain, while holes leave the device more often through the path between the body region and the contact region of the P-type transistor. Under high output power, the impact ionization intensity of the device gradually increases. As a switch, the MOSFET can easily enter avalanche mode when the induced electromotive force is turned off. Although the body region is grounded together with the source through the contact region, as the hole current flowing through the body region gradually increases, when the forward voltage drop generated by the lateral current flowing through the body region exceeds the forward turn-on voltage of the PN junction between the body region and the source region of the parasitic NPN transistor, the device becomes increasingly vulnerable to avalanche mode. If the threshold is reached, the parasitic NPN transistor will turn on, and the resulting high current will burn out the device. The impact ionization of the device often leads to the turn-on of the parasitic NPN transistor, and high electric field strength and high current strength will generate even higher impact ionization intensity. By introducing the well region structure, the side field plate of the PN junction formed by the top well region and the drift region reduces the surface electric field strength, thereby pulling the impact ionization center of the device into the device body. This is beneficial for the hole current to leave from the bottom well region, and the structure itself extends to the heavily doped second connection layer and the first connection layer, which is beneficial for shunting the hole current generated by impact ionization, further ensuring the good reliability and stability of the device.

[0044] Specifically, the doping concentration of the multiple well regions can be adjusted according to actual needs, and the doping concentration of the multiple well regions can be different. In one specific embodiment, the well regions closer to the substrate in the above-mentioned well region structure have a higher doping concentration.

[0045] According to another specific embodiment of this application, the doping type of the epitaxial layer is P-type, and the doping type of the drift region is N-type.

[0046] Specifically, the doping type of the aforementioned well structure, the aforementioned first interconnecting layer, and the aforementioned second interconnecting layer is P-type.

[0047] According to an embodiment of this application, a method for fabricating an LDMOS device is also provided.

[0048] Figure 1 This is a flowchart illustrating a method for fabricating an LDMOS device according to an embodiment of this application. For example... Figure 1 As shown, the method includes the following steps:

[0049] Step S101, as follows Figure 2 As shown, a substrate 101 is provided;

[0050] Step S102, as follows Figure 12As shown, an epitaxial layer 102, a well structure 20, and a connection structure 30 are formed on the substrate 101. A body region 103, a drift region 104, and a source region 105 are formed in the epitaxial layer 102. The body region 103 is in contact with the drift region 104, and the source region 105 is located within the body region 103. The body region 103 and the drift region 104 are located on the side of the well structure 20 away from the substrate 101. The well structure 20 is in contact with both the body region 103 and the drift region 104. The connection structure 30... Located in the epitaxial layer 102 and on the side of the body region 103 away from the drift region 104, the connection structure 30 is in contact with the substrate 101, the source region 105, and the well region structure 20, respectively. The well region structure 20, the epitaxial layer 102, the body region 103, and the substrate 101 have the same doping type, and the doping concentration of the well region structure 20 is higher than that of the epitaxial layer 102. The drift region 104 and the source region 105 have the same doping type but different doping type from that of the epitaxial layer 102.

[0051] In the above-described method for fabricating an LDMOS device, firstly, a substrate is provided; then, an epitaxial layer, a well structure, and a connection structure are formed on the substrate. A body region, a drift region, and a source region are formed in the epitaxial layer. The body region is in contact with the drift region, the source region is located within the body region, and the body region and the drift region are located on the side of the well structure away from the substrate. The well structure is in contact with both the body region and the drift region. The connection structure is located in the epitaxial layer and on the side of the body region away from the drift region. The connection structure is in contact with the substrate, the source region, and the well structure. The well structure, the epitaxial layer, the body region, and the substrate have the same doping type, and the doping concentration of the well structure is higher than that of the epitaxial layer. The drift region and the source region have the same doping type but different doping type from the epitaxial layer. Compared to existing technologies where low avalanche withstand capability leads to poor reliability and stability, the LDMOS device fabrication method of this application addresses this issue by forming a well structure and a connection structure in the epitaxial layer. The well structure contacts the connection structure, the substrate, and the source region, and also contacts the body region and the drift region. The well structure has the same doping type as the epitaxial layer, but a higher doping concentration. This allows the well structure and connection structure to guide the hole current generated by avalanche from the well structure and connection structure to the substrate and then away when avalanche occurs in the source region, drift region, and body region. This mitigates the intensity of the avalanche current flowing through the body region and source region, ensuring high avalanche withstand capability and solving the problem of poor reliability and stability caused by low avalanche withstand capability in existing technologies. This method ensures better reliability and stability for the device.

[0052] According to a specific embodiment of this application, an epitaxial layer, a well region structure, and a connection structure are formed on the substrate, and a body region, a drift region, and a source region are formed in the epitaxial layer, including: Figure  2 As shown, the epitaxial layer 102 and the first oxide layer 110 are sequentially stacked on the exposed surface of the substrate 101, as follows: Figure 3 As shown, ion implantation is performed on the epitaxial layer 102 to obtain the well structure 20, as described above. Figure 4 As shown, the first oxide layer 110 is removed, as follows: Figure 7 As shown, ion implantation is performed on the epitaxial layer 102 on which the well region structure 20 is formed to form the body region 103 and the drift region 104; ion implantation is then performed on the body region 103 to obtain the source region 105, as shown. Figure 8As shown, ion implantation is performed on the epitaxial layer 102 on which the source region 105 is formed to obtain a first pre-connection layer 304, as shown. Figure 9 As shown, the first pre-connection layer 304 is ion implanted to obtain the second connection layer 302. The remaining first pre-connection layer 304 forms the first connection layer 301. The surface of the second connection layer 302 away from the substrate 101 is flush with the surface of the epitaxial layer 102 away from the substrate 101. The second connection layer 302 contacts the source region 105 and the well region structure 20, respectively. The first connection layer 301 contacts the well region structure 20. The first connection layer 301, the second connection layer 302, and the epitaxial layer 102 have the same doping type. The doping concentration of the first connection layer 301 is lower than that of the second connection layer 302. Figure 11 As shown, by removing a portion of the first interconnect layer 301, a portion of the second interconnect layer 302, and a portion of the epitaxial layer 102, a first opening 80 is obtained. The first opening 80 penetrates the first interconnect layer 301 and the second interconnect layer 302, exposing a portion of the substrate 101. Figure 12 As shown, a metal material is deposited in the first opening 80 to obtain a third connecting layer 303. The first connecting layer 301, the second connecting layer 302, and the third connecting layer 303 constitute the connecting structure. The first oxide layer can serve as a protective layer for subsequent ion implantation. By first forming the drift region and the body region, then forming the first connecting layer and the second connecting layer through ion implantation, and removing part of the first connecting layer, part of the second connecting layer, and part of the epitaxial layer to form the third connecting layer, the connecting structure is obtained. This ensures that when avalanche occurs in the source region, the drift region, and the body region, the hole current generated by the avalanche can be guided from the well structure and the connecting structure to the substrate and then away, mitigating the intensity of the avalanche current flowing through the body region and the source region. This ensures that the device has a high avalanche withstand capability, solving the problem of poor reliability and stability of the device due to low avalanche withstand capability in the prior art, and further ensuring good reliability and stability of the device.

[0053] Specifically, in order to achieve a higher breakdown voltage, a thicker epitaxial layer is often used. This increases the manufacturing difficulty of forming the first and second interconnect layers by ion implantation. Here, the coupling process between the third interconnect layer and the first and second interconnect layers is adopted. The first and second interconnect layers are shorted to the well structure and the body region, respectively, to better shunt the hole current generated by collisional ionization. Moreover, the first and second interconnect layers can reduce the inductance of the source region, ensuring higher gain of the device.

[0054] In one specific embodiment, compared to forming the first and second interconnect layers by ion implantation, the process of removing a portion of the first interconnect layer, a portion of the second interconnect layer, and a portion of the epitaxial layer to finally obtain the third interconnect layer ensures that the fabrication of the device is relatively simple and is applicable to cases where the epitaxial layer is thick.

[0055] According to another specific embodiment of this application, after removing the first oxide layer, the method further includes: as follows Figure 5 As shown, a pre-gate oxide layer 90 and a pre-gate 100 are sequentially formed on the exposed surface of the epitaxial layer 102; as Figure 6 As shown, by removing a portion of the pre-existing gate oxide layer 90 and a portion of the pre-existing gate 100, a gate oxide layer 40 and a gate 50 are obtained. By forming the gate oxide layer, the gate, and the field plate, the performance of the LDMOS device is ensured to be good.

[0056] Specifically, the above-mentioned pre-gate oxide layer is grown using a wet oxygen method, followed by the deposition of polysilicon and doping at the target concentration to obtain the above-mentioned pre-gate. Finally, the above-mentioned gate oxide layer and the above-mentioned gate are formed by etching.

[0057] According to another specific embodiment of this application, before removing a portion of the first connecting layer, a portion of the second connecting layer, and a portion of the epitaxial layer, and after forming the volume region and the drift region, the method further includes: as follows: Figure 10 As shown, ion implantation is performed on the drift region 104 to obtain a buffer zone 106. The surface of the buffer zone 106 away from the substrate 101 is flush with the surface of the drift region 104 away from the substrate 101. Ion implantation is then performed on the buffer zone 106 to obtain a drain region 107. The surface of the drain region 107 away from the substrate 101 is flush with the surface of the drift region 104 away from the substrate 101. The buffer zone can alleviate the electric field concentration in the drain region, ensuring a high breakdown voltage of the device and further guaranteeing the reliability and stability of the device.

[0058] According to a specific embodiment of this application, an epitaxial layer, a well region structure, and a connection structure are formed on the substrate, and a body region, a drift region, and a source region are formed in the epitaxial layer, including: Figure 2 As shown, the epitaxial layer 102 and the first oxide layer 110 are sequentially formed on the exposed surface of the substrate 101; as Figure 3 As shown, ion implantation is performed on the epitaxial layer 102 to obtain a plurality of well regions 201 sequentially stacked along the thickness direction of the substrate 101, and the plurality of well regions 201 form the well region structure 20; as Figure 14 As shown, ion implantation is performed on the epitaxial layer 102 on which the well structure 20 is formed to obtain the first pre-connection layer 304, which is in contact with the well structure 20; as Figure 15 As shown, ion implantation is performed on the first pre-connection layer 304 to obtain the second connection layer 302, and the remaining first pre-connection layer 304 forms the first connection layer 301; as Figure 16 As shown, the first oxide layer 110 is removed; as Figure 17 As shown, ion implantation is performed on the epitaxial layer 102 forming the first interconnecting layer 301 to obtain the body region 103 and the drift region 104. Ion implantation is then performed on the body region 103 to obtain the source region 105. Figure 11 As shown, by removing a portion of the first interconnect layer 301, a portion of the second interconnect layer 302, and a portion of the epitaxial layer 102, a first opening 80 is obtained. The first opening 80 penetrates the first interconnect layer 301 and the second interconnect layer 302, exposing a portion of the substrate 101. Figure 12 As shown, a metal material is deposited in the first opening 80 to obtain a third connecting layer 303. The first connecting layer 301, the second connecting layer 302, and the third connecting layer 303 constitute the connecting structure 30. The first oxide layer can serve as a protective layer for subsequent ion implantation. By directly forming the epitaxial layer and then forming the first and second connecting layers through ion implantation, the fabrication process is kept relatively simple, and the manufacturing cost of the device is kept low.

[0059] Specifically, the method of directly forming the epitaxial layer and then forming the first and second connecting layers by ion implantation is suitable for cases where the epitaxial layer is relatively thin.

[0060] In one specific embodiment, compared to forming the first connecting layer and the second connecting layer after forming the drift region and the body region, forming the first connecting layer and the second connecting layer directly after forming the epitaxial layer reduces the difficulty of the process.

[0061] To further ensure the reliability and stability of the aforementioned LDMOS device, according to another specific embodiment of this application, an epitaxial layer, a well region structure, and a connection structure are formed on the substrate, and a body region, a drift region, and a source region are formed in the epitaxial layer, including: Figure 18 As shown, a first pre-epitaxial layer 108 and a second oxide layer 120 are sequentially formed on the exposed surface of the substrate 101; as Figure 19 As shown, ion implantation is performed on the first pre-epithetical layer 108 to obtain a plurality of well regions 201 sequentially stacked along the thickness direction of the substrate 101, and the plurality of well regions 201 form the well region structure 20; as Figure 20 As shown, ion implantation is performed on the first pre-epithetical layer 108 on which the above-mentioned well structure 20 is formed to obtain a second pre-connection layer 305, as follows. Figure 21 As shown, the second pre-connection layer 305 is ion implanted to obtain a third pre-connection layer 306. The second and third pre-connection layers 305 are in contact with the well structure 20. The remaining second pre-connection layer 305 forms the first connection layer 301. The doping concentration of the third pre-connection layer 306 is higher than that of the second pre-connection layer 305. Figure 22 As shown, the second oxide layer 120 is removed to expose the first pre-epitaxial layer 108; as Figure 23 As shown, a second pre-epitaxial layer 109 is formed on the exposed surface of the first pre-epitaxial layer 108. The first pre-epitaxial layer 108 and the second pre-epitaxial layer 109 constitute the epitaxial layer 102. Ion implantation is performed on the second pre-epitaxial layer 109 to form a fourth pre-connection layer 307. The fourth pre-connection layer 307 is in contact with the third pre-connection layer 306. The doping concentration of the fourth pre-connection layer 307 is equal to the doping concentration of the third pre-connection layer 306. The fourth pre-connection layer 307 and the third pre-connection layer 306 form the second connection layer 302. Figure 17 As shown, ion implantation is performed on the epitaxial layer 102 forming the second interconnecting layer 302 to obtain the body region 103 and the drift region 104. Ion implantation is then performed on the body region 103 to obtain the source region 105. Figure 11 As shown, by removing a portion of the first interconnect layer 301, a portion of the second interconnect layer 302, and a portion of the epitaxial layer 102, a first opening 80 is obtained. The first opening 80 penetrates the first interconnect layer 301 and the second interconnect layer 302, exposing a portion of the substrate 101. Figure 12As shown, a metal material is deposited in the first opening 80 to obtain a third interconnect layer 303. The first interconnect layer 301, the second interconnect layer 302, and the third interconnect layer 303 constitute the interconnect structure 30. The second oxide layer can serve as a protective layer for subsequent ion implantation. By first forming the first pre-epitaxial layer and then forming the well structure, the first interconnect layer, and the third pre-epitaxial layer through ion implantation, the ion implantation energy is kept low. Then, the second pre-epitaxial layer and the fourth pre-epitaxial layer are formed to obtain the epitaxial layer and the second interconnect layer. This ensures that the ion implantation energy for forming the first interconnect layer and the second interconnect layer is kept low, while minimizing damage to the epitaxial layer during the ion implantation process. This further ensures the good reliability and stability of the LDMOS device.

[0062] In one specific embodiment, the method of first forming the first pre-epilithographic layer, then forming the well structure, the first interconnecting layer, and the third pre-epilithographic layer by ion implantation, and then forming the second pre-epilithographic layer and the fourth pre-epilithographic layer, is suitable for cases where the epitaxial layer is relatively thick, ensuring minimal damage to the epitaxial layer.

[0063] Specifically, the aforementioned body region is first implanted with ions on the side of the gate near the first interconnecting layer, and then diffused laterally to the side of the gate near the epitaxial layer.

[0064] In one specific embodiment, the first oxide layer and the second oxide layer are removed by a standard cleaning method.

[0065] According to another specific embodiment of this application, the aforementioned metallic material includes tungsten.

[0066] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0067] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An LDMOS device, characterized in that, include: The substrate includes a substrate, an epitaxial layer, a body region, a drift region, and a source region. The substrate and the epitaxial layer are stacked sequentially. The body region is in contact with the drift region and is located within the epitaxial layer. The source region is located within the body region. The substrate, the epitaxial layer, and the body region have the same doping type. The drift region has the same doping type as the source region but a different doping type than the epitaxial layer. A well region structure is located in the epitaxial layer, and the well region structure is located on the side of the body region and the drift region closer to the substrate. The well region structure is in contact with the body region and the drift region, respectively. The doping type of the well region structure is the same as that of the epitaxial layer, and the doping concentration of the well region structure is higher than that of the epitaxial layer. A connection structure is located in the epitaxial layer and on the side of the body region away from the drift region. The connection structure is in contact with the substrate, the source region, and the well region structure, respectively. The connection structure is used to connect the substrate and the well region structure. The connection structure includes: A first interconnect layer and a second interconnect layer are sequentially stacked along a direction away from the substrate. The surface of the second interconnect layer away from the substrate is flush with the surface of the epitaxial layer away from the substrate. The second interconnect layer is in contact with the source region and a portion of the well region structure. The first interconnect layer is in contact with a portion of the well region structure. The first interconnect layer, the second interconnect layer and the epitaxial layer have the same doping type. The doping concentration of the first interconnect layer is lower than that of the second interconnect layer. The third connecting layer is located among the first connecting layer, the second connecting layer, and the epitaxial layer, and is in contact with the substrate.

2. The LDMOS device according to claim 1, characterized in that, The well structure includes multiple well regions stacked sequentially along the thickness direction of the substrate. Among the multiple well regions, the well region farthest from the substrate is in contact with the body region and the drift region, respectively.

3. The LDMOS device according to claim 1 or 2, characterized in that, The epitaxial layer is doped with P-type, and the drift region is doped with N-type.

4. A method for fabricating an LDMOS device, characterized in that, The method includes: Provide substrate; An epitaxial layer, a well region structure, and a connection structure are formed on the substrate. A body region, a drift region, and a source region are formed in the epitaxial layer. The body region is in contact with the drift region, and the source region is located in the body region. The body region and the drift region are located on the side of the well region structure away from the substrate. The well region structure is in contact with both the body region and the drift region. The connection structure is located in the epitaxial layer and on the side of the body region away from the drift region. The connection structure is in contact with the substrate, the source region, and the well region structure. The well region structure, the epitaxial layer, the body region, and the substrate have the same doping type, and the doping concentration of the well region structure is higher than that of the epitaxial layer. The drift region and the source region have the same doping type but different doping type from that of the epitaxial layer. An epitaxial layer, a well region structure, and a connection structure are formed on the substrate, and a body region, a drift region, and a source region are formed in the epitaxial layer, including: An epitaxial layer and a first oxide layer are sequentially stacked on the exposed surface of the substrate, and the epitaxial layer is ion implanted to obtain the well region structure. The first oxide layer is removed, and the epitaxial layer with the well region structure is ion implanted to form the bulk region and the drift region. Ion implantation is performed on the body region to obtain the source region, and ion implantation is performed on the epitaxial layer on which the source region is formed to obtain a first pre-connection layer. Ion implantation is then performed on the first pre-connection layer to obtain a second connection layer. The remaining first pre-connection layer forms the first connection layer. The surface of the second connection layer away from the substrate is flush with the surface of the epitaxial layer away from the substrate. The second connection layer is in contact with both the source region and the well region structure. The first connection layer is in contact with the well region structure. The first connection layer, the second connection layer, and the epitaxial layer have the same doping type. The doping concentration of the first connection layer is lower than that of the second connection layer. A portion of the first connection layer, a portion of the second connection layer, and a portion of the epitaxial layer are removed to obtain a first opening. The first opening penetrates the first connection layer and the second connection layer, exposing a portion of the substrate. Metallic material is deposited in the first opening to obtain a third connecting layer. The first connecting layer, the second connecting layer, and the third connecting layer constitute the connecting structure.

5. The method according to claim 4, characterized in that, After removing the first oxide layer, the method further includes: A pre-gate oxide layer and a pre-gate are sequentially formed on the exposed surface of the epitaxial layer; Remove a portion of the prepared gate oxide layer and a portion of the prepared gate to obtain the gate oxide layer and the gate.

6. The method according to claim 4, characterized in that, Before removing a portion of the first connecting layer, a portion of the second connecting layer, and a portion of the epitaxial layer, and after forming the body region and the drift region, the method further includes: Ion implantation is performed on the drift region to obtain a buffer zone, wherein the surface of the buffer zone away from the substrate is flush with the surface of the drift region away from the substrate; Ion implantation is performed on the buffer zone to obtain a drain region, wherein the surface of the drain region away from the substrate is flush with the surface of the drift region away from the substrate.

7. The method according to claim 4, characterized in that, An epitaxial layer, a well region structure, and a connection structure are formed on the substrate, and a body region, a drift region, and a source region are formed in the epitaxial layer, including: The epitaxial layer and the first oxide layer are sequentially formed on the exposed surface of the substrate; Ion implantation is performed on the epitaxial layer to obtain a plurality of well regions that are sequentially stacked along the thickness direction of the substrate, and the plurality of well regions form the well region structure; Ion implantation is performed on the epitaxial layer on which the well region structure is formed to obtain the first pre-connection layer, which is in contact with the well region structure. Ion implantation is performed on the first pre-connection layer to obtain the second connection layer, and the remaining first pre-connection layer forms the first connection layer; Remove the first oxide layer; Ion implantation is performed on the epitaxial layer forming the first interconnect layer to obtain the bulk region and the drift region, and ion implantation is performed on the bulk region to obtain the source region; A portion of the first interconnect layer, a portion of the second interconnect layer, and a portion of the epitaxial layer are removed to obtain a first opening. The first opening penetrates the first interconnect layer and the second interconnect layer, thereby exposing a portion of the substrate. Metallic material is deposited in the first opening to obtain a third connecting layer. The first connecting layer, the second connecting layer, and the third connecting layer constitute the connecting structure.

8. The method according to claim 4, characterized in that, An epitaxial layer, a well region structure, and a connection structure are formed on the substrate, and a body region, a drift region, and a source region are formed in the epitaxial layer, including: A first pre-epipolar layer and a second oxide layer are sequentially formed on the exposed surface of the substrate; Ion implantation is performed on the first pre-epithetical layer to obtain a plurality of well regions that are sequentially stacked along the thickness direction of the substrate, and the plurality of well regions form the well region structure; Ion implantation is performed on the first pre-epithetical layer having the well region structure to obtain a second pre-connection layer, and ion implantation is performed on the second pre-connection layer to obtain a third pre-connection layer. The second and third pre-connection layers are respectively in contact with the well region structure, and the remaining second pre-connection layer forms the first connection layer. The doping concentration of the third pre-connection layer is higher than that of the second pre-connection layer. Remove the second oxide layer to expose the first prepared epitaxial layer; A second pre-epitaxial layer is formed on the exposed surface of the first pre-epitaxial layer, and the first pre-epitaxial layer and the second pre-epitaxial layer constitute the epitaxial layer; Ion implantation is performed on the second pre-epithetical layer to form a fourth pre-connection layer. The fourth pre-connection layer is in contact with the third pre-connection layer. The doping concentration of the fourth pre-connection layer is equal to the doping concentration of the third pre-connection layer. The fourth pre-connection layer and the third pre-connection layer form the second connection layer. Ion implantation is performed on the epitaxial layer forming the second interconnecting layer to obtain the bulk region and the drift region, and ion implantation is performed on the bulk region to obtain the source region; A portion of the first interconnect layer, a portion of the second interconnect layer, and a portion of the epitaxial layer are removed to obtain a first opening. The first opening penetrates the first interconnect layer and the second interconnect layer, thereby exposing a portion of the substrate. Metallic material is deposited in the first opening to obtain a third connecting layer. The first connecting layer, the second connecting layer, and the third connecting layer constitute the connecting structure.

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