Semiconductor power device with back-gate structure and method of manufacturing the same
By employing a back-source structure in semiconductor power devices, placing the source on the back of the chip and the drain and gate on the front, vertical current conduction is achieved, solving the problems of large area and insufficient heat dissipation in traditional planar gate LDMOS, improving current handling capability and heat dissipation performance, and reducing parasitic inductance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 深圳市创飞芯源半导体有限公司
- Filing Date
- 2026-01-20
- Publication Date
- 2026-05-29
AI Technical Summary
Traditional planar gate lateral conductive MOSFETs have their source, drain, and gate located on the same side, resulting in a large chip area, limited power density, and insufficient heat dissipation capacity. This is especially problematic in high-voltage, high-current applications where current carrying capacity is insufficient and thermal management is difficult.
The chip employs a back-source structure, placing the source on the back of the chip and the drain and gate on the front. Current flows vertically through the chip and is dissipated through the substrate, shortening the current loop to reduce parasitic inductance.
It improves power density, enhances heat dissipation, reduces parasitic inductance, optimizes current handling capability, and retains the advantage of low input capacitance.
Smart Images
Figure CN122121197A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a semiconductor power device with a back-source structure and its fabrication method. Background Technology
[0002] In traditional planar gate lateral conduction MOSFETs (LDMOS), the source, drain, and gate are all located on the same side (the front of the chip). This design requires all pins (source, drain, and gate) to occupy area on the front of the chip, limiting power density. When applied to high-power scenarios, the lateral structure exposes significant limitations. The presence of the source, drain, and gate on the front of the chip in traditional planar gate LDMOS results in a large pin footprint, limited power density, long heat dissipation paths, and high parasitic inductance. Especially in high-voltage, high-current applications, the traditional lateral structure faces problems such as insufficient current carrying capacity and difficulties in thermal management.
[0003] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor power device with a back-source electrode structure and its fabrication method, so as to solve the problems of large chip electrode area and insufficient heat dissipation capacity in the prior art.
[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor power device with a back-source structure. The method includes: providing an N-type substrate; sequentially forming a gate dielectric layer and a gate layer on the N-type substrate; forming a P-type body region below one side of the gate layer, and forming a drain region in the N-type substrate on the other side of the gate layer; forming an N-type source region on the surface of the P-type body region; forming an isolation layer on the front side of the N-type substrate, and forming a drain via and a gate via in the isolation layer; forming a front metal in the isolation layer, the drain via, and the gate via, and patterning the front metal to form a drain and a gate; etching the back side of the N-type substrate to form a source via, the source via exposing the P-type body region and the N-type source region; forming an insulating layer on the back side of the N-type substrate and the sidewall of the source via, the insulating layer at least covering the N-type substrate exposed by the source via; depositing a source electrode in the back side of the N-type substrate and the source via, the source electrode being connected to the N-type source region and the P-type body region.
[0006] Optionally, the resistivity of the N-type substrate is 0.1 ohm·cm to 10 ohm·cm, the thickness is 1 micrometer to 10 micrometers, the thickness of the gate dielectric layer is 100 angstroms to 1000 angstroms, and the thickness of the gate layer is 0.3 micrometers to 2 micrometers.
[0007] Optionally, the thickness of the isolation layer is 0.5 micrometers to 1 micrometer, the thickness of the insulating layer is 0.5 micrometers to 2 micrometers, and the thickness of the drain and gate is 2 micrometers to 6 micrometers.
[0008] Optionally, forming the P-type body region includes implanting boron ions below one side of the gate layer, wherein the implantation dose is 1e12cm. -2 ~3e13cm -2 The injection energy is 30keV~200keV, and a high-temperature diffusion process is carried out at 1000℃~1150℃ for 30min~90min to form the P-type body region.
[0009] Optionally, forming the N-type source region includes: implanting arsenic ions into the surface layer of the P-type body region at an implantation dose of 1e15cm. -2 ~3e16cm -2 The injection energy is 20keV~200keV, and then a high-temperature diffusion process is carried out at 900℃~1000℃ for 30min~90min to form an N-type source region.
[0010] Optionally, the N-type source region extends beyond the edge of the P-type body region in a direction away from the gate layer, and the source is connected to the N-type source region extending beyond the edge of the P-type body region.
[0011] Optionally, the source region and the drain region are isolated by the P-type body region and the source via.
[0012] The present invention also provides a semiconductor power device having a back-source structure, the semiconductor power device comprising: an N-type substrate; a gate dielectric layer and a gate layer sequentially formed on the N-type substrate; a P-type body region formed below one side of the gate layer; a drain region formed in the N-type substrate on the other side of the gate layer; an N-type source region formed on the surface of the P-type body region; an isolation layer formed on the front side of the N-type substrate, wherein a drain via and a gate via are formed in the isolation layer; a drain and a gate are formed on the isolation layer and connected to the drain region and the gate layer respectively through the drain via and the gate via; a source via formed on the back side of the N-type substrate, the source via exposing the P-type body region and the N-type source region; an insulating layer formed on the back side of the N-type substrate and the sidewall of the source via, the insulating layer at least covering the N-type substrate exposed by the source via; and a source formed on the back side of the N-type substrate, the source being connected to the N-type source region and the P-type body region.
[0013] Optionally, the resistivity of the N-type substrate is 0.1 ohm·cm to 10 ohm·cm, the thickness is 1 micrometer to 10 micrometers, the thickness of the gate dielectric layer is 100 angstroms to 1000 angstroms, and the thickness of the gate layer is 0.3 micrometers to 2 micrometers.
[0014] Optionally, the thickness of the isolation layer is 0.5 micrometers to 1 micrometer, the thickness of the insulating layer is 0.5 micrometers to 2 micrometers, and the thickness of the drain and gate is 2 micrometers to 6 micrometers.
[0015] Optionally, the N-type source region extends beyond the edge of the P-type body region in a direction away from the gate layer, and the source is connected to the N-type source region extending beyond the edge of the P-type body region.
[0016] Optionally, the source region and the drain region are isolated by the P-type body region and the source via.
[0017] As described above, the semiconductor power device with a back-source structure and its fabrication method of the present invention have the following beneficial effects:
[0018] In this invention, the gate and drain are placed on the front side, while the source is placed on the back side for heat dissipation, resulting in high area utilization and effectively improving the power density of the device.
[0019] This invention changes the current direction to pass vertically through the entire semiconductor substrate, which can effectively improve the current handling capability of the device and optimize device performance.
[0020] The gate and drain of the device of the present invention are located on the front side of the chip, and the source of the device is located on the back side of the chip. This structure retains the advantage of low input capacitance of LDMOS, and places the source on the back side of the chip, which can be directly dissipated through the substrate (such as PCB), greatly increasing the heat conduction area. At the same time, the back-source structure can significantly reduce parasitic inductance by shortening the current loop. Attached Figure Description
[0021] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.
[0022] Figures 1-11 The diagram shows the structural schematics of each step in the fabrication method of a semiconductor power device with a back-source structure according to an embodiment of the present invention. Figure 11 The diagram shown is a schematic diagram of a semiconductor power device with a back-source structure according to an embodiment of the present invention.
[0023] Component designation explanation
[0024] 101 N-type substrate 102 Gate dielectric layer 103 gate layer 104 P-type body region 105 N-type source region 106 isolation layer 107 Drain 108 Insulation layer 109 Source via 110 Source 111 Leakage area Detailed Implementation
[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0026] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.
[0027] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.
[0028] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0029] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.
[0030] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0031] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0032] Traditional planar LDMOS transistors have their source, drain, and gate all located on the front side of the chip, resulting in a large pin footprint, limited power density, long heat dissipation paths, and high parasitic inductance. Especially in high-voltage, high-current applications, traditional lateral structures face problems such as insufficient current carrying capacity and difficulties in thermal management. To address these issues, this embodiment proposes a vertically current-conducting LDMOS structure. The source is located on the back side of the chip, while the drain and gate are located on the front side, enabling current to flow vertically through the chip. This improves current handling capacity, enhances heat dissipation, reduces parasitic inductance, and retains the advantage of low input capacitance of LDMOS transistors.
[0033] like Figures 1-11 As shown, this embodiment provides a method for fabricating a semiconductor power device with a back-source structure, the method comprising:
[0034] like Figures 1-3 As shown, step 1) is performed first, providing an N-type substrate 101, on which a gate dielectric layer 102 and a gate layer 103 are sequentially formed.
[0035] In some embodiments, the N-type substrate 101 can be an N-type substrate or an N-type epitaxial layer, and its material can be silicon, germanium, germanium silicon, silicon carbide, etc. The resistivity of the N-type substrate can be 0.1 ohm·cm to 10 ohm·cm, for example, 0.1 ohm·cm, 0.5 ohm·cm, 2 ohm·cm, 5 ohm·cm, 8 ohm·cm, 10 ohm·cm, etc. The thickness of the N-type substrate 101 can be 1 micrometer to 10 micrometers, for example, 1 micrometer, 2 micrometer, 4 micrometer, 6 micrometer, 8 micrometer, 10 micrometer, etc. The thickness of the gate dielectric layer 102 is 100 angstroms to 1000 angstroms, for example, 100 angstroms, 200 angstroms, 500 angstroms, 800 angstroms, 1000 angstroms, etc. The thickness of the gate layer 103 is 0.3 micrometers to 2 micrometers, for example, 0.3 micrometers, 0.8 micrometers, 1 micrometer, 1.5 micrometers, 2 micrometers, etc.
[0036] In some embodiments, the gate dielectric layer 102 may be silicon dioxide, silicon nitride, or a silicon dioxide / silicon nitride / silicon dioxide stack, etc., and the gate layer 103 may be polysilicon or metal, etc.
[0037] In some embodiments, the semiconductor power device includes at least two adjacent gate layers 103.
[0038] like Figure 4 As shown, then step 2) is performed, a P-type body region 104 is formed below one side of the gate layer 103, and a drain region 111 is formed in the N-type substrate 101 on the other side of the gate layer 103.
[0039] In some embodiments, forming the P-type body region 104 includes implanting boron ions below one side of the gate layer 103, wherein the implantation dose is 1e12cm. -2 ~3e13cm -2 The injection energy is 30keV~200keV, and a high-temperature diffusion process is carried out at 1000℃~1150℃ for 30min~90min to form the P-type body region 104.
[0040] In one embodiment, the semiconductor power device includes at least two P-type body regions 104 located inside two gate layers 103 facing each other, and a gap between the two P-type body regions 104.
[0041] like Figure 5 As shown, step 3) is then performed to form an N-type source region 105 on the surface of the P-type body region 104.
[0042] In some embodiments, forming the N-type source region 105 includes: implanting arsenic ions into the surface layer of the P-type body region 104 at an implantation dose of 1e15cm. -2~3e16cm -2 The injection energy is 20keV~200keV, and then a high-temperature diffusion process is carried out at 900℃~1000℃ for 30min~90min to form an N-type source region 105.
[0043] In some embodiments, the N-type source region 105 is also formed in the gap between the two P-type body regions 104.
[0044] like Figure 6 As shown, then step 4) is performed to form an isolation layer 106 on the front side of the N-type substrate 101. Drain vias and gate vias are formed in the isolation layer 106. The drain via exposes the drain region 111, and the gate via exposes the gate layer 103.
[0045] In some embodiments, the thickness of the isolation layer 106 is 0.5 micrometers to 1 micrometer. The isolation layer 106 may be, for example, silicon dioxide, silicon nitride, or a stacked structure thereof.
[0046] like Figure 7 As shown, step 5) is then performed, forming a front metal in the isolation layer 106, the drain via, and the gate via, and patterning the front metal to form the drain 107 and the gate.
[0047] In some embodiments, the front metal can be, for example, Al or Cu.
[0048] In some embodiments, the thickness of the drain 107 and the gate is 2 micrometers to 6 micrometers.
[0049] like Figures 8-9 As shown, then step 6) is performed to etch the back side of the N-type substrate 101 to form a source via 109, which exposes the P-type body region 104 and the N-type source region 105.
[0050] In some embodiments, the source region and the drain region 111 are isolated by the P-type body region 104 and the source via 109. When a voltage is applied to the gate layer 103, a channel can be formed in the P-type body region 104 to make the source region and the drain region 111 conduct.
[0051] Specifically, etching the back side of the N-type substrate 101 to form a source via 109 includes: forming an insulating layer on the back side of the N-type substrate 101; forming a photolithographic pattern on the surface of the insulating layer; etching the insulating layer to transfer the photolithographic pattern to the insulating layer; etching the N-type substrate 101 to form the source via 109, wherein the source via 109 is etched at least to the P-type body region 104 and exposes the N-type source region 105, so as to at least isolate the N-type source region 105 and the N-type substrate 101.
[0052] like Figure 10 As shown, then step 7) is performed to form an insulating layer on the back side of the N-type substrate 101 and the sidewall of the source via 109, the insulating layer at least covering the N-type substrate 101 exposed by the source via 109.
[0053] In some embodiments, the thickness of the insulating layer is 0.5 micrometers to 2 micrometers. The insulating layer may be silicon dioxide, silicon carbide, polymer, etc.
[0054] In some embodiments, forming an insulating layer on the back side of the N-type substrate 101 and the sidewall of the source via 109 includes: forming an insulating layer on the back side of the N-type substrate 101 and the sidewall and bottom of the source via 109 by an oxidation process or a deposition process; and removing the insulating layer at the bottom of the source via 109 by an etching process to expose the P-type body region 104 and the N-type source region 105 at the bottom of the source via 109.
[0055] like Figure 11 As shown, step 8) is performed last, depositing a source electrode 110 in the back side of the N-type substrate 101 and the source via 109, wherein the source electrode 110 is connected to the N-type source region 105 and the P-type body region 104.
[0056] In some embodiments, the N-type source region 105 extends beyond the edge of the P-type body region 104 in a direction away from the gate layer 103, and the source 110 is connected to the N-type source region 105 extending beyond the edge of the P-type body region 104.
[0057] In some embodiments, the source electrode 110 can be a Ti / Ni / Ag stack, etc.
[0058] like Figure 11As shown, this embodiment also provides a semiconductor power device with a back-source structure 110. The semiconductor power device includes: an N-type substrate 101; a gate dielectric layer 102 and a gate layer 103, sequentially formed on the N-type substrate 101; a P-type body region 104, formed below one side of the gate layer 103; a drain region 111, formed in the N-type substrate 101 on the other side of the gate layer 103; an N-type source region 105, formed on the surface of the P-type body region 104; an isolation layer 106, formed on the front side of the N-type substrate 101, wherein a drain via and a gate via are formed; and a drain 107 and a gate are formed. On the isolation layer 106, and connected to the drain region 111 and the gate layer 103 respectively through the drain via and the gate via; a source via 109 is formed on the back side of the N-type substrate 101, the source via 109 exposing the P-type body region 104 and the N-type source region 105; an insulating layer is formed on the back side of the N-type substrate 101 and the sidewall of the source via 109, the insulating layer at least covering the N-type substrate 101 exposed by the source via 109; a source 110 is formed on the back side of the N-type substrate 101, the source 110 is connected to the N-type source region 105 and the P-type body region 104.
[0059] In some embodiments, the resistivity of the N-type substrate 101 is 0.1 ohm·cm to 10 ohm·cm, and the thickness is 1 micrometer to 10 micrometers; the thickness of the gate dielectric layer 102 is 100 angstroms to 1000 angstroms; and the thickness of the gate layer 103 is 0.3 micrometers to 2 micrometers.
[0060] In some embodiments, the thickness of the isolation layer 106 is 0.5 micrometers to 1 micrometer, the thickness of the insulating layer is 0.5 micrometers to 2 micrometers, and the thickness of the drain 107 and the gate is 2 micrometers to 6 micrometers.
[0061] In some embodiments, the N-type source region 105 extends beyond the edge of the P-type body region 104 in a direction away from the gate layer 103, and the source 110 is connected to the N-type source region 105 extending beyond the edge of the P-type body region 104.
[0062] In some embodiments, the source region and the drain region 111 are isolated by the P-type body region 104 and the source via 109.
[0063] In some embodiments, the source electrode 110 on the back side can directly contact the circuit board (such as a PCB), which can effectively enhance the heat dissipation of semiconductor power devices.
[0064] As described above, the semiconductor power device with a back-source structure and its fabrication method of the present invention have the following beneficial effects:
[0065] In this invention, the gate and drain are placed on the front side, while the source is placed on the back side for heat dissipation, resulting in high area utilization and effectively improving the power density of the device.
[0066] This invention changes the current direction to pass vertically through the entire semiconductor substrate, which can effectively improve the current handling capability of the device and optimize device performance.
[0067] The gate and drain of the device of the present invention are located on the front side of the chip, and the source of the device is located on the back side of the chip. This structure retains the advantage of low input capacitance of LDMOS, and places the source on the back side of the chip, which can be directly dissipated through the substrate (such as PCB), greatly increasing the heat conduction area. At the same time, the back-source structure can significantly reduce parasitic inductance by shortening the current loop.
[0068] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a semiconductor power device with a back-source structure, characterized in that, The preparation method includes: Provides N-type substrate; A gate dielectric layer and a gate layer are sequentially formed on the N-type substrate; A P-type body region is formed below one side of the gate layer, and a drain region is formed in the N-type substrate on the other side of the gate layer; An N-type source region is formed on the surface of the P-type body region; An isolation layer is formed on the front side of the N-type substrate, and a drain via and a gate via are formed in the isolation layer; A front-side metal is formed in the isolation layer, drain via, and gate via, and the front-side metal is patterned to form the drain and gate. The back side of the N-type substrate is etched to form a source via, the source via exposing the P-type body region and the N-type source region; An insulating layer is formed on the back side of the N-type substrate and the sidewall of the source via, the insulating layer at least covering the N-type substrate exposed by the source via; A source electrode is deposited on the back side of the N-type substrate and in the source via, the source electrode being connected to the N-type source region and the P-type body region.
2. The method for fabricating a semiconductor power device with a back-source structure according to claim 1, characterized in that: The resistivity of the N-type substrate is 0.1 ohm·cm to 10 ohm·cm, and the thickness is 1 micrometer to 10 micrometers. The thickness of the gate dielectric layer is 100 angstroms to 1000 angstroms, and the thickness of the gate layer is 0.3 micrometers to 2 micrometers.
3. The method for fabricating a semiconductor power device with a back-source structure according to claim 1, characterized in that: The thickness of the isolation layer is 0.5 micrometers to 1 micrometer, the thickness of the insulating layer is 0.5 micrometers to 2 micrometers, and the thickness of the drain and gate is 2 micrometers to 6 micrometers.
4. The method for fabricating a semiconductor power device with a back-source structure according to claim 1, characterized in that: Forming the P-type body region includes implanting boron ions below one side of the gate layer, wherein the implantation dose is 1e12cm. -2 ~3e13cm -2 The injection energy is 30keV~200keV, and a high-temperature diffusion process is carried out at 1000℃~1150℃ for 30min~90min to form the P-type body region.
5. The method for fabricating a semiconductor power device with a back-source structure according to claim 1, characterized in that: Forming the N-type source region includes: implanting arsenic ions into the surface layer of the P-type body region at an implantation dose of 1e15cm. -2 ~3e16cm -2 The injection energy is 20keV~200keV, and then a high-temperature diffusion process is carried out at 900℃~1000℃ for 30min~90min to form an N-type source region.
6. The method for fabricating a semiconductor power device with a back-source structure according to claim 1, characterized in that: The N-type source region extends beyond the edge of the P-type body region in a direction away from the gate layer, and the source is connected to the N-type source region that extends beyond the edge of the P-type body region.
7. The method for fabricating a semiconductor power device with a back-source structure according to claim 1, characterized in that: The source region and the drain region are isolated by the P-type body region and the source via.
8. A semiconductor power device with a back-source structure, characterized in that, The semiconductor power device includes: N-type substrate; A gate dielectric layer and a gate layer are sequentially formed on the N-type substrate; A P-type body region is formed below one side of the gate layer; The drain region is formed in the N-type substrate on the other side of the gate layer; An N-type source region is formed on the surface of the P-type body region; An isolation layer is formed on the front side of the N-type substrate, and a drain via and a gate via are formed in the isolation layer; The drain and gate are formed on the isolation layer and are connected to the drain region and the gate layer through the drain via and the gate via, respectively. A source via is formed on the back side of the N-type substrate, the source via exposing the P-type body region and the N-type source region; An insulating layer is formed on the back side of the N-type substrate and the sidewall of the source via, the insulating layer at least covering the N-type substrate exposed by the source via; A source electrode is formed on the back side of the N-type substrate, and the source electrode is connected to the N-type source region and the P-type body region.
9. The semiconductor power device with a back-source structure according to claim 8, characterized in that: The resistivity of the N-type substrate is 0.1 ohm·cm to 10 ohm·cm, and the thickness is 1 micrometer to 10 micrometers. The thickness of the gate dielectric layer is 100 angstroms to 1000 angstroms, and the thickness of the gate layer is 0.3 micrometers to 2 micrometers.
10. The semiconductor power device with a back-source structure according to claim 8, characterized in that: The thickness of the isolation layer is 0.5 micrometers to 1 micrometer, the thickness of the insulating layer is 0.5 micrometers to 2 micrometers, and the thickness of the drain and gate is 2 micrometers to 6 micrometers.
11. The semiconductor power device with a back-source structure according to claim 8, characterized in that: The N-type source region extends beyond the edge of the P-type body region in a direction away from the gate layer, and the source is connected to the N-type source region that extends beyond the edge of the P-type body region.
12. The semiconductor power device with a back-source structure according to claim 8, characterized in that: The source region and the drain region are isolated by the P-type body region and the source via.