Overlapping tile component, manufacturing method of overlapping tile component, and photovoltaic cell

Abstract

The embodiments of the present application disclose a shingled assembly, a method for manufacturing a shingled assembly, and a photovoltaic cell. The shingled assembly includes at least two cells. Two adjacent cells partially overlap to form an overlapping area. The cell includes a substrate, a first tunneling layer, a first doped polysilicon layer, and a first main gate. The first tunneling layer is arranged on a first surface of the substrate, the first surface is a light-receiving surface, the first doped polysilicon layer is arranged on a side of the first tunneling layer away from the substrate, and the first main gate is arranged on a side of the first doped polysilicon layer away from the first tunneling layer; in two adjacent cell slices, the first tunneling layer, the first doped polysilicon layer, and the first main gate of the cell slice located below are arranged in the overlapping area.

Description

Technical Field

[0001] The present application relates to the photovoltaic field, and in particular to a shingled assembly, a method for manufacturing a shingled assembly, and a photovoltaic cell. Background Art

[0002] In solar cell technology, surface passivation is one of the key points. Currently, the mature PERC (Passivated Emitter and Rear Cell) cells are facing a bottleneck in efficiency breakthroughs, and there is still a large recombination in the area where the metal electrode contacts the silicon substrate. TOPCon (Tunnel Oxide Passivated Contact SolarCell) cells use a passivation structure in which a tunnel layer is superimposed on a doped polysilicon layer to achieve a passivation contact structure in which the electrode does not need to contact the silicon substrate, reducing recombination. However, due to the serious parasitic absorption of light by doped polysilicon, the light-receiving surface of the TOPCon cell still uses a traditional passivation structure, which results in a certain loss of efficiency.

[0003] Therefore, a technical solution that can improve the above problems is urgently needed. Summary of the invention

[0004] The embodiments of the present application provide a shingled assembly, a method for manufacturing a shingled assembly, and a photovoltaic cell, which can improve the serious problem of recombination between the main grid on the light-receiving surface of a TOPCon cell and the silicon substrate, and avoid the parasitic absorption problem of polycrystalline silicon.

[0005] The embodiment of the present application provides a shingled assembly, comprising at least two battery cells, wherein two adjacent battery cells partially overlap to form an overlapping area, and the battery cell comprises:

[0006] A substrate having a first surface, wherein the first surface is a light-receiving surface;

[0007] A first tunneling layer, disposed on a portion of the first surface;

[0008] A first doped polysilicon layer is disposed on a side of the first tunneling layer away from the substrate; and

[0009] A first main gate is disposed on a side of the first doped polysilicon layer away from the first tunneling layer;

[0010] Among the two adjacent battery cells, the first tunneling layer, the first doped polysilicon layer and the first main gate of the battery cell located at the bottom are arranged in the overlapping area.

[0011] Optionally, in some embodiments of the present application, the width of the first main grid is greater than or equal to 0.2 mm.

[0012] Optionally, in some embodiments of the present application, the substrate further has a second surface, the first surface and the second surface are located on opposite sides of the substrate, and the shingled assembly further includes:

[0013] A second tunneling layer disposed on the second surface;

[0014] A second doped polysilicon layer disposed on a side of the second tunneling layer away from the substrate;

[0015] A second main gate disposed on a side of the second doped polysilicon layer away from the second tunneling layer;

[0016] In two adjacent solar cells, the second main gate of the upper solar cell is disposed in the overlapping region, and the first main gate of the lower solar cell and the second main gate of the upper solar cell overlap and are electrically connected in the overlapping region.

[0017] Optionally, in some embodiments of the present application, the substrate is an N-type silicon substrate, the first doped polysilicon layer is a P-type doped polysilicon layer, and the second doped polysilicon layer is an N-type doped polysilicon layer.

[0018] Optionally, in some embodiments of the present application, the shingled assembly further includes a conductive adhesive. In two adjacent solar cells, the first main gate of the lower solar cell is electrically connected to the second main gate of the upper solar cell through the conductive adhesive.

[0019] Optionally, in some embodiments of the present application, the solar cell further includes:

[0020] A first passivation layer covering the first surface and the first doped polysilicon layer, and the first passivation layer is provided with a first groove and a first through hole;

[0021] The first main gate covers the first groove, and the first main gate contacts the first doped polysilicon layer through the first groove;

[0022] The conductive adhesive covers the first through hole, and the conductive adhesive contacts the first doped polysilicon layer through the first through hole.

[0023] Optionally, in some embodiments of the present application, the first passivation layer includes a lower passivation layer and an upper passivation layer, the lower passivation layer covers the first surface and the first doped polysilicon layer, and the upper passivation layer covers the lower passivation layer.

[0024] Optionally, in some embodiments of the present application, the solar cell further includes:

[0025] A second passivation layer, covering the second surface and the second doped polysilicon layer, the second passivation layer being provided with a second groove and a second through hole;

[0026] The second main gate covers the inside of the second groove, and the second main gate contacts the second doped polysilicon layer through the second groove;

[0027] The conductive adhesive covers the second through hole, and the conductive adhesive contacts the second doped polysilicon layer through the second through hole.

[0028] The embodiment of the present application further provides a method for manufacturing an overlapping tile assembly, including:

[0029] Forming a first tunneling layer on a first surface of a substrate, and forming a second tunneling layer on a second surface of the substrate, the first surface and the second surface being located on opposite sides of the substrate;

[0030] Forming a first doped polysilicon layer on the first tunneling layer, and forming a second doped polysilicon layer on the second tunneling layer;

[0031] Performing a patterning process on the first tunneling layer and the first doped polysilicon layer to obtain the local first tunneling layer and the first doped polysilicon layer sequentially disposed on the first surface;

[0032] Forming a first main gate on the first doped polysilicon layer, and forming a second main gate on the second doped polysilicon layer to obtain a cell;

[0033] Stacking and laminating and curing at least two of the cells, such that adjacent two of the cells partially overlap to form an overlapping region, and the portions of the first doped polysilicon layer corresponding to the overlapping region overlap; in two adjacent cells, the first tunneling layer and the first doped polysilicon layer of the cell located below are disposed in the overlapping region, and the first main gate of the cell located below and the second main gate of the cell located above overlap and are electrically connected in the overlapping region.

[0034] The embodiment of the present application further provides a photovoltaic cell, including the above-mentioned overlapping tile assembly.

[0035] The embodiment of the present application adopts an overlapping tile assembly, a method for manufacturing an overlapping tile assembly, and a photovoltaic cell. By providing a first tunneling layer and a first doped polysilicon layer between the first main gate and the substrate in the overlapping region, local passivation of the light-receiving surface of the cell can be achieved, the recombination problem between the first main gate and the substrate can be improved, and at the same time, since the first doped polysilicon layer is only provided in the shielded overlapping region, the parasitic absorption problem of polysilicon is avoided. Description of the Drawings

[0036] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0037] Figure 1 is a schematic cross-sectional structure diagram of an overlapping tile component provided by an embodiment of the present application;

[0038] Figure 2 is a partial microscopic view of the first battery cell in the overlapping area provided by an embodiment of the present application;

[0039] Figure 3 is a partial microscopic view of the second battery cell in the overlapping area provided by an embodiment of the present application;

[0040] Figure 4 is a partial microscopic view of the first battery cell and the second battery cell in the overlapping area provided by an embodiment of the present application;

[0041] Figure 5 is a schematic flowchart of a manufacturing method of an overlapping tile component provided by an embodiment of the present application;

[0042] Figure 6 is a schematic structure diagram of forming a tunneling layer and a doped polysilicon layer on a substrate provided by an embodiment of the present application;

[0043] Figure 7 is a schematic structure diagram after patterning the first tunneling layer and the first doped polysilicon layer provided by an embodiment of the present application;

[0044] Figure 8 is a schematic structure diagram of forming a passivation layer on the doped polysilicon layer and patterning the passivation layer provided by an embodiment of the present application;

[0045] Figure 9 is a partial microscopic view after patterning the passivation layer provided by an embodiment of the present application;

[0046] Figure 10 is a schematic structure diagram of forming a main grid on the doped polysilicon layer provided by an embodiment of the present application;

[0047] Figure 11 is a schematic top view structure diagram of a battery semi-finished product provided by an embodiment of the present application;

[0048] Figure 12 is a schematic bottom view structure diagram of a battery semi-finished product provided by an embodiment of the present application. Detailed implementation manners

[0049] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0050] The embodiments of the present application provide an overlapping tile assembly, a manufacturing method of the overlapping tile assembly, and a photovoltaic cell. The following will be described in detail respectively. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0051] Please refer to Figure 1 , the embodiments of the present application provide an overlapping tile assembly, including at least two overlapping cell sheets 1. Two adjacent cell sheets 1 partially overlap to form an overlapping area, that is, at least two cell sheets 1 are arranged in sequence, and there is partial overlap between two adjacent cell sheets 1. The overlapping part of two adjacent cell sheets 1 is the overlapping area. The overlapping tile assembly in the embodiments of the present application arranges the cell sheets 1 in an overlapping tile manner, and the edges of the cell sheets 1 are partially stacked, eliminating the spacing between the cell sheets 1, which is beneficial to improving the component efficiency.

[0052] As Figure 1 shown, the overlapping tile assembly only includes two cell sheets 1. For the convenience of explanation, two adjacent cell sheets 1 are respectively defined as the first cell sheet 1A and the second cell sheet 1B. The first cell sheet 1A and the second cell sheet 1B are arranged in sequence from left to right, and a part of the second cell sheet 1B is stacked on the first cell sheet 1A, so that the first cell sheet 1A and the second cell sheet 1B are partially overlapped. In this structure, when the light-receiving surface is above the first cell sheet 1A and the second cell sheet 1B, a part of the first cell sheet 1A is shielded by the first cell sheet 1A, and another part of the first cell sheet 1A is exposed and can receive light irradiation. Therefore, the exposed part of the first cell sheet 1A by the second cell sheet 1B can normally carry out the photovoltaic reaction; and the second cell sheet 1B is located at the top of the overlapping tile assembly, so the second cell sheet 1B will not be blocked by other cell sheets 1, and the second cell sheet 1B can receive light irradiation and carry out the photovoltaic reaction.

[0053] It is understandable that, according to the actual needs, the shingled assembly can include more cells 1, and the number of cells 1 is not limited here. When the shingled assembly includes more cells 1, the arrangement principle of the cells 1 is also the same, and they are arranged from top to bottom. The first cell 1 is located at the top, and the first cell 1 will not be blocked by other cells 1 and can perform photovoltaic reactions normally, while other cells 1 will be partially blocked by the cells 1 above them, and the exposed parts of other cells 1 can perform photovoltaic reactions normally.

[0054] Specifically, Figure 1 As shown, the cell 1 includes a substrate 11. The substrate 11 has a first surface 111 and a second surface 112, and the first surface 111 and the second surface 112 are located on opposite sides of the substrate 11. Specifically, the first surface 111 is located on the upper side of the substrate 11, and the second surface 112 is located on the lower side of the substrate 11. In this embodiment, the first surface 111 is a light-receiving surface.

[0055] Specifically, Figure 1 As shown, the cell 1 further includes a first tunneling layer 12, a first doped polysilicon layer 13 and a first main gate 15. The first tunneling layer 12 is disposed on a portion of the first surface 111. The first doped polysilicon layer 13 is disposed on a side of the first tunneling layer 12 that is away from the substrate 11. The first main gate 15 is disposed on a side of the first doped polysilicon layer 13 that is away from the first tunneling layer 12.

[0056] The side of the light-receiving surface of the cell 1 is defined as the upper side, and the side of the cell 1 away from the light-receiving surface is defined as the lower side. In two adjacent cells 1, the first tunneling layer 12 and the first doped polysilicon layer 13 of the cell 1 located at the lower side are arranged in the overlapping area. Figure 1 In the embodiment shown, the first cell 1A is located below the second cell 1B, and the first tunneling layer 12 and the first doped polysilicon layer 13 of the first cell 1A are arranged in the overlapping region. In this embodiment, in two adjacent cells 1, the first main grid 15 of the cell 1 located below is also arranged in the overlapping region.

[0057] Under this structure, the side of the cell 1 corresponding to the first main grid 15 is the light-receiving side. By arranging the first tunneling layer 12 and the first doped polysilicon layer 13 between the first main grid 15 and the substrate 11, the light-receiving surface of the cell 1 can be locally passivated, so that the first main grid 15 and the substrate 11 are in passivation contact through the first doped polysilicon layer 13 and the first tunneling layer 12, thereby improving the recombination problem between the first main grid 15 and the substrate 11. At the same time, since the first doped polysilicon layer 13 of the cell 1 below is only arranged in the shielded overlapping area, the parasitic absorption problem of polysilicon is avoided.

[0058] It is worth mentioning that the battery cell 1 also includes a first fine grid (not shown) arranged on the side of the first surface 111 of the substrate 11, and the first fine grid is used to collect photogenerated carriers of the substrate 11. The first fine grid intersects with the first main grid 15, and the first main grid 15 is used to collect photogenerated carriers of the substrate 11 and to collect the current of the first fine grid.

[0059] Specifically, Figure 1 As shown, the cell 1 further includes a second tunneling layer 16, a second doped polysilicon layer 17 and a second main gate 19, the second tunneling layer 16 is disposed on the second surface 112, the second doped polysilicon layer 17 is disposed on the side of the second tunneling layer 16 away from the substrate 11, and the second main gate 19 is disposed on the side of the second doped polysilicon layer 17 away from the second tunneling layer 16. Under this structure, by arranging the second tunneling layer 16 and the second doped polysilicon layer 17 between the second main gate 19 and the substrate 11, the second main gate 19 and the substrate 11 can be passivated through the second polysilicon and the second tunneling layer 16 to improve the recombination problem between the second main gate 19 and the substrate 11.

[0060] like Figure 1 As shown, in the shingled assembly of the embodiment of the present application, the light-receiving surfaces of different cells 1 are all located on the same side, each first busbar 15 is located on the light-receiving side of the corresponding cell 1, and each second busbar 19 is located on the side of the corresponding cell 1 away from the light-receiving side. In two adjacent cells 1, the second busbar 19 of the cell 1 located on the upper side is arranged in the overlapping area, and the second busbar 19 of the cell 1 located on the upper side and the first busbar 15 of the cell 1 located on the lower side overlap and are electrically connected in the overlapping area.

[0061] It is worth mentioning that the battery cell 1 also includes a second fine grid (not shown) arranged on the second surface 112 side of the substrate 11, and the second fine grid is used to collect photogenerated carriers of the substrate 11. The second fine grid intersects with the second main grid 19, and the second main grid 19 is used to collect photogenerated carriers of the substrate 11 and collect the current of the second fine grid.

[0062] Specifically, in each cell 1, the projections of the first main grid 15 and the second main grid 19 on the substrate 11 are staggered. In some embodiments of the present application, the first main grid 15 and the second main grid 19 are arranged on opposite sides of the substrate 11 in the horizontal direction, so that the projections of the first main grid 15 and the second main grid 19 on the substrate 11 are staggered. Under this structure, when different cells 1 are stacked, the second main grid 19 of the upper cell 1 overlaps and is electrically connected to the first main grid 15 of the lower cell 1 in the overlapping area, and the portion of the lower cell 1 outside the overlapping area can still receive light normally, so that all cells 1 can perform photovoltaic reactions. It should be noted that the horizontal direction refers to the direction parallel to the first surface 111 or the second surface 112 of the substrate 11.

[0063] Optionally, the width of the first doped polysilicon layer 13 is equal to the width of the overlapping region. In this structure, the space of the overlapping region can be fully utilized to achieve the passivation contact effect between the first main grid 15 and the substrate 11, which is beneficial to the widening design of the first main grid 15, thereby increasing the area of the first main grid 15, and further reducing the contact resistance between the first main grid 15 and the second main grid 19 between two adjacent solar cells 1. It should be noted that the width refers to the distance along the overlapping direction of adjacent solar cells 1, and the overlapping direction is the arrangement direction of the first solar cell 1A and the second solar cell 1B from left to right. The meaning of the width will not be repeated hereinafter. In this embodiment, the width of the overlapping region is greater than the width of the first main grid 15, and the width of the overlapping region is greater than the width of the second main grid 19.

[0064] It can be understood that, according to the requirements of the actual situation, the width of the first doped polysilicon layer 13 can also be less than the width of the overlapping region, as long as the first doped polysilicon layer 13 of one of the two adjacent solar cells 1 is arranged corresponding to the overlapping region, and there is no unique limitation here.

[0065] Specifically, the width of the first main grid 15 is greater than or equal to 0.2 mm. In the prior art, if the main grid on the light-receiving surface is widened, it will cause serious recombination problems. Therefore, it is difficult to widen the main grid on the light-receiving surface. In the embodiment of the present application, since the first tunneling layer 12 and the first doped polysilicon layer 13 are provided between the first main grid 15 and the substrate 11, the passivation contact effect can be achieved through the first tunneling layer 12 and the first doped polysilicon layer 13. Therefore, the recombination problem can be well improved. Therefore, the width of the first main grid 15 can be increased to more than 0.2 mm, thereby increasing the area of the first main grid 15, and further reducing the contact resistance between the first main grid 15 and the second main grid 19 between two adjacent solar cells 1. In this embodiment, the width of the second main grid 19 can also be greater than or equal to 0.2 mm, so that the specifications of the first main grid 15 and the second main grid 19 are adapted.

[0066] Furthermore, the width of the first main grid 15 is 1 mm to 2 mm, that is, the width of the first main grid 15 can be 1 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.4 mm, 1.5 mm, 1.6 mm, 1.7 mm, 1.8 mm, 1.9 mm or 2 mm. In this structure, both the width of the first main grid 15 can be increased, and the edge of the first main grid 15 can be prevented from exceeding the edge of the first doped polysilicon layer 13. In this embodiment, the width of the second main grid 19 can also be 1 mm to 2 mm, so that the specifications of the first main grid 15 and the second main grid 19 are adapted.

[0067] Specifically, the substrate 11 is a semiconductor substrate. Specifically, the substrate 11 can be an N-type silicon substrate 11. In this case, the first doped polysilicon layer 13 is a P-type doped polysilicon layer, and the second doped polysilicon layer 17 is an N-type doped polysilicon layer. Of course, according to the requirements of the actual situation, the substrate 11 can be other semiconductor materials or substrates 11 of other doping types, and the doping types of the first doped polysilicon layer 13 and the second doped polysilicon layer 17 are adaptively modified according to the doping type of the substrate 11, and no unique limitation is made here.

[0068] Specifically, the materials of the first tunneling layer 12 and the second tunneling layer 16 can be oxides. For example, the first tunneling layer 12 and the second tunneling layer 16 can be silicon oxide layers. Of course, according to the requirements of the actual situation, the materials of the first tunneling layer 12 and the second tunneling layer 16 can be appropriately modified, and no unique limitation is made here.

[0069] Specifically, the materials of the first main gate 15, the first fine gate, the second main gate 19 and the second fine gate can be metal materials. Among them, the materials of the first main gate 15 and the first fine gate can be silver and aluminum, and the materials of the second main gate 19 and the second fine gate can be silver. Of course, according to the requirements of the actual situation, the materials of the first main gate 15, the first fine gate, the second main gate 19 and the second fine gate can be appropriately modified, and no unique limitation is made here.

[0070] Specifically, as Figure 1 shown, the shingled module further includes a conductive adhesive 20. In two adjacent solar cells 1, the first main gate 15 of the lower solar cell 1 is electrically connected to the second main gate 19 of the upper solar cell 1 through the conductive adhesive 20.

[0071] Specifically, the conductive adhesive 20 includes conductive fillers. The materials of the conductive fillers are one or more combinations of conductive materials such as silver, gold, nickel, copper, aluminum, graphite, carbon black, and carbon nanotubes. The above-mentioned conductive materials have good electrical conductivity, which can make the first main gate 15 and the second main gate 19 better electrically connected. Of course, according to the requirements of the actual situation, the materials of the conductive fillers can be appropriately modified, and no unique limitation is made here.

[0072] In the embodiment of the present application, the conductive filler can specifically be silver particles, and the particle size of the silver particles is less than or equal to 10 microns. In this particle size range, the number of silver particles per unit volume of the conductive adhesive 20 is large, and the conductivity of the conductive adhesive 20 is good, which is beneficial to reducing the contact resistance between the first main gate 15 and the second main gate 19.

[0073] Specifically, as Figure 1As shown, the cell 1 further includes a first passivation layer 14. The first passivation layer 14 covers the first surface 111 and the first doped polysilicon layer 13, and the first passivation layer 14 is provided with a first hollow portion 143. The first main grid 15 covers the first passivation layer 14, and the first main grid 15 contacts the first doped polysilicon layer 13 through the first hollow portion 143.

[0074] Specifically, the first passivation layer 14 includes a lower passivation layer 141 and an upper passivation layer 142. Among them, the lower passivation layer 141 covers the first surface 111 and the first doped polysilicon layer 13, and the upper passivation layer 142 covers the lower passivation layer 141. The first hollow portion 143 can be etched in the upper passivation layer 142 and the lower passivation layer 141 by means of laser grooving.

[0075] Specifically, as Figure 1 As shown, the cell 1 further includes a second passivation layer 18. The second passivation layer 18 covers the second surface 112 and the second doped polysilicon layer 17, and the second passivation layer 18 is provided with a second hollow portion 181. The second main grid 19 covers the second passivation layer 18, and the second main grid 19 contacts the second doped polysilicon layer 17 through the second hollow portion 181.

[0076] Specifically, the lower passivation layer 141 can be an alumina passivation layer. The alumina surface has a high density of fixed negative charges and has an excellent field passivation effect on the surface of the P-type doped polysilicon layer. The upper passivation layer 142 and the second passivation layer 18 can be hydrogenated silicon nitride passivation layers, which play the roles of passivation, anti-pollution and anti-oxidation. Of course, according to the actual situation requirements, the materials of the lower passivation layer 141, the upper passivation layer 142 and the second passivation layer 18 can be appropriately modified, and are not uniquely limited here.

[0077] In the prior art, generally, a conductive adhesive 20 is used to connect the cells 1. However, due to the narrow coating process window of the conductive adhesive 20 and the fluid nature of the conductive adhesive 20 itself, glue overflow is likely to occur during the production process, resulting in short circuits of the battery string, and uneven coating of the conductive adhesive 20 leads to weak adhesion between the cells 1. In the outdoor harsh environment, due to thermal expansion and contraction, the connection part between the cells 1 is likely to shift, and the stability of the overlapping tile assembly is poor.

[0078] To solve the above problems that lead to poor stability of the overlapping tile assembly, in some embodiments of the present application, the following improvements are made to the overlapping tile assembly. Combining Figure 1 With Figure 2 , Figure 2 Only a partial microscopic view of the first cell 1A in the overlapping area is shown. From Figure 2It can be seen that among two adjacent solar cells 1, the lower solar cell 1 (the first solar cell 1A) has the following characteristics: the first main grid 15 covers a part of the first hollow portion 143, and the first main grid 15 is in contact with the first doped polysilicon layer 13 through the first hollow portion 143; the conductive adhesive 20 covers a part of the first hollow portion 143, and the conductive adhesive 20 is in contact with the first doped polysilicon layer 13 through the first hollow portion 143. In this structure, when there is enough conductive adhesive 20 between the first main grid 15 and the second main grid 19, the conductive adhesive 20 will penetrate into a part of the first hollow portion 143. The first hollow portion 143 can play a role in accommodating the excess conductive adhesive 20, improving the problem of short circuit caused by overflow of the adhesive, and also increasing the contact area between the conductive adhesive 20 and the solar cell 1, which is beneficial to increasing the adhesion force between two adjacent solar cells 1; moreover, since the conductive adhesive 20 is also in contact with the first doped polysilicon layer 13 through the first hollow portion 143, it is beneficial to improving the electrical contact between the solar cells 1, thereby improving the stability of the overlapping tile assembly.

[0079] Specifically, as Figure 2 shown, the first hollow portion 143 includes a first groove 1431 and a first through hole 1432. The first main grid 15 covers the first groove 1431, so that the first main grid 15 is in contact with the first doped polysilicon layer 13 through the first groove 1431. The conductive adhesive 20 covers the first through hole 1432, so that the conductive adhesive 20 is in contact with the first doped polysilicon layer 13 through the first through hole 1432. In this structure, among the lower solar cells 1 corresponding to two adjacent solar cells 1, the first main grid 15 covers a part of the first hollow portion 143, and the first main grid 15 is in contact with the first doped polysilicon layer 13 through the first hollow portion 143; the conductive adhesive 20 covers a part of the first hollow portion 143, and the conductive adhesive 20 is in contact with the first doped polysilicon layer 13 through the first hollow portion 143, which can improve the stability of the overlapping tile assembly. In this embodiment, the first fine grid also covers the corresponding first groove 1431.

[0080] Specifically, in combination with Figure 2 and Figure 11, the first main grid 15 is in a mesh shape, such that a plurality of first openings 151 are provided on the first main grid 15, and the first openings 151 are correspondingly arranged with the first through holes 1432, such that the first openings 151 communicate with the corresponding first through holes 1432. Specifically, one first opening 151 corresponds to one first through hole 1432 and is in communication therewith, or one first opening 151 may also correspond to at least two second through holes 1812 and be in communication therewith. In this structure, the conductive adhesive 20 can contact the first doped polysilicon layer 13 after passing through the first openings 151 and the first through holes 1432, which can further increase the contact area between the conductive adhesive 20 and the first main grid 15, facilitating the improvement of the electrical contact between the conductive adhesive 20 and the first main grid 15, and at the same time further increasing the adhesion force between the conductive adhesive 20 and the first main grid 15; moreover, since the first main grid 15 is a hollow structure, the metal paste used for manufacturing the first main grid 15 can be saved.

[0081] Specifically, the cross-sectional shape of the first opening 151 may be a polygon. For example, the cross-sectional shape of the first opening 151 may be a rectangle. Of course, according to the requirements of the actual situation, the cross-sectional shape of the first opening 151 may also be other quadrilaterals, pentagons, hexagons or other shapes, and is not uniquely limited herein.

[0082] Specifically, in two adjacent solar cells 1, the first passivation layer 14 of the solar cell 1 located below is provided with a plurality of first through holes 1432, and the plurality of first through holes 1432 are arranged in a matrix. In this embodiment, in two adjacent solar cells 1, the plurality of first through holes 1432 of the solar cell 1 located below are at least provided in the overlapping area. For example, the plurality of first through holes 1432 of the solar cell 1 located below may be only provided in the overlapping area, or may be provided in the light-receiving area outside the overlapping area, and is not uniquely limited herein. It should be noted that the light-receiving area refers to the area where the solar cell 1 can receive light irradiation.

[0083] Optionally, the first through hole 1432 may be, but is not limited to, a round hole, and the aperture of the first through hole 1432 may be greater than 10 microns, so that the conductive filler in the conductive adhesive 20 can be filled into the first through hole 1432, facilitating the realization of the electrical contact between the conductive adhesive 20 and the first doped polysilicon layer 13.

[0084] Optionally, the aperture of the first through hole 1432 is 60 microns to 150 microns. For example, the aperture of the first through hole 1432 may be 60 microns, 70 microns, 80 microns, 90 microns, 100 microns, 110 microns, 120 microns, 130 microns, 140 microns or 150 microns. In this structure, it can be ensured that the conductive adhesive 20 can be smoothly filled into the first through hole 1432, and at the same time it is also beneficial to increase the contact area between the conductive adhesive 20 and the first doped polysilicon layer 13, facilitating the improvement of the electrical contact between the conductive adhesive 20 and the first doped polysilicon layer 13.

[0085] Optionally, the cross-sectional area of the first opening 151 is larger than that of the first through hole 1432, so that a part of the surface of the corresponding overlapping area of the first passivation layer 14 can also be exposed. After the conductive adhesive 20 is filled into the first opening 151, it will contact the surface of the corresponding overlapping area of the first passivation layer 14, which can increase the contact area between the conductive adhesive 20 and the first passivation layer 14, and is beneficial to improving the adhesion between the conductive adhesive 20 and the battery cell 1, thereby improving the stability of the shingled module.

[0086] In some other embodiments of the present application, in combination with Figure 1 and Figure 3 , Figure 3 only a partial microscopic view of the second battery cell 1B in the overlapping area is shown. Figure 3 The corresponding embodiment is different from the embodiment corresponding to Figure 2 in that: the first hollow portion 143 only includes the first groove 1431, and the conductive adhesive 20 covers the first groove 1431; the second main grid 19 covers a part of the second hollow portion 181, and the second main grid 19 contacts the second doped polysilicon layer 17 through the second hollow portion 181; the conductive adhesive 20 covers a part of the second hollow portion 181, and the conductive adhesive 20 contacts the second doped polysilicon layer 17 through the second hollow portion 181. In this structure, when there is enough conductive adhesive 20 between the first main grid 15 and the second main grid 19, the conductive adhesive 20 will penetrate into a part of the second hollow portion 181, and the second hollow portion 181 can play a role in accommodating the excess conductive adhesive 20, improving the problem of short circuit caused by glue overflow, and can also increase the contact area between the conductive adhesive 20 and the battery cell 1, which is beneficial to increasing the adhesion between two adjacent battery cells 1; moreover, since the conductive adhesive 20 also contacts the second doped polysilicon layer 17 through the second hollow portion 181, it is beneficial to improving the electrical contact between the battery cells 1, thereby improving the stability of the shingled module.

[0087] Specifically, as Figure 3As shown, the second hollow portion 181 includes a second groove 1811 and a second through hole 1812. The second main grid 19 covers the inside of the second groove 1811, so that the second main grid 19 contacts the second doped polysilicon layer 17 through the second groove 1811. The conductive adhesive 20 covers the second through hole 1812, so that the conductive adhesive 20 contacts the second doped polysilicon layer 17 through the second through hole 1812. In this structure, among two adjacent solar cells 1, for the upper solar cell 1, the second main grid 19 covers a part of the second hollow portion 181, and the second main grid 19 contacts the second doped polysilicon layer 17 through the second hollow portion 181; the conductive adhesive 20 covers a part of the second hollow portion 181, and the conductive adhesive 20 contacts the second doped polysilicon layer 17 through the second hollow portion 181, which can improve the stability of the overlapping shingle module. In this embodiment, the second fine grid also covers the corresponding second groove 1811.

[0088] Specifically, Figure 3 the second main grid 19 and the second passivation layer 18 of the corresponding embodiment are the same as Figure 2 the first main grid 15 and the first passivation layer 14 of the corresponding embodiment. Please refer to Figure 3 and, at the same time, refer to Figure 11 The second main grid 19 is in a mesh shape, so that a plurality of second openings 191 are provided on the second main grid 19. The second openings 191 are correspondingly arranged with the second through holes 1812, so that the second openings 191 communicate with the corresponding second through holes 1812. Specifically, one second opening 191 corresponds to and communicates with one second through hole 1812, or one second opening 191 corresponds to and communicates with at least two second through holes 1812. In this structure, the conductive adhesive 20 can contact the second doped polysilicon layer 17 after passing through the second openings 191 and the second through holes 1812, which can further increase the contact area between the conductive adhesive 20 and the second main grid 19, is beneficial to improving the electrical contact between the conductive adhesive 20 and the second main grid 19, and at the same time further increases the adhesion between the conductive adhesive 20 and the second main grid 19; moreover, since the second main grid 19 is a hollow structure, the metal paste used for manufacturing the second main grid 19 can be saved.

[0089] Specifically, the cross-sectional shape of the second opening 191 can be a polygon. For example, the cross-sectional shape of the second opening 191 can be a rectangle. Of course, according to the actual requirements, the cross-sectional shape of the second opening 191 can also be other quadrilaterals, pentagons or hexagons, etc., and is not uniquely limited here.

[0090] Specifically, in two adjacent solar cells 1, the second passivation layer 18 of the upper solar cell 1 is provided with a plurality of second through-holes 1812, and the plurality of second through-holes 1812 are arranged in a matrix. In this embodiment, in two adjacent solar cells 1, the plurality of second through-holes 1812 of the upper solar cell 1 are at least provided in the overlapping area. For example, the plurality of second through-holes 1812 of the upper solar cell 1 can be only provided in the overlapping area, or can be provided in the light-receiving area outside the overlapping area, and there is no unique limitation here. It should be noted that the light-receiving area refers to the area where the solar cell 1 can receive light irradiation.

[0091] Optionally, the second through-hole 1812 can be, but is not limited to, a round hole, and the aperture of the second through-hole 1812 can be greater than 10 microns, so that the conductive filler in the conductive adhesive 20 can be filled into the second through-hole 1812, facilitating the electrical contact between the conductive adhesive 20 and the second doped polysilicon layer 17.

[0092] Optionally, the aperture of the second through-hole 1812 is 60 microns to 150 microns. For example, the aperture of the second through-hole 1812 can be 60 microns, 70 microns, 80 microns, 90 microns, 100 microns, 110 microns, 120 microns, 130 microns, 140 microns or 150 microns. In this structure, it can ensure that the conductive adhesive 20 can be smoothly filled into the second through-hole 1812, and at the same time, it is beneficial to increase the contact area between the conductive adhesive 20 and the second doped polysilicon layer 17, which is beneficial to improving the electrical contact between the conductive adhesive 20 and the second doped polysilicon layer 17.

[0093] Optionally, the cross-sectional area of the second opening 191 is larger than the cross-sectional area of the second through-hole 1812, so that the second opening 191 can also expose a part of the surface of the second passivation layer 18 corresponding to the overlapping area. After the conductive adhesive 20 is filled into the second opening 191, it will contact the surface of the second passivation layer 18 corresponding to the overlapping area, which can increase the contact area between the conductive adhesive 20 and the second passivation layer 18, beneficial to improving the adhesion force between the conductive adhesive 20 and the solar cell 1, thereby improving the stability of the overlapping tile assembly.

[0094] In other embodiments of the present application, in combination with Figure 1 and Figure 4 , Figure 4 shows a partial microscopic view of the overlapping area of the first solar cell 1A and the second solar cell 1B, Figure 4 the corresponding embodiment includes Figure 2 and Figure 3 the technical features of the corresponding embodiment, which can better improve the stability of the overlapping tile assembly.

[0095] In an embodiment of the present application, in two adjacent solar cells 1, the conductive adhesive 20 includes a first conductive portion 21 and a second conductive portion 22. The first conductive portion 21 is disposed between the first main grid 15 of the lower solar cell 1 and the second main grid 19 of the upper solar cell 1, and the second conductive portion 22 is filled in the first opening 151, the second opening 191, the first hollow portion 143 (the first through hole 1432), and the second hollow portion 181 (the second through hole 1812).

[0096] Please refer to Figure 5 , an embodiment of the present application further provides a method for manufacturing the above shingled assembly, including:

[0097] Step B1, as Figure 6 shown, a first tunneling layer 12 is formed on the first surface 111 of the substrate 11, and a second tunneling layer 16 is formed on the second surface 112 of the substrate 11. The first surface 111 and the second surface 112 are located on opposite sides of the substrate 11;

[0098] Step B2, as Figure 6 shown, a first doped polysilicon layer 13 is formed on the first tunneling layer 12, and a second doped polysilicon layer 17 is formed on the second tunneling layer 16;

[0099] Step B3, as Figure 7 shown, the first tunneling layer 12 and the first doped polysilicon layer 13 are patterned to obtain the first tunneling layer 12 and the first doped polysilicon layer 13 that are sequentially disposed locally on the first surface 111;

[0100] Step B4, as Figure 10 shown, a first main grid 15 is formed on the first doped polysilicon layer 13, and a second main grid 19 is formed on the second doped polysilicon layer 17 to obtain the solar cell 1;

[0101] Step B5, as Figure 1 shown, at least two solar cells 1 are stacked and laminated and cured, so that two adjacent solar cells 1 partially overlap to form an overlapping area, and the portions of the first doped polysilicon layer 13 corresponding to the overlapping area overlap; in two adjacent solar cells 1, the first tunneling layer 12 and the first doped polysilicon layer 13 of the lower solar cell 1 are disposed in the overlapping area, and the first main grid 15 of the lower solar cell 1 and the second main grid 19 of the upper solar cell 1 overlap and are electrically connected in the overlapping area.

[0102] Specifically, in step B1, before forming the first tunneling layer 12 and the second tunneling layer 16, the substrate 11 is textured and cleaned to remove impurities on the substrate 11 and improve the adhesion of the first tunneling layer 12 and the second tunneling layer 16 to the substrate 11.

[0103] Specifically, in step B3, the first tunneling layer 12 and the first doped polysilicon layer 13 can be patterned by laser or mask etching to remove the first tunneling layer 12 and the first doped polysilicon layer 13 in the regions other than the corresponding first main gate 15. Of course, according to the requirements of the actual situation, other methods can be used to pattern the first tunneling layer 12 and the first doped polysilicon layer 13, and this is not limited to a single method here.

[0104] Specifically, as Figure 8 and Figure 9 shown, after step B3 and after step B4, the manufacturing method of the overlapping tile assembly further includes:

[0105] Step B31: Form a first passivation layer 14 on the first doped polysilicon layer 13;

[0106] Step B32: Form a second passivation layer 18 on the second doped polysilicon layer 17;

[0107] Step B33: Pattern the first passivation layer 14 and / or the second passivation layer 18 to form a first hollow portion 143 provided in the first passivation layer 14 and a second hollow portion 181 provided in the second passivation layer 18. The specific structures of the first hollow portion 143 and the second hollow portion 181 are the same as those described above, and the specific structures of the first hollow portion 143 and the second hollow portion 181 will not be elaborated here. In this setting, the subsequently formed first main gate 15 covers the first passivation layer 14, and the first main gate 15 covers at least a part of the first hollow portion 143, so that the first main gate 15 contacts the first doped polysilicon layer 13 through the first hollow portion 143; the subsequently formed second main gate 19 covers the second passivation layer 18, and the second main gate 19 covers at least a part of the second hollow portion 181, so that the second main gate 19 contacts the second doped polysilicon layer 17 through the second hollow portion 181.

[0108] Specifically, the first passivation layer 14 includes a lower passivation layer 141 and an upper passivation layer 142, and step B31 includes:

[0109] Step B311: Form a lower passivation layer 141 on the first doped polysilicon layer 13;

[0110] Step B312: Form an upper passivation layer 142 on the lower passivation layer 141.

[0111] Specifically, in step B33, the first passivation layer 14 and / or the second passivation layer 18 can be patterned by a laser grooving process. Of course, according to the requirements of the actual situation, other methods can be used to pattern the first passivation layer 14 and / or the second passivation layer 18, and this is not limited to a single method here.

[0112] Specifically, in step B4, during the process of forming the first main grid 15, a first fine grid is also formed, that is, the first fine grid and the first main grid 15 are formed through the same process; during the process of forming the second main grid 19, a second fine grid is also formed, that is, the second fine grid and the second main grid 19 are formed through the same process.

[0113] Specifically, in step B4, silver-aluminum paste is used for screen printing on the first passivation layer 14 to form the first main grid 15 and the first fine grid, and silver paste is used for screen printing on the second passivation layer 18 to form the second main grid 19 and the second fine grid. Of course, according to the requirements of the actual situation, other processes can be used to form the first main grid 15, the first fine grid, the second main grid 19, and the second fine grid, and no unique limitation is made here.

[0114] Specifically, in step B33, at least two first hollow portions 143 and at least two second hollow portions 181 are formed. The number of the first hollow portions 143 is the same as the number of the first main grids 15 to be formed subsequently, and the number of the second hollow portions 181 is the same as the number of the second main grids 19 to be formed subsequently. In step B4, at least two first main grids 15 and at least two second main grids 19 are formed. Each first main grid 15 corresponds to a second main grid 19, and each first main grid 15 is arranged staggeredly with the corresponding second main grid 19, thereby forming a battery semi-finished product 10. In this structure, the battery semi-finished product 10 includes at least two battery cells 1. Therefore, after the first main grid 15 and the second main grid 19 are formed, the battery semi-finished product 10 needs to be cut and sliced to obtain at least two battery cells 1. Specifically, the battery semi-finished product 10 can be cut and sliced by means of laser cutting.

[0115] In the embodiment of the present application, in step B33, four first hollow portions 143 and four second hollow portions 181 are formed. In step B4, four first main grids 15 and four second main grids 19 are formed. Each first main grid 15 corresponds to a second main grid 19, and each first main grid 15 is arranged staggeredly with the corresponding second main grid 19, thereby forming a battery semi-finished product 10. In this structure, the battery semi-finished product 10 includes four battery cells 1. Therefore, after the first main grid 15 and the second main grid 19 are formed, the battery semi-finished product 10 needs to be cut and sliced to obtain four battery cells 1. Specifically, the battery semi-finished product 10 can be cut and sliced by means of laser cutting.

[0116] It can be understood that, according to the requirements of the actual situation, the number of the first hollow portions 143 and the second hollow portions 181 formed in step B33 can be appropriately adjusted, and the number of the first main grids 15 and the second main grids 19 formed in step B4 can be appropriately adjusted. For example, in step B33, only one first hollow portion 143 and one second hollow portion 181 can be formed, and in step B4, only one first main grid 15 and one second main grid 19 can be formed. In this case, there is no need to obtain the battery chip 1 by means of additional cutting and slicing; in step B33, six first hollow portions 143 and six second hollow portions 181 can also be formed, and in step B4, six first main grids 15 and six second main grids 19 can also be formed. In this case, six battery chips 1 are obtained by means of cutting and slicing.

[0117] Specifically, in step B5, first, a conductive adhesive 20 is coated on the part of the battery chip 1 corresponding to the overlapping area, then at least two battery chips 1 are stacked, and then at least two battery chips 1 are laminated and cured, so that the conductive adhesive 20 fills the first openings 151, the second openings 191, the first hollow portions 143 and the second hollow portions 181, thereby forming an overlapping shingle assembly.

[0118] The embodiment of the present application further provides a photovoltaic cell, including the above-mentioned overlapping shingle assembly.

[0119] The above has introduced in detail an overlapping shingle assembly, a manufacturing method of the overlapping shingle assembly, and a photovoltaic cell provided by the embodiment of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A shingled module, characterized in that, The invention comprises at least two battery cells, wherein two adjacent battery cells partially overlap to form an overlapping area, and the battery cell comprises: A substrate having a first surface, the first surface being a light-receiving surface; and a second surface, the first surface and the second surface being located on opposite sides of the substrate; A first tunneling layer, disposed on a portion of the first surface; A first doped polysilicon layer is disposed on a side of the first tunneling layer away from the substrate; and A first main gate is disposed on a side of the first doped polysilicon layer away from the first tunneling layer; Among them, in two adjacent battery cells, the first tunneling layer, the first doped polysilicon layer and the first main gate of the battery cell located at the bottom are arranged in the overlapping area; A second tunneling layer, disposed on the second surface; A second doped polysilicon layer is disposed on a side of the second tunneling layer away from the substrate; A second main gate is provided on a side of the second doped polysilicon layer away from the second tunneling layer; Conductive glue, in two adjacent battery cells, the second main grid of the battery cell located on the upper side is arranged in the overlapping area, and the first main grid of the battery cell located on the lower side overlaps and is electrically connected with the second main grid of the battery cell located on the upper side in the overlapping area through the conductive glue; A first passivation layer, covering the first surface and the first doped polysilicon layer, wherein the first passivation layer is provided with a first groove and a first through hole; The first main gate is covered in the first groove, and the first main gate is in contact with the first doped polysilicon layer through the first groove; The conductive adhesive covers the first through hole.

2. The shingled module according to claim 1, characterized in that, The width of the first main grid is greater than or equal to 0.2 mm.

3. The shingled module according to claim 1, characterized in that, The substrate is an N-type silicon substrate, the first doped polysilicon layer is a P-type doped polysilicon layer, and the second doped polysilicon layer is an N-type doped polysilicon layer.

4. The shingled module according to claim 1, characterized in that, The conductive paste contacts the first doped polysilicon layer through the first through hole.

5. The shingled module according to claim 4, characterized in that, The first passivation layer includes a lower passivation layer and an upper passivation layer, the lower passivation layer covers the first surface and the first doped polysilicon layer, and the upper passivation layer covers the lower passivation layer.

6. The shingled module according to claim 1, characterized in that, The battery cell also includes: A second passivation layer, covering the second surface and the second doped polysilicon layer, wherein the second passivation layer is provided with a second groove and a second through hole; The second main gate is covered in the second groove, and the second main gate is in contact with the second doped polysilicon layer through the second groove; The conductive adhesive covers the second through hole, and the conductive adhesive contacts the second doped polysilicon layer through the second through hole.

7. A method for manufacturing a shingled module, characterized in that, include: forming a first tunneling layer on a first surface of a substrate, and forming a second tunneling layer on a second surface of the substrate, wherein the first surface and the second surface are located on opposite sides of the substrate; forming a first doped polysilicon layer on the first tunneling layer, and forming a second doped polysilicon layer on the second tunneling layer; Performing patterning on the first tunneling layer and the first doped polysilicon layer to obtain the first tunneling layer and the first doped polysilicon layer sequentially disposed on a part of the first surface; A first passivation layer is formed on the first doped polysilicon layer; The first passivation layer is patterned to form a first hollowed portion provided in the first passivation layer; the first hollowed portion includes a first groove and a first through hole; A first main gate is formed on the first doped polysilicon layer, and a second main gate is formed on the second doped polysilicon layer to obtain a cell; the first main gate covers the first groove, and the first main gate contacts the first doped polysilicon layer through the first groove; A conductive adhesive covers the first through hole; At least two of the cells are stacked and laminated and cured so that two adjacent cells partially overlap to form an overlapping region; in two adjacent cells, the first tunneling layer and the first doped polysilicon layer of the cell located below are provided in the overlapping region, and the first main gate of the cell located below and the second main gate of the cell located above overlap and are electrically connected through the conductive adhesive in the overlapping region.

8. A photovoltaic cell, characterized in that, Comprising a shingled module according to any one of claims 1-6.

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