A double-gate heterostructure exciton transistor, a preparation method and use thereof

Abstract

The application provides a double-gate heterostructure exciton transistor, a preparation method and an application. The transistor comprises a SiO2 / Si substrate plated with a bottom gate electrode on a surface, a two-dimensional layered material heterojunction attached to the SiO2 / Si substrate, a dielectric layer film attached to a middle region of the two-dimensional layered material heterojunction, two side light-transmitting conductive layer films attached to the two-dimensional layered material heterojunction and located on two sides of the dielectric layer film, and a middle light-transmitting conductive layer film attached to the dielectric layer film. A gate electrode is attached to the middle light-transmitting conductive layer film, and a drain electrode and a source electrode are respectively attached to the two side light-transmitting conductive layer films. During operation, surface plasmon resonance effect is generated by the interaction between incident light and the bottom gate electrode on the SiO2 / Si substrate. The surface plasmon resonance effect can enhance the light absorption efficiency of the semiconductor material. An integrated system composed of a plurality of the exciton transistors also has the advantages of an optical data transmission system and an electronic data processing system.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic components, in particular to a double-gate heterostructure exciton transistor, a preparation method and an application. BACKGROUND

[0002] With the development of new infrastructure construction such as big data and artificial intelligence, higher requirements are put forward for the power efficiency and integration density of devices, and exciton devices begin to appear in people's field of vision. When the exciton device works, the light signal transmits through the source electrode and is incident on the channel material to excite the channel material to generate interlayer excitons. Under the action of the source-drain voltage, an electric field is generated in the channel to make the interlayer excitons realize the transmission of micron-level distance. The interlayer excitons are dissociated into electrons and holes at the drain and release energy in the form of light. By changing the gate voltage, the transmission of the interlayer excitons can be controlled, that is, the on-off of the exciton device can be controlled. However, due to problems such as common defects in the channel material and poor coupling between material layers, the effective absorption of the channel material to the light signal transmitted through the source electrode is reduced, and the interlayer exciton yield in the source-channel region is reduced. Because the generated interlayer excitons are reduced, the light signal generated by the dissociation of the interlayer excitons at the drain is attenuated, so the signal conversion efficiency of the transistor is seriously reduced. Therefore, it is particularly important to solve the technical problems of low absorption and conversion efficiency of the exciton device to the light signal at room temperature. SUMMARY

[0003] In view of the technical problems of low absorption and conversion efficiency of the existing exciton transistor to the incident light, the present application provides a preparation method of a double-gate heterostructure exciton transistor. The surface plasmon resonance effect generated by the interaction between the bottom gate electrode arranged in the groove on the SiO2 / Si substrate and the incident light limits the light field in a very small range near the bottom gate electrode, greatly enhances the absorption of the exciton transistor to the incident light, and thus more incident light is converted into excitons. At the same time, the problem of large energy loss in the signal transmission process of the exciton transistor is also solved.

[0004] The technical scheme adopted by the present application is as follows:

[0005] A double-gate heterostructure exciton transistor, characterized in that it comprises a SiO2 / Si substrate with a bottom gate electrode plated on the surface, a two-dimensional layered material heterojunction attached to the SiO2 / Si substrate, a dielectric layer film attached to the middle region of the two-dimensional layered material heterojunction, two side light-transmitting conductive layer films attached to the two-dimensional layered material heterojunction and located on both sides of the dielectric layer film, and a middle light-transmitting conductive layer film attached to the dielectric layer film. The middle light-transmitting conductive layer film and the two side light-transmitting conductive layer films are not in contact with each other. A gate electrode is attached to the middle light-transmitting conductive layer film, and a drain electrode and a source electrode are respectively attached to the two side light-transmitting conductive layer films.

[0006] Further, the two-dimensional layered material heterojunction is composed of two stacked monolayer chalcogenide films, the monolayer chalcogenide films being monolayer MoS2 films or monolayer WSe2 films; the dielectric layer film is a monolayer h-BN film; and the intermediate light-transmitting conductive layer film and the two side light-transmitting conductive layer films are both monolayer graphene films.

[0007] Further, a plurality of grooves are formed on the SiO2 / Si substrate, and the bottom gate electrode is attached to the grooves and fills the grooves completely.

[0008] Further, the thickness of the dielectric layer film is 0.4-2 nm, and the thickness of the light-transmitting conductive layer film is 0.4-4 nm.

[0009] Further, the grooves are arranged in parallel, the number of the grooves is 5-8, the depth of the grooves is 45-50 nm, the length of the grooves is 10-15 μm, and the distance between adjacent grooves is 500 nm.

[0010] The preparation method of the double-gate heterostructure exciton transistor is characterized in that it comprises the following steps:

[0011] Step 1: etching a plurality of grooves on the SiO2 / Si substrate;

[0012] Step 2: spin-coating photoresist on the SiO2 / Si substrate treated in step 1, using an electron beam to pattern the bottom gate electrode in the grooves, and using an electron beam evaporation process to evaporate a gold film in the grooves, the thickness of the evaporated gold film being consistent with the depth of the grooves, and then removing the photoresist and the gold film outside the exposed area to form a SiO2 / Si substrate with a bottom gate electrode on the surface;

[0013] Step 3: mechanically peeling off two monolayer chalcogenide films, a dielectric layer film and a light-transmitting conductive layer film by means of a two-dimensional material transfer platform, and transferring them to the SiO2 / Si substrate with the bottom gate electrode on the surface in sequence, wherein the length of the dielectric layer film is less than that of the two monolayer chalcogenide films and the light-transmitting conductive layer film, and the dielectric layer film is located in the middle region between the two monolayer chalcogenide films and the light-transmitting conductive layer film;

[0014] Step 4: spin-coating photoresist on the light-transmitting conductive layer film again, using an electron beam to pattern the source electrode, the gate electrode and the drain electrode, and using an electron beam evaporation process to evaporate a gold film on the light-transmitting conductive layer film, and then removing the photoresist and the gold film outside the exposed area;

[0015] Step 5: etching the light-transmitting conductive layer film into three parts of middle light-transmitting conductive layer film and two side light-transmitting conductive layer films which are not in contact with each other, so that the middle light-transmitting conductive layer film is attached to the dielectric layer film, and the two side light-transmitting conductive layer films are attached to the two-dimensional layered material heterojunction and are located on the two sides of the dielectric layer film, to obtain a double-gate heterostructure exciton transistor.

[0016] Further, the spin-coating photoresist process in step 2 is: dropping the photoresist onto the SiO2 dielectric layer, first spin-coating at a speed of 800 r / min for 20 s, and then spin-coating at a speed of 2000 r / min for 50 s; after the photoresist is uniform, electron beam exposure and development are performed, and the photoresist is developed for 50 s using a developer; and the spin-coating photoresist process in step 4 is: dropping the photoresist onto the light-transmitting conductive layer film, first spin-coating at a speed of 400 r / min for 20 s, and then spin-coating at a speed of 1000 r / min for 50 s; after the photoresist is uniform, electron beam exposure and development are performed.

[0017] Further, the electron beam lithography process in step 2 is: introducing nitrogen into the photoetching equipment, then vacuumizing, the vacuum degree is 5*10 -3 Pa, and then performing electron beam lithography pattern after loading an acceleration voltage of 30 kV.

[0018] Further, when the gold film outside the exposed area is removed in step 2, the SiO2 / Si substrate is soaked in acetone until the gold film outside the exposed area is completely separated from the SiO2 / Si substrate together with the photoresist.

[0019] The integrated system composed of a plurality of the double-gate heterostructure exciton transistors is used for the purpose of integrating an optical data transmission and an electronic data processing system.

[0020] In the present application, the interaction between the incident light and the bottom gate electrode on the SiO2 / Si substrate produces a surface plasmon resonance effect, which can enhance the light absorption efficiency of the channel material and convert more incident light into excitons. The combination of the bottom gate electrode and the exciton device can effectively solve the problem of low light absorption and conversion rate of the channel material. Moreover, the light-transmitting conductive layer film as a light-transmitting gate electrode can also form a good coupling between the layers.

[0021] The electrons are located in the conduction band, and the holes are located in the valence band. By using the characteristics that the electrons and holes in the interlayer exciton are in different layers, the upper and lower gate voltages and the source and drain voltages can simultaneously complete the electrically controlled transport and modulation of the interlayer exciton of the hetero-bilayer film in the same physical space. Compared with the traditional field effect transistor, the double-gate heterostructure bilayer transistor is not only smaller and faster, but also has the advantages of optical data transmission and electronic data processing system, so that the integrated system is more efficient and has a very broad prospect.

[0022] The interlayer exciton in the double-gate heterostructure exciton transistor has long life, micron-level diffusion length, and unique features such as polarization, wavelength, intensity, etc. of the emission which can be conveniently controlled by electricity, thereby improving the power efficiency of the transistor and overcoming the problem that the exciton diffusion length of a single two-dimensional material is insufficient to limit its practical application at room temperature.

[0023] The application uses a two-dimensional material heterojunction as a channel material, under the action of incident light, electrons undergo transition and leave holes, forming the characteristics that electrons and holes are in different layers, and the space separation of interlayer exciton charges prolongs the life of the exciton by two orders of magnitude. At the same time, the two-dimensional material transition metal dichalcogenides such as molybdenum disulfide and tungsten disulfide have important potential application value in optoelectronics and valley electronics due to their direct band gap and single-molecular-layer-limiting semiconductor properties. The two-dimensional characteristics of single-layer transition metal dichalcogenides enhance the Coulomb interaction, thereby generating bound electron-hole pairs, making it possible to develop exciton devices at room temperature. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a schematic diagram of a SiO2 / Si substrate structure with a bottom gate electrode plated on the surface.

[0025] Figure 2 is a perspective view of the double-gate heterostructure exciton transistor prepared in the embodiment of the application.

[0026] Figure 3 is a front view of the double-gate heterostructure exciton transistor prepared in the embodiment of the application.

[0027] In the figure: 1-silicon substrate; 2-silicon dioxide layer; 3-bottom gate electrode; 4-two-dimensional layered material heterojunction; 5-dielectric layer film; 6-intermediate light-transmitting conductive layer film; 7-left light-transmitting conductive layer film; 8-source electrode; 9-gate electrode; 10-drain electrode; 11-right light-transmitting conductive layer film. DETAILED DESCRIPTION

[0028] The application will be further described below in conjunction with the drawings and specific embodiments, but the scope of protection of the application is not limited thereto.

[0029] The dual-gate heterostructure exciton transistor of the present invention includes a SiO2 / Si substrate with a bottom gate electrode 3 deposited on its surface, a two-dimensional layered material heterojunction 4 attached to the SiO2 / Si substrate, a dielectric thin film 5 centrally attached to the two-dimensional layered material heterojunction 4, a left transparent conductive layer thin film 7 and a right transparent conductive layer thin film 11 attached to the two-dimensional layered material heterojunction 4 and located on both sides of the dielectric thin film 5, and a middle transparent conductive layer thin film 6 attached to the dielectric thin film 5. The middle transparent conductive layer thin film 6, the left transparent conductive layer thin film 7 and the right transparent conductive layer thin film 11 are not in contact with each other. A gate electrode 9 is attached to the middle transparent conductive layer thin film 6, a source electrode 8 is attached to the left transparent conductive layer thin film 7, and a drain electrode 10 is attached to the right transparent conductive layer thin film 11.

[0030] The two-dimensional layered heterojunction 4 is composed of two stacked monolayers of chalcogenide compounds, such as a heterojunction composed of molybdenum disulfide and tungsten diselenide. The dielectric layer film 5 is a monolayer h-BN film; the middle transparent conductive layer film 6, the left transparent conductive layer film 7, and the right transparent conductive layer film 11 are all monolayer graphene films.

[0031] The following example uses a heterojunction composed of molybdenum disulfide and tungsten diselenide thin films to illustrate the fabrication method of the dual-gate heterostructure exciton transistor.

[0032] First, the silicon substrate 1 was sequentially placed in anhydrous ethanol and deionized water for ultrasonic cleaning using low-frequency ultrasonic vibration. The ultrasonic frequency was 20kHz, and the power density was 1W / cm². 2 The cleaning time was 2 minutes, and nitrogen gas was used to dry the substrate after cleaning. A 300 nm thick silicon dioxide layer 2 was deposited on the silicon substrate 1 by chemical vapor deposition.

[0033] The Si / SiO2 substrate was etched using focused ion beam etching (FIE). Five trenches were formed, each 500 nm wide, 10 μm long, and 50 nm deep, with a spacing of 500 nm between adjacent trenches. The etched SiO2 / Si substrate was then rinsed with deionized water and dried under nitrogen. The etched Si / SiO2 substrate was placed on a spin coater, and photoresist was dropped onto the silicon dioxide layer 2. Spin-coating was performed at 800 rpm for 20 s, followed by 2000 rpm for 50 s. After spin-coating, the bottom gate electrode 3 pattern was fabricated using EBL (Extended Laser Patterning). The photolithography process involved introducing nitrogen gas into the photolithography equipment, followed by evacuation to a vacuum level of 5 × 10⁻⁶. -3After the electron beam lithography pattern is drawn at 30 kV, the SiO2 / Si substrate is placed in the developing solution for 50 s, and then shaken gently to disperse the photoresist. A 50-nm-thick gold film is deposited on the exposed area by electron beam evaporation technology. The coated substrate is immersed in acetone for 4 h, so that the metal film in the unexposed area is completely separated from the substrate. The substrate is taken out and washed with deionized water, and then dried with nitrogen for standby.

[0034] High-quality monolayer MoS2 film, monolayer WSe2 film, monolayer h-BN film and monolayer graphene film are prepared by mechanical exfoliation, and are characterized by Raman spectroscopy. The thickness of the monolayer MoS2 film and the monolayer WSe2 film is 0.7 nm, and the thickness of the monolayer h-BN film and the monolayer graphene film is 0.4 nm. The characterized monolayer MoS2 film, monolayer WSe2 film, monolayer h-BN film and monolayer graphene film are transferred onto the SiO2 / Si substrate coated with the bottom gate electrode 3 by dry transfer method. During the transfer process, the materials should be accurately attached. The length of the monolayer h-BN film is less than that of the other three films, and the monolayer h-BN film is placed between the monolayer MoS2 film and the monolayer WSe2 film to form a two-dimensional layered material heterojunction 4 and the monolayer graphene film. After the transfer is completed, the substrate is placed on a uniform glue disc, and the photoresist is dropped onto the uppermost monolayer graphene film. First, spin at 400 r / min for 20 s, and then spin at 1000 r / min for 50 s. After the glue is uniform, the top gate electrode pattern is exposed and drawn by EBL technology. The lithography process is as follows: nitrogen is introduced into the lithography equipment, and then vacuum is applied. The vacuum degree is 5x10 -3 After the electron beam lithography pattern is drawn at 30 kV, the SiO2 / Si substrate is placed in the developing solution for 50 s, and then shaken gently to disperse the photoresist. A 50-nm-thick gold film is deposited on the exposed area by electron beam evaporation technology. The coated substrate is immersed in acetone for 4 h, so that the metal film in the unexposed area is completely separated from the substrate. The substrate is taken out and washed with deionized water, and then dried with nitrogen for standby.

[0035] The above embodiments are preferred embodiments of the present application, but the present application is not limited to the above embodiments. Any obvious improvements, replacements or modifications made by those skilled in the art without departing from the essential content of the present application shall fall within the protection scope of the present application.

Claims

1. A double-gate heterostructure excitonic transistor, characterized in that, The application relates to a two-dimensional layered material heterojunction device, which comprises a SiO2 / Si substrate plated with a bottom gate electrode (3), a two-dimensional layered material heterojunction (4) attached to the SiO2 / Si substrate, a dielectric layer film (5) attached to the middle region of the two-dimensional layered material heterojunction (4), two side light-transmitting conductive layer films attached to the two-dimensional layered material heterojunction (4) and located on the two sides of the dielectric layer film (5), and a middle light-transmitting conductive layer film (6) attached to the dielectric layer film (5), wherein the middle light-transmitting conductive layer film (6) is not in contact with the two side light-transmitting conductive layer films, the middle light-transmitting conductive layer film (6) is attached with a gate electrode (9), and the two side light-transmitting conductive layer films are respectively attached with a drain electrode (10) and a source electrode (8); a plurality of grooves are formed in the SiO2 / Si substrate, the bottom gate electrode (3) is attached in the grooves and fills the grooves completely; the grooves are arranged in parallel, the number of the grooves is 5-8, the groove depth is 45-50 nm, the groove length is 10-15 mu m, and the distance between adjacent grooves is 500 nm; the thickness of the dielectric layer film (5) is 0.4-2 nm; and the thickness of the middle light-transmitting conductive layer film (6) and the two side light-transmitting conductive layer films is 0.4-4 nm.

2. The double-gate heterostructure excitonic transistor of claim 1, wherein: The two-dimensional layered material heterojunction (4) is composed of two stacked monolayer chalcogenide compound films, the monolayer chalcogenide compound films are monolayer MoS2 films or monolayer WSe2 films, the dielectric layer film (5) is a monolayer h-BN film, and the middle light-transmitting conductive layer film (6) and the two side light-transmitting conductive layer films are both monolayer graphene films.

3. The method of claim 1 or 2, wherein the method further comprises: The application further discloses a two-dimensional layered material heterojunction device manufacturing method, which comprises the following steps: Step 1: etching a plurality of grooves on a SiO2 / Si substrate; Step 2: spin-coating photoresist on the SiO2 / Si substrate treated in step 1, using an electron beam to pattern a bottom gate electrode (3) in the grooves, evaporating a gold film in the grooves through an electron beam evaporation process, the thickness of the evaporated gold film being consistent with the groove depth, then removing the photoresist and the gold film outside the exposed region to form a SiO2 / Si substrate plated with a bottom gate electrode (3); Step 3: mechanically peeling off two monolayer chalcogenide compound films, a dielectric layer film (5) and a light-transmitting conductive layer film from a two-dimensional material transfer platform and transferring them onto the SiO2 / Si substrate plated with the bottom gate electrode (3) in sequence, wherein the length of the dielectric layer film (5) is smaller than that of the two monolayer chalcogenide compound films and the light-transmitting conductive layer film, and the dielectric layer film (5) is located in the middle region between the two monolayer chalcogenide compound films and the light-transmitting conductive layer film; Step 4: spin-coating photoresist on the light-transmitting conductive layer film again, using an electron beam to pattern a source electrode (8), a gate electrode (9) and a drain electrode (10), evaporating a gold film on the light-transmitting conductive layer film through an electron beam evaporation process, and then removing the photoresist and the gold film outside the exposed region. Step 5: etching the transparent conductive layer film into three non-contact parts of the middle transparent conductive layer film (6) and the two side transparent conductive layer films, so that the middle transparent conductive layer film (6) is attached to the dielectric layer film (5), and the two side transparent conductive layer films are attached to the two-dimensional layered material heterojunction (4) and located on the two sides of the dielectric layer film (5), obtaining a double-gate heterostructure exciton transistor.

4. The method of claim 3, wherein the method further comprises: The spin-coating photoresist process in step 2 is: dropping the photoresist onto the SiO2 dielectric layer, first spin-coating at a speed of 800 r / min for 20 s, and then spin-coating at a speed of 2000 r / min for 50 s; after the photoresist is uniform, electron beam exposure and development are carried out, and the photoresist is developed by using a developer for 50 s; the spin-coating photoresist process in step 4 is: dropping the photoresist onto the transparent conductive layer film, first spin-coating at a speed of 400 r / min for 20 s, and then spin-coating at a speed of 1000 r / min for 50 s; after the photoresist is uniform, electron beam exposure and development are carried out.

5. The method of claim 3, wherein the method further comprises: The electron beam lithography process in step 2 is: nitrogen is introduced into the lithography equipment, then vacuum is pumped, the vacuum degree is 5x10 -3 Pa, electron beam lithography pattern is performed after the accelerating voltage is loaded to 30 kV.

6. The method of claim 3, wherein the method further comprises: In step 2, when the photoresist and the gold film outside the exposed area are removed, the SiO2 / Si substrate is immersed in acetone until the gold film outside the exposed area is completely separated from the SiO2 / Si substrate with the photoresist.

7. Use of an integrated system composed of several double-gate heterostructure exciton transistors according to any one of claims 1-2 for an integrated optical data transmission and electronic data processing system.

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