monostable circuit
By introducing a combination of a shielding time window circuit and an RC delay circuit into the monostable circuit, the problem of abnormal pulse mis-triggering in low-speed logic chips is solved, and an anti-interference monostable circuit design is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SG MICRO CORP
- Filing Date
- 2022-09-01
- Publication Date
- 2026-05-12
AI Technical Summary
Existing monostable circuits are easily triggered by abnormal pulses in input signals in low-speed logic chips, affecting normal operation.
A combination of a monostable main circuit and a shielded time window circuit is adopted. Input signals and output signals are received and fed back through NOR gates, and are processed by RC delay circuits and logic gates. The shielded time window circuit is added to resist abnormal pulse interference.
It effectively eliminates the false triggering of monostable circuits by abnormal pulses, ensuring that the circuit remains undisturbed within the preset time interval and continues to operate normally.
Smart Images
Figure CN115498981B_ABST
Abstract
Description
Technical Field
[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to monostable circuits. Background Technology
[0002] One-shot circuits are widely used for pulse shaping, delay (generating an output pulse that lags behind the trigger pulse), and timing (generating pulse signals with a fixed duration). The delay effect is achieved by the charging and discharging of an RC circuit, and the duration depends on the circuit parameters.
[0003] In some low-speed logic chips, it is often desirable to allow a relatively long interval T between the triggering of a One-Shot (the output signal of a One-Shot circuit) and the subsequent One-Shot. For traditional One-Shot circuits, abnormal pulses may appear in the input signal of the One-Shot circuit during this interval T, and these abnormal pulses may falsely trigger the One-Shot signal, affecting practical applications. Summary of the Invention
[0004] The embodiments described herein provide a monostable circuit to address the problem that existing monostable circuits may be falsely triggered by abnormal pulses in the input signal.
[0005] The first aspect of this disclosure provides a monostable circuit, comprising: a monostable main circuit and a shielded time window circuit; wherein, the monostable main circuit is configured to receive the input signal of the monostable circuit, feedback of the output signal of the monostable circuit, and a time window signal output by the shielded time window circuit through an NOR gate, and then obtain the output signal after passing through a first RC delay circuit and logic gates, wherein the time window signal is a signal that resists interference from abnormal pulses of the input signal on the output signal; the shielded time window circuit is configured to receive feedback of the output signal, and then obtain the time window signal after passing through a second RC delay circuit and logic gates.
[0006] Optionally, the monostable main circuit includes: the NOR gate, the first RC delay circuit, the first NOT gate, the second NOT gate, and the NAND gate; wherein, the input terminal of the NOR gate receives the input signal, the feedback of the output signal, and the time window signal, and the output terminal of the NOR gate is connected to the first RC delay circuit; the first RC delay circuit is configured to delay the signal by charging and discharging a capacitor, and the output terminal of the first RC delay circuit is connected to the input terminal of the first NOT gate; the output terminal of the first NOT gate is connected to one input terminal of the NAND gate, the other input terminal of the NAND gate is connected to the input signal, and the output terminal of the NAND gate is connected to the input terminal of the second NOT gate; the output terminal of the second NOT gate outputs the output signal.
[0007] Optionally, the shielding time window circuit includes: a second RC delay circuit and a third NOT gate; wherein, the second RC delay circuit is configured to delay the signal by charging and discharging a capacitor, the input terminal of the second RC delay circuit receives feedback from the output signal, the output terminal of the second RC delay circuit is connected to the input terminal of the third NOT gate, and the output terminal of the third NOT gate outputs the time window signal.
[0008] Optionally, the first RC delay circuit includes: a first transistor, a second transistor, a first resistor, and a first capacitor; wherein the gates of the first transistor and the second transistor are both connected to the output terminal of the NOR gate, the source of the first transistor is connected to the power supply terminal, the source of the second transistor is connected to the ground terminal, the drain of the first transistor is connected to one end of the first resistor, and the drain of the second transistor is connected to the other end of the first resistor; the first transistor is a P-type transistor, and the second transistor is an N-type transistor; the first capacitor is connected in parallel with the second transistor, one end of the first capacitor is connected to the drain of the second transistor, and the other end of the first capacitor is connected to the source of the second transistor; the intermediate node between the first resistor and the second transistor is connected to the input terminal of the first NOT gate.
[0009] Optionally, the second RC delay circuit includes: a third transistor, a fourth transistor, a second resistor, and a second capacitor; wherein the gates of the third transistor and the fourth transistor both receive feedback from the output signal, the source of the third transistor is connected to the power supply terminal, the source of the fourth transistor is connected to the ground terminal, the drain of the third transistor is connected to one end of the second resistor, and the drain of the fourth transistor is connected to the other end of the second resistor; the third transistor is a P-type transistor, and the fourth transistor is an N-type transistor; the second capacitor is connected in parallel with the fourth transistor, one end of the second capacitor is connected to the drain of the fourth transistor, and the other end of the second capacitor is connected to the source of the fourth transistor; the intermediate node between the second resistor and the fourth transistor is connected to the input terminal of the third NOT gate.
[0010] Optionally, the discharge time constant of the second RC delay circuit is less than the charging time of the first RC delay circuit.
[0011] Optionally, the initial low-level duration of the input signal is longer than a first preset duration, where the first preset duration is the duration during which the third transistor and the second resistor pull the input of the third NOT gate to a high level.
[0012] Optionally, the sum of the discharge duration of the second RC delay circuit and the charging duration of the second RC delay circuit is less than or equal to a second preset duration, where the second preset duration is a preset interval for triggering the monostable circuit.
[0013] Optionally, the monostable circuit is a monostable circuit in a low-speed chip.
[0014] A second aspect of this disclosure provides a monostable circuit comprising: a NOR gate, a first to a fourth transistor, a first resistor, a second resistor, a first capacitor, a second capacitor, a first NOT gate, a second NOT gate, a third NOT gate, and a NAND gate; wherein the input terminal of the NOR gate receives the input signal of the monostable circuit, feedback of the output signal of the monostable circuit, and a time window signal; the output terminal of the NOR gate is connected to the gate of the first transistor and the gate of the second transistor; the source of the first transistor is connected to a power supply terminal, the source of the second transistor is connected to a ground terminal, the drain of the first transistor is connected to one end of the first resistor, and the drain of the second transistor is connected to the other end of the first resistor; the first transistor is a P-type transistor, and the second transistor is an N-type transistor; the first capacitor and the second transistor are connected in parallel, one end of the first capacitor is connected to the drain of the second transistor, and the other end of the first capacitor is connected to the source of the second transistor; an intermediate node is provided between the first resistor and the second transistor. The input terminal of the first NOT gate is connected, the output terminal of the first NOT gate is connected to one input terminal of the NAND gate, the other input terminal of the NAND gate is connected to the input signal, the output terminal of the NAND gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate outputs the output signal; the gates of the third transistor and the fourth transistor receive feedback from the output signal, the source of the third transistor is connected to the power supply terminal, the source of the fourth transistor is connected to the ground terminal, the drain of the third transistor is connected to one end of the second resistor, and the drain of the fourth transistor is connected to the other end of the second resistor; the third transistor is a P-type transistor, and the fourth transistor is an N-type transistor; the second capacitor is connected in parallel with the fourth transistor, one end of the second capacitor is connected to the drain of the fourth transistor, and the other end of the second capacitor is connected to the source of the fourth transistor; the intermediate node between the second resistor and the fourth transistor is connected to the input terminal of the third NOT gate, and the output terminal of the third NOT gate outputs the time window signal.
[0015] The monostable circuit of this disclosure includes: a monostable main circuit and a shielded time window circuit. The monostable main circuit is configured to receive the input signal of the monostable circuit, feedback of the output signal of the monostable circuit, and a time window signal output by the shielded time window circuit via a NOR gate. The output signal is then obtained after passing through a first RC delay circuit and logic gates. The time window signal is a signal that resists interference from abnormal pulses of the input signal on the output signal. The shielded time window circuit is configured to receive feedback from the output signal, and then obtain the time window signal after passing through a second RC delay circuit and logic gates. Compared with existing monostable circuits, the monostable circuit of this disclosure replaces the NOT gate that receives the input signal with a NOR gate that can receive three signals, and adds a shielded time window circuit. This shielded time window circuit can obtain a time window signal that resists interference from abnormal pulses of the input signal on the output signal based on the feedback of the output signal, effectively eliminating the false triggering of the One-Shot signal by abnormal pulses. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:
[0017] Figure 1 This is an exemplary circuit diagram of an existing monostable circuit;
[0018] Figure 2 yes Figure 1 Waveform diagram of the signal corresponding to the circuit;
[0019] Figure 3 This is a schematic diagram of the structure of a monostable circuit according to an embodiment of the present disclosure;
[0020] Figure 4 This is a schematic diagram of the structure of a monostable main circuit according to an embodiment of this disclosure;
[0021] Figure 5 This is a schematic diagram of the shielding time window circuit according to an embodiment of the present disclosure;
[0022] Figure 6 This is an exemplary circuit diagram of a monostable circuit according to an embodiment of the present disclosure;
[0023] Figure 7 yes Figure 6 Waveform diagram of the signal corresponding to the monostable circuit.
[0024] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation
[0025] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.
[0026] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.
[0027] In all embodiments of this disclosure, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).
[0028] To address the problem of existing monostable circuits being falsely triggered by abnormal pulses in the input signal, this disclosure first analyzes the operating process of existing monostable circuits, such as... Figure 1 The diagram shown is an exemplary circuit diagram of a conventional monostable circuit 100. Figure 2 for Figure 1 The waveform diagram of the signal corresponding to the circuit. The following is in conjunction with... Figure 1 and Figure 2Analyzing the existing monostable circuit 100: When In is logic "0", one input of the NAND gate is "0", therefore the NAND output is logic "1", and the inverter 103 output signal One-shot is logic "0". When In is logic "0", the inverter 101 output is logic "1", Mp is cut off, and Mn is turned on, pulling the input of inverter 102 low to logic "0", therefore 102 output is logic "1". At time t1, In goes high. Due to the presence of R and C, the input of 102 cannot change immediately, and the output is still logic "1", therefore One-Shot becomes logic "1". After In goes high, the output of 101 is logic "0", Mp is turned on, Mn is cut off, Mp and R charge the input of inverter 102. Assuming the impedance of Mp is negligible, the charging time constant is τ = R * C. Assuming that the switching level of all inverters is half of the power supply voltage, after 0.7 time constants, i.e. at time t2, the output of inverter 102 switches to logic "0", and the One-Shot becomes logic "0".
[0029] In some low-speed logic chips, it is often desirable to allow a relatively long interval T between one-shot triggers before allowing the next one-shot to be triggered. For Figure 1 In the monostable circuit 100, within this time interval T, for example... Figure 2 When an abnormal downward pulse appears in In at time t3, if the pulse amplitude is low enough to make the output of inverter 101 become logic "1", then Mn conducts to discharge the input of inverter 102, and the output of 102 will become logic "1". When the abnormal pulse returns to a high level, it will make One-Shot become logic "1" again. Therefore, the abnormal pulse falsely triggers the One-Shot signal.
[0030] In response to the above analysis of the existing monostable circuit 100 and the problem of false triggering by abnormal pulses, this disclosure proposes a new monostable circuit 200. The monostable circuit of this disclosure is an anti-interference monostable circuit. It mainly addresses the problem of false triggering by abnormal pulses in low-speed chip applications, providing an optimization solution. The monostable circuit 200 of this disclosure will be described in detail below.
[0031] like Figure 3The diagram shows a structural schematic of a monostable circuit 200 according to an embodiment of the present disclosure. The monostable circuit 200 includes: a monostable main circuit 210 and a shielded time window circuit 220. The monostable main circuit 210 is connected to the shielded time window circuit 220 and is configured to receive the input signal In of the monostable circuit, the feedback of the output signal One-shot of the monostable circuit, and the time window signal Window output by the shielded time window circuit 220 through a NOR gate. After passing through a first RC delay circuit and logic gates, the output signal One-shot is obtained. The time window signal Window is a signal that resists the interference of abnormal pulses of the input signal In on the output signal One-shot. The shielded time window circuit 220 is configured to receive the feedback of the output signal One-shot and then pass through a second RC delay circuit and logic gates to obtain the time window signal Window. Compared with the existing monostable circuit 100, the monostable circuit 200 of this embodiment replaces the NOT gate 101 that receives the input signal In with a NOR gate that can receive three signals, and adds a shielding time window circuit 220. The shielding time window circuit 220 can obtain a time window signal that can resist the interference of abnormal pulses of the input signal In on the output signal One-shot according to the output signal One-shot, effectively eliminating the false triggering of the One-shot signal by abnormal pulses.
[0032] Furthermore, such as Figure 4 As shown, the monostable main circuit 210 includes: a NOR gate NOR1, a first RC delay circuit 211, a first NOT gate I1, a second NOT gate I2, and a NAND gate NAND1; wherein, the input terminal of the NOR gate NOR1 receives the input signal In, the feedback of the output signal One-shot, and the time window signal Window, and the output terminal of the NOR gate NOR1 is connected to the first RC delay circuit 211; the first RC delay circuit 211 is configured to delay the signal by charging and discharging the capacitor, and the output terminal of the first RC delay circuit 211 is connected to the input terminal of the first NOT gate I1; the output terminal of the first NOT gate I1 is connected to one input terminal of the NAND gate NAND1, the other input terminal of the NAND gate NAND1 is connected to the input signal In, and the output terminal of the NAND gate NAND1 is connected to the input terminal of the second NOT gate I2; the output terminal of the second NOT gate I2 outputs the output signal One-shot.
[0033] Furthermore, such as Figure 5As shown, the shielding time window circuit 220 includes: a second RC delay circuit 221 and a third NOT gate I3; wherein, the second RC delay circuit 221 is configured to delay the signal by charging and discharging the capacitor, the input terminal of the second RC delay circuit 221 receives feedback of the output signal One-shot, the output terminal of the second RC delay circuit 221 is connected to the input terminal of the third NOT gate I3, and the output terminal of the third NOT gate I3 outputs the time window signal Window.
[0034] Furthermore, such as Figure 6 As shown, the first RC delay circuit 211 includes: a first transistor Mp1, a second transistor Mn1, a first resistor R1, and a first capacitor C1; the gates of both the first transistor Mp1 and the second transistor Mn1 are connected to the output terminal of the NOR gate NOR1, the source of the first transistor Mp1 is connected to the power supply terminal, the source of the second transistor Mn1 is connected to the ground terminal, the drain of the first transistor Mp1 is connected to one end of the first resistor R1, and the drain of the second transistor Mn1 is connected to the other end of the first resistor R1. The first transistor Mp1 is a P-type transistor, and the second transistor Mn1 is an N-type transistor; the first capacitor C1 is connected in parallel with the second transistor Mn1, one end of the first capacitor C1 is connected to the drain of the second transistor Mn1, and the other end of the first capacitor C1 is connected to the source of the second transistor Mn1; the intermediate node between the first resistor R1 and the second transistor Mn1 is connected to the input terminal of the first NOT gate I1. The second RC delay circuit 221 includes: a third transistor Mp2, a fourth transistor Mn2, a second resistor R2, and a second capacitor C2; the gates of both the third transistor Mp2 and the fourth transistor Mn2 receive feedback from the output signal One-shot; the source of the third transistor Mp2 is connected to the power supply terminal, the source of the fourth transistor Mn2 is connected to the ground terminal, the drain of the third transistor Mp2 is connected to one end of the second resistor R2, and the drain of the fourth transistor Mn2 is connected to the other end of the second resistor R2; the third transistor Mp2 is a P-type transistor, and the fourth transistor Mn2 is an N-type transistor; the second capacitor C2 is connected in parallel with the fourth transistor Mn2, one end of the second capacitor C2 is connected to the drain of the fourth transistor Mn2, and the other end of the second capacitor C2 is connected to the source of the fourth transistor Mn2; the intermediate node between the second resistor R2 and the fourth transistor Mn2 is connected to the input terminal of the third NOT gate I3.
[0035] It should also be noted that the discharge time constant of the second RC delay circuit 221 is less than the charging time of the first RC delay circuit 211. This allows the Window signal to quickly become logic "1". Specifically, this can be achieved by making the aspect ratio of Mn2 larger to accelerate the discharge speed. Furthermore, the low-level duration of the initial input signal In is greater than the first preset duration, which is the duration for the third transistor Mp2 and the second resistor R2 to pull the input of the third NOT gate I3 to a high level. This is to ensure that, initially, One-Shot and Window do not affect the state of NOR1. Additionally, the sum of the discharge duration and charging duration of the second RC delay circuit 221 is less than or equal to the second preset duration, which is the preset interval duration for the monostable circuit triggering (corresponding to the aforementioned...). Figure 1 The time interval T in the embodiment.
[0036] In combination with the above Figure 6 The monostable circuit 200 in the middle, and Figure 7 The waveform diagrams of the signals corresponding to the monostable circuit 200 in this embodiment (from top to bottom, the waveform diagrams corresponding to the input signal In, the output signal One-shot, and the time window signal Window) provide a detailed explanation of the principle of the monostable circuit 200 in this disclosure. It is assumed that the initial input signal In has a sufficiently long time (greater than a first preset time) to be logic "0", then One-Shot is logic "0". Because the time is long enough, M... p2 R2 pulls the input of inverter I3 high to logic "1", and Window is logic "0". Therefore, One-Shot and Window do not affect the state of NOR1. NOR1 functions as an inverter. At this time, the monostable main circuit 210 is the same as the traditional monostable circuit 100, so the operation is the same. Figure 7 As shown, at time t1, In becomes logic "1". Assuming the impedance of Mp1 is negligible, the charging time constant (the charging time constant of the first RC delay circuit 211) is τ1 = R1 * C1. Assuming the switching level of all inverters is half the power supply voltage, the monostable circuit generates a one-shot pulse signal with a width of 0.7 * τ1 = 0.7 * R1 * C1. When the one-shot becomes logic "1", M... p2 As of now, M n2 The circuit is turned on, discharging C2. M... n2 The aspect ratio is relatively large, resulting in a fast discharge speed. The discharge time constant (the discharge time constant of the second RC delay circuit 221) can be much smaller than 0.7*τ1, allowing the Window signal to quickly become logic "1". When the One-shot signal becomes logic "0" again, M... n2 As of now, M p2Conduction, via M p2 R2 charges the input node of inverter I3. The charging time constant (the charging time constant of the second RC delay circuit 221) τ2 = R2 * C2. Before the output of I3 flips, the Window signal is always logic "1". When the One-shot signal or the Window signal is logic "1", the NOR1 output is always logic "0", and abnormal pulses on the input signal In will not affect the output of NOR1, so the One-shot signal will not be falsely triggered. After 0.7 * τ2 = 0.7 * R2 * C2, both the One-shot signal and the Window signal are logic "0", and only then can the One-shot circuit receive the trigger signal from the input In. From the above analysis and Figure 7 The waveform diagram shows that the One-shot signal will not be falsely triggered when either the One-shot signal or the Window signal is logic "1". From... Figure 7 As can be seen, the period when the One-shot signal or Window signal is logic "1" is between t1 and t4. This period is equal to the "discharge duration of the second RC delay circuit 221 + charging duration of the second RC delay circuit 221". Therefore, if this period is equal to the preset interval for triggering the monostable circuit, it can be ensured that there will be no false triggering within the preset interval for triggering the monostable circuit. The discharge duration and charging duration of the second RC delay circuit 221 can be easily adjusted by adjusting the parameters of the circuit elements in the second RC circuit. In addition, if the time of occurrence of the abnormal pulse can be predicted in advance, the right boundary of the period "discharge duration of the second RC delay circuit 221 + charging duration of the second RC delay circuit 221" can be adjusted to the time when the abnormal pulse ends (i.e., the discharge duration of the second RC delay circuit 221 + charging duration of the second RC delay circuit 221 is less than the preset interval for triggering the monostable circuit).
[0037] In summary, the monostable circuit 200 of this embodiment, by adding feedback for the output signal One-shot and a shielding time window circuit 220 to a conventional monostable circuit, can prevent false triggering caused by abnormal pulses of the input signal In. Within a certain time window, the One-shot circuit is in an anti-interference state, unaffected by abnormal pulses of the input signal In. Furthermore, during normal operation, the width of the shielding time window does not affect the pulse width of the One-shot signal.
[0038] The descriptions of the same or corresponding module units in the various embodiments of this disclosure can be referenced in turn.
[0039] In the above description, well-known structural elements and steps have not been described in detail. However, those skilled in the art should understand that the corresponding structural elements and steps can be implemented through various technical means. Furthermore, in order to form the same structural elements, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0040] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.
[0041] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.
[0042] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.
[0043] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.
Claims
1. A monostable circuit, characterized in that, The monostable circuit includes: a monostable main circuit and a shielding time window circuit; The monostable main circuit is configured to receive the input signal of the monostable circuit, the feedback of the output signal of the monostable circuit, and the time window signal output by the shielding time window circuit through an NOR gate, and then obtain the output signal after passing through a first RC delay circuit and logic gates. The time window signal is a signal that resists the interference of abnormal pulses of the input signal on the output signal. The shielding time window circuit is configured to receive feedback from the output signal, and then obtain the time window signal after passing through the second RC delay circuit and logic gates.
2. The monostable circuit according to claim 1, characterized in that, The monostable main circuit includes: the NOR gate, the first RC delay circuit, the first NOT gate, the second NOT gate, and the NAND gate; The input terminal of the NOR gate receives the input signal, the feedback of the output signal, and the time window signal, and the output terminal of the NOR gate is connected to the first RC delay circuit. The first RC delay circuit is configured to delay the signal by charging and discharging the capacitor, and the output terminal of the first RC delay circuit is connected to the input terminal of the first NOT gate. The output of the first NOT gate is connected to one input of the NAND gate, the other input of the NAND gate is connected to the input signal, and the output of the NAND gate is connected to the input of the second NOT gate. The output signal is output from the output terminal of the second NOT gate.
3. The monostable circuit according to claim 2, characterized in that, The shielding time window circuit includes: a second RC delay circuit and a third NOT gate; The second RC delay circuit is configured to delay the signal by charging and discharging the capacitor. The input terminal of the second RC delay circuit receives feedback from the output signal, and the output terminal of the second RC delay circuit is connected to the input terminal of the third NOT gate. The output terminal of the third NOT gate outputs the time window signal.
4. The monostable circuit according to claim 3, characterized in that, The first RC delay circuit includes: a first transistor, a second transistor, a first resistor, and a first capacitor; In this configuration, the gates of both the first transistor and the second transistor are connected to the output of the NOR gate, the source of the first transistor is connected to the power supply terminal, the source of the second transistor is connected to the ground terminal, the drain of the first transistor is connected to one end of the first resistor, and the drain of the second transistor is connected to the other end of the first resistor. The first transistor is a P-type transistor, and the second transistor is an N-type transistor. The first capacitor is connected in parallel with the second transistor, one end of the first capacitor is connected to the drain of the second transistor, and the other end of the first capacitor is connected to the source of the second transistor; The intermediate node between the first resistor and the second transistor is connected to the input terminal of the first NOT gate.
5. The monostable circuit according to claim 4, characterized in that, The second RC delay circuit includes: a third transistor, a fourth transistor, a second resistor, and a second capacitor; In this embodiment, the gates of the third transistor and the fourth transistor both receive feedback from the output signal. The source of the third transistor is connected to the power supply terminal, the source of the fourth transistor is connected to the ground terminal, the drain of the third transistor is connected to one end of the second resistor, and the drain of the fourth transistor is connected to the other end of the second resistor. The third transistor is a P-type transistor, and the fourth transistor is an N-type transistor. The second capacitor is connected in parallel with the fourth transistor, one end of the second capacitor is connected to the drain of the fourth transistor, and the other end of the second capacitor is connected to the source of the fourth transistor. The intermediate node between the second resistor and the fourth transistor is connected to the input terminal of the third NOT gate.
6. The monostable circuit according to claim 5, characterized in that, The discharge time constant of the second RC delay circuit is less than the charging time of the first RC delay circuit.
7. The monostable circuit according to claim 6, characterized in that, The initial low-level duration of the input signal is greater than a first preset duration, which is the duration during which the third transistor and the second resistor pull the input of the third NOT gate to a high level.
8. The monostable circuit according to claim 7, characterized in that, The sum of the discharge duration of the second RC delay circuit and the charging duration of the second RC delay circuit is less than or equal to a second preset duration, which is a preset interval duration for triggering the monostable circuit.
9. The monostable circuit according to claim 8, characterized in that, The monostable circuit mentioned is a monostable circuit in a low-speed chip.
10. A monostable circuit, characterized in that, The monostable circuit includes: a NOR gate, a first transistor to a fourth transistor, a first resistor, a second resistor, a first capacitor, a second capacitor, a first NOT gate, a second NOT gate, a third NOT gate, and a NAND gate; The input terminal of the NOR gate receives the input signal of the monostable circuit, the feedback of the output signal of the monostable circuit, and the time window signal; the output terminal of the NOR gate is connected to the gate of the first transistor and the gate of the second transistor. The source of the first transistor is connected to the power supply terminal, the source of the second transistor is connected to the ground terminal, the drain of the first transistor is connected to one end of the first resistor, and the drain of the second transistor is connected to the other end of the first resistor. The first transistor is a P-type transistor, and the second transistor is an N-type transistor. The first capacitor is connected in parallel with the second transistor, with one end of the first capacitor connected to the drain of the second transistor and the other end connected to the source of the second transistor; the intermediate node between the first resistor and the second transistor is connected to the input terminal of the first NOT gate. The output of the first NOT gate is connected to one input of the NAND gate, the other input of the NAND gate is connected to the input signal, the output of the NAND gate is connected to the input of the second NOT gate, and the output of the second NOT gate outputs the output signal. The gate of the third transistor and the gate of the fourth transistor receive feedback from the output signal. The source of the third transistor is connected to the power supply terminal, the source of the fourth transistor is connected to the ground terminal, the drain of the third transistor is connected to one end of the second resistor, and the drain of the fourth transistor is connected to the other end of the second resistor. The third transistor is a P-type transistor, and the fourth transistor is an N-type transistor. The second capacitor is connected in parallel with the fourth transistor, one end of the second capacitor is connected to the drain of the fourth transistor, and the other end of the second capacitor is connected to the source of the fourth transistor. The intermediate node between the second resistor and the fourth transistor is connected to the input terminal of the third NOT gate, and the output terminal of the third NOT gate outputs the time window signal.