An ultra-low power analog multiplier and divider based on current mirror structure

Abstract

The present invention belongs to the technical field of integrated circuit and circuit operation module design, and relates to an ultra-low power analog multiplier and divider based on a current mirror structure. The multiplier and divider, relying on the current mirror structure, includes a connected divider module and a multiplier module. The divider module includes N divider units, each of which includes a first divider PMOS transistor, a second divider PMOS transistor, a first divider switch, and a second divider switch. The multiplier module includes K multiplication units, each of which includes a first multiplication PMOS transistor, a second multiplication PMOS transistor, a first multiplication switch, and a second multiplication switch. The divider and multiplication units each include an opening unit and a closing unit. The input current signal passes through the division opening unit and the multiplication opening unit, and finally outputs the result of the multiplication and division operation. The multiplier and divider utilizes a current mirror structure, which has low power consumption, high efficiency, and is suitable for integrated storage and calculation structures, reducing complexity.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit and circuit operation module design, and relates to an ultra-low power consumption analog multiplier and divider based on a current mirror structure. Background Art

[0002] With the rise of the intelligent Internet of Things (IoT), demand for devices and equipment requiring large-scale computing is increasing. Integrated storage and computing architectures based on resistive-switching memory (RSM) hold great potential for applications such as convolutional neural networks. Intelligent edge computing devices requiring image processing typically require image acquisition, image preprocessing, neural network operations, and output. In addition to the normalization steps in neural network algorithms, which require division, image preprocessing also requires real-time image processing. Algorithms such as histogram equalization and mean filtering often require both multiplication and division. Traditionally, these operations were implemented in software simulation or skipped, limiting system energy efficiency and accuracy. Algorithms that avoid division are complex, and using traditional digital division methods results in large area, high power consumption, and slow speed. For operations with lower bit counts, using analog multipliers and dividers can achieve faster speeds while reducing power consumption and circuit complexity.

[0003] Traditional analog dividers are primarily implemented using two methods. One uses current-mode amplifiers, such as current-following transconductance amplifiers (CFTAs). These active amplifiers can achieve high gain, resulting in more accurate multiplication and division results. However, these can waste significant power due to the use of numerous amplifiers. Furthermore, these amplifiers are typically implemented using bipolar transistors, which require a high power supply voltage and often a negative supply. Another approach utilizes the unique square characteristics of CMOS, or the exponential characteristics of the subthreshold region. These multipliers and dividers can achieve high bandwidth with low area and power consumption. However, due to the inherent operating region limitations of the transistors, their operational range is limited, power consumption exceeds 100 μW, and accuracy is somewhat poor at both ends of the operational range. Recently, pulse-based analog dividers have also been proposed. These use digital codeword outputs, are compatible with digital systems, and offer high accuracy. However, they are large in area, consume high power, and are relatively slow.

[0004] This analog multiplier and divider is based on current mirror technology, which allows for convenient and precise current multiplication or subtraction. Simply controlling the multiple across the mirror allows for simultaneous current multiplication and division. This process eliminates the need for approximations, allowing for a wide input and output range and high precision. Furthermore, it is compatible with digital codewords and can be used for real-time division operations in edge devices. Summary of the Invention

[0005] The purpose of the present invention is to overcome the problems of high power consumption, low precision, and small input and output range of existing dividers. An ultra-low power analog multiplier and divider based on a current mirror structure is proposed to perform multiplication and division of any number of bits, ensuring very low power and a very simple circuit in lower-bit operations; while meeting the requirements of speed and power consumption, it can ensure stable accuracy for all signals within a wide data input range and temperature range, and is compatible with digital codewords.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] An ultra-low power analog multiplier and divider based on a current mirror structure, relying on the current mirror structure, includes a divider module and a multiplier module, and the divider module and the multiplier module are connected;

[0008] The divider module includes N divider units, and each divider unit includes a first divider PMOS transistor, a second divider PMOS transistor, a first divider switch, and a second divider switch;

[0009] The N division units include a division start unit and a division stop unit;

[0010] The division-on unit refers to a division unit in which the first division switch is on and the second division switch is on;

[0011] The division-off unit refers to a division unit in which the first division switch and the second division switch are closed;

[0012] The multiplier module includes K multiplication units, and each multiplication unit includes a first multiplication PMOS tube, a second multiplication PMOS tube, a first multiplication switch and a second multiplication switch;

[0013] The K multiplication units include a multiplication opening unit and a multiplication closing unit;

[0014] The multiplication-on unit refers to a multiplication unit in which all multiplication first switches and multiplication second switches in the multiplier module are turned on;

[0015] The multiplication-off unit refers to a multiplication unit in which all multiplication first switches and multiplication second switches in the multiplier module are off;

[0016] When the first switch is turned on, the gate of the corresponding first multiplication PMOS transistor is connected to the gates of the corresponding first multiplication PMOS transistors in all division start-up units and the gates of the corresponding first multiplication PMOS transistors in all multiplication start-up units;

[0017] When the multiplication switch No. 1 is closed, the gate of the corresponding multiplication PMOS tube No. 1 is connected to the power supply;

[0018] When the second multiplication switch is turned on, the gate of the corresponding second multiplication PMOS tube is connected to the input terminal;

[0019] When the second multiplication switch is closed, the gate of the corresponding second multiplication PMOS tube is connected to the power supply, and the drains of all the second multiplication PMOS tubes of the multiplier module are connected to the output end.

[0020] The current mirror structure is a common-source common-gate structure, including four PMOS tubes, denoted as PMOS1, PMOS2, PMOS3 and PMOS4; the sources of PMOS1 and PMOS3 are connected to the power supply; the gates of PMOS1 and PMOS3 are connected; the drain of PMOS1 is connected to the source of PMOS2; the drain of PMOS3 is connected to the source of PMOS4; the drain of PMOS1 is connected to the gate of PMOS1; the drain of PMOS2 is connected to the gate of PMOS2; the input end is connected to the drain of PMOS2; and the output end is connected to the drain of PMOS4.

[0021] The N division units, namely the first division unit to the Nth division unit, and the first division unit to the Nth division unit correspond to D0 to D0 of the divisor respectively. N-1 Bit.

[0022] The K multiplication units, namely the first multiplication unit to the Kth multiplication unit, and the first multiplication unit to the Kth multiplication unit, respectively correspond to the multiplier M K-1 To M0 position.

[0023] The first division switch and the second division switch are turned on and off synchronously; the first multiplication switch and the second multiplication switch are turned on and off synchronously.

[0024] The number of division-on units in the N division units is N1; the number of division-off units is N-N1; and N is greater than or equal to 0; N1 is greater than or equal to 0 and less than or equal to N.

[0025] The number of multiplication-on units in the K multiplication units is K1; the number of multiplication-off units is K-K1; and K is greater than or equal to 0; K1 is greater than or equal to 0 and less than or equal to K.

[0026] The first division switch is turned on, and the gate and drain of the corresponding first division PMOS tube are connected; the second division switch is turned on, and the gate and drain of the corresponding second division PMOS tube are connected to the input end.

[0027] When the first division switch is closed, the gate of the corresponding first division PMOS tube is connected to the power supply; when the second division switch is closed, the gate of the corresponding second division PMOS tube is connected to the power supply.

[0028] The function of the multiplier module is to perform N-bit division on the input current; the function of the multiplier module is to perform K-bit multiplication on the input current;

[0029] The working process of the analog multiplier and divider includes the following steps:

[0030] S1. Connect the multiplier module and the divider module to power and start working;

[0031] S2. Determine K1 multiplier on units and K-K1 multiplier off units and their distribution according to the multiplication multiple; and determine N1 divider on units and N-N1 divider off units and their distribution according to the division multiple;

[0032] S3, input the current signal into the divider module, and complete the N-bit division operation through N1 division start units;

[0033] S4. After completing the N-bit division operation of S3, it enters the multiplier module, completes the K-bit multiplication operation through K1 multiplication start units, and outputs the final calculation result.

[0034] Beneficial effects

[0035] Compared with existing analog multipliers and dividers, the ultra-low power consumption analog multiplier and divider based on the current mirror structure has the following beneficial effects:

[0036] 1. The ultra-low-power analog multiplier and divider achieves higher bit counts and speeds than digital multipliers and dividers, and can maintain very low power and a very simple circuit in lower-bit operations, thereby improving efficiency.

[0037] 2. Compared with traditional BJT multipliers and dividers, the ultra-low power analog multiplier and divider is implemented in full CMOS, which improves integration. Compared with traditional CMOS analog multipliers and dividers, it has a wider operating range and higher precision.

[0038] 3. The ultra-low power analog multiplier and divider uses analog circuits to complete multiplication and division operations in one step while also completing rounding and zero operations. It uses current signals without the need for analog voltage, resulting in high speed.

[0039] 4. The ultra-low power analog multiplier and divider consumes less power than a divider using a current conveyor or an operational amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is a diagram of the basic current mirror structure;

[0041] Figure 2 This is a basic circuit module diagram of the ultra-low power analog multiplier and divider based on the current mirror structure described in the present invention;

[0042] Figure 3 This is a detailed structural diagram of an ultra-low power analog multiplier and divider based on a current mirror structure;

[0043] Figure 4 This is a specific example diagram of an ultra-low power analog multiplier and divider based on a current mirror structure;

[0044] Figure 5 This is an equivalent diagram of the current mirror-on state of an ultra-low power analog multiplier and divider based on a current mirror structure. DETAILED DESCRIPTION

[0045] The specific implementation of the ultra-low power consumption analog multiplier and divider based on the current mirror structure of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0046] Example 1

[0047] This embodiment describes the specific implementation of the ultra-low power analog multiplier and divider based on the current mirror structure of the present invention.

[0048] When N is specifically implemented as 8, the divider module includes 8 division units, namely, division units 1 to 8; the division units 1 to 8 correspond to bits D0 to D7 of the divisor, respectively, and each division unit includes a division PMOS transistor 1, a division PMOS transistor 2, a division switch 1, and a division switch 2; and the division switch 1 and the division switch 2 are turned on and off synchronously;

[0049] When the first division switch is turned on, the gate and drain of the corresponding first division PMOS tube are connected;

[0050] When the first division switch is closed, the gate of the corresponding first division PMOS tube is connected to the power supply;

[0051] When the second division switch is turned on, the gate and drain of the corresponding second division PMOS tube are connected to the input terminal;

[0052] When the second division switch is closed, the gate of the corresponding second division PMOS tube is connected to the power supply;

[0053] The K is 8 in a specific implementation, that is, the multiplier module includes 8 multiplication units, namely, multiplication units 1 to 8; the multiplication units 1 to 8 correspond to bits M7 to M0 of the multiplier, respectively, and each multiplication unit includes a multiplication 1 PMOS transistor, a multiplication 2 PMOS transistor, a multiplication 1 switch, and a multiplication 2 switch; and the opening and closing of the multiplication 1 switch and the multiplication 2 switch are synchronized;

[0054] When the first switch is turned on, the gate of the corresponding first multiplication PMOS transistor is connected to the gates of the corresponding first multiplication PMOS transistors in all turned-on units of the divider module and the gates of the corresponding first multiplication PMOS transistors in all turned-on units of the multiplier module; when the first multiplication switch is turned off, the gate of the corresponding first multiplication PMOS transistor is connected to the power supply;

[0055] All the enabled units of the divider module refer to all the division units in the divider module with the first division switch and the second division switch enabled;

[0056] All the enabled units of the multiplier module refer to all the division units in the multiplier module with their first multiplication switch and their second multiplication switch enabled;

[0057] When the second multiplication switch is turned on, the gate of the corresponding second multiplication PMOS tube is connected to the input terminal; when the second multiplication switch is turned off, the gate of the corresponding second multiplication PMOS tube is connected to the power supply;

[0058] The drains of all the second multiplication PMOS tubes of the multiplier module are connected to the output terminal;

[0059] The first division unit includes a first output terminal, and the second to eighth division units each include their corresponding input terminals and output terminals. The first to seventh multiplication units each include their corresponding input terminals and output terminals, and the eighth multiplication unit includes a first input terminal. The first to eighth division units each include a power supply terminal and a current input terminal, and the first to eighth multiplication units each include a power supply terminal and a current output terminal.

[0060] The first switch includes an a_0 port and a b_0 port, and the second switch includes an a_0 port and a b_0 port.

[0061] The connection relationship between the modules of the analog multiplier and divider is as follows:

[0062] The divider module is connected to the multiplier module, specifically:

[0063] The source of the first PMOS tube corresponding to the division unit 1 to the division unit 8 is connected to the power supply, and the source of the first PMOS tube corresponding to the multiplication unit 1 to the multiplication unit 8 is connected to the power supply; the a_0 end of the first switch and the second switch corresponding to the division unit 1 to the division unit 8 and the multiplication unit 1 to the multiplication unit 8 are connected to the DC voltage power supply; the b_0 port of the first switch corresponding to the division unit 1 to the division unit 8 and the multiplication unit 1 to the multiplication unit 8 are connected to the drain of the first PMOS tube; the b_0 port of the second switch corresponding to the division unit 1 to the division unit 8 is connected to the current input end, and the b_0 port of the second switch corresponding to the multiplication unit 1 to the division unit 8 is connected to the current output end; the drain of the first PMOS tube corresponding to the division unit 1 to the division unit 8 and the multiplication unit 1 to the multiplication unit 8 is connected to the second The sources of the PMOS tubes are connected; the gates of the first PMOS tubes corresponding to the division units 1 to 8 and the multiplication units 1 to 8 are connected to their corresponding first switches, and the gates of the second PMOS tubes corresponding to the division units 1 to 8 and the multiplication units 1 to 8 are connected to their corresponding second switches; the drains of the first PMOS tubes corresponding to the division units 1 to 8 and the multiplication units 1 to 8 are connected.

[0064] The divider module controls the access to the division unit. The multiples of the first to eighth division units are 1, 2, 4, 8, 16, 32, 64, and 128, respectively. Therefore, a maximum of 255 times can be accessed to perform a division operation on the input current. The multiplier module receives the current after the division operation, controls the access to the multiplication unit. The multiples of the first to eighth multiplication units are 128, 64, 32, 16, 8, 4, 2, and 1, respectively. The input current is multiplied and finally the current after the multiplication and division operation is output.

[0065] The signal flow relationship of each module in the analog multiplier and divider is as follows:

[0066] The input current first enters the divider module. The 1st to 8th division units in the divider module correspond to the binary 1 bit respectively, controlling the corresponding 1st switch and 2nd switch. The 1st division unit controls the lowest bit 1 times unit, and the 8th division unit controls the highest bit 128 times unit. When the divisor input is high, the switch is connected to port 1, and the gate of the module unit is connected to the gate of the output side and to the drain of all input side MOS tubes at the same time. When it is low, the switch is connected to port 0 and connected to the power supply. The divider module passes the input current that has completed the division operation through the drain of the 1st PMOS tube. The data is transmitted to the multiplier module. The multiplication units 1 to 8 in the multiplier module correspond to the binary bit 1 respectively, and control the corresponding 1st switch and 2nd switch. The multiplication unit 1 controls the highest bit 128 times unit, and the multiplication unit 8 controls the lowest bit 1 times unit. When the divisor input is high, the switch is connected to port 1, and the gate of the module unit is connected to the gate of the first PMOS tube connected to the divider module, and at the same time connected to the drain of the first PMOS tube corresponding to the divider module. When it is low, the switch is connected to port 0 and connected to the power supply. Finally, after the multiplication operation, the final calculation result is output.

[0067] The working process of the analog multiplier and divider includes the following steps:

[0068] Step 1: Connect the multiplier module and the divider module to power and start working;

[0069] Step 2: Determine the number and corresponding positions of the multiplier on units and the multiplier off units according to the multiplication multiple; and determine the number and corresponding positions of the divider on units and the divider off units according to the division multiple;

[0070] Step 3: The input signal enters the divider part and passes through N1 open cells to complete N-bit division; after completing the division operation, it enters the multiplier part and passes through K1 open cells to complete K-bit multiplication;

[0071] Step 4: After the divider start unit and the multiplier start unit are turned on, the multiplication and division operations are completed and the final calculation result is output.

[0072] Example 2

[0073] This embodiment describes in detail the input and output conditions of an ultra-low power analog multiplier and divider based on a current mirror structure when it is implemented under normal working conditions.

[0074] The ultra-low power analog multiplier and divider based on the current mirror structure mainly uses the current mirror structure to conveniently and accurately multiply or subtract the current. The multiplication and division of the current can be completed by simply controlling the multiples at both ends of the current mirror. The entire process does not require any approximation and can meet a large input and output range and high precision.

[0075] Figure 1 This is a basic current mirror structure diagram, which consists of four PMOS tubes, namely PMOS1 to PMOS4; the input current Iin is connected to the gates of PMOS2 and PMOS4, and the output current Iout is connected to the drain of PMOS4.

[0076] Figure 2 D7 to D0 in the figure are the 8th division unit to the 1st division unit; M7 to M0 are the 8th multiplication unit to the 1st multiplication unit.

[0077] Figure 3 D7_PMOS1 is the first PMOS transistor for the eighth division unit, D7_PMOS2 is the second PMOS transistor for the eighth division unit, SWD7a is the first switch for the eighth division unit, and SWD7b is the second switch for the eighth division unit; similarly, D6_PMOS1 to D0_PMOS1 are the first PMOS transistor for the seventh division unit to the first division unit, D6_PMOS2 to D0_PMOS2 are the second PMOS transistors for the seventh division unit to the first division unit, SWD6a-SWD0a are the first switches for the seventh division unit to the first division unit, and SWD6b- SWD0b is the second division switch from the seventh division unit to the first division unit; D7a_0 to D0a_0 are the a_0 port of the first division switch from the eighth division unit to the first division unit; D7a_1 to D0a_1 are the a_1 port of the second division switch from the eighth division unit to the first division unit; D7b_0 to D0b_0 are the b_0 port of the second division switch from the eighth division unit to the first division unit; D7b_1 to D0b_1 are the b_1 port of the first division switch from the eighth division unit to the first division unit;

[0078] Figure 3In the figure, M7_PMOS1 is the first multiplication PMOS transistor of the eighth multiplication unit, M7_PMOS2 is the second multiplication PMOS transistor of the eighth multiplication unit, SWD7a is the first multiplication switch of the eighth multiplication unit, and SWM7b is the second multiplication switch of the eighth multiplication unit; similarly, M6_PMOS1 to M0_PMOS1 are the first multiplication PMOS transistors from the seventh multiplication unit to the first multiplication unit, M6_PMOS2 to M0_PMOS2 are the second multiplication PMOS transistors from the seventh multiplication unit to the first multiplication unit, SWM6a-SWM0a are the first multiplication switches from the seventh multiplication unit to the first multiplication unit, and SWM6b-SWM0b are the second multiplication switches from the seventh multiplication unit to the first multiplication unit. M7a_0 to M0a_0, that is, the a_0 port of the multiplication 1st switch from the 8th multiplication unit to the 1st multiplication unit, M7a_1 to M0a_1, that is, the a_1 port of the multiplication 2nd switch from the 8th multiplication unit to the 1st multiplication unit, M7b_0 to M0b_0, that is, the b_0 port of the multiplication 2nd switch from the 8th multiplication unit to the 1st multiplication unit, and M7b_1 to M0b_1, that is, the b_1 port of the multiplication 1st switch from the 8th multiplication unit to the 1st multiplication unit.

[0079] Figure 3 In a specific implementation of a DC voltage, the power supply is the power supply voltage, which is 1.2V. Regarding the size selection of all PMOS tubes, the length is 4 μm and the width is 300 nm. The 1.2V DC power supply voltage is connected to the sources of all first PMOS tubes, the a_0 ports of all first switches, and the b_0 ports of all second switches. The drains of all first PMOS tubes are connected to the sources of the second PMOS tubes in their respective units. The drains of all second dividing PMOS tubes are connected to the input port, the drains of all second multiplying PMOS tubes are connected to the output port, the b_1 ports of all second dividing switches are connected to the input port, and the b_1 ports of all second multiplying switches are connected to the output port.

[0080] Figure 3This connection method allows for arbitrary configuration of current mirrors with integer multiples. At different multiples, only the gate of the connected MOS transistor is connected to the circuit, reducing the capacitive load on the input stage. To ensure the accuracy of the current mirror, a two-stage cascode current mirror structure is used. A current mirror with a maximum magnification of 255 can be connected, fully representing an eight-bit binary value. When the output magnification N = MIN = 1, the output current mirror magnification is 1, and the output current is Iin divided by the input current mirror magnification. The input current mirror is divided into eight groups, each corresponding to a single binary bit. The most significant bit controls the 128-magnitude current mirror, and the least significant bit controls the 1-magnitude current mirror. When the divisor input is high, the gate of the unit is connected to the output gate and simultaneously to the drains of all input MOS transistors. When it is low, it is connected to the power supply. This allows for full implementation of all eight-bit binary multiples, completing the division of analog input currents and digital inputs. When the input is a discrete current with an integer multiple of a unit current, the output current is a multiple of that integer multiple of the same unit current.

[0081] At the same time, it exhibits analog circuit characteristics, resulting in a continuous output. In this case, the multiple is not rounded to the nearest integer, thus naturally implementing the four-set-five-entry requirement for division results often required in image algorithms. The circuit is also naturally compatible with division by zero. When the input is 0, the gates of all PMOS transistors in the divider are connected to the power supply, while the gates of all PMOS transistors in the multiplier are directly connected to the drain of the trigger. When current flows into the input, a large voltage drop occurs here due to the large off-resistance. However, the second PMOS transistor has a higher threshold voltage and a larger off-resistance than the first due to substrate bias, so most of the voltage drop occurs across this transistor, while the voltage drop across the first PMOS transistor is smaller. As a result, the gate of the second PMOS transistor in the multiplier is almost grounded, fully conducting, while the gate voltage of the first PMOS transistor is higher, close to the power supply. At this point, the total current in the circuit is the current of the transistor with the smaller current, a very small value, and the output is almost zero, simulating the situation where the valid bit wraps back to 0 after a division overflow.

[0082] Because multiplication shares the same analog circuit characteristics as division, the result of multiplication is a direct multiplication of the previously mentioned decimal-place division result. Unlike the digital circuit's integer division followed by multiplication operation, which directly discards decimal places and generates errors, it naturally ensures the accuracy of the final result without any intermediate discards. Furthermore, if the result is also a decimal, it is not discarded. Similarly, when the multiplier input is 0, the gates of all PMOS transistors in the multiplier are connected to the power supply, effectively shutting down the transistors, ensuring a very strong output current of 0. This shows that the analog multiplier and divider can perform rounding and zero operations using current signals without the involvement of analog voltages, resulting in relatively fast speeds.

[0083] Figure 4 As shown, taking the example of an input current divided by 5 and then multiplied by 192, the corresponding binary numbers are 0000101 and 11000000. The circuit is turned on, and the corresponding switches 1 and 2 in the division unit 1 and division unit 3 are closed, respectively, and the corresponding switches 1 and 2 in the multiplication unit 1 and multiplication unit 2 are closed. The input current passes through the enabled division unit 1 and division unit 3, exits the divider portion, enters the multiplier portion, passes through the enabled multiplication unit 1 and multiplication unit 4, and finally outputs the result of the multiplication and division operations. The current can be multiplied or subtracted using the current mirror. Simply controlling the multiple at both ends of the current mirror allows for current multiplication and division. By extension, multiplication and division within the range of 0-256 can be performed. This analog multiplier and divider can achieve a higher bit count and a wider current range.

[0084] like Figure 5 As shown, after the input passes through D times the MOS tube and the output mirror passes through M times the MOS tube, the current becomes M / D times, that is, Iout = Iin / D*M, which realizes multiplication and division in one step; and the current mirror has the characteristic of being independent of temperature. Even if the temperature changes and the threshold voltage changes, as long as the transistors are still in a matching state, its operation accuracy will not be affected. Moreover, when the current mirror operates, the average current of the transistors on both sides is consistent, and there will be no mismatch problem caused by serious imbalance in temperature distribution. The loss of accuracy depends only on the transistor mismatch caused by deviations in production, and this mismatch is fixed after production is completed and can be calibrated in some later stages. Compared with traditional CMOS analog multipliers and dividers, it has a wider operating range, higher accuracy, and faster speed.

[0085] The analog input and output of the analog multiplier and divider are all currents, not voltages. Due to the square-rate IV characteristics of MOS transistors, charging and discharging the capacitors only requires relatively small voltage fluctuations. This results in higher speeds and lower power consumption compared to voltage-based operations, with power consumption of less than 6.15uW. The output capacitance is also the source-drain capacitance of 255 MOS transistors, so the output speed is also related to the voltage gain of the load. The greater the load voltage gain, the smaller the required voltage fluctuation and the faster the speed. If connected to a resistor output, the gain is the conductance value, and the speed is proportional to its conductance value.

[0086] The analog multiplier and divider uses a 55nm process and can operate at a power supply voltage of 1.2V. Its analog operating bandwidth is 1.4MHz, the signal delay is 1us at eight-bit operation accuracy, and the maximum power within the eight-bit data range does not exceed 6.15uW.

[0087] In summary, the circuit structure designed by the present invention is compatible with digital codewords and can be used for real-time division operations on edge devices. It uses a current mirror structure to implement multiplication and division operations on current. Compared with digital multipliers and dividers that achieve higher bit counts and speeds, it can ensure very low power and a very simple circuit in operations with lower bit counts, thereby improving efficiency. It is also applicable to a storage and calculation integrated structure, increasing computing power through the division of current and digital code, reducing the power and complexity required for division, and more in line with current requirements for multipliers and dividers.

[0088] The specific descriptions or embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An ultra-low power analog multiplier and divider based on a current mirror structure, relying on the current mirror structure, characterized in that: The divider module and the multiplier module are connected to each other. The divider module includes N divider units, and each divider unit includes a first divider PMOS transistor, a second divider PMOS transistor, a first divider switch, and a second divider switch; The N division units include a division start unit and a division stop unit; The division-on unit refers to a division unit in which the first division switch is on and the second division switch is on; The division-off unit refers to a division unit in which the first division switch and the second division switch are closed; The multiplier module includes K multiplication units, and each multiplication unit includes a first multiplication PMOS transistor, a second multiplication PMOS transistor, a first multiplication switch, and a second multiplication switch; The K multiplication units include a multiplication opening unit and a multiplication closing unit; The multiplication-on unit refers to a multiplication unit in which all multiplication first switches and multiplication second switches in the multiplier module are turned on; The multiplication-off unit refers to a multiplication unit in which all multiplication first switches and multiplication second switches in the multiplier module are off; When the first switch is turned on, the gate of the corresponding first multiplication PMOS transistor is connected to the gates of the corresponding first multiplication PMOS transistors in all division-on units and the gates of the corresponding first multiplication PMOS transistors in all multiplication-on units; When the multiplication switch No. 1 is closed, the gate of the corresponding multiplication PMOS tube No. 1 is connected to the power supply; When the second multiplication switch is turned on, the gate of the corresponding second multiplication PMOS tube is connected to the input terminal; When the second multiplication switch is closed, the gate of the corresponding second multiplication PMOS tube is connected to the power supply, and the drains of all the second multiplication PMOS tubes of the multiplier module are connected to the output end.

2. The analog multiplier and divider according to claim 1, wherein: The current mirror structure is a common-source common-gate structure, including four PMOS tubes, denoted as PMOS1, PMOS2, PMOS3 and PMOS4; the sources of PMOS1 and PMOS3 are connected to the power supply; the gates of PMOS1 and PMOS3 are connected; the drain of PMOS1 is connected to the source of PMOS2; the drain of PMOS3 is connected to the source of PMOS4; the drain of PMOS1 is connected to the gate of PMOS1; the drain of PMOS2 is connected to the gate of PMOS2; the input end is connected to the drain of PMOS2; and the output end is connected to the drain of PMOS4.

3. The analog multiplier and divider according to claim 1, wherein: The N division units, namely the first division unit to the Nth division unit, and the first division unit to the Nth division unit correspond to D0 to D0 of the divisor respectively. N-1 Bit.

4. The analog multiplier and divider according to claim 1, wherein: The K multiplication units, namely the first multiplication unit to the Kth multiplication unit, and the first multiplication unit to the Kth multiplication unit, respectively correspond to the multiplier M K-1 To M0 position.

5. The analog multiplier and divider according to claim 1, wherein: The first division switch and the second division switch are turned on and off synchronously; the first multiplication switch and the second multiplication switch are turned on and off synchronously.

6. The analog multiplier and divider according to claim 1, wherein: The number of division-on units in the N division units is N1; the number of division-off units is N-N1; and N is greater than or equal to 0; N1 is greater than or equal to 0 and less than or equal to N.

7. The analog multiplier and divider according to claim 1, wherein: The number of multiplication-on units in the K multiplication units is K1; the number of multiplication-off units is K-K1; and K is greater than or equal to 0; K1 is greater than or equal to 0 and less than or equal to K.

8. The analog multiplier and divider according to claim 1, wherein: The first division switch is turned on, and the gate and drain of the corresponding first division PMOS tube are connected; the second division switch is turned on, and the gate and drain of the corresponding second division PMOS tube are connected to the input end.

9. The analog multiplier and divider according to claim 1, wherein: The first division switch is closed, and the gate of the corresponding first division PMOS tube is connected to the power supply; the second division switch is closed, and the gate of the corresponding second division PMOS tube is connected to the power supply.

10. The analog multiplier and divider according to claim 1, wherein: The function of the multiplier module is to perform N-bit division on the input current; the function of the multiplier module is to perform K-bit multiplication on the input current; the working process of the analog multiplier and divider includes the following steps: S1. Connect the multiplier module and the divider module to power and start working; S2. Determine K1 multiplier on units and K-K1 multiplier off units and their distribution according to the multiplication multiple; and determine N1 divider on units and N-N1 divider off units and their distribution according to the division multiple; S3, input the current signal into the divider module, and complete the N-bit division operation through N1 division start units; S4. After completing the N-bit division operation of S3, it enters the multiplier module, completes the K-bit multiplication operation through K1 multiplication start units, and outputs the final calculation result.

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