Integrated circuit verification apparatus, integrated circuit verification method, and non-transitory computer readable medium

Abstract

The present application relates to an integrated circuit verification device, an integrated circuit verification method, and a non-temporary computer readable medium. The integrated circuit verification device of the embodiment includes a conditional attribute information generation section that generates a plurality of conditional attributes having information that restricts circuit operation or input signals, based on conditional statements of a code list of a design data file; an exclusion code generation section that generates exclusion codes that are proven to be not statically covered, and a first exclusion code list to which the plurality of conditional attributes are applied, based on the code list; and an exclusion code comparison section that generates a second exclusion code list based on a difference between the exclusion codes and the first exclusion code.

Description

[0001] [Cross-reference to related applications]

[0002] This application claims priority based on the priority of the prior Japanese Patent Application No. 2021-102948, filed on June 22, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of the present invention relate to an integrated circuit verification apparatus, an integrated circuit verification method, and a non-transitory computer-readable medium. Background Technology

[0004] Currently, code coverage is widely used as a representative indicator of the test coverage of logic circuits, i.e., the accuracy of verification. In addition, engineers sometimes collect coverage databases from simulations to generate coverage reports to analyze the design of the tested items. Summary of the Invention

[0005] One embodiment provides an integrated circuit verification apparatus, an integrated circuit verification method, and a non-transitory computer-readable medium capable of efficiently eliminating unverified code caused by the same underlying reasons.

[0006] An integrated circuit verification apparatus according to an embodiment includes: a condition attribute information generation unit that generates multiple condition attributes containing information restricting circuit operation or input signals based on conditional statements in a code list of a design data file; an exclusion code generation unit that generates exclusion codes proven to be statically uncovered and a first exclusion code list applying the multiple condition attributes based on the code list; and an exclusion code comparison unit that generates a second exclusion code list based on the difference between the exclusion code and the first exclusion code. The exclusion code comparison unit determines whether the first condition attribute and the second condition attribute are present among the multiple condition attributes that are at least partially identical to the uncovered codes in the second exclusion code list. When the first condition attribute and the second condition attribute are present, the unit extracts the condition attribute containing the signal closest to the input signal from the first condition attribute and the second condition attribute.

[0007] Based on the aforementioned configuration, an integrated circuit verification apparatus, an integrated circuit verification method, and a non-transitory computer-readable medium can be provided that are capable of efficiently excluding unverified code due to the same underlying causes. Attached Figure Description

[0008] Figure 1 This is a schematic diagram showing the block configuration of an integrated circuit verification device according to an implementation method.

[0009] Figure 2 This is a detailed functional block diagram of the CPU and storage medium of the integrated circuit verification device according to the implementation method.

[0010] Figure 3 is a summary diagram of a flowchart of an integrated circuit verification method of an integrated circuit verification apparatus of an embodiment.

[0011] Figure 4A is a detail diagram (first half) of a flowchart of an integrated circuit verification method of an integrated circuit verification apparatus of an embodiment.

[0012] Figure 4B is a detail diagram (second half) of a flowchart of an integrated circuit verification method of an integrated circuit verification apparatus of an embodiment.

[0013] Figure 5A represents an example of a coverage database code of an embodiment.

[0014] Figure 5B represents an example of a coverage database code and an example of a conditional attribute generated based on the example of the coverage database code.

[0015] Figure 6 represents an example of a listed conditional attribute list.

[0016] Figure 7A represents an example of exclusion code when a conditional attribute list is not applied.

[0017] Figure 7B represents an example of a first exclusion code list when a conditional attribute list is applied.

[0018] Figure 8A represents an example of a comparison of a second exclusion code list when a conditional attribute list is applied.

[0019] Figure 8B is an explanatory diagram for explaining deletion of uncovered code from the example of the second exclusion code list when a conditional attribute list is applied, according to a conditional attribute of an object.

[0020] Figure 9 represents an example of a conditional attribute list and an exclusion code list prompted to a user. DETAILED DESCRIPTION

[0021] Hereinafter, an embodiment will be described with reference to the accompanying drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. The drawings are schematic diagrams.

[0022] In addition, the embodiment shown below exemplifies an apparatus and a method for realizing the technical idea, and does not specify the material, shape, structure, arrangement, and the like of each constituent part. The embodiment can be variously changed within the scope of the claims.

[0023] In the following description, the central processing unit and the register transfer level are sometimes simply referred to as CPU and RTL.

[0024] [Embodiment]

[0025] (Integrated circuit verification device)

[0026] Figure 1 An example of a block configuration of an integrated circuit verification device 1 of the embodiment is shown in Fig. 1. As shown in Fig. 1, the integrated circuit verification device 1 is provided with a central processing unit 2, an input / output control device 31, an input device 32, an output device 33, a main storage device 35, and a storage medium 4. In the following description, the central processing unit 2 is referred to as CPU 2. Figure 1

[0027] The integrated circuit verification device 1 is constituted at least by the CPU 2, the input device 32 and the output device 33 connected to the CPU 2 via the input / output control device 31, and the main storage device 35 and the storage medium 4 connected to the CPU 2. In fact, it is not limited to these examples.

[0028] The CPU 2 is provided with a logic simulator section 21 and a formal verification section 22. The CPU 2 stores a computer program used by the integrated circuit verification device 1. In addition, the details of the logic simulator section 21 and the formal verification section 22 will be described later.

[0029] The input / output control device 31 is an interface for connecting the input device 32, the output device 33, and a readout section (omitted from the drawing) for reading out data of an external storage medium such as a compact disc ROM, a magneto-optical disk, a floppy disk, and the like, to the CPU 2. The input / output control device 31 functions as an interface for the input device 32, the output device 33, and the readout section of the external storage device.

[0030] The input device 32 includes, for example, a keyboard, a mouse, an identification device such as an OCR (Optical Character Reader), a graphical input device such as an image scanner, a special input device such as a voice recognition device, and the like.

[0031] The output device 33 includes, for example, a display device such as a liquid crystal display, a CRT (Cathode-ray tube) display, a printing device such as an inkjet printer, a laser printer, and the like.

[0032] ​The main storage device 35 includes, for example, ROM and RAM. ROM functions as a program storage device for storing programs executed in CPU2. ROM may also be a non-transitory computer-readable recording medium storing programs. RAM functions as temporary storage, temporarily storing data used in the program execution processing of CPU2, and is used as the working area.

[0033] Storage medium 4 includes a first information storage unit 41 and a second information storage unit 42. Storage medium 4 stores: input information data required for executing a computer program used for logic simulation and formal verification, execution result data of the logic simulation, and execution result data of the formal verification. Details of the first information storage unit 41 and the second information storage unit 42 will be described below.

[0034] Next, Figure 2 The diagram shows an example of a detailed functional block configuration of the CPU 2 and storage medium 4 of the integrated circuit verification device 1 according to an embodiment. Figure 2 As shown, the CPU2 includes: a logic simulator unit 21, which executes a computer program used for logic simulation of the integrated circuit verification device 1; and a formal verification unit 22, which executes a computer program used for formal verification of the integrated circuit verification device 1.

[0035] Furthermore, the logic simulator unit 21 and the formal verification unit 22 may also be, for example, a microprocessor processing device and a semiconductor integrated circuit (IC) with the same function. However, they are not actually limited to these examples.

[0036] The logic simulator unit 21 includes a coverage database output unit 211. After performing logic simulation, the coverage database output unit 211 outputs the coverage database 421A to the coverage database information storage unit 421.

[0037] The coverage database 421A, for example, contains coverage information of the source code used to manage the verification process, output through logic simulation. Furthermore, the source code used may also be, for example, a Design Under Test (DUT) data file being verified.

[0038] The formal verification unit 22 includes an uncovered code information extraction unit 221, a condition attribute information generation unit 222, a condition attribute list information output unit 223, an exclusion code generation unit 224, an exclusion code comparison unit 225, and an exclusion code information output unit 226.

[0039] The uncovered code information extraction section 221 reads the coverage database 421A stored in the coverage database information storage section 421, and extracts the unverified code. In the following description, the unverified code will also be referred to as uncovered code or uncovered. In addition, the verified code will be referred to as covered code or covered.

[0040] The condition attribute information generation section 222 generates a plurality of condition attributes based on the condition statement of each uncovered reason extracted by the uncovered code information extraction section 221. The plurality of condition attributes have, for example, information that restricts the operation of the circuit or the input signal.

[0041] The condition attribute list information output section 223 lists the plurality of condition attributes generated by the condition attribute information generation section 222, and outputs the condition attribute list 422A to the condition attribute list information storage section 422. In addition, the condition attribute list information output section 223 lists the condition attributes in order from the largest to the smallest in terms of the excluded code amount excluded according to the condition attribute, and outputs the prompt condition attribute list 422C to the condition attribute list information storage section 422.

[0042] The excluded code generation section 224 generates the excluded code that is proven to be statically uncovered by formal verification, and the first excluded code to which a plurality of condition attributes are applied. In the following description, the code that is proven to be uncovered after formal verification will be referred to as excluded code. In addition, the code to which a plurality of condition attributes are applied will be referred to as first excluded code.

[0043] The excluded code comparison section 225 generates a second excluded code list based on the difference between the excluded code and the first excluded code list. In the following description, the excluded code when the condition attribute list is not applied will also be referred to as excluded code 423A to which the condition attribute is not applied. In addition, the first excluded code list when the condition attribute list is applied will also be referred to as excluded code list 423B to which the condition attribute is applied.

[0044] The excluded code comparison section 225 determines whether the first condition attribute and the second condition attribute exist in the plurality of condition attributes in which at least a part of the uncovered code of the second excluded code list is the same. Here, when the first condition attribute and the second condition attribute exist, the condition attribute that includes the condition closest to the input signal among the first condition attribute and the second condition attribute is extracted. In addition, the condition attribute that is determined among the plurality of condition attributes is not limited to the first condition attribute and the second condition attribute, and can be two or more condition attributes.

[0045] The exclusion code information output unit 226 outputs the exclusion code 423A in which the conditional attribute is not applied to the exclusion code information storage unit 423 in a case where the conditional attribute list is not applied when performing formal verification. In addition, the exclusion code information output unit 226 outputs the exclusion code list 423B in which the conditional attribute is applied to the exclusion code information storage unit 423 in a case where the conditional attribute list is applied when performing formal verification. Furthermore, the exclusion code information output unit 226 outputs the prompt exclusion code list 423C in which the conditional attribute is listed in order from the exclusion code amount according to the conditional attribute from the most to the least to the exclusion code information storage unit 423.

[0046] The first information storage unit 41 has a test pattern information storage unit 411 and an RTL source code information storage unit 412.

[0047] The test pattern information storage unit 411 stores, for example, an input signal data file input to the verification target circuit. In addition, a simulation control instruction can also be included. In the following description, the input signal data file input to the verification target circuit is referred to as a test pattern 411A.

[0048] The test pattern 411A is input information data required for a computer program used by the integrated circuit verification device 1 to execute. In addition, the test pattern 411A can also be input information data required for the logic simulator unit 21 to execute.

[0049] The RTL source code information storage unit 412 stores, for example, a design under test (DUT) data file in verification. In addition, the design under test (DUT) data file can also be, for example, a source code of a register transfer level (RTL). In the following description, the design under test data file is referred to as an RTL source code 412A.

[0050] The RTL source code 412A is input information data required for a computer program used by the integrated circuit verification device 1 to execute. In addition, the RTL source code 412A can also be input information data required for the logic simulator unit 21 to execute. In addition, the RTL source code 412A can also be input information data required for the formal verification unit 22 to execute.

[0051] The second information storage unit 42 has a coverage database information storage unit 421, a conditional attribute list information storage unit 422, and an exclusion code information storage unit 423.

[0052] The coverage database information storage unit 421 stores, for example, a coverage database 421A output by the coverage database information storage unit 421.

[0053] The coverage database 421A is input information data required for a computer program used by the integrated circuit verification apparatus 1. Further, the coverage database 421A can also be input information data required for the formal verification section 22.

[0054] The condition attribute list information storage section 422 stores the condition attribute list 422A and the prompt condition attribute list 422C, which are output by the condition attribute list information output section 223.

[0055] The condition attribute list 422A is input information data required for a computer program used by the integrated circuit verification apparatus 1. Further, the condition attribute list 422A can also be input information data required for the formal verification section 22.

[0056] The exclusion code information storage section 423 stores the exclusion code 423A of which the condition attribute is not applied, the exclusion code list 423B of which the condition attribute is applied, and the prompt exclusion code list 423C, which are output by the exclusion code information output section 226.

[0057] (Integrated circuit verification method)

[0058] Next, a flowchart of the integrated circuit verification method of the integrated circuit verification apparatus 1 of the embodiment will be described.

[0059] Figure 3 An example of a flowchart of the integrated circuit verification method of the integrated circuit verification apparatus 1 of the embodiment is shown in FIG. 12.

[0060] First, the logic simulator section 21 performs dynamic analysis using the test pattern 411A and the RTL source code 412A as input data. The dynamic analysis refers to analysis performed using the logic simulator section 21.

[0061] Next, the formal verification section 22 performs static analysis using the coverage database 421A as input data. The static analysis refers to analysis performed using the formal verification section 22. Specifically, the uncovered code information extraction section 221 extracts uncovered code from the read-in coverage database 421A. The condition attribute information generation section 222 generates a plurality of condition attributes based on the extracted condition statement that causes the uncovered code to be generated. The condition attribute list information output section 223 lists the generated plurality of condition attributes and outputs the condition attribute list 422A.

[0062] Next, the formal verification section 22 performs static analysis using the RTL source code 412A as input data. Specifically, the exclusion code generation section 224 generates, as exclusion codes, codes that are proven to be uncovered from the read-in RTL source code 412A. Further, the condition attribute list information output section 223 can also output the generated exclusion codes, i.e., exclusion codes 423A that do not apply a condition attribute. The exclusion codes are codes that are not statically covered among the codes that are not covered in the coverage database, because of a fixed value assignment to a signal or a signal propagation without passing a conditional branch on one side, and the like.

[0063] Next, the formal verification section 22 performs static analysis using the RTL source code 412A and the condition attribute list 422A as input data. Specifically, the exclusion code generation section 224 generates, as a first exclusion code list, codes that are not covered for each condition attribute based on the read-in RTL source code 412A and the condition attribute list 422A. Further, the condition attribute list information output section 223 can also sort the listed exclusion codes and output the first exclusion code list, i.e., an exclusion code list 423B that applies a condition attribute. Each exclusion code in the list is a code that, in addition to the exclusion codes 423A that do not apply a condition attribute, has codes that are proven to be uncovered by applying each condition attribute.

[0064] Finally, the formal verification section 22 performs static analysis using the exclusion codes 423A that do not apply a condition attribute and the exclusion code list 423B that applies a condition attribute as input data. Specifically, the exclusion code comparison section 225 compares the exclusion codes of the read-in exclusion codes 423A that do not apply a condition attribute with the exclusion code list of the exclusion code list 423B that applies a condition attribute. Then, the exclusion code comparison section 225 determines, based on the exclusion codes, whether there are a plurality of condition attributes that are identical to at least a portion of the exclusion codes that are present in the exclusion code list. The exclusion code comparison section 225 lists the plurality of condition attributes and the exclusion code list. The condition attribute list information output section 223 and the exclusion code information output section 226 output a prompt condition attribute list 422C and a prompt exclusion code list 423C.

[0065] Next, a detailed view of a flowchart of the integrated circuit verification method of the integrated circuit verification apparatus 1 of the embodiment will be described.

[0066] Figure 4A and Figure 4B A detailed view of a flowchart of the integrated circuit verification method of the integrated circuit verification apparatus 1 of the embodiment is shown in FIG. 10. In addition, Figure 5A An example of the coverage database code is shown in FIG. 11. Figure 5B An example of the coverage database code and an example of the condition attribute generated based on the example of the coverage database code are shown in FIG. 12.Figure 6 An example of the listed condition attribute list is shown in Figure 7A An example of the exclusion code when the condition attribute list is not applied is shown in Figure 7B An example of the first exclusion code list when the condition attribute list is applied is shown in Figure 8A An example of comparing the exclusion code list is shown in Figure 8B An explanatory diagram showing the deletion of the uncovered code is shown in Figure 9 An example of the condition attribute list and the exclusion code list prompted to the user is shown in

[0067] In step Sll, the logic simulator section 21 performs logic simulation.

[0068] In step S12, the uncovered code information extraction section 221 reads in the coverage database 421A and extracts the uncovered code. Specifically, as shown in Figure 5A the uncovered code information extraction section 221 extracts the uncovered codes pl, p2, p3, p4, for example, in the order of the 5th, 9th, 16th, and 17th lines of code in Figure 5A In the following description, the 20th to 25th lines of the coverage database code are a part of the code that is proven to be not statically covered (indicated as "···" in the diagram).

[0069] In step S13, the condition attribute information generation section 222 generates a plurality of condition attributes from the extracted uncovered code based on the conditional statement that caused the uncovered code to be generated. Specifically, as shown in Figure 5B the condition attribute information generation section 222 generates a condition attribute pl, for example, for the uncovered code pl extracted from the 5th line in Figure 5B based on the conditional statement (a Figure 5B the condition attribute information generation section 222 generates a condition attribute p2, for example, for the uncovered code p2 extracted from the 9th line in Figure 5B based on the conditional statement (g Figure 5B the condition attribute information generation section 222 generates a condition attribute p4, for example, for the uncovered code p4 extracted from the 17th line in

[0070] In step S14, the condition attribute list information output section 223 lists the generated condition attributes. Specifically, as shown in Figure 6 the condition attribute list information output section 223 sequentially lists each of the generated condition attributes in the condition attribute list.

[0071] In step S15, the uncovered code information extraction section 221 outputs the listed condition attribute list 422A in a case where all the uncovered codes of the read-in coverage database 421A are extracted, and proceeds to step S16. Specifically, the condition attribute list information output section 223 outputs the condition attribute list 422A to the condition attribute list information storage section 422, for example, in a case where all the uncovered codes are extracted. The uncovered code information extraction section 221 proceeds to step S12 in a case where all the uncovered codes of the read-in coverage database 421A are not extracted.

[0072] In step S16, the exclusion code generation section 224 generates, as exclusion codes, codes that are proven to be not statically covered from the read-in RTL source code 412A. Specifically, as shown in FIG. 20, the exclusion code generation section 224 performs formal verification without applying the condition attribute list, and generates exclusion codes of codes that are proven to be not statically covered in lines 20 to 25. Figure 7A

[0073] In step S17, the exclusion code generation section 224 generates, as a first exclusion code list, codes that are proven to be not statically covered by applying each condition attribute based on the read-in RTL source code 412A and the condition attribute list 422A. Specifically, as shown in FIG. 21, the exclusion code generation section 224 performs formal verification by applying the condition attribute list, and generates codes that are proven to be not statically covered by applying each condition attribute. Figure 7B Figure 7B In step S17, the exclusion code generation section 224 generates, as a first exclusion code list, codes that are proven to be not statically covered by applying each condition attribute based on the read-in RTL source code 412A and the condition attribute list 422A. Specifically, as shown in FIG. 21, the exclusion code generation section 224 performs formal verification by applying the condition attribute list, and generates codes that are proven to be not statically covered by applying each condition attribute.

[0074] In step S18, the exclusion code generation section 224 generates an exclusion code list 423B in which exclusion codes that are not covered by each condition attribute are listed based on the read-in RTL source code 412A and the condition attribute list 422A, and proceeds to step S19. Further, the condition attribute list information output section 223 can sort the generated exclusion list, and output the exclusion codes 423A in which the condition attribute is not applied and the exclusion code list 423B in which the condition attribute is applied. The exclusion code generation section 224 proceeds to step S17 in a case where all the not-covered codes for each condition attribute are not extracted based on the read-in RTL source code 412A and the condition attribute list 422A.

[0075] ​​In step S19, the exclusion code comparison section 225 creates a second exclusion code list from the difference between the exclusion code of the read-in exclusion code 423A of the unapplied condition attribute and the first exclusion code list of the applied condition attribute exclusion code list 423B. Specifically, as shown in Figure 8A the exclusion code generation section 224 lists, for example, the exclusion code that was added based on the condition attribute pi and that is not covered, the exclusion code that was added based on the condition attribute p2 and that is not covered, and the exclusion code that was added based on the condition attribute p3 and that is not covered, as the difference.

[0076] In step S20, the exclusion code comparison section 225 selects one of the exclusion codes of the second exclusion code list of the applied condition attribute exclusion code list 423B in order to perform comparison.

[0077] In step S21, the exclusion code comparison section 225 determines whether the exclusion codes that exist in the second exclusion code list of the applied condition attribute exclusion code list 423B have the same condition attribute based on the selected exclusion code. Specifically, as shown in Figure 8A the exclusion code comparison section 225 determines that the fifth row and the ninth row that are not covered based on the condition attribute pi of the applied condition attribute exclusion code list 423B and the fifth row and the ninth row that are not covered based on the condition attribute p2 of the applied condition attribute exclusion code list 423B are the same, and proceeds to step S22. The exclusion code comparison section 225 proceeds to step S24 in the case where the exclusion codes that exist in the exclusion list of the applied condition attribute exclusion code list 423B do not have the same condition attribute based on the compared exclusion codes.

[0078] In step S22, the exclusion code comparison section 225 extracts, for example, the condition attribute that is closest to the input signal among the first condition attribute and the second condition attribute. Specifically, as shown in Figure 8B the exclusion code comparison section 225 compares the condition attribute pi (first condition attribute) of the applied condition attribute exclusion code list 423B with the condition attribute p2 (second condition attribute) of the applied condition attribute exclusion code list 423B. Thereafter, the exclusion code comparison section 225 extracts, for example, the condition attribute pi (first condition attribute) that is closest to the input signal among the first condition attribute and the second condition attribute, and proceeds to step S24. The exclusion code comparison section 225 proceeds to step S23 in the case where there is no condition attribute that is closest to the input signal.

[0079] In step S23, the exclusion code comparison section 225 deletes the exclusion codes of the condition attributes other than the extracted condition attribute. Specifically, as shown in Figure 8BAs shown, the exclusion code comparison section 225 deletes the item of the condition attribute p2 of the exclusion code list 423B of the application condition attribute. In addition, the exclusion code comparison section 225 deletes the item of the condition attribute p2 from the read condition attribute list 422A.

[0080] In step S24, the exclusion code comparison section 225 lists the plurality of condition attributes and the exclusion codes. Specifically, the exclusion code comparison section 225 lists the codes that are not deleted as the exclusion codes for each condition attribute of the exclusion code list 423B of the application condition attribute, which are not covered.

[0081] In step S25, the exclusion code comparison section 225 judges whether the comparison and the listing have been completed for all the condition attributes for the exclusion list of the exclusion code list 423B of the application condition attribute. Specifically, the exclusion code comparison section 225 proceeds to step S26 when the comparison and the listing have been completed for all the condition attributes. The exclusion code comparison section 225 proceeds to step S20 when the comparison and the listing have not been completed for all the condition attributes.

[0082] In step S26, the condition attribute list information output section 223 and the exclusion code information output section 226 output the prompt condition attribute list 422C and the prompt exclusion code list 423C. Specifically, as shown in Figure 9 As shown, the condition attribute list information output section 223 and the exclusion code information output section 226 output, for example, the prompt condition attribute list 422C and the prompt exclusion code list 423C in which the condition attributes are listed in the order of the number of codes not covered from the most to the least, based on the condition attributes.

[0083] As described above, according to the embodiment, the integrated circuit verification device 1 deletes the condition attributes having the same not covered codes existing in the exclusion list based on the compared exclusion codes by the integrated circuit verification method, and thus can efficiently exclude the not covered caused by the same root cause.

[0084] The embodiments of the present application have been described, but these embodiments are presented only as examples, and are not intended to limit the scope of the present application. The novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the present application. The embodiments and changes thereof are included in the scope or spirit of the present application, and are included in the scope of the present application and equivalents thereof recited in the claims.

[0085] For example, in another embodiment, a circuit of a register transfer level (RTL) source code of a design under test (DUT) data file in verification can also be described in units of a logic cone. In addition, the exclusion code comparison section 225 can also select a circuit on the input side of the logic cone in the circuit description in a case where the condition attribute closest to the input signal is included in the extraction of the first condition attribute and the second condition attribute.

Claims

1. An integrated circuit verification apparatus comprising: a conditional attribute information generation section that generates a plurality of conditional attributes having information that restricts a circuit operation or an input signal, from conditional statements of a code list of a design data file; an exclusion code generation section that generates an exclusion code that is proven to be not statically covered, from the code list, and a first exclusion code list to which the plurality of conditional attributes are applied; and an exclusion code comparison section that generates a second exclusion code list from a difference between the exclusion code and the first exclusion code list; the exclusion code comparison section, determining whether a first conditional attribute and a second conditional attribute exist in the plurality of conditional attributes that are identical to at least a part of an uncovered code of the second exclusion code list, and extracting a conditional attribute that includes a signal closest to an input, from among the first conditional attribute and the second conditional attribute, when the first conditional attribute and the second conditional attribute exist.

2. The integrated circuit verification apparatus according to claim 1, wherein the exclusion code is generated by performing formal verification on the code list, and the first exclusion code list is generated by performing formal verification on the code list to which the plurality of conditional attributes are applied.

3. The integrated circuit verification apparatus according to claim 1, comprising an uncovered code information extraction section that extracts the code list of the design data file from a coverage database that includes the design data file, as an uncovered code.

4. The integrated circuit verification apparatus according to claim 3, wherein the conditional attribute information generation section generates the plurality of conditional attributes based on conditions of reasons of each uncovered code extracted by the uncovered code information extraction section.

5. The integrated circuit verification apparatus according to claim 1, wherein the exclusion code comparison section deletes the plurality of conditional attributes and the exclusion code other than the extracted conditional attributes.

6. The integrated circuit verification apparatus according to claim 1, wherein the exclusion code comparison section lists the plurality of conditional attributes and the exclusion code.

7. The integrated circuit verification apparatus according to claim 1, wherein the design data file is a register transfer level source code.

8. The integrated circuit verification apparatus according to claim 7, wherein a circuit description of the register transfer level source code is described in units of logic cones.

9. The integrated circuit verification apparatus according to claim 8, wherein the exclusion code comparison section selects a circuit on an input side of the logic cone in the circuit description, in a case where the conditional attribute that includes a signal closest to an input is included in the first conditional attribute and the second conditional attribute.

10. An integrated circuit verification method comprising: generating a plurality of conditional attributes having information that restricts a circuit operation or an input signal, from conditional statements of a code list of a design data file; generating an exclusion code that is proven to be not statically covered, from the code list, and a first exclusion code list to which the plurality of conditional attributes are applied; and generating a second exclusion code list from a difference between the exclusion code and the first exclusion code list. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ generating a second exclusion code list from a difference between the exclusion code and the first exclusion code list, determining whether there are first and second condition attributes that are identical to at least a part of the plurality of condition attributes of the uncovered code of the second exclusion code list, determining whether there are first and second condition attributes among the plurality of condition attributes, when there are the first and second condition attributes, extracting a condition attribute that is closest to an input signal among the first and second condition attributes, outputting a listed prompt attribute list and a prompt exclusion list in order of the condition attributes from a larger to a smaller amount of code of the uncovered code according to the condition attributes.

11. The integrated circuit verification method according to claim 10, which is generating an exclusion code by formal verification of the code list, generating the first exclusion code list by formal verification of the code list to which the plurality of condition attributes are applied.

12. The integrated circuit verification method according to claim 10, wherein in the uncovered code information extraction section, the code list of the design data file is extracted as uncovered code from a coverage database including the design data file.

13. The integrated circuit verification method according to claim 12, wherein in the condition attribute information generation section, the plurality of condition attributes are generated based on a condition of a reason of each of the uncovered codes.

14. The integrated circuit verification method according to claim 10, which deletes the plurality of condition attributes and the exclusion code other than the extracted condition attributes.

15. The integrated circuit verification method according to claim 10, which lists the plurality of condition attributes and the exclusion code.

16. A non-transitory computer-readable recording medium storing a program, and the program causes a computer to execute the steps of: generating a plurality of condition attributes having information of restricting a circuit operation or an input signal from a condition statement of a code list of a design data file; generating an exclusion code that is proven to be not statically covered and a first exclusion code list to which the plurality of condition attributes are applied from the code list; generating a second exclusion code list from a difference between the exclusion code and the first exclusion code list; determining whether there are first and second condition attributes that are identical to at least a part of the plurality of condition attributes of the uncovered code of the second exclusion code list; when there are the first and second condition attributes, extracting a condition attribute that is closest to an input signal among the first and second condition attributes; and outputting a listed prompt attribute list and a prompt exclusion list in order of the condition attributes from a larger to a smaller amount of code of the uncovered code according to the condition attributes.

17. The non-transitory computer-readable recording medium according to claim 16, which causes a computer to execute the steps of: generating an exclusion code by formal verification of the code list; and The first excluded code list is generated by performing formal verification applied with the plurality of conditional attributes on the code list.

18. The non-transitory computer-readable recording medium according to claim 16, which causes a computer to execute the steps of: In the uncovered code information extraction section, the code list of the design data file is extracted from a coverage database including the design data file as uncovered code.

19. The non-transitory computer-readable recording medium according to claim 18, which causes a computer to execute the steps of: In the conditional attribute information generation section, the plurality of conditional attributes are generated based on the condition of the reason of each of the uncovered codes.

20. The non-transitory computer-readable recording medium according to claim 16, which causes a computer to execute the steps of: In the excluded code comparison section, the plurality of conditional attributes and the excluded code other than the extracted conditional attributes are deleted.

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