A data processing method and related apparatus

Abstract

A data processing method, the method comprising: obtaining sequence information of a circuit layout; wherein the circuit layout comprises a polygon element, the polygon element comprising a plurality of sides; the sequence information comprising side information of each side and a connection order between the plurality of sides, the side information comprising a direction and a length of the side; processing the sequence information by a machine learning model to obtain a processing result corresponding to the circuit layout. The application can explicitly model the information of the geometric shape and the layout layout of the circuit layout at the polygon level, can efficiently and losslessly compress the integrated circuit layout into sequence information, so that the machine learning model can extract more accurate features.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductors, and in particular to a data processing method and related apparatus. BACKGROUND

[0002] In recent years, artificial intelligence (AI) has been widely applied in the field of semiconductor design and manufacturing, such as optical proximity correction, integrated circuit layout generation, hotspot detection, and yield detection.

[0003] Optical proximity correction is to adjust the shape of a mask to reduce the impact of light diffraction, so that the shape of the lithography is similar to the shape of the chip design. Integrated circuit layout is a key resource in the field of semiconductor design and manufacturing, and is widely used in lithography modeling, optical proximity correction, and layout hotspot detection. However, due to the complexity of the design and manufacturing process, it is both expensive and time-consuming to obtain sufficient integrated circuit layout. Especially in the evolution process of manufacturing technology, changes in parameters and design rules require the redesign of integrated circuit layout. In addition, AI methods are applied to the field of semiconductor design and manufacturing, which requires more integrated circuit layout as training data. Generating layout based on a generative model can meet the needs of semiconductor design and manufacturing.

[0004] The application of AI in the field of semiconductor design and manufacturing usually regards integrated circuit layout as an image and models the pixel-level relationship. For example, for optical proximity correction, the layout is generally regarded as an image, and a machine learning model is used to output the image after optical correction. Integrated circuit layout generation is also to regard the layout as an image, and a machine learning model is used to fit the distribution of the image, and then generate a new circuit layout.

[0005] However, layout is different from natural image, but is composed of some regular polygon elements, the size and layout between them require to meet the design rules. Therefore, the image modeling method based on pixel level cannot fully capture the polygon level information such as geometric shape and layout. This will lead to the generation of a large number of irregular patterns, which requires a lot of post-processing, and the accuracy of the data output by the machine learning model is low. SUMMARY

[0006] The present application provides a data processing method, which can explicitly model the polygon level information such as geometric shape and layout of the circuit layout, more easily learn the layout design rules, and efficiently losslessly compress the integrated circuit layout into a symbol sequence (sequence information), so that the machine learning model can extract more accurate features.

[0007] In a first aspect, the present application provides a data processing method, which comprises: obtaining sequence information of a circuit layout; wherein the circuit layout comprises polygon elements, and each polygon element comprises a plurality of sides; the sequence information comprises side information of each side and a connection order between the plurality of sides, and the side information comprises a direction and a length of the side; and processing the sequence information by using a machine learning model to obtain a processing result corresponding to the circuit layout.

[0008] In a possible implementation, the circuit layout (for example, data in the form of a picture or other information) can be converted into sequence information, which can be represented by data in a text format. The original circuit layout is represented by multi-dimensional information (for example, an image), and the sequence information can be one-dimensional information.

[0009] In the circuit layout, one or more polygon elements can be included. In order to describe the geometry of the polygon elements in the circuit layout, the layout of the polygon elements, and other polygon-level information, the polygon elements in the circuit layout need to be encoded to obtain the sequence information of the circuit layout. The sequence information of the circuit layout can exemplarily include geometry information and position information of the polygon elements, or one of the geometry information and the position information. The geometry information can include side information of each side of the polygon elements and a connection order between the plurality of sides. The position information can include a position of the polygon elements in the circuit layout.

[0010] According to the above rules, the circuit layout can be losslessly compressed into a symbol sequence, and the circuit layout can also be losslessly recovered from the sequence.

[0011] In the above manner, the geometry of the circuit layout and the layout of the circuit layout, and other polygon-level information can be explicitly modeled, the layout design rules can be more easily learned, and the integrated circuit layout can be efficiently and losslessly compressed into a symbol sequence (sequence information), so that the machine learning model can extract more accurate features.

[0012] In a possible implementation, the plurality of sides comprises a first side, and the direction of the first side is one of the following directions: an up-down direction, a left-right direction, a direction from top to bottom, a direction from bottom to top, a direction from left to right, or a direction from right to left. The direction is defined in a local coordinate system of the circuit layout.

[0013] In a possible implementation, the direction of the first side is indicated by an identifier.

[0014] In a possible implementation, the side information of the plurality of sides is arranged in a target order in the sequence information, and the connection order between the plurality of sides is indicated by the target order.

[0015] It should be understood that when determining the local coordinate system of a circuit layout, the direction of the reference axis of the coordinate system can be set so that most edges in that coordinate system are in the left-right or up-down direction, which can greatly reduce the difficulty of coding. In addition, the direction of the edges can also be represented in other ways, such as the angle between the edge and the reference axis, etc., which are not limited here.

[0016] In the coordinate system defined by the circuit layout, some edges can be inclined (that is, neither in the left-right direction nor the up-down direction, and the angle between them and the x-axis is an acute angle). For such edges (taking the edge with the above characteristics as the second edge as an example), any inclined edge can be represented as the hypotenuse of a right triangle and is represented by the right side.

[0017] In one possible implementation, the multiple sides include a second side, which is the hypotenuse of a triangle with the third and fourth sides as right angles. The third and fourth sides are not polygonal elements. The edge information of the second side is represented by the edge information of the third and fourth sides. The directions of the third and fourth sides are either up / down or left / right. The directions of the third and fourth sides are defined in the local coordinate system of the circuit layout.

[0018] In one possible implementation, the sequence information may include the position of a feature point on the polygonal element on the circuit layout; that is, the position of the polygonal element on the circuit layout can be represented by the position of a point on the polygonal element. For example, it may include the coordinates of the position of a point on the polygonal element on the circuit layout.

[0019] In one possible implementation, the sequence information may include the position of one or more edges on a polygonal element on the circuit layout.

[0020] For example, the position information of a point on a polygonal element can be used as a reference for the overall position. Combined with the position information of each side (such as the length, direction, and connection relationship of the side), the position of the polygonal element in the circuit layout can be characterized.

[0021] For example, the position information of one edge of a polygonal element can serve as a reference for the overall position. By combining the position information of each edge (e.g., represented by edge length, direction, connection relationship, etc.), the position of the polygonal element in the circuit layout can be characterized. Alternatively, the position information of each edge can be combined with the length, direction, and other information of each edge to characterize the position of the polygonal element in the circuit layout.

[0022] In addition, the positions of each polygonal element in the circuit layout can be described in other ways, such as using the center point of the polygon to represent the position of the polygonal element in the circuit layout, which is not limited here.

[0023] In a possible implementation, the circuit layout includes a plurality of polygon elements, the sequence information includes polygon information of each of the polygon elements, the polygon information includes side information of each side of the polygon element and a connection order between a plurality of sides included in the polygon element, and an arrangement order of the polygon information in the sequence information is related to a positional relationship of the plurality of polygon elements in the circuit layout.

[0024] In the circuit layout, a plurality of polygon elements can be included, and each polygon information in the sequence information of the circuit layout can be arranged according to a certain rule. For example, a polygon element with a larger y value in a priority position, or a polygon element with a larger x value in the case of the same y value, is given priority.

[0025] The polygon element is a polygon with an internal hollow region, the plurality of sides are outer sides of the polygon element, the polygon element further includes a plurality of inner sides, the inner sides are outer edges of the internal hollow region, the outer sides are outer edges of the polygon element, and the sequence information further includes information indicating the plurality of inner sides.

[0026] In a possible implementation, the machine learning model is used to implement an optical proximity effect correction task, the plurality of sides of the polygon element further include breakpoints, the plurality of sides of the polygon element include at least one adjustment segment, and the sequence information includes a position of the at least one adjustment segment. For example, the adjustment segment can be understood as a segment whose position can be moved, and the segment can be part of a side of the polygon. The position of the adjustment segment can be represented by the positions of two end points (or can be referred to as breakpoints). That is, the sequence information can include the positions of a plurality of breakpoints. Further, the processing result corresponding to the circuit layout is obtained by processing the sequence information by using the machine learning model, including: predicting a position offset of the at least one adjustment segment by processing the sequence information by using the machine learning model.

[0027] In a possible implementation, the sequence information further includes an initial feature representation (or can be referred to as a learnable semantic vector) corresponding to each of the adjustment segments. The position offset of the at least one adjustment segment is predicted by processing the sequence information by using the machine learning model, including: obtaining a target feature representation of the sequence information by performing feature extraction on the sequence information by using a feature extraction network in the machine learning model; and predicting the position offset of the at least one adjustment segment by using a prediction network in the machine learning model according to the target feature representation.

[0028] The above-mentioned serialized OPC learning method can learn the OPC process through training data, and finally realize the prediction of the corrected layout shape. In this way, a learnable semantic vector is introduced for each edge at the breakpoint, and the offset of the edge is predicted by modeling the Polygon-level information. Compared with the existing OPC based on images, the operation is faster, the prediction accuracy is higher, and post-processing is not required.

[0029] It should be understood that the positions of the adjustment segments can be specified by a user or obtained by recognizing the circuit layout. The recognition method can be based on experience or a numerical method such as a neural network, which is not limited here.

[0030] In a possible implementation, the machine learning model is used to implement a circuit layout generation task; the plurality of edges are partial edges on a polygon element; and the machine learning model is used to process the sequence information to obtain a processing result corresponding to the circuit layout, including: the machine learning model is used to process the sequence information to obtain edge information of another partial edge on the polygon element.

[0031] Without any post-processing, the serialized layout generation method is obviously better than the existing method with a large amount of post-processing in terms of generation quality and diversity performance. The generation quality, diversity, and other indicators of the circuit layout of the present application exceed those of other SOTA methods, and a large amount of post-processing is not required.

[0032] In a possible implementation, the machine learning model is used to implement a hot spot detection task or a yield detection task of the circuit layout.

[0033] In a second aspect, the present application provides a data processing method, including:

[0034] An image of the circuit layout is obtained, and the image content of the image includes a polygon element;

[0035] Sequence information of the circuit layout is generated according to the image; the polygon element includes a plurality of edges; the sequence information includes edge information of each edge and a connection order between the plurality of edges; and the edge information includes a direction and a length of the edge.

[0036] In a possible implementation, the plurality of edges include a first edge, and the direction of the first edge is one of the following directions: an up-down direction, a left-right direction, a direction from top to bottom, a direction from bottom to top, a direction from left to right, or a direction from right to left, which is defined in a local coordinate system of the circuit layout.

[0037] In a possible implementation, the direction of the first edge is indicated by a mark.

[0038] In a possible implementation, the edge information of the plurality of edges is arranged in the sequence information in a target order, and the connection order between the plurality of edges is indicated by the target order.

[0039] In a possible implementation, the plurality of edges includes a second edge, the second edge being a diagonal of a triangle with a third edge and a fourth edge as right-angle edges, the third edge and the fourth edge not belonging to the polygon element, the edge information of the second edge being represented by the edge information of the third edge and the fourth edge, the directions of the third edge and the fourth edge being up-down direction or left-right direction, and the directions of the third edge and the fourth edge being directions defined in a local coordinate system of the circuit layout.

[0040] In a possible implementation, the circuit layout includes a plurality of polygon elements, the sequence information includes polygon information of each of the polygon elements, the polygon information including edge information of each edge in the polygon element and a connection order between a plurality of edges included in the polygon element, and an arrangement order of the polygon information in the sequence information is related to a positional relationship of the plurality of polygon elements in the circuit layout.

[0041] In a possible implementation, the sequence information further includes a position of the polygon element in the circuit layout.

[0042] In a possible implementation, the position is represented by a position coordinate of a point on the polygon element in the circuit layout.

[0043] In a possible implementation, the polygon element is a polygon with an internal hollow region, the plurality of edges are outer edges of the polygon element, the polygon element further includes a plurality of inner edges, the inner edges are outer edges of the internal hollow region, the outer edges are outer edges of the polygon element, and the sequence information further includes information indicating the plurality of inner edges.

[0044] In a third aspect, a data processing apparatus is provided, and the apparatus includes:

[0045] The obtaining module is configured to obtain sequence information of a circuit layout, where the circuit layout includes a polygon element, the polygon element includes a plurality of edges, the sequence information includes edge information of each edge and a connection order between the plurality of edges, and the edge information includes a direction and a length of the edge.

[0046] The processing module is configured to process the sequence information by using a machine learning model, to obtain a processing result corresponding to the circuit layout.

[0047] In a possible implementation, the plurality of edges includes a first edge, the direction of the first edge is one of the following directions: up-down direction, left-right direction, direction from top to bottom, direction from bottom to top, direction from left to right, or direction from right to left, and the direction is a direction defined in a local coordinate system of the circuit layout.

[0048] In a possible implementation, the direction of the first side is indicated by the flag.

[0049] In a possible implementation, the side information of the plurality of sides is arranged in the sequence information in a target order, and the connection order between the plurality of sides is indicated by the target order.

[0050] In a possible implementation, the plurality of sides includes a second side, the second side is a diagonal side in a triangle with a third side and a fourth side as right-angle sides, the third side and the fourth side do not belong to the polygon element, the side information of the second side is represented by the side information of the third side and the fourth side, the direction of the third side and the direction of the fourth side are up-down direction or left-right direction, and the direction of the third side and the direction of the fourth side are directions defined in a local coordinate system of the circuit layout.

[0051] In a possible implementation, the sequence information further includes a position of the polygon element in the circuit layout.

[0052] In a possible implementation, the position is represented by a position coordinate of a point on the polygon element in the circuit layout.

[0053] In a possible implementation, the circuit layout includes a plurality of polygon elements, the sequence information includes polygon information of each of the polygon elements, the polygon information includes side information of each side in the polygon element and a connection order between a plurality of sides included in the polygon element, and an arrangement order of the polygon information in the sequence information is related to a positional relationship of the plurality of polygon elements in the circuit layout.

[0054] In a possible implementation, the polygon element is a polygon with an internal hollow region, the plurality of sides are outer sides of the polygon element, the polygon element further includes a plurality of inner sides, the inner sides are outer edges of the internal hollow region, the outer sides are outer edges of the polygon element, and the sequence information further includes information indicating the plurality of inner sides.

[0055] In a possible implementation, the machine learning model is used to implement an optical proximity correction task, the plurality of sides of the polygon element include at least one adjustment segment, and the sequence information includes a position of the at least one adjustment segment.

[0056] The processing module is specifically configured to:

[0057] The sequence information is processed by the machine learning model to predict a position offset of the at least one adjustment segment.

[0058] In a possible implementation, the sequence information further includes an initial feature representation corresponding to each of the adjustment segments.

[0059] The processing module is specifically configured to:

[0060] The sequence information is subjected to feature extraction through a feature extraction network in the machine learning model, to obtain a target feature representation of the sequence information.

[0061] According to the target feature representation, a position offset of the at least one adjustment segment is predicted through a prediction network in the machine learning model.

[0062] In a possible implementation, the machine learning model is used to implement a circuit layout generation task; and the multiple edges are partial edges on the polygon element.

[0063] The processing module is specifically configured to:

[0064] The sequence information is subjected to processing through a machine learning model, to obtain edge information of another partial edge on the polygon element.

[0065] In a possible implementation, the machine learning model is used to implement a hot spot detection task or a yield detection task of a circuit layout.

[0066] In a fourth aspect, the present application provides a data processing apparatus, the apparatus comprising:

[0067] An acquisition module is configured to acquire an image of a circuit layout, image content of the image comprising a polygon element.

[0068] A generation module is configured to generate sequence information of the circuit layout according to the image; wherein the polygon element comprises multiple edges; the sequence information comprises edge information of each edge and a connection order between the multiple edges, and the edge information comprises a direction and a length of the edge.

[0069] In a possible implementation, the multiple edges comprise a first edge, and the direction of the first edge is one of the following directions: an up-down direction, a left-right direction, a direction from top to bottom, a direction from bottom to top, a direction from left to right, or a direction from right to left, the direction being defined in a local coordinate system of the circuit layout.

[0070] In a possible implementation, the direction of the first edge is indicated by an identifier.

[0071] In a possible implementation, the edge information of the multiple edges is arranged in a target order in the sequence information, and the connection order between the multiple edges is indicated by the target order.

[0072] In a possible implementation, the plurality of sides includes a second side, the second side being a hypotenuse in a triangle with a third side and a fourth side as the right-angled sides, the third side and the fourth side not belonging to the polygon element, the side information of the second side being represented by the side information of the third side and the fourth side, the directions of the third side and the fourth side being the up-down direction or the left-right direction, and the directions of the third side and the fourth side being directions defined in a local coordinate system of the circuit layout.

[0073] In a possible implementation, the sequence information further includes a position of the polygon element in the circuit layout.

[0074] In a possible implementation, the position is represented by position coordinates of a point on the polygon element in the circuit layout.

[0075] In a possible implementation, the circuit layout includes a plurality of polygon elements, the sequence information includes polygon information of each of the polygon elements, the polygon information includes side information of each side in the polygon element and a connection sequence between a plurality of sides included in the polygon element, and an arrangement sequence of the polygon information in the sequence information is related to a positional relationship of the plurality of polygon elements in the circuit layout.

[0076] In a possible implementation, the polygon element is a polygon with an internal hollow region, the plurality of sides are outer sides of the polygon element, the polygon element further includes a plurality of inner sides, the inner sides are outer edges of the internal hollow region, the outer sides are outer edges of the polygon element, and the sequence information further includes information indicating the plurality of inner sides.

[0077] In a fifth aspect, an embodiment of the present application provides a semiconductor design device, which can include a memory, a processor, and a bus system, wherein the memory is configured to store a program, and the processor is configured to execute the program in the memory to perform the method in the first aspect and any optional method in the first aspect, and the method in the second aspect and any optional method in the second aspect.

[0078] In a sixth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, and when the computer program is run on a computer, the computer program causes the computer to perform the method in the first aspect and any optional method in the first aspect, and the method in the second aspect and any optional method in the second aspect.

[0079] In a seventh aspect, an embodiment of the present application provides a computer program, and when the computer program is run on a computer, the computer program causes the computer to perform the method in the first aspect and any optional method in the first aspect, and the method in the second aspect and any optional method in the second aspect.

[0080] Eighthly, this application provides a chip system including a processor for supporting the execution of functions related to the foregoing aspects by a semiconductor design device, such as transmitting or processing data or information involved in the foregoing methods. In one possible design, the chip system further includes a memory for storing program instructions and data necessary for the execution or training device. This chip system may be composed of chips or may include chips and other discrete devices. Attached Figure Description

[0081] Figure 1 and Figure 2 This is a schematic diagram of the application system framework of the present invention;

[0082] Figure 3 This is a schematic diagram of an optional hardware structure for a terminal.

[0083] Figure 4 This is a schematic diagram of the structure of a server;

[0084] Figure 5 This is a schematic diagram of a system architecture according to this application;

[0085] Figure 6 A process for providing a cloud service;

[0086] Figure 7 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0087] Figures 8 to 11 A schematic circuit layout provided for an embodiment of this application;

[0088] Figures 12 to 15 This is a flowchart illustrating a data processing method.

[0089] Figure 16 and Figure 17 A schematic diagram of the structure of a data processing apparatus provided in an embodiment of this application;

[0090] Figure 18 A schematic diagram of the structure of the execution device provided in the embodiments of this application;

[0091] Figure 19 A schematic diagram of the structure of the training device provided in the embodiments of this application;

[0092] Figure 20 This is a schematic diagram of a chip structure provided in an embodiment of this application. Detailed Implementation

[0093] The embodiments of the present application will be described below in conjunction with the accompanying drawings. The terms used in the embodiments of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0094] The terms "first", "second", and the like used in the description and the claims of the present application and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, and this is only a way of distinguishing the objects of the same attribute used in the description of the embodiments of the present application. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, so that a process, method, system, product or apparatus including a series of units does not necessarily limit those units, but can include other units not clearly listed or inherent to the process, method, product or apparatus.

[0095] The terms "substantially", "about" and the like used herein are used as approximate terms, not as degree terms, and are intended to take into account the inherent deviations of measured or calculated values known by those skilled in the art. In addition, the use of "may" in describing the embodiments of the present application means "one or more embodiments". The terms "use", "using", and "used" used herein can be considered as synonymous with the terms "utilize", "utilizing", and "utilized", respectively. In addition, the term "exemplary" is intended to refer to an example or an illustration.

[0096] First, the application scenario of the present application is introduced, the present application can be applied in semiconductor design application program or cloud service provided by cloud side server, etc., which is not limited to the following introduction:

[0097] I. Semiconductor design application program

[0098] The product form of the embodiment of the present application can be a semiconductor design application program. The semiconductor design application program can run on a terminal device or a server on the cloud side.

[0099] In one possible implementation, the semiconductor design application program can implement optical proximity correction (OPC), integrated circuit layout generation, layout hotspot detection and yield detection, circuit layout sequence information generation, circuit layout sequence information generation, etc. The semiconductor design application program can respond to the input information of the circuit layout, and implement the above tasks based on the input information.

[0100] In a possible implementation, a user can open a semiconductor design application installed on a terminal device, and input information of a circuit layout. The semiconductor design application can process the information of the circuit layout by using the method provided in the embodiments of the present application, and present the processing result to the user.

[0101] 1. Optical proximity correction

[0102] Optical proximity correction is a lithography enhancement technique, usually used to compensate for image errors due to diffraction or process effects. The need for OPC is mainly seen in the manufacture of semiconductor devices, as the limitations of light to maintain the integrity of the edge placement of the original design, after processing, into an etch image on a silicon wafer. These projected images appear irregular, such as line width narrower or wider than designed, which can be compensated by changing the pattern on the mask used for imaging. Other deformations, such as rounding, are driven by the resolution of the optical imaging tool, and are difficult to compensate. If not corrected, such deformations can greatly change the electrical properties of the material being manufactured.

[0103] Optical proximity correction is to adjust the mask shape to reduce the impact of light diffraction, so that the shape of the lithography is close to the shape of the chip design. The existing Rule-base and Model-base adjustment method mainly relies on optical simulation to adjust step by step. In actual production process, such adjustment will reach 10 to 20 times, and the optical simulation calculation cost is very large, and the whole process will last for several months. Therefore, the optical proximity correction process can be understood as an end-to-end process, the input is the layout of the integrated circuit design, and the output is the shape of the corrected layout. Therefore, the whole process can be learned through deep learning. Finally, the trained deep network is directly predicted to reduce the number of iterations and even give the final result, which greatly improves the efficiency of OPC.

[0104] When the semiconductor design application performs OPC, the information of the input circuit layout can be obtained, and the information of the corrected circuit layout can be obtained.

[0105] 2. Integrated circuit layout generation

[0106] The integrated circuit layout is a planar geometric shape description of the physical situation of the real integrated circuit. The integrated circuit layout is the result of the bottom step physical design in the integrated circuit design. The physical design converts the netlist of the gate level, which is the result of logic synthesis, into a physical layout file through layout and wiring technology. This file contains the shape, area and position information of each hardware unit on the chip.

[0107] Due to the complexity of the design and manufacturing process, it is both expensive and time-consuming to obtain sufficient integrated circuit layout. Especially in the evolution of the manufacturing process, the change of parameters and design rules requires the redesign of the integrated circuit layout. Therefore, AI methods are applied to the field of semiconductor design and manufacturing, using integrated circuit layout as training data. Generating layout based on generative model can meet the needs of semiconductor design and manufacturing.

[0108] The semiconductor design application program can obtain the information of the input circuit layout when performing the task of integrated circuit layout generation, and obtain the information of the corrected circuit layout.

[0109] 3, Layout hotspot detection

[0110] As the gap between modern integrated circuit feature size and lithography wavelength increases, it is essential to ensure the printability of circuit layout design. However, there are some layout patterns sensitive to lithography process, and will produce undesirable printing. These layout patterns are called layout hotspots, which need to be detected in the physical verification stage.

[0111] The semiconductor design application program can obtain the information of the input circuit layout when performing the task of layout hotspot detection, and obtain the detection result of the layout hotspot.

[0112] 4, Yield detection

[0113] With the development of electronic product functions and the expansion of application fields, as the core component of electronic products, circuit layout has become an indispensable part of people's lives. Circuit layout production is mainly divided into layout design and manufacturing. Layout design usually contains multi-layer circuit function design, and manufacturing includes production, packaging, testing and other processes. When the same circuit layout design uses different manufacturing processes, some circuit structures in the circuit layout design may have defects under the original process, resulting in lower-than-expected circuit layout yield. Such design defects due to process changes are called systematic defects.

[0114] The existence of systematic defects will increase the probability of circuit function failure of the circuit layout, and the circuit layout with circuit function failure will not be able to be used normally, thus leading to a decrease in the yield of the circuit layout. The decline in yield will increase production costs, and even cause related products to miss the sales window period. Therefore, the root cause identification of systematic defects is crucial to the yield of the product. In order to identify systematic defects, the design structure of the circuit layout can be analyzed to determine the type of local segment on the circuit layout that causes potential circuit layout failure.

[0115] The semiconductor design application program can obtain the information of the input circuit layout when performing the task of layout yield detection, and obtain the yield detection result.

[0116] 5. Generation of sequence information for circuit layout

[0117] In semiconductor design tasks (such as tasks 1-4 above), machine learning models are typically used to process circuit layout information, which is presented as pixel images. However, circuit layouts differ from natural images; they are composed of regular polygons whose size and arrangement must conform to design rules. Therefore, pixel-level image modeling methods cannot adequately capture polygon-level information such as geometry and layout. This results in the generation of numerous irregular patterns, requiring extensive post-processing.

[0118] In this embodiment, pixel images can be converted into sequence information of circuit layout. This sequence information can explicitly model polygon-level information such as geometry and layout, making it easier to learn layout design rules. Moreover, it can efficiently and losslessly compress integrated circuit layout into symbol sequences, which is more suitable for machine learning models (such as serialization models like transformers) to extract features and improve the execution accuracy of subsequent semiconductor design tasks.

[0119] When semiconductor design applications perform the task of generating sequence information for circuit layouts, they can obtain an image of the input circuit layout and get the sequence information of the circuit layout.

[0120] In one possible implementation, a user can open a semiconductor design application installed on a terminal device and input circuit layout information. The semiconductor design application can then send the circuit layout information to a cloud-based server. The cloud-based server processes the circuit layout information using the method provided in this application embodiment and sends the processing result back to the terminal device. The terminal device can then present the processing result to the user.

[0121] The following sections will introduce the semiconductor design application in this application from the perspectives of functional architecture and product architecture that implements the functions.

[0122] Reference Figure 1 , Figure 1 This is a schematic diagram of the functional architecture of the semiconductor design application in the embodiments of this application:

[0123] In one possible implementation, such as Figure 1As shown, the semiconductor design application 102 can receive input parameters 101 (e.g., information of a circuit layout) and generate a processing result 103 of the information of the circuit layout. The semiconductor design application 102 can be executed on, for example, at least one computer system, and include computer code that, when executed by one or more computers, causes the computers to perform the methods described herein.

[0124] Referring to Figure 2 , Figure 2 An entity architecture for running a semiconductor design application in embodiments of the present application is shown:

[0125] Referring to Figure 2 , Figure 2 A system architecture is shown. The system can include a terminal 100 and a server 200. The server 200 can include one or more servers (as an example, one server is shown in the figure), and the server 200 can provide one or more terminals with semiconductor design services. Figure 2 The terminal 100 can have a semiconductor design application installed thereon or open a webpage related to semiconductor design. The application and the webpage can provide a semiconductor design interface, and the terminal 100 can receive parameters input by a user on the semiconductor design interface and send the parameters to the server 200. The server 200 can obtain a processing result based on the received parameters and return the processing result to the terminal 100.

[0126] It should be understood that in some optional implementations, the terminal 100 can also complete the action of obtaining a data processing result based on received parameters by itself without the cooperation of the server, and embodiments of the present application do not limit this.

[0127] Next, the product form of the terminal 100 is described.

[0128] Figure 2 The terminal 100 in embodiments of the present application can be a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device, an augmented reality (AR) / virtual reality (VR) device, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), etc., and embodiments of the present application do not limit this.

[0129]

[0130] Figure 3 ​​An optional hardware structure diagram of the terminal 100 is shown.

[0131] Reference Figure 3 As shown, the terminal 100 can include a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, a camera 150 (optional), an audio circuit 160 (optional), a speaker 161 (optional), a microphone 162 (optional), a processor 170, an external interface 180, a power supply 190, and the like. Those skilled in the art can understand that the terminal 100 can include more or less components than those shown, or combine some components, or different components. Figure 3 The terminal or multi-functional device is merely an example and does not constitute a limitation on the terminal or multi-functional device, which can include more or less components than those shown, or combine some components, or different components.

[0132] The input unit 130 can be used to receive inputted digital or character information, and generate key signal input related to user settings and function control of the portable multi-functional device. Specifically, the input unit 130 can include a touch screen 131 (optional) and / or other input devices 132. The touch screen 131 can collect user touch operations (such as user operations on or near the touch screen using fingers, joints, stylus, or any suitable object) and drive corresponding connected devices according to pre-set programs. The touch screen can detect user touch actions on the touch screen, convert the touch actions into touch signals and send them to the processor 170, and can receive commands from the processor 170 and execute them; the touch signals at least include touch point coordinate information. The touch screen 131 can provide an input interface and an output interface between the terminal 100 and the user. In addition, the touch screen can be implemented in various types such as resistive, capacitive, infrared, and surface acoustic wave. In addition to the touch screen 131, the input unit 130 can also include other input devices. Specifically, the other input devices 132 can include one or more of a physical keyboard, function keys (such as volume control buttons, on-off buttons, etc.), trackballs, mice, joysticks, etc.

[0133] Among them, the input device 132 can receive inputted circuit diagram information, etc.

[0134] The display unit 140 can be used to display information input by the user or information provided to the user, various menus of the terminal 100, interactive interfaces, file display, and / or playing of any kind of multimedia files. In the embodiments of the present application, the display unit 140 can be used to display the interface of the semiconductor design application program, the processing result, etc.

[0135] The memory 120 can be used to store instructions and data. The memory 120 can mainly include a storage instruction area and a storage data area. The storage data area can store various data such as multimedia files, texts, etc. The storage instruction area can store software units such as operating systems, applications, instructions required by at least one function, etc. or their subsets, extended sets. Non-volatile random access memory can also be included. The processor 170 is provided with software and applications that include management of hardware, software and data resources in the computing processing device, support control. It is also used for the storage of multimedia files, and the storage of running programs and applications.

[0136] The processor 170 is the control center of the terminal 100, which connects each part of the entire terminal 100 through various interfaces and lines, executes various functions of the terminal 100 and processes data by running or executing instructions stored in the memory 120 and calling data stored in the memory 120, thereby performing overall control of the terminal device. Optionally, the processor 170 can include one or more processing units. Preferably, the processor 170 can integrate an application processor and a modem processor, wherein the application processor mainly processes operating systems, user interfaces and application programs, etc., and the modem processor mainly processes wireless communication. It can be understood that the above-mentioned modem processor can also not be integrated into the processor 170. In some embodiments, the processor, the memory, can be implemented on a single chip, and in some embodiments, they can also be implemented on separate chips respectively. The processor 170 can also be used to generate corresponding operation control signals to the corresponding components of the computing processing device, read and process data in the software, especially read and process data and programs in the memory 120, so that each functional module therein performs corresponding functions, thereby controlling the corresponding components to act according to the requirements of the instructions.

[0137] The memory 120 can be used to store instructions and data. The memory 120 can mainly include a storage instruction area and a storage data area. The storage data area can store various data such as multimedia files, texts, etc. The storage instruction area can store software units such as operating systems, applications, instructions required by at least one function, etc. or their subsets, extended sets. Non-volatile random access memory can also be included. The processor 170 is provided with software and applications that include management of hardware, software and data resources in the computing processing device, support control. It is also used for the storage of multimedia files, and the storage of running programs and applications.

[0138] The RF unit 110 (optional) can be used for transmitting and receiving signals in information or communication processes, for example, receiving downlink information from a base station and sending uplink data to the base station. Generally, the RF circuit includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier (LNA), a duplexer, etc. In addition, the RF unit 110 can also communicate with network devices and other devices through wireless communication. The wireless communication can use any communication standard or protocol, including but not limited to Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), email, Short Messaging Service (SMS), etc.

[0139] In the embodiments of the present application, the RF unit 110 can send the parameters of the chip to the server 200 and receive the processing results sent by the server 200.

[0140] It should be understood that the RF unit 110 is optional, which can be replaced by other communication interfaces, for example, a network interface.

[0141] The terminal 100 also includes a power supply 190 (such as a battery) for supplying power to each component. Preferably, the power supply can be logically connected to the processor 170 through a power management system, so as to realize the functions of power management, such as charge management, discharge management and power consumption management, through the power management system.

[0142] The terminal 100 also includes an external interface 180, which can be a standard Micro USB interface or a multi-pin connector, and can be used for connecting the terminal 100 with other devices for communication, or for connecting a charger to charge the terminal 100.

[0143] Although not shown, the terminal 100 can also include a flash, a wireless fidelity (WiFi) module, a Bluetooth module, different function sensors, etc., which will not be described here. Some or all of the methods described below can be applied in the terminal 100 as shown. Figure 3 ​

[0144] Next, the product form of the server 200 is described. Figure 2

[0145] Figure 4 A structural diagram of the server 200 is provided, as shown in the figure. Figure 4 The server 200 includes a bus 201, a processor 202, a communication interface 203, and a memory 204. The processor 202, the memory 204, and the communication interface 203 communicate through the bus 201.

[0146] The bus 201 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 In the figure, only one thick line is used, but it does not mean that there is only one bus or one type of bus.

[0147] The processor 202 can be any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP), etc.

[0148] The memory 204 can include a volatile memory, such as a random access memory (RAM). The memory 204 can also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid state drive (SSD).

[0149] The memory 204 can be used to store software codes related to the method, and the processor 202 can execute the steps of the method of the chip, or can schedule other units to realize the corresponding functions.

[0150] ​It should be understood that the terminal 100 and the server 200 described above can be centralized or distributed devices, and the processors (for example, the processor 170 and the processor 202) in the terminal 100 and the server 200 can be hardware circuits (for example, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a general-purpose processor, a digital signal processing (DSP), a microprocessor, a microcontroller, or the like) or a combination of the hardware circuits. For example, the processor can be a hardware system with an instruction execution function, such as a CPU, a DSP, or the like, or a hardware system without an instruction execution function, such as an ASIC, an FPGA, or the like, or a combination of the hardware system without an instruction execution function and the hardware system with an instruction execution function.

[0151] It should be understood that the data processing method in the embodiments of the present application involves AI-related operations. The following will be described in combination with Figure 5 The system architecture provided in the embodiments of the present application will be described in detail.

[0152] Figure 5 The system architecture provided in the embodiments of the present application will be described in detail. Figure 5 As shown in the system architecture 500, the system architecture 500 includes an execution device 510, a training device 520, a database 530, a client device 540, a data storage system 550, and a data collection device 560.

[0153] The execution device 510 includes a computing module 511, an I / O interface 512, a preprocessing module 513, and a preprocessing module 514. The target model / rule 501 can be included in the computing module 511, and the preprocessing module 513 and the preprocessing module 514 are optional.

[0154] The data collection device 560 is configured to collect training samples. The training samples can include information of a circuit layout, and the like. After the training samples are collected, the data collection device 560 stores the training samples in the database 530.

[0155] The training device 520 can obtain the target model / rule 501 by training a neural network (for example, a machine learning model in the embodiments of the present application, or the like) based on the training samples maintained in the database 530.

[0156] It should be noted that in practical applications, the training samples maintained in database 530 may not all come from the data acquisition device 560; they may also be received from other devices. Furthermore, it should be noted that training device 520 may not necessarily train the target model / rule 501 entirely based on the training samples maintained in database 530; it may also obtain training samples from the cloud or other sources for model training. The above description should not be construed as limiting the embodiments of this application.

[0157] The target model / rule 501 trained using training device 520 can be applied to different systems or devices, such as... Figure 5 The execution device 510 shown can be a terminal, such as a mobile phone terminal, tablet computer, laptop computer, augmented reality (AR) / virtual reality (VR) device, vehicle terminal, etc., or it can be a server, etc.

[0158] Specifically, the training device 520 can transfer the trained model to the execution device 510.

[0159] exist Figure 5 In the execution device 510, an input / output (I / O) interface 512 is configured for data interaction with external devices. Users can input data (such as circuit layout information in the embodiments of this application) into the I / O interface 512 through the client device 540.

[0160] Preprocessing modules 513 and 514 are used to preprocess the input data received from the I / O interface 512. It should be understood that preprocessing modules 513 and 514 may be absent, or only one preprocessing module may be used. When preprocessing modules 513 and 514 are absent, the calculation module 511 can be used directly to process the input data.

[0161] During the preprocessing of input data by the execution device 510, or the calculation module 511 of the execution device 510 performing calculations and other related processes, the execution device 510 can call data, code, etc. in the data storage system 550 for corresponding processing, or store the data, instructions, etc. obtained from the corresponding processing into the data storage system 550.

[0162] Finally, the I / O interface 512 provides the processing result to the client device 540, thereby providing it to the user.

[0163] exist Figure 5In the case shown, the user can manually give input data, which can be operated through the interface provided by the I / O interface 512. In another case, the client device 540 can automatically send input data to the I / O interface 512, and if the user's authorization is required to enable the client device 540 to automatically send input data, the user can set the corresponding permission in the client device 540. The user can view the results output by the execution device 510 in the client device 540, and the specific presentation form can be a specific way such as display, sound, action, etc. The client device 540 can also serve as a data acquisition end to collect the input data input into the I / O interface 512 and the output results output from the I / O interface 512 as new sample data and store them into the database 530. Of course, the collection can also be performed without the client device 540, and the I / O interface 512 can directly store the input data input into the I / O interface 512 and the output results output from the I / O interface 512 as new sample data into the database 530.

[0164] It is worth noting that, Figure 5 The system architecture provided in the embodiments of the present application is only a schematic diagram, and the positional relationship between the devices, components, modules, etc. shown in the diagram does not constitute any limitation. For example, in the case shown in FIG. 5, the data storage system 550 is an external memory relative to the execution device 510, and in other cases, the data storage system 550 can also be placed in the execution device 510. It should be understood that the execution device 510 described above can be deployed in the client device 540. Figure 5

[0165] From the inference side of the model:

[0166] In the embodiments of the present application, the computing module 511 of the execution device 510 can obtain the code stored in the data storage system 550 to implement the data processing method in the embodiments of the present application.

[0167] ​In the embodiments of the present application, the computing module 511 of the execution device 510 can include a hardware circuit (such as an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a general-purpose processor, a digital signal processor (DSP), a microprocessor or a microcontroller, etc.), or a combination of these hardware circuits. For example, the training device 520 can be a hardware system with an execution instruction function, such as a CPU, a DSP, etc., or a hardware system without an execution instruction function, such as an ASIC, an FPGA, etc., or a combination of the hardware system without an execution instruction function and the hardware system with an execution instruction function.

[0168] Specifically, the computing module 511 of the execution device 510 can be a hardware system with an execution instruction function. The connection relationship prediction method provided in the embodiments of the present application can be a software code stored in a memory. The computing module 511 of the execution device 510 can obtain the software code from the memory and execute the obtained software code to implement the data processing method provided in the embodiments of the present application.

[0169] It should be understood that the computing module 511 of the execution device 510 can be a combination of a hardware system without an execution instruction function and a hardware system with an execution instruction function. Part of the steps of the data processing method provided in the embodiments of the present application can also be implemented by the hardware system without an execution instruction function in the computing module 511 of the execution device 510, which is not limited here.

[0170] From the training side of the model:

[0171] In the embodiments of the present application, the training device 520 can obtain the code stored in the memory (not shown in the figure) to implement the steps related to model training in the embodiments of the present application. Figure 5

[0172] ​In an embodiment of the present application, the training device 520 can include a hardware circuit (such as an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a general processor, a digital signal processor (DSP), a microprocessor or a microcontroller, etc.), or a combination of these hardware circuits. For example, the training device 520 can be a hardware system with an instruction execution function, such as a CPU, a DSP, etc., or a hardware system without an instruction execution function, such as an ASIC, an FPGA, etc., or a combination of the hardware system without an instruction execution function and the hardware system with an instruction execution function.

[0173] It should be understood that the training device 520 can be a combination of a hardware system without an instruction execution function and a hardware system with an instruction execution function. The part of the steps related to the neutral model training provided in the embodiment of the present application can also be implemented by the hardware system without an instruction execution function in the training device 520, which is not limited here.

[0174] II. Semiconductor design cloud service provided by the server

[0175] In a possible implementation, the server can provide the terminal with a semiconductor design service through an application programming interface (API).

[0176] In this case, the terminal device can send relevant parameters (such as information of a circuit layout) to the server through the API provided by the cloud, the server can obtain a processing result based on the received parameters, and return the processing result (such as a processing result of information of a circuit layout, etc.) to the terminal.

[0177] In this case, the terminal device can send relevant parameters (such as an image of a circuit layout) to the server through the API provided by the cloud, the server can obtain a processing result based on the received parameters, and return the processing result (such as sequence information of a circuit layout, etc.) to the terminal.

[0178] The description of the terminal and the server can be described in the above embodiment, which is not described here.

[0179] For example, Figure 6 The process of using a semiconductor design cloud service provided by a cloud platform is shown.

[0180] 1. Open and purchase a content review service.

[0181] 2. The user can download the software development kit (SDK) corresponding to the content review service. The cloud platform usually provides multiple development versions of the SDK for the user to select according to the needs of the development environment, such as a JAVA version of the SDK, a python version of the SDK, a PHP version of the SDK, an Android version of the SDK, and the like.

[0182] 3. The user downloads the corresponding version of the SDK to the local according to the needs, imports the SDK project to the local development environment, configures and debugs in the local development environment, and can also develop other functions in the local development environment, so as to form an application that integrates the semiconductor design class capability.

[0183] 4. In the process of using the semiconductor design class application, when semiconductor design is needed, the API call of semiconductor design can be triggered. When the application triggers the semiconductor design function, an API request is initiated to the running instance of the semiconductor design class service in the cloud environment, wherein the API request carries the information of the circuit layout. The running instance in the cloud environment processes the information of the circuit layout and obtains a processing result.

[0184] 5. The cloud environment returns the processing result to the application, thereby completing a semiconductor design service call.

[0185] The description of the terminal and the server can refer to the description of the above embodiments, which will not be repeated here.

[0186] The embodiments of the present application relate to many related knowledge about semiconductor design and artificial intelligence. In order to better understand the scheme of the embodiments of the present application, the related terms and concepts that may be involved in the embodiments of the present application will be introduced first. It should be understood that the explanation of the related concepts may be limited due to the specific situation of the embodiments of the present application, but it does not mean that the present application can only be limited to this specific situation. In different embodiments, the specific situation may also be different, and the specific situation is not limited here.

[0187] (1) Circuit layout

[0188] is a planar geometric shape description of the physical situation of a real integrated circuit. The integrated circuit layout is the result of the bottom layer step physical design in the integrated circuit design. The physical design converts the netlist of the logic synthesis result-gate level into a physical layout file through layout and wiring technology. This file contains the shape, area and position information of each hardware unit on the chip.

[0189] (2) Neural network

[0190] The neural network can be composed of neural units, which can refer to an operation unit taking xs (i.e., input data) and intercept 1 as input, and the output of the operation unit can be:

[0191] ;

[0192] where s = 1, 2, … n, n is a natural number greater than 1, Ws is the weight of xs, b is the bias of the neural unit. f is the activation function of the neural unit, which is used to introduce non-linear characteristics into the neural network to convert the input signal in the neural unit into an output signal. The output signal of the activation function can be used as the input of the next convolutional layer, and the activation function can be a sigmoid function. The neural network is a network formed by connecting a plurality of the above single neural units, that is, the output of one neural unit can be the input of another neural unit. The input of each neural unit can be connected to the local receptive field of the previous layer to extract the features of the local receptive field, and the local receptive field can be a region composed of a plurality of neural units.

[0193] (3) Deep neural network

[0194] Deep neural network (DNN), also known as multi-layer neural network, can be understood as a neural network with many hidden layers, where "many" has no special measurement standard. From the division of DNN according to the position of different layers, the neural network inside the DNN can be divided into three categories: input layer, hidden layer, and output layer. Generally, the first layer is the input layer, and the last layer is the output layer, and the number of layers in between is the hidden layer. The layers are fully connected, that is, any neuron in the i-th layer is connected to any neuron in the i+1-th layer. Although DNN looks very complex, in terms of the work of each layer, it is actually not complex, which can be simply expressed as the following linear relationship expression: wherein, is the input vector, is the output vector, is the offset vector, is the weight matrix (also known as coefficient), is the activation function. Each layer only performs the following simple operation on the input vector to obtain the output vector . Since the number of layers of DNN is large, the number of coefficients and offset vectors is also large. These parameters in the DNN are defined as follows: taking the coefficient as an example: assuming that in a three-layer DNN, the linear coefficient of the fourth neuron in the second layer to the second neuron in the third layer is defined as The superscript 3 represents the layer number where the coefficient The subscript corresponds to the output third layer index 2 and the input second layer index 4. In summary, the coefficient from the kth neuron of the L−1th layer to the jth neuron of the Lth layer is defined as It is noted that the input layer is not parameterized. In deep neural networks, more hidden layers allow the network to better capture the complexity of real-world situations. In theory, the more parameters a model has, the higher its complexity, and the greater its "capacity" to perform more complex learning tasks. Training a deep neural network is essentially a process of learning the weight matrices, and the ultimate goal is to obtain the trained weight matrices of all layers of the deep neural network (the weight matrices formed by the vectors W of many layers).

[0195] (4) Loss function

[0196] In the process of training a deep neural network, because the output of the deep neural network is expected to be as close as possible to the value that is truly intended to be predicted, the weight vectors of each layer of the neural network can be updated according to the difference between the predicted value of the current network and the target value that is truly intended to be predicted (of course, before the first update, there is usually an initialization process, i.e., pre-configuring parameters for each layer of the deep neural network), for example, if the predicted value of the network is too high, the weight vector is adjusted to make it predict a lower value, and the adjustment is continuously made until the deep neural network can predict the target value that is truly intended to be predicted or a value very close to it. Therefore, it is necessary to define "how to compare the difference between the predicted value and the target value" in advance, which is the loss function or the objective function, which is an important equation for measuring the difference between the predicted value and the target value. Among them, taking the loss function as an example, the higher the output value (loss) of the loss function, the greater the difference, and then the training of the deep neural network becomes a process of trying to minimize this loss.

[0197] (5) Back propagation algorithm

[0198] The convolutional neural network can use the back propagation (BP) algorithm to correct the size of the parameters in the initial super-resolution model during the training process, so that the reconstruction error loss of the super-resolution model becomes smaller and smaller. Specifically, the forward propagation of the input signal until the output produces an error loss, and the error loss information is propagated backward to update the parameters in the initial super-resolution model, so as to make the error loss converge. The back propagation algorithm is a back propagation movement dominated by error loss, aiming to obtain the optimal parameters of the super-resolution model, such as the weight matrix.

[0199] (6)transformer

[0200] The neural network comprises an embedding layer and at least one transformer layer, the at least one transformer layer can be N transformer layers (N is an integer greater than 0), wherein each transformer layer comprises, in sequence, an attention layer, an add&norm layer, a feed forward layer and an add&norm layer. In the embedding layer, the current input is embedded to obtain a plurality of embedding vectors; in the attention layer, P input vectors are obtained from the previous layer of the first transformer layer, and a first input vector in the P input vectors is taken as a center, and based on the correlation between each input vector in a preset attention window range and the first input vector, an intermediate vector corresponding to the first input vector is obtained, and thus P intermediate vectors corresponding to the P input vectors are determined; in the pooling layer, the P intermediate vectors are merged into Q output vectors, and the plurality of output vectors obtained by the last transformer layer in the transformer layer are used as the feature representation of the current input.

[0201] (7)attention mechanism

[0202] The attention mechanism simulates the internal process of biological observation behavior, that is, a mechanism that aligns internal experience and external feeling to increase the observation fineness of a part of the region, and can quickly filter out high-value information from a large amount of information using limited attention resources. The attention mechanism can quickly extract important features of sparse data, and is therefore widely used in natural language processing tasks, especially machine translation. The self-attention mechanism is an improvement of the attention mechanism, which reduces the dependence on external information and is better at capturing the internal correlation of data or features. The essential idea of the attention mechanism can be rewritten as the following formula:

[0203] Wherein, Lx=||Source|| represents the length of Source, the formula means that the elements in Source are imagined to be composed of a series of data pairs, and then the weight coefficient of each Key corresponding to Value is obtained by calculating the similarity or correlation between Query in the given target Target and each Key, and then the weighted sum of Value is obtained, that is, the final Attention value is obtained. Therefore, the essence of Attention mechanism is to weight and sum the Value values of the elements in Source, and Query and Key are used to calculate the weight coefficient of the corresponding Value. Conceptually, Attention can be understood as selectively filtering out a small amount of important information from a large amount of information and focusing on these important information, ignoring a large amount of unimportant information. The focusing process is reflected in the calculation of the weight coefficient, and the greater the weight, the more focused on the corresponding Value value, that is, the weight represents the importance of the information, and the Value is the corresponding information. The self-attention mechanism can be understood as intra attention, and the Attention mechanism occurs between the element Query in the Target and all the elements in the Source. The self-attention mechanism refers to the Attention mechanism occurring between the elements in the Source or between the elements in the Target. It can also be understood as the attention mechanism of the special case of Target=Source, and the specific calculation process is the same, only the calculation object changes.

[0204] In recent years, AI has been widely applied in optical proximity correction, integrated circuit layout generation, layout hotspot detection, yield detection and other semiconductor design and manufacturing fields.

[0205] Optical proximity correction is to adjust the shape of the mask to reduce the impact of light diffraction, so that the shape of the lithography is similar to the shape of the chip design. Integrated circuit layout is a key resource in the field of semiconductor design and manufacturing, and is widely used in lithography modeling, optical proximity correction, and layout hotspot detection. However, due to the complexity of the design and manufacturing process, it is both expensive and time-consuming to obtain sufficient integrated circuit layout. Especially in the evolution process of manufacturing technology, changes in parameters and design rules require the redesign of integrated circuit layout. In addition, AI methods are applied to the field of semiconductor design and manufacturing, which requires more integrated circuit layout as training data. Generating layout based on generative model can meet the needs of semiconductor design and manufacturing.

[0206] The AI application in the semiconductor design and manufacturing field usually takes the integrated circuit layout as an image and models the pixel-level relationship. For example, for optical proximity correction, the layout is generally taken as an image, and a machine learning model is used to output the picture after optical correction. The integrated circuit layout generation also takes the layout as an image, uses a machine learning model to fit the distribution of the image, and then generates a new circuit layout.

[0207] However, the layout is different from the natural image, but is composed of some regular polygon elements, the size and the layout between them require to meet the design rules. Therefore, the image modeling method based on the pixel level cannot fully capture the polygon level information such as the geometric shape and the layout of the layout. This will lead to the generation of a large number of irregular patterns, which requires a lot of post-processing, and the accuracy of the data output by the machine learning model is low.

[0208] To solve the above problems, the present application provides a data processing method.

[0209] Reference Figure 7 , Figure 7 The flowchart of an embodiment of a data processing method provided by an embodiment of the present application is shown, wherein the data processing method comprises:

[0210] 701, obtaining sequence information of a circuit layout; wherein the circuit layout comprises a polygon element, the polygon element comprises a plurality of edges; the sequence information comprises edge information of each edge and connection order between the plurality of edges, and the edge information comprises direction and length of the edge.

[0211] In a possible implementation, the circuit layout (for example, picture or other information format data) can be converted into sequence information, and the sequence information can be represented by text format data.

[0212] Wherein, one circuit layout can comprise one or more polygon elements, in order to describe the polygon level information such as the geometric shape of the polygon element in the circuit layout and the layout of the polygon element, the polygon element in the circuit layout needs to be coded to obtain the sequence information of the circuit layout, which can exemplarily contain the geometric information and the position information of the polygon element, or one of the geometric information and the position information, wherein the geometric information can comprise edge information of each edge of the polygon element and connection order between the plurality of edges. The position information can comprise the position of the polygon element in the circuit layout.

[0213] Wherein, the edge information of each edge and the connection order between the plurality of edges can be represented by characters.

[0214] Regarding the position information:

[0215] In a possible implementation, the sequence information further includes a position of the polygon element in the circuit layout.

[0216] In a possible implementation, the sequence information can include a position of a feature point on the polygon element in the circuit layout, that is, the position of the polygon element in the circuit layout can be represented by the position of a point on the polygon element. For example, the sequence information can include coordinates of a point on the polygon element in the circuit layout.

[0217] In a possible implementation, the sequence information can include a position of a side or each side on the polygon element in the circuit layout.

[0218] For example, the polygon element can select a starting point according to a uniform rule, and coordinates of the starting point in the circuit layout can represent the position of the polygon element in the circuit layout. For example, the polygon element can select a point with the minimum y coordinate, and if the y coordinates are equal, select a point with the minimum x coordinate (or select a point with the minimum x coordinate, and if the x coordinates are equal, select a point with the minimum y coordinate).

[0219] It should be understood that the position information can be indicated by the position information alone in the sequence information, or by the position information alone in the sequence information in combination with other information (for example, the side information described later).

[0220] For example, the position information of a point on the polygon element can be used as a reference for the overall position, and the position information of each side (which can be represented by, for example, the length, direction, connection relationship, and the like of the side) can represent the position of the polygon element in the circuit layout.

[0221] For example, the position information of a side on the polygon element can be used as a reference for the overall position, and the position information of each side (which can be represented by, for example, the length, direction, connection relationship, and the like of the side) can represent the position of the polygon element in the circuit layout. For another example, the position information of each side can be combined with the length, direction, and the like of each side to represent the position of the polygon element in the circuit layout.

[0222] In addition, the position of each polygon element in the circuit layout can also be described in other manners, for example, the position of the polygon element in the circuit layout can be represented by the position of a center point of the polygon, which is not limited herein.

[0223] Regarding the side information:

[0224] In a possible implementation, the side information can be used to describe the geometric information of the side, for example, the side information can include the direction and length of the side.

[0225] In the local coordinate system defined by the circuit layout, some edges can be in the left-right direction (or can be referred to as the horizontal direction) or in the up-down direction (or can be referred to as the vertical direction or the vertical direction). For such an edge (for example, taking an edge with the above characteristics as a first edge), the direction of the first edge can be one of the following directions: up-down direction, left-right direction, from top to bottom direction, from bottom to top direction, from left to right direction, or from right to left direction.

[0226] For example, referring to Figure 8 In one possible implementation, the direction of the first edge is indicated by a mark, for example, four symbols: [Up], [Left], [Right], and [Down] can be defined to represent the four directions in the horizontal and vertical directions. [Up] can represent the direction from bottom to top, [Left] can represent the direction from right to left, [Right] can represent the direction from left to right, and [Down] can represent the direction from top to bottom.

[0227] In the coordinate system defined by the circuit layout, some edges can be inclined (that is, neither left-right nor up-down, and the included angle with the x-axis is an acute angle). For such an edge (for example, taking an edge with the above characteristics as a second edge), any inclined edge can be used as a hypotenuse of a right triangle and represented by a right angle edge.

[0228] In one possible implementation, the plurality of edges can include a second edge, the second edge being a hypotenuse in a triangle with a third edge and a fourth edge as right angle edges, the third edge and the fourth edge not belonging to the polygon element, the edge information of the second edge being represented by the edge information of the third edge and the fourth edge, the direction of the third edge and the direction of the fourth edge being the up-down direction or the left-right direction, the direction of the third edge and the direction of the fourth edge being the direction defined in the local coordinate system of the circuit layout.

[0229] For example, referring to Figure 9 . Figure 9 The circuit layout shown has a diagonal line, a virtual point V can be added as shown, and a pair of identifiers such as [SOV] and [EOV] can be introduced to identify the layout diagonal line in the sequence. Therefore, the above polygon sequence with an arbitrary angle diagonal line can be serialized as: [SOP], x0, y0, [Down], d1, [SOV], d2, [Right], d3, [EOV], d4, [Up], d5, [Left], d6, [Up], d7, [L], d8, [EOP].

[0230] It should be understood that when determining the local coordinate system of a circuit layout, the direction of the reference axis of the coordinate system can be set so that most edges in that coordinate system are in the left-right or up-down direction, which can greatly reduce the difficulty of coding. In addition, the direction of the edges can also be represented in other ways, such as the angle between the edge and the reference axis, etc., which are not limited here.

[0231] In one possible implementation, the sequence information includes the connection order between multiple edges. For example, the edge information of the multiple edges is arranged in a target order in the sequence information, and the connection order between the multiple edges is indicated by the target order. For two adjacent edges in a polygonal element, their edge information in the sequence information is also adjacent. For example, if edge 1, edge 2, and edge 3 are connected sequentially in a polygonal element, then the edge information of edge 1, edge 2, and edge 3 are also set sequentially in the sequence information.

[0232] like Figure 9 As shown, each polygon is represented by the coordinates of its starting point and a sequence of directions and offsets traversing all edges counter-clockwise (or clockwise) from that point. Specifically, each polygon is identified by a pair of symbols, such as [SOP] and [EOP], indicating the start and end of the pattern sequence, respectively. All polygons are selected with their starting points according to a uniform rule: for example, the point with the smallest y-coordinate is selected; if the y-coordinates are equal, the point with the smallest x-coordinate is selected (or the point with the smallest x-coordinate is selected; if the x-coordinates are equal, the point with the smallest y-coordinate is selected). Four symbols, such as [Up], [Left], [Right], and [Down], are defined to represent the horizontal and vertical directions. Each direction is followed by an offset value indicating the edge length. A minimum unit of length, 1, is defined, and the coordinates of the starting point and offset are discretized into integers in the range [1, N], where 1 is the minimum distance unit and N is the maximum length of the layout.

[0233] All polygons in the layout are contained in a pair of symbols, such as [SOB] and [EOB], which represent the header and tail of the layout serialization, respectively. All polygons in the layout are sorted according to the coordinates of their starting points according to certain rules. For example, they can be sorted from smallest to largest based on the y-coordinate of their starting points. If the y-coordinates are the same, the polygon with the smaller x-coordinate takes priority (or they can be sorted from smallest to largest based on the x-coordinate of their starting points. If the x-coordinates are the same, the polygon with the smaller y-coordinate takes priority).

[0234] In a possible implementation, the polygon element is a polygon with an internal hollow region, the plurality of sides are outer sides of the polygon element, the polygon element further comprises a plurality of inner sides, the inner sides are outer edges of the internal hollow region, the outer sides are outer edges of the polygon element, and the sequence information further comprises information indicative of the plurality of inner sides. Optionally, the information indicative of the plurality of inner sides can be a projection point of a point on the inner side on the outer side.

[0235] For example, there can be a polygon with an internal hollow region (or can be described as a polygon element with a hollow region or an embedded figure) in a circuit layout, which can be divided into two polygons, and the outer polygon can be serialized according to the rules defined for normal polygons, for example, serialized as [P0, P1, P2, P5, P0]. Figure 10 For the embedded figure, rules can be uniformly defined for serialization, for example, in the order of y coordinate maximum, if the y left sides are the same, in the order of x left maximum point as the starting point, in the order of clockwise [P7, P8, P9, P10]. Then, a virtual length is introduced as shown in the following formula: Figure 10 Therefore, the polygon element shown in FIG. 6 can be serialized as [P0, P1, P2, P5, P6, P7, P8, P9, P10, P6, P0]. Figure X

[0236] Each polygon element in the circuit layout can be encoded in the above manner to obtain the sequence information.

[0237] In a possible implementation, the circuit layout comprises a plurality of polygon elements, the sequence information comprises polygon information of each of the polygon elements, the polygon information comprises side information of each side in the polygon element and a connection order between the plurality of sides included in the polygon element, and an arrangement order of the polygon information in the sequence information is related to a positional relationship of the plurality of polygon elements in the circuit layout.

[0238] In the sequence information of the circuit layout, each polygon information can be arranged according to a certain rule, and the rule can be related to the positional relationship of the plurality of polygon elements in the circuit layout. For example, a polygon element with a larger y value is preferred, and in the case of the same y value, a polygon element with a larger x value is preferred.

[0239] According to the above rule, the circuit layout can be losslessly compressed into a symbol sequence, and a sequence conforming to the rule can also be losslessly restored into the circuit layout.

[0240] ​702、processing the sequence information through the machine learning model to obtain a processing result corresponding to the circuit layout.

[0241] In a possible implementation, the machine learning model can be used to implement an optical proximity correction task; when performing the optical proximity correction task, at least one segment of the upper edge of the polygon element in the original circuit layout can be designated as an adjustment segment, where the adjustment segment refers to a segment that can be allowed to be offset in a certain direction (for example, towards the inside or outside of the polygon element) during correction. In this case, the sequence information can further include position information of the adjustment segment.

[0242] In a possible implementation, the machine learning model is used to implement an optical proximity correction task; the plurality of edges of the polygon element further include breakpoints, the plurality of edges of the polygon element include at least one adjustment segment, and the sequence information includes a position of the at least one adjustment segment; for example, the adjustment segment can be understood as a segment whose position can be moved, and the segment can be part of an edge of the polygon. Wherein the position of the adjustment segment can be represented by the positions of two end points (or can be referred to as breakpoints); that is, the sequence information can include positions of a plurality of breakpoints; and further, the sequence information is processed through the machine learning model to obtain a processing result corresponding to the circuit layout, including: the sequence information is processed through the machine learning model to predict a position offset of the at least one adjustment segment.

[0243] It should be understood that the position of the adjustment segment can be specified by a user or obtained by recognizing the circuit layout, and the recognition method can be based on experience or a numerical method such as a neural network, which is not limited here.

[0244] In a possible implementation, the sequence information further includes an initial feature representation (or can be referred to as a learnable semantic vector) corresponding to each of the adjustment segments; and the processing of the sequence information through the machine learning model to predict the position offset of the at least one adjustment segment includes: performing feature extraction on the sequence information through a feature extraction network in the machine learning model to obtain a target feature representation of the sequence information; and predicting the position offset of the at least one adjustment segment through a prediction network in the machine learning model according to the target feature representation.

[0245] Exemplarily, polygons in a circuit layout can have at least one adjusted edge, and OPC generates a pattern satisfying OPC by adjusting the offset of the edge. OPC can be understood as an end-to-end process, and the input is the layout of an integrated circuit design, and the output is the shape of the corrected layout. The serialized OPC prediction learning method converts the layout containing polygon breakpoints into a sequence, and models the Polygon-Level information through a sequence model (Transformer, RNNs, etc.) to predict the corrected layout.

[0246] As shown in Figure 11 The polygon containing breakpoints can be converted into the following sequence according to the integrated circuit layout serialization method:

[0247] [SOP], x0, y0, [Down], d1, [Right], d21, d22, d23, d24, [Down], d31, d32, d33, d34, [Right], d4, [Up], d51, d52, d53, d54, d55, [Left], d61, d62, d63, d64, [EOP].

[0248] A learnable vector is introduced for each edge at the breakpoint to represent the offset of the edge, denoted by [M]. Therefore, the following sequence can be obtained:

[0249] [SOP], x0, y0, [Down], d1, [Right], d21, [M], d22, [M], d23, [M], d24, [M], [Down], d31, [M], d32, [M], d33, [M], d34, [M], [Right], d4, [Up], d51, [M], d52, [M], d53, [M], d54, [M], d55, [M], [Left], d61, [M], d62, [M], d63, [M], d64, [M], [EOP]. (It should be understood that the semantic symbol [M] can also be placed in front of the edge at the breakpoint, such as ……[M], d21, [M], d22, ……).

[0250] According to the above method, the layout containing breakpoints can be serialized, and the semantic symbol [M] and the corresponding learnable vector are introduced. Then a serialized model such as Transformer is used to model [M] and the geometric shape and position relationship in the sequence, and finally the offset of the edge at the breakpoint is predicted according to the corresponding learnable vector. Two schemes are used to predict the offset, one scheme is regression prediction, and the other scheme is to discretize the offset of the edge at the breakpoint, and convert the offset prediction into a classification problem.

[0251] The above-mentioned serialized OPC learning method can learn the OPC process through training data, and finally realize the prediction of the corrected layout shape. The specific learning and prediction framework can be exemplarily shown as Figure 12 In the above manner, a learnable semantic vector M is introduced for each edge at the breakpoint, and the offset of the edge is predicted by modeling the Polygon-level information. Compared with the existing OPC based on images, the operation is faster, the prediction accuracy is higher, and post-processing is not needed.

[0252] In a possible implementation, the machine learning model is used to implement a circuit layout generation task; the plurality of edges are partial edges on the polygon element; and the processing of the sequence information by the machine learning model to obtain the processing result corresponding to the circuit layout includes: processing the sequence information by the machine learning model to obtain edge information of another partial edge on the polygon element.

[0253] Exemplarily, the real layout can be serialized by using the data processing method in the embodiment of the present application, and then a self-recurrent generation model is trained. For example, as shown in FIG. 13, specifically, each symbol in the sequence can be generated based on the previously generated symbol, as shown in Figure 14 As shown in FIG. 13, a starting prompt is given as input, for example, ''[SOB],[SOP]", which is input to the serialized model to obtain a category distribution of all symbols. A symbol is sampled from the distribution as a generated symbol, and then added to the sequence as a prediction of the subsequent symbol input to the model for continuous generation. The above generation process is repeated until the end-of-sequence symbol [EOB] is encountered, and the generation ends. The generated layout sequence can be converted into a layout.

[0254] The generated layout not only needs to conform to the design rules but also needs to be similar to the real layout. At the same time, in order to better apply to the fields of semiconductor design and manufacturing such as lithography modeling, optical proximity correction, and layout hotspot detection, the diversity of the generated layout needs to be maximized. 100,000 patterns are generated from the trained model, and their diversity and legality are evaluated. Whether the layout conforms to the design rules is checked by the tool Klayout. Then, the diversity of the legal layout is further evaluated. The specific results are shown in the following table:

[0255]

[0256] In addition, the similarity between the generated legal layout and the real layout is evaluated, and the results are as follows:

[0257]

[0258] The sequence layout generation method is obviously better than the existing method with a large amount of post-processing in terms of generation quality legitimacy and diversity performance without any post-processing.

[0259] The present application exceeds other SOTA methods in terms of generation quality, diversity and other indicators of circuit layout, and does not require a large amount of post-processing.

[0260] In a possible implementation, the machine learning model is used to implement a hot spot detection task or a yield detection task of a circuit layout.

[0261] The embodiment of the present application provides a data processing method, which comprises: acquiring sequence information of a circuit layout; wherein the circuit layout comprises a polygon element, the polygon element comprises a plurality of edges; the sequence information comprises edge information of each edge and a connection order between the plurality of edges, and the edge information comprises a direction and a length of the edge; and processing the sequence information through a machine learning model to obtain a processing result corresponding to the circuit layout. In the foregoing manner, the information of the polygon level such as the geometric shape and the layout of the circuit layout can be explicitly modeled, the layout design rules can be more easily learned, and the integrated circuit layout can be efficiently and losslessly compressed into a symbol sequence (sequence information), so that the machine learning model can extract more accurate features.

[0262] Reference Figure 15 The embodiment of the present application further provides a data processing method, which comprises:

[0263] 1501, acquiring an image of a circuit layout, and the image content of the image comprises a polygon element;

[0264] 1502, generating sequence information of the circuit layout according to the image; wherein the polygon element comprises a plurality of edges; the sequence information comprises edge information of each edge and a connection order between the plurality of edges, and the edge information comprises a direction and a length of the edge.

[0265] The specific description of step 1502 can refer to the description of step 701 in the above embodiment, which will not be repeated here.

[0266] In a possible implementation, the plurality of edges comprises a first edge, and the direction of the first edge is one of the following directions: an up-down direction, a left-right direction, a direction from top to bottom, a direction from bottom to top, a direction from left to right or a direction from right to left, and the direction is defined in a local coordinate system of the circuit layout.

[0267] In a possible implementation, the direction of the first edge is indicated by an identifier.

[0268] In a possible implementation, the edge information of the plurality of edges is arranged in the sequence information according to a target order, and the connection order between the plurality of edges is indicated by the target order.

[0269] In a possible implementation, the plurality of edges includes a second edge, the second edge being a diagonal of a triangle with a third edge and a fourth edge as right-angle edges, the third edge and the fourth edge not belonging to the polygon element, the edge information of the second edge being represented by the edge information of the third edge and the fourth edge, the directions of the third edge and the fourth edge being up-down direction or left-right direction, and the directions of the third edge and the fourth edge being directions defined in a local coordinate system of the circuit layout.

[0270] In a possible implementation, the circuit layout includes a plurality of polygon elements, the sequence information includes polygon information of each of the polygon elements, the polygon information including edge information of each edge in the polygon element and a connection order between a plurality of edges included in the polygon element, and an arrangement order of the polygon information in the sequence information is related to a positional relationship of the plurality of polygon elements in the circuit layout.

[0271] In a possible implementation, the sequence information further includes a position of the polygon element in the circuit layout.

[0272] In a possible implementation, the position is represented by a position coordinate of a point on the polygon element in the circuit layout.

[0273] In a possible implementation, the polygon element is a polygon with an internal hollow region, the plurality of edges are outer edges of the polygon element, the polygon element further includes a plurality of inner edges, the inner edges being outer edges of the internal hollow region, the outer edges being outer edges of the polygon element, and the sequence information further includes information indicating the plurality of inner edges.

[0274] Reference Figure 16 , Figure 16 A structure of a data processing apparatus provided by an embodiment of the present application is shown in FIG. 16. Figure 16 As shown in FIG. 16, the apparatus 1600 can include:

[0275] The apparatus 1600 can further include an obtaining module 1601 configured to obtain sequence information of a circuit layout, wherein the circuit layout includes a polygon element, the polygon element including a plurality of edges, and the sequence information includes edge information of each edge and a connection order between the plurality of edges, the edge information including a direction and a length of the edge.

[0276] The description of the obtaining module 1601 can refer to the description of step 701 in the above embodiments, which is not repeated here.

[0277] The processing module 1602 is configured to process the sequence information by using a machine learning model to obtain a processing result corresponding to the circuit layout.

[0278] The description of the processing module 1602 can refer to the description of step 702 in the above embodiments, and will not be repeated here.

[0279] In a possible implementation, the plurality of edges includes a first edge, and a direction of the first edge is one of the following: an up-down direction, a left-right direction, a direction from top to bottom, a direction from bottom to top, a direction from left to right, or a direction from right to left, and the direction is defined in a local coordinate system of the circuit layout.

[0280] In a possible implementation, the direction of the first edge is indicated by a flag.

[0281] In a possible implementation, the edge information of the plurality of edges is arranged in the sequence information according to a target order, and the connection order between the plurality of edges is indicated by the target order.

[0282] In a possible implementation, the plurality of edges includes a second edge, the second edge is a diagonal of a triangle with a third edge and a fourth edge as right-angle edges, the third edge and the fourth edge do not belong to the polygon element, the edge information of the second edge is represented by the edge information of the third edge and the fourth edge, the direction of the third edge and the direction of the fourth edge are the up-down direction or the left-right direction, and the directions of the third edge and the fourth edge are defined in the local coordinate system of the circuit layout.

[0283] In a possible implementation, the sequence information further includes a position of the polygon element in the circuit layout.

[0284] In a possible implementation, the position is represented by a position coordinate of a point on the polygon element in the circuit layout.

[0285] In a possible implementation, the circuit layout includes a plurality of polygon elements, the sequence information includes polygon information of each of the polygon elements, the polygon information includes edge information of each edge of the polygon element and a connection order between a plurality of edges included in the polygon element, and an arrangement order of the polygon information in the sequence information is related to a positional relationship of the plurality of polygon elements in the circuit layout.

[0286] In a possible implementation, the polygon element is a polygon with an internal hollow region, the plurality of edges are outer edges of the polygon element, the polygon element further includes a plurality of inner edges, the inner edges are outer edges of the internal hollow region, the outer edges are outer edges of the polygon element, and the sequence information further includes information indicating the plurality of inner edges.

[0287] In a possible implementation, the machine learning model is used to implement an optical proximity correction task; the plurality of sides of the polygon element include at least one adjustment segment, and the sequence information includes a position of the at least one adjustment segment.

[0288] The processing module is specifically configured to:

[0289] The sequence information is processed by the machine learning model to predict the position offset of the at least one adjustment segment.

[0290] In a possible implementation, the sequence information further includes an initial feature representation corresponding to each of the adjustment segments.

[0291] The processing module is specifically configured to:

[0292] The sequence information is feature-extracted by a feature extraction network in the machine learning model to obtain a target feature representation of the sequence information.

[0293] According to the target feature representation, a prediction network in the machine learning model is used to predict the position offset of the at least one adjustment segment.

[0294] In a possible implementation, the machine learning model is used to implement a circuit layout generation task; the plurality of sides are part of sides on the polygon element.

[0295] The processing module is specifically configured to:

[0296] The sequence information is processed by the machine learning model to obtain side information of another part of sides on the polygon element.

[0297] In a possible implementation, the machine learning model is used to implement a hot spot detection task or a yield detection task of a circuit layout.

[0298] Reference Figure 17 , Figure 17 The structure of a data processing apparatus provided by the embodiments of the present application is shown in FIG. 17. Figure 17 The apparatus 1700 can include the following components:

[0299] The acquisition module 1701 is configured to acquire an image of a circuit layout, and image content of the image includes a polygon element.

[0300] The description of the acquisition module 1701 can be referred to the description of the step 1501 in the above embodiments, which will not be repeated here.

[0301] The generating module 1702 is configured to generate sequence information of the circuit layout according to the image, wherein the polygon element comprises a plurality of sides, and the sequence information comprises side information of each side and a connection order between the plurality of sides, and the side information comprises a direction and a length of the side.

[0302] The description of the generating module 1702 can refer to the description of step 1502 in the above embodiments, and will not be repeated here.

[0303] In a possible implementation, the plurality of sides comprises a first side, and the direction of the first side is one of the following directions: an up-down direction, a left-right direction, a direction from top to bottom, a direction from bottom to top, a direction from left to right, or a direction from right to left, and the direction is defined in a local coordinate system of the circuit layout.

[0304] In a possible implementation, the direction of the first side is indicated by a mark.

[0305] In a possible implementation, the side information of the plurality of sides is arranged in the sequence information according to a target order, and the connection order between the plurality of sides is indicated by the target order.

[0306] In a possible implementation, the plurality of sides comprises a second side, the second side is a diagonal side in a triangle with a third side and a fourth side as right-angled sides, the third side and the fourth side do not belong to the polygon element, the side information of the second side is represented by side information of the third side and the fourth side, the direction of the third side and the direction of the fourth side are the up-down direction or the left-right direction, and the directions of the third side and the fourth side are defined in the local coordinate system of the circuit layout.

[0307] In a possible implementation, the sequence information further comprises a position of the polygon element in the circuit layout.

[0308] In a possible implementation, the position is represented by a position coordinate of a point on the polygon element in the circuit layout.

[0309] In a possible implementation, the circuit layout comprises a plurality of polygon elements, the sequence information comprises polygon information of each of the polygon elements, the polygon information comprises side information of each side in the polygon element and a connection order between a plurality of sides included in the polygon element, and an arrangement order of the polygon information in the sequence information is related to a positional relationship of the plurality of polygon elements in the circuit layout.

[0310] In a possible implementation, the polygon element is a polygon with an internal hollow region, the plurality of sides are outer sides of the polygon element, the polygon element further comprises a plurality of inner sides, the inner sides are outer edges of the internal hollow region, the outer sides are outer edges of the polygon element, and the sequence information further comprises information indicating the plurality of inner sides.

[0311] Next, a semiconductor design device provided by an embodiment of the present application is introduced. Referring to FIG. 18, a structure of the semiconductor design device is shown. Figure 18 Figure 18 A structure of the semiconductor design device provided by an embodiment of the present application is shown. Specifically, the semiconductor design device 1800 includes a receiver 1801, a transmitter 1802, a processor 1803, and a memory 1804 (wherein the number of the processor 1803 in the semiconductor design device 1800 can be one or more, and one processor is taken as an example in the description below), wherein the processor 1803 can include an application processor 18031 and a communication processor 18032. In some embodiments of the present application, the receiver 1801, the transmitter 1802, the processor 1803, and the memory 1804 can be connected through a bus or other means. Figure 18

[0312] The memory 1804 can include a read-only memory and a random access memory, and provide the processor 1803 with instructions and data. A part of the memory 1804 can also include a non-volatile random access memory (NVRAM). The memory 1804 stores processor and operation instructions, executable modules or data structures, or a subset thereof, or an extended set thereof, wherein the operation instructions can include various operation instructions for implementing various operations.

[0313] ​​The method disclosed in the embodiments of the present application can be applied to the processor 1803 or implemented by the processor 1803. The processor 1803 can be an integrated circuit chip having a signal processing capability. In the implementation process, the steps of the above method can be completed by hardware integrated logic circuits in the processor 1803 or by instructions in the form of software. The processor 1803 described above can be a general processor, a digital signal processor (DSP), a microprocessor or a microcontroller, and can further include an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The processor 1803 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor can be a microprocessor or the processor can also be any conventional processor or the like. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware code processor to execute, or be executed by a combination of hardware and software modules in the code processor. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the storage 1804, and the processor 1803 reads the information in the storage 1804 and combines the hardware to complete the steps of the method provided in the above embodiments.

[0314] The receiver 1801 can be used to receive input digital or character information, and generate signal input related to the relevant settings and function control of the radar system. The transmitter 1802 can be used to output digital or character information through the first interface; the transmitter 1802 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group.

[0315] The embodiments of the present application also provide a server, please refer to Figure 19 , Figure 19Fig. 1 is a schematic diagram of a server according to an embodiment of the present application. The server can be configured or have different performance, and can include one or more central processing units (CPU) 1922 (e.g., one or more processors) and a memory 1932, one or more storage media 1930 (e.g., one or more mass storage devices) storing applications 1942 or data 1944. The memory 1932 and the storage media 1930 can be volatile or non-volatile storage. The programs stored in the storage media 1930 can include one or more modules (not shown in the figure), each of which can include a series of instructions for operating on the training device. Further, the central processing unit 1922 can be configured to communicate with the storage media 1930 and execute the series of instructions in the storage media 1930 on the server 1900.

[0316] The server 1900 can also include one or more power supplies 1926, one or more wired or wireless network interfaces 1950, one or more input / output interfaces 1958, and / or one or more operating systems 1941, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0317] In an embodiment of the present application, the central processing unit 1922 is configured to execute the data processing method described in the above embodiments.

[0318] In an embodiment of the present application, a computer program product is also provided, which, when running on a computer, causes the computer to execute the method described in the above embodiments.

[0319] In an embodiment of the present application, a computer readable storage medium is also provided, which stores a program for signal processing, and when running on a computer, causes the computer to execute the method described in the above embodiments.

[0320] The semiconductor design apparatus provided in the embodiments of the present application can be a chip, which includes a processing unit, for example, a processor, and a communication unit, for example, an input / output interface, a pin, a circuit or the like. The processing unit can execute computer execution instructions stored in a storage unit, so that the chip in the execution device executes the image enhancement method described in the above embodiments, or so that the chip in the training device executes the image enhancement method described in the above embodiments. Alternatively, the storage unit is a storage unit in the chip, such as a register, a cache or the like, and the storage unit can also be a storage unit outside the chip in the wireless access device, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or the like.

[0321] Specifically, refer to Figure 20 , Figure 20 A structural schematic diagram of the chip provided in the embodiments of the present application is shown in FIG. 2. The chip can be a neural network processor NPU 2000, which is mounted on a host CPU as a coprocessor and is assigned tasks by the host CPU. The core part of the NPU is an operation circuit 2003, which extracts matrix data in a memory and performs multiplication operation under the control of a controller 2004.

[0322] In some implementations, the operation circuit 2003 internally includes a plurality of processing units (Process Engine, PE). In some implementations, the operation circuit 2003 is a two-dimensional systolic array. The operation circuit 2003 can also be a one-dimensional systolic array or other electronic circuits capable of performing mathematical operations such as multiplication and addition. In some implementations, the operation circuit 2003 is a general matrix processor.

[0323] For example, it is assumed that there are an input matrix A, a weight matrix B and an output matrix C. The operation circuit takes corresponding data of the matrix B from the weight memory 2002 and caches it on each PE in the operation circuit. The operation circuit takes the matrix A data from the input memory 2001 and performs matrix operation with the matrix B, and the partial result or final result of the obtained matrix is saved in an accumulator 2008.

[0324] The unified memory 2006 is used to store input data and output data. The weight data is transferred to the weight memory 2002 through a direct memory access controller (DMAC) 2005. The input data is also transferred to the unified memory 2006 through the DMAC.

[0325] BIU for Bus Interface Unit, which is used for the interaction between AXI bus and DMAC and instruction fetch buffer (IFB) 2009.

[0326] The bus interface unit 2010 (BIU) is used for the instruction fetch buffer 2009 to obtain instructions from the external memory, and also used for the storage unit access controller 2005 to obtain the original data of the input matrix A or the weight matrix B from the external memory.

[0327] The DMAC is mainly used to carry the input data in the external memory DDR to the unified memory 2006, or carry the weight data to the weight memory 2002, or carry the input data to the input memory 2001.

[0328] The vector calculation unit 2007 includes a plurality of operation processing units, which further process the output of the operation circuit as needed, such as vector multiplication, vector addition, exponential operation, logarithmic operation, size comparison, etc. It is mainly used for non-convolution / full connection layer network calculation in neural network, such as batch normalization, pixel-level summation, upsampling of feature plane, etc.

[0329] In some implementations, the vector calculation unit 2007 can store the processed output vector to the unified memory 2006. For example, the vector calculation unit 2007 can apply a linear function and / or a nonlinear function to the output of the operation circuit 2003, such as linear interpolation on the feature plane extracted by the convolution layer, and for example, a vector of accumulated values to generate activation values. In some implementations, the vector calculation unit 2007 generates normalized values, pixel-level summation values, or both. In some implementations, the processed output vector can be used as an activation input to the operation circuit 2003, for example, for use in subsequent layers in the neural network.

[0330] The instruction fetch buffer 2009 connected to the controller 2004 is used to store instructions used by the controller 2004;

[0331] The unified memory 2006, the input memory 2001, the weight memory 2002, and the instruction fetch buffer 2009 are all on-chip memories. The external memory is private to the NPU hardware architecture.

[0332] The processor mentioned in any of the above can be a general central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for executing programs for controlling the steps of the method described in the above embodiments.

[0333] It should be noted that the above-described apparatus embodiments are merely illustrative, and the units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, i.e., can be located in one place or distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment according to actual needs. In addition, the connection relationship between the modules in the apparatus embodiments provided in the present application indicates that there is a communication connection between them, which can be implemented as one or more communication buses or signal lines.

[0334] Through the above description of the embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software and the necessary general hardware, and of course, it can also be implemented by special hardware including special integrated circuits, special CPUs, special memories, special components, etc. Generally, functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structure for implementing the same function can also be various, such as analog circuits, digital circuits or special circuits. However, for the present application, software program implementation is a better embodiment. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer's floppy disk, U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc., including a plurality of instructions for making a computer device (which can be a personal computer, a training device, or a network device, etc.) execute the methods of the embodiments of the present application.

[0335] In the above embodiments, all or part can be realized by software, hardware, firmware or any combination thereof. When realized by software, it can be realized in the form of a computer program product in whole or in part.

[0336] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the flow or function according to the embodiments of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from one website site, computer, training device or data center to another website site, computer, training device or data center through wired (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example, infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be stored by the computer or a data storage device such as a training device, a data center, etc. integrated with one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)), etc.

Claims

1. A data processing method, characterized by, The method comprises: obtaining sequence information of a circuit layout; wherein the circuit layout comprises a polygon element, the polygon element comprises a plurality of edges; the sequence information comprises edge information of each edge and a connection order between the plurality of edges, the edge information comprises a direction and a length of an edge; the plurality of edges comprises a second edge, the second edge is a hypotenuse in a triangle with a third edge and a fourth edge as right-angle edges, the third edge and the fourth edge do not belong to the polygon element, the edge information of the second edge is represented by the edge information of the third edge and the fourth edge, the direction of the third edge and the direction of the fourth edge are up-down direction or left-right direction, the direction of the third edge and the fourth edge are defined in a local coordinate system of the circuit layout; processing the sequence information through a machine learning model to obtain a processing result corresponding to the circuit layout.

2. The method of claim 1, wherein, The plurality of edges comprises a first edge, the direction of the first edge is one of the following directions: up-down direction, left-right direction, from top to bottom direction, from bottom to top direction, from left to right direction or from right to left direction, the direction is defined in a local coordinate system of the circuit layout.

3. The method of claim 2, wherein, The direction of the first edge is indicated by a mark.

4. The method according to any one of claims 1 to 3, characterized in that, The edge information of the plurality of edges is arranged in the sequence information according to a target order, and the connection order between the plurality of edges is indicated by the target order.

5. The method of claim 1, wherein, The sequence information further comprises a position of the polygon element in the circuit layout.

6. The method of claim 5, wherein, The position is represented by position coordinates of a point on the polygon element in the circuit layout.

7. The method according to any one of claims 1 to 3, characterized in that, The polygon element is a polygon with an internal hollow region, the plurality of edges are outer edges of the polygon element, the polygon element further comprises a plurality of inner edges, the inner edges are outer edges of the internal hollow region, the outer edges are outer edges of the polygon element, and the sequence information further comprises information indicating the plurality of inner edges.

8. The method according to any one of claims 1 to 3, characterized in that, The circuit layout comprises a plurality of polygon elements, the sequence information comprises polygon information of each polygon element, the polygon information comprises edge information of each edge in the polygon element and a connection order between a plurality of edges included in the polygon element; and an arrangement order of the polygon information in the sequence information is related to a positional relationship of the plurality of polygon elements in the circuit layout.

9. The method according to any one of claims 1 to 3, characterized in that, The machine learning model is used to implement an optical proximity effect correction task; the plurality of edges of the polygon element comprises at least one adjustment segment, and the sequence information comprises a position of the at least one adjustment segment; The processing of the sequence information through the machine learning model to obtain the processing result corresponding to the circuit layout comprises: processing the sequence information through the machine learning model to predict a positional offset of the at least one adjustment segment.

10. The method of claim 9, wherein, The sequence information further comprises an initial feature representation corresponding to each adjustment segment; The processing of the sequence information through the machine learning model to predict the positional offset of the at least one adjustment segment comprises: The sequence information is processed by the machine learning model to obtain a processing result corresponding to the circuit layout, including: The sequence information is processed by the machine learning model to obtain a processing result corresponding to the circuit layout, including:

11. The method according to any one of claims 1 to 3, characterized in that, The machine learning model is used to implement a hot spot detection task or a yield detection task of the circuit layout. The method includes: An image of a circuit layout is obtained, and image content of the image includes a polygon element; 12. The method according to any one of claims 1 to 3, characterized in that, Sequence information of the circuit layout is generated according to the image; wherein the polygon element includes a plurality of edges; the sequence information includes edge information of each edge and a connection order between the plurality of edges, the edge information includes a direction and a length of the edge; the plurality of edges include a second edge, the second edge is a hypotenuse in a triangle with a third edge and a fourth edge as right-angle edges, the third edge and the fourth edge do not belong to the polygon element, the edge information of the second edge is represented by edge information of the third edge and the fourth edge, the direction of the third edge and the direction of the fourth edge are up-down direction or left-right direction, and the direction of the third edge and the fourth edge is defined in a local coordinate system of the circuit layout.

13. A data processing method, characterized by, The plurality of edges include a first edge, and the direction of the first edge is one of the following directions: up-down direction, left-right direction, from-top-to-bottom direction, from-bottom-to-top direction, from-left-to-right direction, or from-right-to-left direction, and the direction is defined in a local coordinate system of the circuit layout. The direction of the first edge is indicated by an identifier. The edge information of the plurality of edges is arranged in a target order in the sequence information, and the connection order between the plurality of edges is indicated by the target order.

14. The method of claim 13, wherein, The circuit layout includes a plurality of polygon elements, the sequence information includes polygon information of each of the polygon elements, the polygon information includes edge information of each edge in the polygon element and a connection order between a plurality of edges included in the polygon element, and an arrangement order of the polygon information in the sequence information is related to a positional relationship of the plurality of polygon elements in the circuit layout.

15. The method of claim 14, wherein, The polygon element is a polygon with an internal hollow region, the plurality of edges are outer edges of the polygon element, the polygon element further includes a plurality of inner edges, the inner edges are outer edges of the internal hollow region, the outer edges are outer edges of the polygon element, and the sequence information further includes information indicating the plurality of inner edges.

16. The method according to any one of claims 13 to 15, characterized in that, The device includes:

17. The method of any one of claims 13 to 15, wherein, ​ 18. The method of any one of claims 13 to 15, wherein, ​ 19. A data processing apparatus, characterized by ​ The acquisition module is configured to acquire sequence information of a circuit layout; the circuit layout comprises a polygon element, and the polygon element comprises a plurality of sides; the sequence information comprises side information of each side and a connection order between the plurality of sides; the side information comprises a direction and a length of a side; the plurality of sides comprise a second side, the second side is a hypotenuse in a triangle with a third side and a fourth side as right-angle sides, the third side and the fourth side do not belong to the polygon element, the side information of the second side is represented by side information of the third side and the fourth side, the direction of the third side and the direction of the fourth side are upward-downward direction or left-right direction, and the direction of the third side and the fourth side is a direction defined in a local coordinate system of the circuit layout. The processing module is configured to process the sequence information by using a machine learning model to obtain a processing result corresponding to the circuit layout.

20. The apparatus of claim 19, wherein, The plurality of sides comprise a first side, and a direction of the first side is one of upward-downward direction, left-right direction, from-top-to-bottom direction, from-bottom-to-top direction, from-left-to-right direction, or from-right-to-left direction, and the direction is a direction defined in a local coordinate system of the circuit layout.

21. The apparatus of claim 20, wherein, The direction of the first side is indicated by an identifier.

22. The apparatus of any one of claims 19 to 21, wherein, The side information of the plurality of sides is arranged in a target order in the sequence information, and the connection order between the plurality of sides is indicated by the target order.

23. The apparatus of claim 19, wherein, The sequence information further comprises a position of the polygon element in the circuit layout.

24. The apparatus of claim 23, wherein, The position is represented by position coordinates of a point on the polygon element in the circuit layout.

25. The apparatus of any one of claims 19 to 21, wherein, The polygon element is a polygon with an internal hollow region, the plurality of sides are outer sides of the polygon element, the polygon element further comprises a plurality of inner sides, the inner sides are outer edges of the internal hollow region, the outer sides are outer edges of the polygon element, and the sequence information further comprises information indicating the plurality of inner sides.

26. The apparatus of any one of claims 19 to 21, wherein, The circuit layout comprises a plurality of polygon elements, the sequence information comprises polygon information of each polygon element, the polygon information comprises side information of each side in the polygon element and a connection order between a plurality of sides included in the polygon element, and an arrangement order of the polygon information in the sequence information is related to a positional relationship between the plurality of polygon elements in the circuit layout.

27. The apparatus of any one of claims 19 to 21, wherein, The machine learning model is used to implement an optical proximity correction task, the plurality of sides of the polygon element comprise at least one adjustment segment, and the sequence information comprises a position of the at least one adjustment segment. The processing module is specifically configured to: process the sequence information by using the machine learning model to predict a positional offset of the at least one adjustment segment.

28. The apparatus of claim 27, wherein, The sequence information further comprises an initial feature representation corresponding to each adjustment segment. The processing module is specifically configured to: extract a feature of the sequence information by using a feature extraction network in the machine learning model to obtain a target feature representation of the sequence information; and predict the positional offset of the at least one adjustment segment by using a prediction network in the machine learning model according to the target feature representation.

29. The apparatus of any one of claims 19 to 21, wherein, The machine learning model is used to implement a circuit layout generation task; the multiple edges are partial edges on the polygon element; The processing module is specifically configured to: The machine learning model is used to implement a circuit layout generation task; the multiple edges are partial edges on the polygon element; 30. The apparatus of any one of claims 19 to 21, wherein, The machine learning model is used to implement a circuit layout generation task; the multiple edges are partial edges on the polygon element.

31. A data processing apparatus, characterized in that, The device comprises: An acquisition module configured to acquire an image of a circuit layout, the image content of the image comprising a polygon element; A generation module configured to generate sequence information of the circuit layout according to the image; wherein the polygon element comprises multiple edges; the sequence information comprises edge information of each edge and a connection order between the multiple edges, the edge information comprising a direction and a length of an edge; the multiple edges comprise a second edge, the second edge being a hypotenuse of a triangle with a third edge and a fourth edge as right-angle edges, the third edge and the fourth edge not belonging to the polygon element, the edge information of the second edge being represented by the edge information of the third edge and the fourth edge, the direction of the third edge and the direction of the fourth edge being an up-down direction or a left-right direction, the direction of the third edge and the direction of the fourth edge being defined in a local coordinate system of the circuit layout.

32. The apparatus of claim 31, wherein, The multiple edges comprise a first edge, the direction of the first edge being one of the following directions: an up-down direction, a left-right direction, a direction from top to bottom, a direction from bottom to top, a direction from left to right, or a direction from right to left, the direction being defined in a local coordinate system of the circuit layout.

33. The apparatus of claim 32, wherein, The direction of the first edge is indicated by a mark.

34. The apparatus of any one of claims 31 to 33, wherein, The edge information of the multiple edges is arranged in a target order in the sequence information, and the connection order between the multiple edges is indicated by the target order.

35. The apparatus of any one of claims 31 to 33, wherein, The circuit layout comprises multiple polygon elements, the sequence information comprises polygon information of each polygon element, the polygon information comprising edge information of each edge in the polygon element and a connection order between multiple edges included in the polygon element, and an arrangement order of the polygon information in the sequence information is related to a positional relationship of the multiple polygon elements in the circuit layout.

36. The apparatus of any one of claims 31 to 33, wherein, The polygon element is a polygon with an internal hollow region, the multiple edges are outer edges of the polygon element, the polygon element further comprises multiple inner edges, the inner edges are outer edges of the internal hollow region, the outer edges are outer edges of the polygon element, and the sequence information further comprises information indicating the multiple inner edges.

37. A data processing apparatus, characterized by: The device comprises: One or more processors and a memory; wherein the memory stores computer readable instructions; The one or more processors read the computer readable instructions to enable the computer device to implement the method of any one of claims 1 to 18.

38. A computer-readable storage medium, characterized in that, The computer readable instructions, when executed on a computer device, enable the computer device to perform the method of any one of claims 1 to 18.

39. A computer program product, characterised in that, computer readable instructions, which, when run on a computer device, cause the computer device to perform the method of any one of claims 1 to 18.

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