Display device and driving method thereof

Abstract

The present disclosure relates to a display device and a driving method thereof. A display device is provided, the display device comprising a display panel configured to display an image, a data driver configured to provide a data voltage to the display panel and having a precharge circuit configured to perform a precharge operation, and a timing controller configured to control the data driver, wherein the precharge circuit generates a precharge voltage based on a precharge signal provided in a horizontal blank period, and controls the precharge circuit to output or not output the precharge voltage based on a precharge selection signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0072765, filed on June 4, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a display device and a driving method thereof. Background Art

[0004] With the development of information technology, the market for display devices, which are the medium between users and information, is also growing. Accordingly, display devices such as light emitting display devices (LEDs), quantum dot display devices (QDDs) and liquid crystal display devices (LCDs) are increasingly being used.

[0005] The above-mentioned display device includes a display panel having sub-pixels, a driver outputting a driving signal for driving the display panel, a power supply generating power to be supplied to the display panel or the driver, and the like.

[0006] The above-mentioned display device can display an image in such a manner that a selected sub-pixel transmits light or directly emits light when a driving signal (eg, a scan signal and a data signal) is supplied to the sub-pixel formed in the display panel. Summary of the invention

[0007] An object of the present invention is to maximize the effect of reducing current consumption without degrading the performance of a specific device by performing an adaptive precharge operation regardless of an image pattern.

[0008] To achieve these objectives and other advantages, and in accordance with the intent of the present invention as embodied and broadly described herein, a display device includes: a display panel configured to display an image; a data driver configured to provide a data voltage to the display panel and having a precharge circuit configured to perform a precharge operation; and a timing controller configured to control the data driver, wherein the precharge circuit generates a precharge voltage based on a precharge signal provided in a horizontal blanking period, and controls the precharge circuit to output or not output the precharge voltage based on a precharge selection signal.

[0009] The precharge circuit may include: a precharge voltage generator configured to generate a precharge voltage based on a precharge signal; and a precharge voltage transfer circuit configured to transfer the precharge voltage to an output channel of the data driver based on a precharge selection signal.

[0010] The precharge voltage transfer circuit may include a precharge switch connected to a charge sharing switch, the charge sharing switch performing a charge sharing operation such that charges are shared between at least two of the output channels of the data driver.

[0011] The precharge operation and the charge sharing operation may partially overlap.

[0012] The precharge operation and the charge sharing operation may be ended at the same time.

[0013] The precharge voltage generator may include a latch configured to generate a precharge voltage based on a precharge signal, a DA converter, and an amplifier.

[0014] The DA converter may be the same as the DA converter included in the data driver, or may have a bit number that is at least 1 bit less than that of the DA converter included in the data driver.

[0015] The precharge voltage generator may include a selector configured to select one of the gamma voltages output from the gamma voltage generator based on the precharge signal and output the selected gamma voltage as the precharge voltage.

[0016] The timing controller may include a precharge signal generator for generating a precharge signal and a precharge selection signal generator for generating a precharge selection signal, wherein the precharge selection signal generator generates the precharge selection signal based on an average value of an absolute value obtained by subtracting a current row data signal from a previous row data signal and an average value of an absolute value obtained by subtracting a current row data signal from a previous precharge data signal.

[0017] In another aspect of the present invention, a method for driving a display device (the display device includes: a display panel configured to display an image; a data driver configured to provide a data voltage to the display panel and having a precharge circuit configured to perform a precharge operation; and a timing controller configured to control the data driver) includes: generating a current precharge signal for generating a current precharge voltage based on an average value of a current row data signal and an average value of a previous row data signal; generating a precharge selection signal for determining whether to output a precharge voltage based on an average value of an absolute value obtained by subtracting the current row data signal from the previous row data signal and an average value of an absolute value obtained by subtracting the current row data signal from the previous precharge signal; and outputting the precharge voltage through an output channel of the data driver based on the current precharge signal and the precharge selection signal.

[0018] The output of the precharge voltage may partially overlap with charge sharing for sharing charges between at least two of the output channels of the data driver.

[0019] The output of the precharge voltage and the charge sharing can be ended at the same time.

[0020] The present invention can maximize the effect of reducing current consumption by performing adaptive precharging operations regardless of image modes without degrading the performance of a specific device (e.g., deterioration in driving performance when outputting data voltage, deterioration in performance of a touch sensor due to a high impedance period, etc.). BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a block diagram schematically showing a configuration of a display device, and Figure 2 It is schematically shown Figure 1 Configuration diagram of sub-pixels in .

[0022] Figure 3A and Figure 3B is a diagram showing an example of arrangement of a gate-in-panel type gate driver, and Figure 4 and Figure 5 is a diagram showing a configuration of devices related to a gate driver of a gate type in a panel.

[0023] Figure 6 is a diagram schematically showing internal blocks of a timing controller and a data driver according to a first embodiment of the present invention, Figure 7 is a diagram showing in detail some internal blocks of a data driver according to a first embodiment of the present invention, Figure 8 1 is a diagram showing a portion of an EPI (Embedded Panel Interface) signal and a driving waveform of a device according to a first embodiment of the present invention, Fig. 9 is a diagram showing an operation state of a switch when a charge sharing and pre-charging operation is performed according to the first embodiment of the present invention, and Fig.10 is a diagram showing in detail some internal blocks of a data driver according to a modified example of the first embodiment of the present invention.

[0024] Fig.11 is a diagram specifically showing some internal blocks of the timing controller according to the first embodiment of the present invention, and Fig.12 Is used to describe Fig.11 A flowchart of the operation of the timing controller is shown in FIG.

[0025] Figure 13 to Figure 17 is a diagram showing an example of a mode in which a precharge operation is performed, and Figure 18 to Figure 21 is a diagram showing an example of a mode in which a precharge operation is not performed.

[0026] Fig. 22 and Fig.23is a diagram specifically showing some internal blocks of a data driver according to a second embodiment of the present invention, Fig.24 is a portion of the EPI signal and driving waveform of the device according to the second embodiment of the present invention, Fig.25 is a diagram showing an operation state of a switch when a charge sharing and pre-charging operation is performed according to a second embodiment of the present invention, and Fig.26 is a diagram specifically showing some internal blocks of a data driver according to a modified example of the second embodiment of the present invention.

[0027] Fig. 27 is a diagram specifically showing some internal blocks of a timing controller according to a second embodiment of the present invention, and Fig.28 Is used to describe Fig. 27 A flowchart of the operation of the timing controller is shown in FIG. DETAILED DESCRIPTION

[0028] The display device according to the present invention can be implemented as a television, a video player, a personal computer (PC), a home theater, an automotive electrical device, a smart phone, etc., but is not limited thereto. The display device according to the present invention can be implemented as a light emitting display device (LED), a quantum dot display device (QDD) or a liquid crystal display device (LCD), etc.

[0029] Figure 1 is a block diagram schematically showing a configuration of a display device, and Figure 2 It is schematically shown Figure 1 Configuration diagram of sub-pixels in .

[0030] like Figure 1 and Figure 2 As shown in , the display device may include an image providing unit 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, and the like.

[0031] The image providing unit 110 (a TV set or a host system) may output various driving signals, and an image data signal provided from the outside or stored in an internal memory. The image providing unit 110 may provide a data signal and various driving signals to the timing controller 120.

[0032] The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the gate driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, and various synchronization signals. The timing controller 120 may provide the data signal DATA provided from the image providing unit 110 together with the data timing control signal DDC to the data driver 140. The timing controller 120 may take the form of an integrated circuit (IC) and be mounted on a printed circuit board, but is not limited thereto.

[0033] The gate driver 130 may output a gate signal (or a scan signal) in response to a gate timing control signal GDC provided from the timing controller 120. The gate driver 130 may provide the gate signal to the sub-pixels included in the display panel 150 through the gate lines GL1 to GLm. The gate driver 130 may take the form of an IC or may be directly formed on the display panel 150 through a gate-in-panel method, but is not limited thereto.

[0034] The data driver 140 may sample and latch the data signal DATA in response to the data timing control signal DDC provided from the timing controller 120, convert the digital data signal into an analog data voltage based on the gamma reference voltage, and output the analog data voltage. The data driver 140 may provide the data voltage to the sub-pixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may take the form of an IC and be mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

[0035] The display panel 150 can display an image in response to a gate signal and a data voltage. The display panel 150 can be manufactured based on a rigid or flexible substrate (e.g., glass, silicon, or polyimide, etc.). The display panel 150 can display an image based on a pixel including a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or a pixel including a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. A sub-pixel SP can receive a data voltage and a gate signal through a first data line DL1 and a first gate line GL1. Although the sub-pixel SP can be configured to have various shapes, it is simply illustrated here as a block. In addition, the display panel 150 may include a touch sensor (or touch screen) capable of sensing a user's touch.

[0036] The timing controller 120, the gate driver 130, and the data driver 140 have been described above as separate components. However, one or more of the timing controller 120, the gate driver 130, and the data driver 140 may be integrated into one IC depending on the implementation method of the display device.

[0037] Figure 3A and Figure 3B is a diagram showing an example of arrangement of a gate type gate driver in a panel, and Figure 4 and Figure 5 is a diagram showing an example of a configuration of a device related to a gate driver of a gate type in a panel.

[0038] like Figure 3A and Figure 3B As shown in FIG. 1 , gate drivers 130 a and 130 b of the gate type in the panel are disposed in the non-display area NA of the display panel 150. Figure 3A As shown in FIG. 1 , the gate drivers 130 a and 130 b may be disposed in the left non-display area NA and the right non-display area NA of the display panel 150. Figure 3B As shown in FIG. 1 , the gate drivers 130 a and 130 b may be disposed in the upper non-display area NA and the lower non-display area NA of the display panel 150 .

[0039] Although the gate drivers 130a and 130b are illustrated and described as being disposed in the non-display area NA located on the left and right sides or upper and lower sides of the display area AA as an example, only one gate driver may be disposed on the left, right, upper, or lower side.

[0040] like Figure 4 As shown in FIG. 1 , the gate driver of the gate type in the panel may include a shift register 131 and a level shifter 135. The level shifter 135 may be based on the timing controller 120 and the power supply unit (such as Figure 5 The clock signal Clks and the start signal Vst are generated by using the signal and voltage output by the power supply unit 180 in the power supply unit 180. The clock signal Clks may be generated in the form of K (K is an integer equal to or greater than 2) phases (eg, 2 phases, 4 phases, or 8 phases) having different phases.

[0041] The shift register 131 operates based on the signals Clks and Vst output from the level shifter 135, and can output gate signals Gate[1] to Gate[m] for turning on or off transistors formed in the display panel. The shift register 131 can take the form of a thin film on the display panel according to the gate method in the panel. Accordingly, Figure 3A and Figure 3B 130 a and 130 b in the figure may correspond to the shift register 131 .

[0042] like Figure 4 and Figure 5As shown in , the level shifter 135 may be independently formed in the form of an IC (different from the shift register 131), or may be included in a power supply unit 180 that generates and outputs power required to drive the display panel. However, this is just an example, and the level shifter is not limited thereto.

[0043] Figure 6 is a diagram schematically showing internal blocks of a timing controller and a data driver according to a first embodiment of the present invention, Figure 7 is a diagram showing in detail some internal blocks of a data driver according to a first embodiment of the present invention, Figure 8 is a diagram showing a portion of an EPI signal and a driving waveform of a device according to a first embodiment of the present invention, Fig. 9 is a diagram showing an operation state of a switch when a charge sharing and pre-charging operation is performed according to the first embodiment of the present invention, and Fig.10 is a diagram showing in detail some internal blocks of a data driver according to a modified example of the first embodiment of the present invention.

[0044] like Figure 6 As shown in FIG. 1 , the timing controller 120 and the data driver 140 transmit and receive various signals through an embedded panel interface (EPI) based on an embedded clock.

[0045] The data driver 140 may include a control circuit (S2P) 141, a shift register (SR) 142, a latch (LAT) 143, a DA converter (DAC) 144, a multi-channel output circuit 145, a precharge circuit (PCC) 148, etc. However, Figure 6 The internal blocks of the data driver 140 shown in FIG. 1 are merely examples and are not limited thereto.

[0046] The control circuit 141 may perform operations of controlling the shift register 142, the latch 143, the DAC 144, and the multi-channel output circuit 145. The shift register 142 and the latch 143 may perform operations of storing parallel digital data signals transmitted through the EPI as serial digital data signals. The DAC 144 and the multi-channel output circuit 145 may perform operations of converting digital data signals into analog data voltages and outputting the analog data voltages. The precharge circuit 148 may perform operations of generating and outputting precharge voltages.

[0047] The timing controller 120 may include a precharge controller 128. The precharge controller 128 included in the timing controller 120 may generate and output a signal for controlling a precharge circuit 148 included in the data driver 140. Hereinafter, an example in which the precharge controller 128 outputs a signal for controlling the precharge circuit 148 through the EPI will be described. However, the precharge controller 128 may directly control the precharge circuit 148 through a separate signal line.

[0048] like Figure 7 As shown in FIG. 1 , the precharge controller 128 includes a precharge voltage generator 148 a that generates a precharge voltage and a precharge voltage transfer unit 148 b that transfers the precharge voltage to output channels CH1 to CHn of the data driver.

[0049] The precharge voltage generator 148 a may be implemented in a manner similar to or identical to components included in the latch 143 , the DAC 144 , and the multi-channel output circuit 145 , and the precharge voltage transfer unit 148 b may be implemented as a switch.

[0050] The precharge voltage generator 148a may generate and output a precharge voltage based on a precharge data signal output by the control circuit 141. For example, according to the first embodiment of the present invention, the precharge voltage generator 148a may be implemented using a 2-line latch, an M-1-bit DAC, and an amplifier AMP.

[0051] The 2-line latch included in the precharge voltage generator 148a may be configured in the same manner as the 2-line latch included in the latch 143 and receive an 8-bit digital data signal from the control circuit 141. The 2-line latch may include first and second latches, but is not limited thereto.

[0052] The M-1-bit DAC included in the precharge voltage generator 148a may be configured in the same manner as the N-bit DAC included in the DAC 144. However, the M-1-bit DAC included in the precharge voltage generator 148a may have a lower resolution than the N-bit DAC included in the DAC 144.

[0053] This is because the precharge voltage generator 148a does not provide voltages of various levels for grayscale expression like data voltages. In addition, this is because even if the M-1 bit DAC is configured as a DAC for realizing half of the full grayscale, it is sufficient to generate and output the precharge voltage. Accordingly, when N in the N-bit DAC is 8 bits, the M in the M-1 bit DAC can be equal to N, but can be 7 bits or less. However, this is just an example, and the present invention is not limited to this.

[0054] The amplifier AMP included in the precharge voltage generator 148a may have the same configuration as the amplifier AMP included in the multi-channel output circuit 145. However, the amplifier AMP included in the precharge voltage generator 148a needs to have a current driving capability superior to that of the amplifier AMP included in the multi-channel output circuit 145 (or the higher the performance, the better).

[0055] The precharge voltage transfer unit 148b may transfer the precharge voltage output from the precharge voltage generator 148a to the output channels CH1 to CHn of the data driver based on the precharge selection signal output by the control circuit 141. For example, according to the first embodiment of the present invention, the precharge voltage transfer unit 148b may be implemented as precharge switches SW2a and SW2b.

[0056] The precharge switches SW2a and SW2b included in the precharge voltage transfer unit 148b may be configured as transistors in the same manner as the charge sharing switches SW1a and SW1b included in the multi-channel output circuit 145. The charge sharing switches SW1a and SW1b may be defined as a charge sharing unit. When the precharge switches SW2a and SW2b are turned on by the precharge selection signal, the precharge voltage is output, and when the precharge switches SW2a and SW2b are not turned on, the precharge voltage is not output.

[0057] For example, the charge sharing switches SW1a and SW1b included in the multi-channel output circuit 145 may include first charge sharing switches SW1a commonly connected to the odd-numbered output channels CH1, CH3, ..., CHn-1 of the data driver, and second charge sharing switches SW1b commonly connected to the even-numbered output channels CH2, CH4, ..., CHn. In addition, the precharge switches SW2a and SW2b included in the precharge voltage transfer unit 148b may include a first precharge switch SW2a connected to the first charge sharing switch SW1a and a second precharge switch SW2b connected to the second charge sharing switch SW1b.

[0058] The first precharge switch SW2a included in the precharge voltage transfer unit 148b can transfer the precharge voltage to the odd-numbered output channels CH1, CH3, ..., CHn-1 of the data driver through the first charge sharing switch SW1a. In addition, the second precharge switch SW2b included in the precharge voltage transfer unit 148b can transfer the precharge voltage to the even-numbered output channels CH2, CH4, ..., CHn of the data driver through the second charge sharing switch SW1b.

[0059] Meanwhile, in the first embodiment, the multi-channel output circuit 145 includes the amplifier AMP, the output multiplexer MUX, and the charge sharing switches SW1 a and SW1 b as an example, but is not limited thereto.

[0060] like Figure 8 As shown in , the signals transmitted through the EPI may include a data signal RGB Data, a precharge selection signal P / C_SEL, a precharge data signal P / C-Data(n), a clock training signal CT, a control signal CTR, etc. In addition to the data signal RGB Data for displaying an image of the Nth row Line(n) or an image of the (N+1)th row Line(n+1), the precharge selection signal P / C_SEL, the precharge data signal P / C-Data(n), the clock training signal CT, and the control signal CTR may all be transmitted in the horizontal blank period H-Blank.

[0061] like Figure 7 and Figure 8 As shown in , the latch 143 operates in response to the logic high latch signal Latch generated in the horizontal blank period H-Blank, and can latch the data signal RGB Data. The charge sharing switches SW1a and SW1b can perform charge sharing in response to the logic high charge sharing signal C / S_SW1 generated in the horizontal blank period H-Blank, so that at least two output channels of the output channels CH1 to CHn of the data driver share charges. The precharge switches SW2a and SW2b can transmit the precharge voltage to the output channels CH1 to CHn of the data driver in response to the logic high precharge signal P / C_SW2 generated in the horizontal blank period H-Blank.

[0062] Meanwhile, the precharge signal P / C_SW2 at logic high or logic low may be generated in response to the precharge selection signal P / C_SEL, and the level of the precharge voltage may vary in response to the precharge data signal P / C-Data(n).

[0063] As from Figure 8 It can be determined that when a precharge selection signal P / C_SEL of 1 rather than 0 is applied, the precharge voltage can be transmitted to the output channels CH1 to CHn of the data driver. In addition, the transition of the precharge signal P / C_SW2 to a logic high can be synchronized with the start time (rising edge) of the latch signal Latch, and the transition of the precharge signal P / C_SW2 to a logic low can be synchronized with the end time (falling edge) of the charge sharing signal C / S_SW1. In other words, the precharge operation can partially overlap with the charge sharing operation and can end at the same time as the charge sharing operation. However, this is just an example.

[0064] exist Figure 8 In the figure, the waveform represented by "Last-Data@Driving Mode, P / C_SEL=0" shows the output state when the precharge selection signal P / C_SEL of 0 is applied when the data voltage is output according to the driving mode of the data driver 140. In addition, the waveform represented by "Pre-Data@Driving Mode, P / C_SEL=1" shows the output state when the precharge selection signal P / C_SEL of 1 is applied when the data voltage is output according to the driving mode of the data driver 140. In addition, the waveform represented by "Hi-Z@C / S Mode, P / C_SEL=0" shows the output state when the precharge selection signal P / C_SEL of 0 is applied during the high impedance period (when the data voltage is not output) caused by the charge sharing mode of the data driver 140.

[0065] As reference Figure 8 and Fig. 9 It can be determined that the time when the charge sharing operation and the precharge operation occur can partially overlap (there can be a time period when the charge sharing operation and the precharge operation occur simultaneously). This is because the precharge voltage is transmitted to the output channels CH1 to CHn of the data driver through the charge sharing switches SW1a and SW1b. Accordingly, the charge sharing switches SW1a and SW1b and the precharge switches SW2a and SW2b can have a time period when they are turned on simultaneously.

[0066] Meanwhile, the example in which the charge sharing switches SW1a and SW1b included in the multi-channel output circuit 145 are respectively connected to the odd-numbered output channels CH1, CH3, ..., CHn-1 and the even-numbered output channels CH2, CH4, ..., CHn has been described above. In this method, charge sharing for all output channels can be performed by dividing the output channels into odd-numbered output channels and even-numbered output channels. However, as Fig.10 As shown in , a charge sharing operation can be performed between three adjacent odd-numbered output channels and three adjacent even-numbered output channels. This scheme will be described below as a modified example.

[0067] like Fig.10 As shown in , the charge sharing switches SW1a and SW1b included in the multi-channel output circuit 145 may include a first charge sharing switch SW1a commonly connecting three adjacent odd-numbered output channels CH1, CH3, and CH5 in the data driver and a second charge sharing switch SW1b commonly connecting three adjacent even-numbered output channels CH2, CH4, and CH6. Note that in Fig.10 In FIG, only some charge sharing switches are illustrated due to space limitations.

[0068] In addition, the precharge switches SW2a to SW2j included in the precharge voltage transfer unit 148b may include a first precharge switch SW2a connected to the first charge sharing switch SW1a and a second precharge switch SW2b connected to the second charge sharing switch SW1b. Fig.10 In the figure, only some pre-charge switches are illustrated due to space limitation.

[0069] The first precharge switch SW2a included in the precharge voltage transfer unit 148b can transfer the precharge voltage to three adjacent odd-numbered output channels CH1, CH3 and CH5 in the data driver through the first charge sharing switch SW1a. In addition, the second precharge switch SW2b included in the precharge voltage transfer unit 148b can transfer the precharge voltage to the even-numbered output channels CH2, CH4 and CH6 of the data driver through the second charge sharing switch SW1b.

[0070] Meanwhile, the structure according to the modified example of the first embodiment differs from the first embodiment in that precharging and charge sharing can be performed for three adjacent odd-numbered output channels CH1 , CH3 and CH5 and three adjacent even-numbered output channels CH2 , CH4 and CH6 .

[0071] Fig.11 is a diagram specifically showing some internal blocks of the timing controller according to the first embodiment of the present invention, and Fig.12 Is used to describe Fig.11 A flowchart of the operation of the timing controller is shown in FIG.

[0072] like Fig.11 As shown in , the timing controller 120 may include a precharge controller 128 having a precharge data signal generator 123 and a precharge selection signal generator 125 in addition to the line memory 121 .

[0073] The row memory 121 may play a role of storing the data signal Data provided row by row from the outside. The precharge data signal generator 123 may play a role of generating the current precharge data signal P / C-Data(n) based on the average value of the current row data signal and the average value of the previous row data signal. The precharge selection signal generator 125 may play a role of generating the precharge selection signal P / C_SEL based on the average value of the absolute value obtained by subtracting the current row data signal from the previous row data signal and the average value of the absolute value obtained by subtracting the current row data signal from the previous precharge data signal.

[0074] like Fig.12As shown in , the data signal Data provided from the outside may be stored in the line memory line by line (S110). An example of storing the previous line data signal Data(n-1) in the line memory is described below.

[0075] Next, an average value Avg(Data(n-1)) of a previous row data signal stored in the row memory may be calculated (S111), and an average value Avg(Data(n)) of a current row data signal may be calculated simultaneously (S112).

[0076] The average value Avg(Data(n-1)) of the previous row data signal may be calculated based on Equation 1 below, and the average value Avg(Data(n)) of the current row data signal may be calculated based on Equation 2 below.

[0077] [Equation 1]

[0078]

[0079] [Equation 2]

[0080]

[0081] In equations 1 and 2, P represents sub-pixel. Note: Because it is related to the number of data drivers (DIC), RGB data signals and horizontal resolution.

[0082] Next, the current precharge data signal P / C-Data(n) can be generated based on the average value Avg(Data(n)) of the current row data signal and the average value Avg(Data(n-1)) of the previous row data signal (S113). The current precharge data signal P / C-Data(n) can be generated based on the following equation 3.

[0083] [Equation 3]

[0084]

[0085] Next, the difference value Subtract between the previous row data signal Data(n-1) and the current row data signal Data(n) may be calculated (S114), the absolute value ABS of the difference value Subtract may be calculated (S115), and the average value Average of the absolute value (ABS) may be calculated (S116). The first difference value diff_Origin may be calculated through these steps S114 to S116. The first difference value diff_Origin may be calculated based on the following equation 4.

[0086] [Equation 4]

[0087]

[0088] Next, the difference value Subtract between the previous precharge data signal P / C-Data(n-1) and the current row data signal Data(n) can be calculated (S117), the absolute value ABS of the difference value Subtract can be calculated (S118), and the average value Average of the absolute value ABS can be calculated (S119). The second difference value diff_pre can be calculated through these steps S117 to S119. The second difference value diff_pre can be calculated based on the following equation 5.

[0089] [Equation 5]

[0090]

[0091] Next, a precharge selection signal P / C_SEL (S120) may be generated based on whether the difference between the first difference diff_Origin and the second difference diff_pre is greater than 0. Here, when the difference between the first difference diff_Origin and the second difference diff_pre is greater than 0 ("Yes"), a precharge selection signal P / C_SEL of 1 may be generated. That is, a signal for performing a precharge operation may be generated. On the other hand, when the difference between the first difference diff_Origin and the second difference diff_pre is less than 0 ("No"), a precharge selection signal P / C_SEL of 0 may be generated. That is, a signal for not performing a precharge operation may be generated.

[0092] In the display device according to the first embodiment of the present invention, the size of the precharge data signal (magnitude of the precharge voltage) and whether to perform a precharge operation (precharge operation / no precharge operation) for each image mode can be determined. An example will be described below.

[0093] In the following, Figure 13 to Figure 17 is a diagram showing an example of a mode in which a precharge operation is performed, and Figure 18 to Figure 21 is a diagram showing an example of a mode in which a precharge operation is not performed.

[0094] Fig.13 An example is shown in which a precharge operation can be performed in the case of a subdot mode in which a data signal Data having a stepping stone form is output for each channel and an output position thereof is alternately changed row by row.

[0095] Fig.14An example is shown in which a precharge operation can be performed in a horizontal one-line (H-1Line) mode, in which data signals Data are output on all channels of one line and data signals Data are not output on all channels of the next line, and this output mode is changed alternately from line to line.

[0096] Fig.15 An example is shown in which a precharge operation can be performed in the case of a sub-2-dot mode in which a data signal Data having a stepping stone form is output for two channels and an output position thereof is alternately changed row by row.

[0097] Fig.16 An example is shown in which the precharge operation can be performed in the case of a dot mode in which a data signal Data in a stepping stone form is output for each RGB channel and an output position thereof is alternately changed row by row.

[0098] Fig.17 An example is shown in which the precharge operation can be performed in the case of a random mode in which data signals Data having different gray levels are randomly output over all channels.

[0099] As described above, according to the first embodiment, Figure 13 to Figure 16 The precharge operation is performed in the mode shown in the figure, wherein the relationship expression diff_Origin-diff_pre>0, the precharge data signal value (P / C-data(n): 127 or 125) and the precharge selection signal value (P / C_SEL: 1) shown on the right can be used to determine the Figure 13 to Figure 16 The mode shown.

[0100] Fig.18 An example is shown in which the precharge operation may not be performed in the case of a red mode in which the data signal Data is output only to the R channel over all rows.

[0101] Fig.19 An example is shown in which the precharge operation may not be performed in the case of a green mode in which the data signal Data is output only to the G channel over all rows.

[0102] Fig. 20 An example is shown in which the precharge operation may not be performed in the case of a full grayscale mode consisting of red, green, and blue colors in which the data signal Data is output to all rows and all channels.

[0103] Fig.21An example is shown in which the precharge operation may not be performed in the case of a vertical sub-mode in which the data signal Data in the form of a stepping stone is output for each channel in a vertical direction and its output position is maintained.

[0104] As described above, according to the first embodiment, Figure 18 to Figure 21 The mode shown does not perform a precharge operation, which can be determined by the relationship expression diff_Origin-diff_pre<0, the precharge data signal value (P / C-data(n): 84, 41, 254 or 127) and the precharge selection signal value (P / C_SEL: 0) shown on the right. Figure 18 to Figure 21 The mode shown.

[0105] However, Figures 13 to 21 Only some examples are shown in which the precharge operation may or may not be performed depending on the mode, and whether the precharge operation is performed may vary depending on the characteristics (grayscale value) of the data signal or a calculation formula.

[0106] Fig. 22 and Fig.23 is a diagram specifically showing some internal blocks of a data driver according to a second embodiment of the present invention, and Fig.24 is a portion of the EPI signal and driving waveform of the device according to the second embodiment of the present invention. Fig.25 is a diagram showing an operation state of a switch when a charge sharing and pre-charging operation is performed according to a second embodiment of the present invention, and Fig.26 is a diagram specifically showing some internal blocks of a data driver according to a modified example of the second embodiment of the present invention.

[0107] like Fig. 22 and Fig.23 As shown in FIG. 1 , the precharge controller 128 may include a precharge voltage generator 148 a that generates a precharge voltage and a precharge voltage transfer unit 148 b that transfers the precharge voltage to output channels CH1 to CHn of the data driver.

[0108] The precharge voltage generator 148 a may be implemented to select one of the gamma voltages and output a precharge voltage based thereon, and the precharge voltage transfer unit 148 b may be implemented as a switch.

[0109] The precharge voltage generator 148a can select one of the gamma voltages in response to the precharge bit signal P / C_COB output by the control circuit 141 and output a precharge voltage based thereon (i.e., using one of the gamma voltages as the precharge voltage). For example, according to the second embodiment of the present invention, the precharge voltage generator 148a can be implemented as a gamma voltage generator GMA and a selector MUX. However, since the gamma voltage generator GMA corresponds to an existing component that provides a gamma voltage to the data driver 140, the description will be based on such an assumption that the existing component rather than the newly added component will be used as the gamma voltage generator GMA to eliminate the redundant configuration of the device and reduce the cost. The gamma voltage generator GMA can be provided separately. However, hereinafter, an example of using eight gamma tap voltages GMA#1 to GMA#8 by a gamma voltage generator GMA with an existing configuration will be described.

[0110] The gamma voltage generator GMA may include a resistor string R, a decoder DEC, and a buffer BUF. In addition, the gamma voltage generator GMA may be divided into a highest gamma tap voltage output unit GMA#0 outputting a maximum gamma voltage G255, a lowest gamma tap voltage output unit GMA#2 outputting a lowest gamma voltage G0, and a lowest gamma tap voltage output unit GMA#3 outputting a lowest gamma voltage G1. n +1, and the highest gamma tap voltage output unit GMA#0 and the lowest gamma tap voltage output unit GMA#2 n +1 between the intermediate gamma tap voltage output units GMA#1 and GMA#2 outputting gamma voltages G224, G192, ..., G1 n .

[0111] The selector MUX included in the precharge voltage generator 148a may be configured as 2 n :1 multiplexer and connected to the gamma voltage generator GMA, and can perform a selection operation based on the precharge bit signal P / C_COB output from the control circuit 141. n :1 multiplexer, n corresponds to the number of gamma taps to be used in the gamma voltage generator GMA. For example, the selector MUX can select and output the gamma voltage output from one buffer BUF of the first to eighth intermediate gamma tap voltage output units GMA#1 to GMA#8 as the precharge voltage in response to the precharge bit signal P / C_COB.

[0112] The precharge voltage transfer unit 148b may transfer the precharge voltage output from the precharge voltage generator 148a to the output channels CH1 to CHn of the data driver based on the precharge selection signal output by the control circuit 141. For example, according to the second embodiment of the present invention, the precharge voltage transfer unit 148b may be implemented as precharge switches SW2a and SW2b.

[0113] The precharge switches SW2a and SW2b included in the precharge voltage transfer unit 148b may include transistors in the same manner as the charge sharing switches SW1a and SW1b included in the multi-channel output circuit 145. The charge sharing switches SW1a and SW1b may be defined as a charge sharing unit.

[0114] For example, the charge sharing switches SW1a and SW1b included in the multi-channel output circuit 145 may include first charge sharing switches SW1a for connecting odd-numbered output channels CH1, CH3, ..., CHn-1 of the data driver in common, and second charge sharing switches SW1b for connecting even-numbered output channels CH2, CH4, ..., CHn in common. In addition, the precharge switches SW2a and SW2b included in the precharge voltage transfer unit 148b may include a first precharge switch SW2a connected to the first charge sharing switch SW1a and a second precharge switch SW2b connected to the second charge sharing switch SW1b.

[0115] The first precharge switch SW2a included in the precharge voltage transfer unit 148b can transfer the precharge voltage to the odd-numbered output channels CH1, CH3, ..., CHn-1 of the data driver through the first charge sharing switch SW1a. In addition, the second precharge switch SW2b included in the precharge voltage transfer unit 148b can transfer the precharge voltage to the even-numbered output channels CH2, CH4, ..., CHn of the data driver through the second charge sharing switch SW1b.

[0116] like Fig.24 As shown in , the signals transmitted through EPI may include data signals RGB Data, precharge selection signals P / C_SEL, precharge bit signals P / C_COB, clock training signals CT, and control signals CTR, etc. In addition to the data signal RGB Data used to display the image of the Nth line Line(n) or the image of the (N+1)th line Line(n+1), the precharge selection signal P / C_SEL, the precharge data signal P / C-Data(n), the clock training signal CT, and the control signal CTR can all be transmitted in the horizontal blank period H-Blank.

[0117] like Figure 22 to Figure 24As shown in , the latch 143 operates in response to the logic high latch signal Latch generated in the horizontal blank period H-Blank, and can latch the data signal RGB Data. The charge sharing switches SW1a and SW1b can perform charge sharing in response to the logic high charge sharing signal C / S_SW1 generated in the horizontal blank period H-Blank, so that at least two of the output channels CH1 to CHn of the data driver share charges. The precharge switches SW2a and SW2b can transmit the precharge voltage to the output channels CH1 to CHn of the data driver in response to the logic high precharge signal P / C_SW2 generated in the horizontal blank period H-Blank.

[0118] Meanwhile, the precharge signal P / C_SW2 at logic high or logic low may be generated in response to the precharge selection signal P / C_SEL, and the level of the precharge voltage may vary in response to the precharge bit signal P / C_COB.

[0119] As from Fig.24 It can be determined that when the precharge selection signal P / C_SEL is applied as 1 instead of 0, the precharge voltage can be transmitted to the output channels CH1 to CHn of the data driver. In addition, the transition of the precharge signal P / C_SW2 to logic high can be synchronized with the start time (rising edge) of the latch signal Latch, and the transition of the precharge signal P / C_SW2 to logic low can be synchronized with the end time (falling edge) of the charge sharing signal C / S_SW1. However, this is just an example.

[0120] exist Fig.24 In the figure, the waveform represented by “Last-Data@Driving Mode, P / C_SEL=0” shows the output state when the precharge selection signal P / C_SEL is applied as 0 when the data voltage is output according to the driving mode of the data driver 140. In addition, the waveform represented by “Pre-Data@Driving Mode, P / C_SEL=1” shows the output state when the precharge selection signal P / C_SEL is applied as 1 when the data voltage is output according to the driving mode of the data driver 140. The waveform represented by “Hi-Z@C / S Mode, P / C_SEL=0” shows the output state when the precharge selection signal P / C_SEL is applied as 0 during the high impedance period (when the data voltage is not output) caused by the charge sharing mode of the data driver 140.

[0121] As reference Fig.24 and Fig.25It can be determined that the time when the charge sharing operation and the precharge operation occur can partially overlap. This is because the precharge voltage is transmitted to the output channels CH1 to CHn of the data driver through the charge sharing switches SW1a and SW1b. Accordingly, the charge sharing switches SW1a and SW1b and the precharge switches SW2a and SW2b can have a time period in which they are simultaneously turned on.

[0122] Meanwhile, the example in which the charge sharing switches SW1a and SW1b included in the multi-channel output circuit 145 are respectively connected to the odd-numbered output channels CH1, CH3, ..., CHn-1 and the even-numbered output channels CH2, CH4, ..., CHn has been described above. In this method, charge sharing for all output channels can be performed by dividing the output channels into odd-numbered output channels and even-numbered output channels. However, as Fig.26 As shown in , a charge sharing operation can be performed between three adjacent odd-numbered output channels and three adjacent even-numbered output channels. This scheme will be described below as a modified example.

[0123] like Fig.26 As shown in , the charge sharing switches SW1a and SW1b included in the multi-channel output circuit 145 may include a first charge sharing switch SW1a commonly connecting three adjacent odd-numbered output channels CH1, CH3, and CH5 in the data driver and a second charge sharing switch SW1b commonly connecting three adjacent even-numbered output channels CH2, CH4, and CH6. Note that in Fig.26 In FIG, only some charge sharing switches are illustrated due to space limitations.

[0124] In addition, the precharge switches SW2a to SW2j included in the precharge voltage transfer unit 148b may include a first precharge switch SW2a connected to the first charge sharing switch SW1a and a second precharge switch SW2b connected to the second charge sharing switch SW1b. Fig.26 In the figure, only some pre-charge switches are illustrated due to space limitation.

[0125] The first precharge switch SW2a included in the precharge voltage transfer unit 148b can transfer the precharge voltage to three adjacent odd-numbered output channels CH1, CH3 and CH5 in the data driver through the first charge sharing switch SW1a. In addition, the second precharge switch SW2b included in the precharge voltage transfer unit 148b can transfer the precharge voltage to the even-numbered output channels CH2, CH4 and CH6 of the data driver through the second charge sharing switch SW1b.

[0126] Meanwhile, the structure according to the modified example of the second embodiment differs from the second embodiment in that precharging and charge sharing can be performed for three adjacent odd-numbered output channels CH1 , CH3 and CH5 and three adjacent even-numbered output channels CH2 , CH4 and CH6 .

[0127] Fig. 27 is a diagram specifically showing some internal blocks of a timing controller according to a second embodiment of the present invention, and Fig.28 Is used to describe Fig. 27 A flowchart of the operation of the timing controller is shown in FIG.

[0128] like Fig. 27 As shown in , the timing controller 120 may include a precharge controller 128 having a precharge bit signal generator 124 and a precharge selection signal generator 125 in addition to the line memory 121 .

[0129] The row memory 121 may play a role of storing the data signal Data provided row by row from the outside. The precharge bit signal generator 124 may play a role of generating the precharge bit signal P / C-COB based on the average value of the current row data signal and the average value of the previous row data signal. The precharge selection signal generator 125 may play a role of generating the precharge selection signal P / C_SEL based on the average value of the absolute value obtained by subtracting the current row data signal from the previous row data signal and the average value of the absolute value obtained by subtracting the current row data signal from the previous precharge data signal.

[0130] like Fig.28 As shown in , the data signal Data provided from the outside may be stored in the line memory line by line (S210). An example of storing the previous line data signal Data (n-1) in the line memory is described below.

[0131] Next, an average value Avg(Data(n-1)) of a previous row data signal stored in the row memory may be calculated (S211), and an average value Avg(Data(n)) of a current row data signal may be calculated simultaneously (S212).

[0132] The average value Avg(Data(n-1)) of the previous row data signal may be calculated based on Equation 1 described in the first embodiment, and the average value Avg(Data(n)) of the current row data signal may be calculated based on Equation 2 described in the first embodiment.

[0133] Next, the current precharge data signal P / C-Data(n) can be generated based on the average value Avg(Data(n)) of the current row data signal and the average value Avg(Data(n-1)) of the previous row data signal (S213). The current precharge data signal P / C-Data(n) can be generated based on Equation 3 described in the first embodiment.

[0134] Next, the difference value Subtract between the previous row data signal Data(n-1) and the current row data signal Data(n) may be calculated (S214), the absolute value ABS of the difference value Subtract may be calculated (S215), and the average value Average of the absolute value ABS may be calculated (S216). The first difference value diff_Origin may be calculated through these steps S214 to S216. The first difference value diff_Origin may be calculated based on equation 4 described in the first embodiment.

[0135] Next, the difference value Subtract between the previous precharge data signal P / C-Data(n-1) and the current row data signal Data(n) may be calculated (S217), the absolute value ABS of the difference value Subtract may be calculated (S218), and the average value Average of the absolute value ABS may be calculated (S219). The second difference value diff_pre may be calculated through these steps S217 to S219. The second difference value diff_pre may be calculated based on equation 5 described in the first embodiment.

[0136] Next, a precharge selection signal P / C_SEL (S220) may be generated based on whether the difference between the first difference diff_Origin and the second difference diff_pre is greater than 0. Here, when the difference between the first difference diff_Origin and the second difference diff_pre is greater than 0 ("Yes"), a precharge selection signal P / C_SEL of 1 may be generated. That is, a signal for performing a precharge operation may be generated. On the other hand, when the difference between the first difference diff_Origin and the second difference diff_pre is less than 0 ("No"), a precharge selection signal P / C_SEL of 0 may be generated. That is, a signal for not performing a precharge operation may be generated.

[0137] Next, the difference value Subtract between the current row data signal Data(n) and the current precharge data signal P / C-Data(n) can be calculated (S221), the absolute value ABS of the difference value Subtract can be calculated (S222), and the minimum value Min of the absolute value ABS can be selected (S223). The precharge bit signal P / C_COB can be finally selected and output through the minimum value selection step S223.

[0138] When calculating the difference Subtract between the current row data signal Data(n) and the current precharge data signal P / C-Data(n), the gamma tap voltage (Data(n) for each GMA tap) may be referenced to more accurately determine the voltage value of the current row data signal Data(n). The gamma tap voltage (Data(n) for each GMA tap) may be an analog voltage value or a digital data value, but is not limited thereto.

[0139] Hereinafter, an example of a process for selecting the precharge bit signal P / C_COB based on the above method is shown in the following Table 1. However, in the following Table 1, it is assumed that the precharge bit signal P / C_COB is 3 bits as an example.

[0140] [Table 1]

[0141]

[0142] As can be determined from Table 1, the absolute value ABS(Data(n)-(P / C-Data(n)) of the difference between the current row data signal Data(n) and the current precharge data signal P / C-Data(n) can be calculated as "6, 38, 102, 166, and 214". In addition, as described above, the minimum value among these values ​​is selected as the precharge bit signal P / C_COB, and thus the gamma voltage corresponding to "000" (e.g., 224) can be the precharge voltage.

[0143] As can be determined with reference to the above embodiments, the present invention can predict the output transition amount of the data driver through a process (e.g., comparing the average value of the previous row data signal and the average value of the current row data signal, etc.), determine whether to perform a precharge operation in the direction of the average transition amount of a row, and output data for precharge. In addition, since the data and control signal for precharge are output in the clock training time period (before the control signal is sent) included in the horizontal blank time period, the precharge voltage can be generated and output without using a power supply separately. Therefore, the display device according to the present invention performs an adaptive precharge operation regardless of the image mode, thereby having the advantage of maximizing the effect of reducing current consumption without degrading the performance of a specific device (e.g., the driving performance deteriorates when the data voltage is output, the performance of the touch sensor deteriorates due to the high impedance time period, etc.).

Claims

1. A display device, comprising: a display panel configured to display an image; A data driver is configured to provide a data voltage to a data line of the display panel and has a pre-charging circuit, wherein the pre-charging circuit is configured to: During charge sharing between the data lines, a precharge voltage is generated based on a precharge signal provided in a horizontal blank period, wherein a level of the precharge voltage varies based on the precharge signal, and selectively outputting the precharge voltage during the charge sharing period based on a precharge selection signal; and The timing controller is configured to control the data driver.

2. The display device according to claim 1, wherein: The pre-charging circuit comprises: a precharge voltage generator configured to generate the precharge voltage based on the precharge signal; and The precharge voltage transmission circuit is configured to transmit the precharge voltage to the output channel of the data driver based on the precharge selection signal.

3. The display device according to claim 2, wherein: The precharge voltage transfer circuit includes a precharge switch connected to a charge sharing switch that performs a charge sharing operation such that charges are shared between at least two of the output channels of the data driver.

4. The display device according to claim 3, wherein: Generating the precharge voltage and the charge sharing operation are ended simultaneously.

5. The display device according to claim 2, wherein: The precharge voltage generator includes a latch, a DA converter, and an amplifier configured to generate the precharge voltage based on the precharge signal.

6. The display device according to claim 5, wherein: The DA converter is included in the data driver or has a smaller number of bits than that of a second DA converter included in the data driver.

7. The display device according to claim 2, wherein: The precharge voltage generator includes a selector configured to select one of the gamma voltages output from the gamma voltage generator based on the precharge signal and output the selected gamma voltage as the precharge voltage.

8. The display device according to claim 1, wherein: The timing controller comprises: a precharge signal generator configured to generate the precharge signal; and a precharge selection signal generator, configured to generate the precharge selection signal, The precharge selection signal generator generates the precharge selection signal based on an average of absolute values ​​obtained by subtracting a current row data signal from a previous row data signal and an average of absolute values ​​obtained by subtracting the current row data signal from a previous precharge data signal.

9. A method for driving a display device, the display device comprising: a display panel configured to display an image; a data driver configured to provide a data voltage to the display panel and having a precharge circuit configured to perform a precharge operation; and a timing controller configured to control the data driver, the method comprising: generating a current precharge signal for generating a precharge voltage based on an average value of a current row data signal and an average value of a previous row data signal during charge sharing between data lines of the display device; generating a precharge selection signal for determining whether to output the precharge voltage based on an average value of absolute values ​​obtained by subtracting the current row data signal from the previous row data signal and an average value of absolute values ​​obtained by subtracting the current row data signal from the previous precharge signal; and During the charge sharing period, the precharge voltage is output through the output channel of the data driver based on the current precharge signal and the precharge selection signal, Wherein, the level of the pre-charge voltage changes in response to the current pre-charge signal.

10. The method according to claim 9, wherein: The output of the precharge voltage partially overlaps with charge sharing for sharing charges between at least two of the output channels of the data driver.

11. The method according to claim 10, wherein: The output of the precharge voltage and the charge sharing are terminated simultaneously.

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