Non-volatile static random access memory

Abstract

The present disclosure relates to a non-volatile static random access memory, comprising: a plurality of storage modules, each of which comprises a switch unit, a storage unit and a backup reload unit, the storage unit is used to perform a static random access operation; the backup reload unit comprises two transistors, and one of the two transistors is a ferroelectric field effect transistor, the backup reload unit is used to perform a data backup operation when the memory is powered off, and perform a data reload operation when the memory is powered on; a control module is used to control the transistors in the switch unit and the backup reload unit to perform at least one of the static random access operation, the data backup operation and the data reload operation. The embodiments of the present disclosure can reduce the transistor overhead, reduce the area overhead of the storage module, improve the storage density, and achieve the power consumption of the flying focus level.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of storage technology, and in particular, to a non-volatile static random access memory. BACKGROUND

[0002] In the Internet of Things application, the endurance and energy consumption of edge devices become important indicators of product. On the one hand, due to the demand for energy saving, the device can be in a power-off state in a non-use scenario, thereby reducing the energy loss caused by leakage; on the other hand, in a specific operating environment, the external power supply of the device is in unstable conditions, and there is a possibility of periodic power failure. In addition, due to the intelligent storage and calculation of artificial intelligence, neural network training and other Internet of Things chips, a large amount of data generated at the end needs to be stored and calculated, and the transfer of data between the on-chip calculation unit and the off-chip storage unit consumes a lot of energy, which makes it a research focus to seek on-chip storage solutions.

[0003] The non-volatile static random access memory (nvSRAM) circuit with on-chip local backup can realize data backup before power failure and automatically reload data reload function when power is restored, ensuring that important data is not lost during power failure, effectively solving the energy consumption challenge faced in the Internet of Things application scenario.

[0004] The non-volatile static random access memory array on the chip is mainly composed of non-volatile static random access units. Each unit is composed of two parts: a static random access unit (SRAM) and a non-volatile storage unit, and the two parts form a whole unit through electrical connection. In the process of device power supply from power-on to power-off, the data of the static random access unit is backed up and stored in the non-volatile storage unit; conversely, in the process of device power supply from power-off to power-on, the non-volatile storage unit reloads the data backed up before power failure to the static random access unit.

[0005] Non-volatile static random access memory (SRAM) circuits based on different devices were designed to achieve proximity backup and reload functions using different schemes and mechanisms. For example: RRAM-based SRAM circuit design (see paper A. Lee, Meng Chang, C. Lin, C. Chen, M. Ho, C. Kuo et al., "RRAM-based 7T1R nonvolatile SRAM with 2x reduction in store energy and 94x reduction in restore energy for frequent-off instant-on applications," 2015 Symposium on VLSI Circuits (VLSICircuits), 2015, pp. C76-C77). STT-RAM-based SRAM circuit design (see paper W. Kang, W. Lv, Y. Zhang and W. Zhao, "Low Store Power High-Speed ​​High-Density Nonvolatile SRAM Design With Spin Hall Effect-Driven Magnetic Tunnel Junctions," in IEEE Transactions on...). Nanotechnology, vol.16, no.1, pp.148-154, Jan.2017), Design of non-volatile static random access memory circuit based on PCRAM (see paper H.-.P.Wong, S.Raoux, S.K.M., J.Liang, J.Reifenberg, B.Rajendran et al., "Phase Change Memory," in Proceedings of the IEEE, vol.98, no.12, pp.2201-2227, Dec.2010), etc.

[0006] Non-volatile static random access memory (SRAM) arrays based on different devices exhibit varying properties and performance characteristics. Compared to the aforementioned novel non-volatile memory devices, ferroelectric transistors (FRTs) offer advantages such as low power consumption, high on / off ratio, and good integration with traditional CMOS processes. FRT-based SRAM circuits also offer superior read / write performance.

[0007] Several designs of non-volatile static random access memory arrays based on ferroelectric transistors have been developed. A novel design of a non-volatile static random access memory based on ferroelectric transistors features low cell area overhead, high reliability, and low power consumption, with higher data capacity per unit area, providing a high-density secure storage solution for IoT chip design. The paper X. Li et al., "Enabling Energy-Efficient Nonvolatile Computing with NegativeCapacitance FET," in IEEE Transactions on Electron Devices, vol. 64, no. 8, pp. 3452-3458, Aug. 2017, doi:10.1109 / TED.2017.2716338, requires an additional 8 transistors to implement the circuit's backup function, resulting in significant area overhead. The paper X. Li, K. Ma, S. George, W. Khwa, J. Sampson, S. Gupta et al., "Design of Nonvolatile SRAM with Ferroelectric FETs for Energy-Efficient Backup and Restore," IEEE Transactions on Electron Devices, vol. 64, no. 7, pp. 3037–3040, 2017, describes a nonvolatile static random access memory array design based on ferroelectric transistors to achieve data backup during circuit power-off and reload functionality during power-on. This design requires an additional 4 transistors.

[0008] It is evident that backup circuit designs already exist in related technologies, but these designs suffer from problems such as redundant transistor overhead, large cell area overhead, and low array storage density. Summary of the Invention

[0009] According to one aspect of this disclosure, a non-volatile static random access memory is provided, the memory comprising:

[0010] Multiple storage modules are provided, each including a switching unit, a storage unit, and a backup reload unit. The switching unit is connected to the storage unit and the backup reload unit, and the backup reload unit is connected to the storage unit. The storage unit is used to perform static random access operations to access data. The backup reload unit includes two transistors, one of which is a ferroelectric field-effect transistor. The backup reload unit is used to perform a data backup operation when the memory is powered off, utilizing the polarization characteristics of the ferroelectric field-effect transistor to back up the data in the storage unit, and to perform a data reload operation when the memory is powered on, writing the data in the backup reload unit into the storage unit.

[0011] A control module, connected to each storage module, is used to control the transistors in the switching unit and the backup reload unit to perform at least one of the static random access operation, the data backup operation, and the data reload operation.

[0012] In one possible implementation, controlling the transistors in the switching unit and the backup reload unit to perform at least one of the static random access operation, the data backup operation, and the data reload operation includes:

[0013] The gate voltage of the ferroelectric field-effect transistor in the backup reload unit is controlled to a preset voltage, another transistor in the backup reload unit is controlled to be in a turned-off state, the memory unit is controlled to be powered normally, and the static random access operation is performed on the memory unit through the switching unit.

[0014] In one possible implementation, controlling the transistors in the switching unit and the backup reload unit to perform at least one of the static random access operation, the data backup operation, and the data reload operation includes:

[0015] The gate voltage of the ferroelectric field-effect transistor is controlled to a preset voltage, the other transistor in the backup reload unit is controlled to be in a turned-off state, and the source of the other transistor in the backup reload unit is controlled to be at a low level.

[0016] The gate voltage of the ferroelectric field-effect transistor is controlled to be maintained at a low level and a high level for a period of time, and then the gate voltage of the ferroelectric field-effect transistor is controlled to be the preset voltage to perform the data backup operation.

[0017] In one possible implementation, controlling the transistors in the switching unit and the backup reload unit to perform at least one of the static random access operation, the data backup operation, and the data reload operation includes:

[0018] The gate voltage of the ferroelectric field-effect transistor is controlled to a preset voltage, the other transistor in the backup reload unit is controlled to be in the on state, and the source of the other transistor in the backup reload unit is controlled to be at a high level.

[0019] The power supply to the inverters of the memory cells is turned on sequentially to perform the data reload operation.

[0020] In one possible implementation, each memory module further includes a first bit line, a second bit line, a first word line, a second word line, a third word line, and a fourth word line; the switching unit includes a first transistor and a second transistor; the backup reload unit includes a third transistor and a fourth transistor; the third transistor is a ferroelectric field-effect transistor; and the memory unit includes a first inverter and a second inverter, wherein...

[0021] The drain of the first transistor is connected to the first bit line, the gate of the first transistor is connected to the first word line, and the source of the first transistor is connected to the input terminal of the first inverter and the output terminal of the second inverter.

[0022] The drain of the second transistor is connected to the second bit line, the gate of the second transistor is connected to the first word line, and the source of the second transistor is connected to the output of the first inverter, the input of the second inverter, and the drain of the third transistor.

[0023] The third transistor is a ferroelectric transistor. The gate of the third transistor is connected to the second word line. The source of the third transistor is connected to the drain of the fourth transistor. The drain of the third transistor is connected to the output terminal of the first inverter, the input terminal of the second inverter, and the source of the second transistor.

[0024] The gate of the fourth transistor is connected to the third word line, the source of the fourth transistor is connected to the fourth word line, and the drain of the fourth transistor is connected to the source of the third transistor.

[0025] In one possible implementation, controlling the transistors in the switching unit and the backup reload unit to perform at least one of the static random access operation, the data backup operation, and the data reload operation includes:

[0026] The second word line controls the gate voltage of the third transistor to a preset voltage, the third word line controls the fourth transistor to be in a turned-off state, the memory cell is powered normally, and the first word line, the first bit line, and the second bit line control the switching unit to perform the static random access operation on the memory cell.

[0027] In one possible implementation, controlling the transistors in the switching unit and the backup reload unit to perform at least one of the static random access operation, the data backup operation, and the data reload operation includes:

[0028] The second word line controls the gate voltage of the third transistor to a preset voltage, the third word line controls the fourth transistor to be in a turned-off state, and the fourth word line controls the source of the fourth transistor to be at a low level.

[0029] The second word line controls the gate voltage of the third transistor to remain at a low level and a high level for a period of time, and then controls the gate voltage of the third transistor to the preset voltage to perform the data backup operation.

[0030] In one possible implementation, controlling the transistors in the switching unit and the backup reload unit to perform at least one of the static random access operation, the data backup operation, and the data reload operation includes:

[0031] The second word line controls the gate voltage of the third transistor to a preset voltage, the third word line controls the fourth transistor to be in a conducting state, and the fourth word line controls the source of the fourth transistor to be at a high level.

[0032] The power supplies for the second inverter and the first inverter are turned on in sequence to perform the data reload operation.

[0033] In one possible implementation, the preset voltage is less than or equal to half of the power supply voltage of the memory.

[0034] In one possible implementation, the storage modules are electrically connected to form a layout of at least one row and at least one column, wherein the first word lines of the storage modules in the same row are connected, the second word lines are connected, the third word lines are connected, and the fourth word lines are connected, and the first word lines of the storage modules in the same column are connected, and the second word lines are connected.

[0035] In one possible implementation, the control module includes a word line driving circuit and a bit line driving circuit, wherein the word line driving circuit is used to drive the first word line, the second word line, the third word line and the fourth word line of each memory module; and the bit line driving circuit is used to drive the first bit line and the second bit line of each memory module.

[0036] The non-volatile static random access memory (SRAM) of this disclosure includes multiple storage modules. Each storage module includes a switching unit, a storage unit, and a backup reload unit. The storage unit is used to perform static random access operations to access data. The backup reload unit includes two transistors, one of which is a ferroelectric field-effect transistor (FET). The backup reload unit is used to perform a data backup operation when the memory is powered off, using the polarization characteristics of the FET to back up the data in the storage unit. When the memory is powered on, it performs a data reload operation to write the data in the backup reload unit into the storage unit. By implementing the backup reload unit with two transistors, compared to related technologies that use at least four transistors, transistor overhead can be reduced, storage module area overhead can be reduced, storage density can be increased, and femtojoule-level power consumption can be achieved.

[0037] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0038] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0039] Figure 1a A schematic diagram of a non-volatile static random access memory according to an embodiment of the present disclosure is shown.

[0040] Figure 1b The timing diagram for backup and reload of the backup and reload unit is shown.

[0041] Figure 2a A schematic diagram of the circuit symbol for a ferroelectric field-effect transistor is shown. Figure 2b A schematic diagram of the circuit structure of a ferroelectric field-effect transistor is shown.

[0042] Figure 2c A schematic diagram showing the variation of drain-source current-gate-source voltage characteristic curves of a ferroelectric field-effect transistor with polarization state is shown.

[0043] Figure 3 A schematic diagram of the circuit structure of a storage module 110 according to an embodiment of the present disclosure is shown.

[0044] Figure 4 A schematic diagram of a non-volatile static random access memory according to an embodiment of the present disclosure is shown.

[0045] Figure 5a and Figure 5bA schematic diagram of a memory backup operation according to an embodiment of this disclosure is shown.

[0046] Figure 6a , Figure 6b A schematic diagram illustrating data reloading in a memory according to an embodiment of the present disclosure is shown.

[0047] Figure 7 The simulation waveforms of backup data and reload data according to embodiments of this disclosure are shown.

[0048] Figure 8 The diagram illustrates the relationship between the ferroelectric layer thickness of the third transistor in the memory of this disclosure and the backup time, as well as the relationship between the power supply voltage and the backup overload energy.

[0049] Figure 9a A schematic diagram comparing the backup and reload energy of related technologies with embodiments of this disclosure is shown. Figure 9b A schematic diagram illustrating the relationship between the operating frequency and normalized backup energy of the memory in relation to the relevant technologies and the present disclosure is shown.

[0050] Figure 10 A schematic diagram comparing the area of ​​a memory according to an embodiment of this disclosure with that of related technologies is shown. Detailed Implementation

[0051] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0052] In the description of this disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0053] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0054] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0055] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0056] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0057] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0058] Please see Figure 1a , Figure 1a A schematic diagram of a non-volatile static random access memory according to an embodiment of the present disclosure is shown.

[0059] Please see Figure 1b , Figure 1b The timing diagram for backup and reload of the backup and reload unit is shown.

[0060] like Figure 1a As shown, the memory includes:

[0061] Multiple storage modules 110 are provided, each including a switching unit 1110, a storage unit 1120, and a backup reload unit 1130. The switching unit 1110 is connected to the storage unit 1120 and the backup reload unit 1130, and the backup reload unit 1130 is connected to the storage unit 1120. The storage unit 1120 is used to perform static random access operations to access data. The backup reload unit 1130 includes two transistors, one of which is a ferroelectric field-effect transistor. The backup reload unit 1130 is used to perform a data backup operation when the memory is powered off, utilizing the polarization characteristics of the ferroelectric field-effect transistor to back up the data in the storage unit 1120, and to perform a data reload operation when the memory is powered on, writing the data in the backup reload unit 1130 into the storage unit 1120 (e.g., ...). Figure 1b (as shown);

[0062] The control module 20 is connected to each storage module 110 and is used to control the transistors in the switching unit 1110 and the backup reload unit 1130 to perform at least one of the static random access operation, the data backup operation, and the data reload operation.

[0063] The non-volatile static random access memory (SRAM) of this disclosure includes multiple storage modules. Each storage module includes a switching unit, a storage unit, and a backup reload unit. The storage unit is used to perform static random access operations to access data. The backup reload unit includes two transistors, one of which is a ferroelectric field-effect transistor (FET). The backup reload unit is used to perform a data backup operation when the memory is powered off, using the polarization characteristics of the FET to back up the data in the storage unit. When the memory is powered on, it performs a data reload operation to write the data in the backup reload unit into the storage unit. By implementing the backup reload unit with two transistors, compared to related technologies that use at least four transistors, transistor overhead can be reduced, storage module area overhead can be reduced, storage density can be increased, and femtojoule-level power consumption can be achieved.

[0064] This disclosure does not limit the specific implementation of the control module 20. Those skilled in the art can configure it according to actual conditions and needs. In one example, the control module 20 may include a processing component, which includes, but is not limited to, a separate processor, discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device with instruction execution capabilities. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions can be executed through hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0065] First, let's take a look at the ferroelectric field-effect transistor as an example. The ferroelectric field-effect transistor is also known as the ferroelectric gate field-effect transistor (MFSFET, Metal-Ferroelectric-Semiconductor FET), or FeFET. It is based on the MOSFET, but the gate SiO2 insulating material is replaced with a ferroelectric material and / or other metal materials with a high dielectric constant.

[0066] Please see Figure 2a , Figure 2b , Figure 2a A schematic diagram of the circuit symbol for a ferroelectric field-effect transistor is shown. Figure 2b A schematic diagram of the circuit structure of a ferroelectric field-effect transistor is shown.

[0067] In one example, such as Figure 2aAs shown, similar to traditional MOSFET devices, ferroelectric transistors are three-port devices, including a gate, source, and drain. Non-volatile storage is achieved through a ferroelectric layer integrated into the gate. By applying a suitable voltage bias between the gate and source, the positive / negative polarization of the ferroelectric layer manifests as different threshold voltages at the analog level, and at the digital level, it represents the storage of logic information 0 / 1. For an introduction to the data storage of ferroelectric field-effect transistors, please refer to the paper M. Trentzschet al., "A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs," 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 11.5.1-11.5.4, doi:10.1109 / IEDM.2016.7838397.

[0068] In one example, such as Figure 2b As shown, FeFET is essentially a field-effect transistor (FET) with an enhanced gate stack sandwiching an additional ferroelectric (FE) capacitor. A ferroelectric layer and optional metal layer can be included between the gate and the substrate, replacing the silicon dioxide insulating layer found in typical MOSFETs. Current ferroelectric field-effect transistors utilize Zr-doped materials based on HfO2, which has enabled FeFETs to demonstrate compatibility with advanced CMOS processes down to a few nanometers. Furthermore, FeFETs can operate at voltages below 2V, further expanding their application range.

[0069] Please see Figure 2c , Figure 2c A schematic diagram showing the variation of drain-source current-gate-source voltage characteristic curves of a ferroelectric field-effect transistor with polarization state is shown.

[0070] In one example, such as Figure 2c As shown, due to its ferroelectric non-volatility, the threshold voltage Vt of the FeFET can be reconfigured; due to the capacitor properties of iron (Fe), threshold voltage Vt tuning does not consume DC power; and the FeFET also has an extremely high on-off ratio. Exemplarily, in the nvSRAM proposed in this disclosure embodiment, the ferroelectric transistor can be an n-type FeFET. Although the FeFET can exhibit multiple threshold voltages Vt (and therefore multiple ID-VGS curves), its operation is in a simplified binary manner: a positive Vt state and a negative Vt state. In the positive Vt state, the transistor is considered off; in the negative Vt state, the transistor is considered on. To switch from the positive Vt state to the negative Vt state, a positive Vt voltage exceeding the coercive voltage is required. GSSimilarly, by applying a negative V exceeding the negative coercive voltage... GS This triggers the transition from a negative Vt state to a positive Vt state. The coercive voltage can be adjusted by the Fe thickness (TFE) and the Fe capacitance matched to the internal gate capacitance. For example, as the TFE increases from 8nm to 12nm, the coercive voltage increases from 0.4V to 0.75V. GS At the falling or rising edge, the FeFET will enter the negative Vt state or the positive Vt state, respectively. When V GS Within the coercive voltage range, the polarization state of the FeFET remains unchanged. Therefore, for positive Vt and negative Vt, the FeFET operates with either a high drain-to-source channel resistance or a low drain-to-source channel resistance, respectively.

[0071] In one example, such as Figure 2c As shown, the V of an n-type FeFET GS The maximum value is VDD / 2.

[0072] This disclosure does not limit the specific implementation of the control module 20, storage unit 1120, switching unit 1110, and backup reload unit 1130. Those skilled in the art can set them according to actual conditions and needs, as long as the backup reload unit 1130 includes a FeFET and a transistor, and the control module 20 can control the switching unit 1110 and the transistor in the backup reload unit 1130 to perform at least one of the static random access operation, the data backup operation, and the data reload operation.

[0073] In one possible implementation, controlling the transistors in the switching unit 1110 and the backup / reload unit 1130 to perform at least one of the static random access operation, the data backup operation, and the data reload operation may include:

[0074] The gate voltage of the ferroelectric field-effect transistor in the backup reload unit 1130 is controlled to a preset voltage, another transistor in the backup reload unit 1130 is controlled to be in a turned-off state, the storage unit 1120 is controlled to be powered normally, and the static random access operation is performed on the storage unit 1120 through the switching unit 1110.

[0075] For example, the preset voltage is less than or equal to half of the power supply voltage of the memory (VDD / 2). In order to minimize the voltage stress applied to the FE layer in the gate stack of the ferroelectric transistor, the preset voltage can be set to be equal to half of the power supply voltage of the memory in this embodiment of the disclosure.

[0076] For example, the other transistor can be an N-type MOSFET. In this case, the control module 20 can output a low-level voltage to the gate of the other transistor to control the other transistor in the backup reload unit 1130 to be in a turned-off state.

[0077] In this embodiment, the gate voltage of the ferroelectric field-effect transistor in the backup reload unit 1130 is controlled to a preset voltage, another transistor in the backup reload unit 1130 is controlled to be in a turned-off state, and the storage unit 1120 is controlled to be powered normally, so as to realize the static random access operation of the storage unit 1120 through the switching unit 1110.

[0078] In one possible implementation, controlling the transistors in the switching unit 1110 and the backup / reload unit 1130 to perform at least one of the static random access operation, the data backup operation, and the data reload operation may include:

[0079] The gate voltage of the ferroelectric field-effect transistor is controlled to a preset voltage, the other transistor in the backup reload unit 1130 is controlled to be in a turned-off state, and the source of the other transistor in the backup reload unit 1130 is controlled to be at a low level.

[0080] The gate voltage of the ferroelectric field-effect transistor is controlled to be maintained at a low level and a high level for a period of time (they can be the same or different, but it is preferred to set them to be the same for easy control), and then the gate voltage of the ferroelectric field-effect transistor is controlled to the preset voltage to perform the data backup operation.

[0081] In this embodiment, the data backup operation is performed by controlling the gate voltage of the ferroelectric field-effect transistor to a preset voltage, controlling another transistor in the backup reload unit 1130 to be in a turned-off state, controlling the source of the other transistor in the backup reload unit 1130 to be at a low level, controlling the gate voltage of the ferroelectric field-effect transistor to be maintained at a low level and a high level for a period of time respectively, and then controlling the gate voltage of the ferroelectric field-effect transistor to the preset voltage.

[0082] In one possible implementation, controlling the transistors in the switching unit 1110 and the backup / reload unit 1130 to perform at least one of the static random access operation, the data backup operation, and the data reload operation may include:

[0083] The gate voltage of the ferroelectric field-effect transistor is controlled to a preset voltage, another transistor in the backup reload unit 1130 is controlled to be in the on state, and the source of the other transistor in the backup reload unit 1130 is controlled to be at a high level.

[0084] The power supplies of the inverters in the storage unit 1120 are turned on sequentially to perform the data reload operation. For example, if the storage unit 1120 includes a first inverter INV1 and a second inverter INV2, the power supplies of the second inverter INV2 and the first inverter INV1 in the storage unit 1120 are turned on sequentially to perform the data reload operation.

[0085] In this embodiment, the gate voltage of the ferroelectric field-effect transistor is controlled to a preset voltage, another transistor in the backup reload unit 1130 is controlled to be in a conducting state, and the source of the other transistor in the backup reload unit 1130 is controlled to be at a high level; the power supply of the inverter of the memory unit 1120 is turned on in sequence to perform the data reload operation.

[0086] The following provides an example of possible implementations of the storage module 110.

[0087] Please see Figure 3 , Figure 3 A schematic diagram of the circuit structure of a storage module 110 according to an embodiment of the present disclosure is shown.

[0088] In one possible implementation, such as Figure 3 As shown, each storage module 110 further includes a first bit line BL1, a second bit line BLB1, a first word line W1, a second word line B1, a third word line R1, and a fourth word line C1. The switching unit 1110 includes a first transistor T1 and a second transistor T2. The backup reload unit 1130 includes a third transistor T3 and a fourth transistor T4. The third transistor T3 is a ferroelectric field-effect transistor. The storage unit 1120 includes a first inverter INV1 and a second inverter INV2.

[0089] The drain of the first transistor T1 is connected to the first bit line BL1, the gate of the first transistor T1 is connected to the first word line W1, and the source of the first transistor T1 is connected to the input terminal of the first inverter INV1 and the output terminal of the second inverter INV2.

[0090] The drain of the second transistor T2 is connected to the second bit line BLB1, the gate of the second transistor T2 is connected to the first word line W1, and the source of the second transistor T2 is connected to the output of the first inverter INV1, the input of the second inverter INV2, and the drain of the third transistor T3.

[0091] The third transistor T3 is a ferroelectric transistor. The gate of the third transistor T3 is connected to the second word line B1. The source of the third transistor T3 is connected to the drain of the fourth transistor T4. The drain of the third transistor T3 is connected to the output terminal of the first inverter INV1, the input terminal of the second inverter INV2, and the source of the second transistor T2.

[0092] The gate of the fourth transistor T4 is connected to the third word line R1, the source of the fourth transistor T4 is connected to the fourth word line C1, and the drain of the fourth transistor T4 is connected to the source of the third transistor T3.

[0093] The backup overload unit 1130 of this embodiment requires only one FeFET and one transistor. Compared with the related art which uses at least four transistors, it can reduce transistor overhead, reduce the area overhead of the storage module 110, and increase storage density.

[0094] It should be noted that, as Figure 3 As shown, in the memory module, the first transistor T1 and the second transistor T2 are equivalent to switches. Only when the first word line W1 is set to a specific level to turn on the first transistor T1 and the second transistor T2 can the first bit line BL1 and point Q be turned on, and the second bit line BLB1 and point QN be turned on. The third transistor T3 is a ferroelectric transistor, which stores single-bit information by changing the polarization state of the ferroelectric layer. The fourth transistor T4 is equivalent to a switch. Only when the third word line R1 is set to a specific level can the fourth word line C1 and the source of the third transistor T3 be turned on. The first word line W1 controls the conduction and cutoff of the first transistor T1 and the second transistor T2 by controlling its level value. The second word line B1 is usually set to a preset voltage (in this example, the preset voltage is half of the voltage corresponding to the high level, VDD / 2. This level value can keep the threshold voltage of the ferroelectric transistor T3 unchanged) so that the conduction state of the third transistor T3 is determined by the polarization state of its ferroelectric layer. When writing is required, the second word line B1 can be controlled to be set to a high level or grounded to transfer the high and low level states on the memory cell 1120 to the polarization state of the ferroelectric layer. The third word line R1 controls the conduction and cutoff of the fourth transistor T4 by controlling the high and low levels. The fourth word line C1 is set to a high level during data reloading and determines the potential of point QN according to the conduction or cutoff state of the third transistor T3 due to the polarization state of the ferroelectric layer, thereby reloading the polarization state of the ferroelectric layer to the memory cell 1120.

[0095] Specifically, in this example, the first transistor T1, the second transistor T2, and the fourth transistor T4 are all NMOS transistors. When the gate voltage is high, these transistors are turned on; when the gate voltage is low, they are turned off. In this example, the third transistor T3 is an N-type ferroelectric transistor. In this example, the high level is the power supply voltage VDD, and the low level is the ground zero voltage GND. This example uses the aforementioned specific implementation method to better illustrate the workflow and principle of the present invention, and does not imply that the exemplified implementation method is the only implementation method.

[0096] In this embodiment of the invention, without loss of generality, the following state mapping method is selected: the state mapping of the third transistor T3 when the ferroelectric layer is positively polarized and exhibits low resistance conduction is "0", and vice versa is "1"; the state mapping of the first bit line BL1 when the voltage to ground is zero is "0", and the state mapping of the high level is "1". The following discussion is based on the above state mapping method.

[0097] Please see Figure 4 , Figure 4 A schematic diagram of a non-volatile static random access memory according to an embodiment of the present disclosure is shown.

[0098] In one possible implementation, such as Figure 4 As shown, the storage modules 110 are combined into a layout of at least one row and at least one column by means of electrical connection. The first word line W1, the second word line B1, the third word line R1, and the fourth word line C1 of the storage modules 110 in the same row are connected. The first word line BL1 and the second word line BLB1 of the storage modules 110 in the same column are connected.

[0099] In one possible implementation, such as Figure 4 As shown, the control module 20 may include a word line driving circuit and a bit line driving circuit. The word line driving circuit is used to drive the first word line W1, the second word line B1, the third word line R1 and the fourth word line C1 of each memory module. The bit line driving circuit is used to drive the first bit line BL1 and the second bit line BLB1 of each memory module.

[0100] The following is based on Figure 3 , Figure 4 Taking the circuit structure of the storage module 110 shown as an example, this paper exemplifies a possible implementation of the control module 20 controlling the transistors in the switching unit 1110 and the backup reload unit 1130 to perform at least one of the static random access operation, the data backup operation, and the data reload operation.

[0101] In one possible implementation, controlling the transistors in the switching unit 1110 and the backup / reload unit 1130 to perform at least one of the static random access operation, the data backup operation, and the data reload operation may include:

[0102] The second word line B1 controls the gate voltage of the third transistor T3 to a preset voltage, the third word line R1 controls the fourth transistor T4 to be in a turned-off state, the memory cell 1120 is powered normally, and the first word line W1, the first bit line BL1, and the second bit line BLB1 control the switching unit 1110 to perform the static random access operation on the memory cell 1120.

[0103] For example, when performing the static random access operation, the gate voltage of the third transistor T3 is controlled to a preset voltage via the second word line B1, and the fourth transistor T4 is controlled to be in a turned-off state via the third word line R1 (the gate voltage and source voltage of the fourth transistor T4 are maintained at GND). The memory cell 1120 is then powered normally (the two power supply voltages VDDA and VDDB are maintained at VDD). As a result, the fourth transistor T4 is turned off, and the backup reload unit 1130 is in a high-resistance turned-off state. Therefore, the backup reload unit 1130 does not affect the memory cell 1120. For example, in SRAM mode (performing the static random access operation), it is necessary to optimize the power supply voltage and bias voltage of the FeFET, i.e., the gate voltage of the third transistor T3 (the maximum V of the FeFET). GS It is Vdd / 2, such as Figure 2c (As shown). In this process, the gate voltage of the third transistor T3 can be set to ~VDD / 2 to minimize the voltage stress applied to the FE layer in the gate stack. Those skilled in the art can choose a preferred power supply voltage VDD and can accordingly design the FeFET polarization switching hysteresis (such as the hysteresis window width) based on the ferroelectric layer thickness TFE and the capacitor matching between the FE capacitor and the gate capacitor, which is not limited by the embodiments disclosed herein.

[0104] In one possible implementation, controlling the transistors in the switching unit 1110 and the backup / reload unit 1130 to perform at least one of the static random access operation, the data backup operation, and the data reload operation may include:

[0105] The gate voltage of the third transistor T3 is controlled to a preset voltage by the second word line B1, the fourth transistor T4 is controlled to be in a turned-off state by the third word line R1, and the source of the fourth transistor T4 is controlled to be at a low level by the fourth word line C1.

[0106] The second word line B1 controls the gate voltage of the third transistor T3 to remain at a low level and a high level for a period of time, and then controls the gate voltage of the third transistor T3 to the preset voltage to perform the data backup operation.

[0107] Please see Figure 5a and Figure 5b , Figure 5a and Figure 5b A schematic diagram of a memory backup operation according to an embodiment of this disclosure is shown.

[0108] For example, when backing up the data stored in memory cell 1120 to the polarization state of the ferroelectric transistor within the cell, the second word line B1 is first set to a preset potential (VDD / 2 in this example); the level of the third word line R1 is set to GND (0 level in this example), causing the fourth transistor T4 to be turned off; the fourth word line C1 is set to a low level (GND, 0 level in this example). Next, the second word line B1 is held at a low potential (GND, 0 level in this example) and a high potential (VDD, the power supply voltage in this example) for a period of time, and then reset to the preset potential. The data stored in memory cell 1120 is stored through the polarization state of the ferroelectric transistor. This process writes the logic data value from the static random access memory into the ferroelectric transistor in a polarized manner. During this process, the fourth transistor T4 is turned off and the fourth word line C1 is kept low by setting the level of the third word line R1, thereby avoiding the consumption of DC current.

[0109] In this data backup operation, the third word line R1 and the fourth word line C1 of this embodiment are kept at a low level GND to avoid DC power consumption, and the first transistor T1 and the second transistor T2 of the switching unit 1110 are turned off by setting the first word line W1 to GND, and the second word line B1 is initially set to VDD / 2.

[0110] For example, such as Figure 5a and Figure 5b As shown, when the backup operation begins, the second word line B1 is first set to GND in step 1, then set to VDD in step 2, and then returns to its original value, i.e., the preset voltage VDD / 2.

[0111] For example, such as Figure 5a and Figure 5b There are two data backup scenarios: '0' backup and '1' backup. The backups of bits '0' and '1' occur in different steps (step-1 or step-2).

[0112] In one example, such as Figure 5aAs shown, if Q and QN are equal to "1" (VDD) and "0" (GND) respectively, then the second word line B1 is lowered to GND so that the VDD of the FeFET is lowered. GS The polarization is zero, thus ensuring no change in the polarization state of the third transistor T3 in step 1. Next, in step 2, the second word line B1 is raised to VDD so that the V of the FeFET... GS This is VDD, which triggers a supercoercive voltage at the internal FE layer. Therefore, the FeFET can be polarized to a positive polarization state with a negative Vt, resulting in a low drain-source channel resistance.

[0113] In one example, such as Figure 5b As shown, if Q and QN are equal to "0" (GND) and "1" (VDD) respectively, then in step 1, the second word line B1 is lowered to GND so that the VDD of the FeFET is lowered. GS The voltage is -VDD, which exceeds the negative coercivity voltage. Therefore, the FeFET will be polarized negatively with positive Vt, resulting in a high drain-source channel resistance. Next, in step 2, the second word line B1 is raised to Vdd, resulting in zero V. GS Furthermore, there was no change in the polarization state of the FeFET.

[0114] After these two steps, the second word line B1 is returned to the preset voltage VDD / 2, and the data backup operation ends.

[0115] In one possible implementation, controlling the transistors in the switching unit 1110 and the backup / reload unit 1130 to perform at least one of the static random access operation, the data backup operation, and the data reload operation may include:

[0116] The gate voltage of the third transistor T3 is controlled to a preset voltage by the second word line B1, the fourth transistor T4 is controlled to be in the on state by the third word line R1, and the source of the fourth transistor T4 is controlled to be high level by the fourth word line C1.

[0117] The power supplies for the second inverter INV2 and the first inverter INV1 are turned on sequentially to perform the data reload operation.

[0118] Please see Figure 6a , Figure 6b , Figure 6a , Figure 6b A schematic diagram illustrating data reloading in a memory according to an embodiment of the present disclosure is shown.

[0119] In one example, such as Figure 6a , Figure 6bAs shown, first, set the second word line B1 to the preset voltage (in this example, half of the high-level voltage, VDD / 2), and set the third word line R1 to a high level (in this example, VDD, i.e., the power supply voltage), and set the fourth word line C1 to a high level. Next, turn on the power to the second inverter INV2I2 and the first inverter INV1I1 in sequence to achieve data reload operation.

[0120] In one example, such as Figure 6a , Figure 6b As shown, the third word line R1 and the fourth word line C1 are initially held at VDD, and the second word line B1 is held at VDD / 2. Before the recovery operation begins, the two power supplies (corresponding to VDDA and VDDB, respectively) of the first inverter INV1 and the second inverter INV2 in memory cell 1120 are grounded. Figure 6a , Figure 6b As shown, in step 1, if the FeFET (third transistor T3) has been set to positive polarity with negative Vt, the VDD voltage of the fourth word line C1 can reach node QN through the third transistor T3 and the fourth transistor T4, causing QN to charge to Vdd-Vt. Otherwise, QN will remain at GND due to the previous power-off phase. In step 2, VDDB is applied to the second inverter INV2 while VDDA remains grounded, resulting in Q being driven by the second inverter INV2 powered by VDDB. In step 3, VDDA is also turned on, and the two inverters form a stable loop.

[0121] Please see Figure 7 , Figure 7 The simulation waveforms of backup data and reload data according to embodiments of this disclosure are shown.

[0122] in, Figure 7 The results were obtained through simulation based on a ferroelectric layer thickness (TFE) of 9 nm, a kinetic coefficient (ρ) of 0.01, and a power supply voltage (VDD) of 0.9 V.

[0123] For example, such as Figure 7 As shown, with Figure 7 Taking the backup "1" corresponding to (1) as an example, Q and QN are equal to "1" (VDD) and "0" (GND) respectively. At this time, VDDA and VDDB are both high level, and the energy storage unit is in normal turn-on state. By first lowering the second word line B1 to GND, the V of the FeFET is made to be high. GS The polarization of the third transistor T3 is zero, thus preventing any change in its polarization state (keeping it low). Next, the second word line B1 is raised to VDD, causing the V of the FeFET to... GSThis is VDD, which triggers the supercoercive voltage at the internal FE layer. Therefore, the FeFET can be polarized to a positive polarization state with negative Vt (becoming high), resulting in a low drain-source channel resistance. During this process, the third word line R1 and the fourth word line C1 are both low.

[0124] For example, such as Figure 7 As shown, with Figure 7 Taking the backup "0" corresponding to (4) as an example, Q and QN are equal to "0" (GND) and "1" (VDD) respectively. At this time, VDDA and VDDB are both high level, and the energy storage unit is in normal turn-on state. First, in step 1, the second word line B1 is lowered to GND so that the V of FeFET is high. GS The voltage is -VDD, which exceeds the negative coercivity voltage. Therefore, the FeFET will be polarized negatively with positive Vt, resulting in a high drain-source channel resistance. Next, in step 2, the second word line B1 is raised to Vdd, resulting in zero V. GS Furthermore, there is no change in the polarization state of the FeFET (the polarization state of the third transistor T3 is always -VP).

[0125] For example, such as Figure 7 As shown, with Figure 7 Taking the reload recovery corresponding to (3) as an example, before the recovery operation begins, the two power supplies (corresponding to VDDA and VDDB respectively) of the first inverter INV1 and the second inverter INV2 in the storage unit 1120 are grounded (low level). First, the second word line B1 is set to the preset voltage (in this example, it is half of the voltage corresponding to the high level, VDD / 2), and the third word line R1 is set to the high level (in this example, it is VDD, i.e., the power supply voltage), and the fourth word line C1 is set to the high level. Next, the power supplies of the second inverter INV2I2 and the first inverter INV1I1 are turned on in sequence (first VDDB is set to the high level, and then VDDA is set to the high level), and the data reload operation can be realized. Figure 7 The recovery (5) is similar and will not be elaborated here.

[0126] Please see Figure 8 , Figure 8 The diagram illustrates the relationship between the ferroelectric layer thickness of the third transistor in the memory of this disclosure and the backup time, as well as the relationship between the power supply voltage and the backup overload energy.

[0127] For example, such as Figure 8As shown, increasing the thickness of the ferroelectric layer can reduce backup time, and increasing VDD helps reduce polarization switching time. However, it may impair the lifespan of the FeFET device and may also consume higher backup load energy. Therefore, the above relationship diagram can be used to achieve a trade-off between durability and backup time for different VDD values.

[0128] Please see Figure 9a , Figure 9b , Figure 9a , Figure 9b A schematic diagram comparing the performance of a memory according to an embodiment of this disclosure with that of a memory in the related art is shown.

[0129] Among them, 7T1R and RRAM represent the work of A. Lee, 4T2MTJ represents the work of T. Ohsawa, and 10T represents the work of X. Li.

[0130] Among them, X. Li's work refers to the nonvolatile static random access memory (SRAM) based on ferroelectric transistors proposed by X. Li et al. (see X. Li, K. Ma, S. George, W. Khwa, J. Sampson, S. Gupta et al., “Design of Nonvolatile SRAM with Ferroelectric FETs for Energy-Efficient Backup and Restore,” IEEE Transactions on Electron Devices, vol. 64, no. 7, pp. 3037–3040, 2017), and A. Lee's work refers to the nonvolatile SRAM based on memristors proposed by A. Lee et al. (see A. Lee, Meng. Chang, C. Lin, C. Chen, M. Ho, C. Kuo et al., “RRAM-based 7T1R nonvolatile SRAM with 2x reduction in store energy and 94x reduction in restore energy for frequent-off instant-on applications,” 2015 Symposium on VLSI Circuits (VLSI)). T. Ohsawa's work refers to the nonvolatile static random access memory proposed by T. Ohsawa et al. (see paper T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda et al., "A 1Mb Nonvolatile Embedded Memory Using 4T2MTJCell With 32b Fine-Grained Power Gating Scheme", IEEE Journal of Solid-State Circuits, vol.48, no.6, pp.1511–1520, 2013).

[0131] in, Figure 9a A schematic diagram comparing the backup and reload energy of related technologies with embodiments of this disclosure is shown, such as... Figure 9a As shown, the nvSRAM of 7T1R RRAM and the nvSRAM of 4T2MTJ consume 178 times and 61 times more energy than those disclosed in this invention, respectively.

[0132] in, Figure 9bA schematic diagram illustrating the relationship between the operating frequency and normalized backup energy of the memory in relation to the relevant technologies and the present disclosure is shown.

[0133] like Figure 9b As shown, compared with related technologies, the embodiments of this disclosure achieve an ultra-high backup energy efficiency (normalized from normal memory access energy) of less than 0.75% in a typical scenario with an operating frequency of 2MHz and a backup frequency fbkp of 10Hz, while significantly reducing backup energy. Compared with nvSRAM of a FeFET-based 10T scheme having a normalized recovery energy of 0.20%, the embodiments of this disclosure show a very small energy performance difference (only 0.5%) at the system level for many low-power IoT applications.

[0134] Please see Figure 10 , Figure 10 A schematic diagram comparing the area of ​​a memory according to an embodiment of this disclosure with that of related technologies is shown.

[0135] like Figure 10 As shown, compared with the area of ​​the storage module 110 in the related art (taking X.Li's work as an example), since the backup reload unit 1130 can be implemented with only 2 transistors in the embodiment of this disclosure, the area of ​​the nvSRAM (including the backup reload unit 1130 + storage unit 1120) in the embodiment of this disclosure is greatly reduced. Even considering the switching unit 1110, additional control and voltage supply lines, the embodiment of this disclosure can reduce the area by about 11% (as shown in Table 1). The reduction in area overhead increases the nvSRAM density, which is beneficial for reducing the total area cost or supporting larger embedded caches.

[0136] Table 1

[0137] Structure cell area (pm 2 ) Normalized area Conventional 6T-SRAM 1.09 1 10T nvSRAM (X. Li’s work) 1.56 1.429 The present disclosure 1.39 1.278

[0138] Table 2 provides a comparison of the relevant technologies with this disclosure in terms of power consumption and density.

[0139] Table 2

[0140]

[0141] As can be seen, the non-volatile static random access memory circuit based on ferroelectric transistors proposed in this disclosure uses only two additional transistors to form a non-volatile memory cell for data backup and reload, reducing the number of transistors in the non-volatile memory cell from the existing four to two. This circuit supports data backup before the power supply system fails. By using step-by-step control technology, the peripheral circuit controls the power-on sequence of the inverter power supply, thereby realizing the reload of the original data when the power supply is restored (this step-by-step control technology reduces the additional area overhead caused by the control of the conducting transistor). The circuit structure is compact, and the power consumption can reach the femtojoule level when performing data backup and reload operations, while reducing the area and increasing the density. That is, the embodiments of this disclosure solve the area overhead problem in the related technology to a certain extent.

[0142] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A non-volatile static random access memory, characterized in that, The memory includes: Multiple storage modules are provided, each including a switching unit, a storage unit, and a backup reload unit. The switching unit is connected to the storage unit and the backup reload unit, and the backup reload unit is connected to the storage unit. The storage unit is used to perform static random access operations to access data. The backup reload unit includes only two transistors, one of which is a ferroelectric field-effect transistor. The backup reload unit is used to perform a data backup operation when the memory is powered off, utilizing the polarization characteristics of the ferroelectric field-effect transistor to back up the data in the storage unit, and to perform a data reload operation when the memory is powered on, writing the data in the backup reload unit into the storage unit. A control module, connected to each storage module, is used to control the transistors in the switching unit and the backup / reload unit to execute at least one of the static random access operation, the data backup operation, and the data reload operation. Each storage module further includes a first bit line, a second bit line, a first word line, a second word line, a third word line, and a fourth word line. The switching unit includes a first transistor and a second transistor. The backup reload unit includes only a third transistor and a fourth transistor. The third transistor is a ferroelectric field-effect transistor. The storage unit includes a first inverter and a second inverter. The drain of the first transistor is connected to the first bit line, the gate of the first transistor is connected to the first word line, and the source of the first transistor is connected to the input terminal of the first inverter and the output terminal of the second inverter. The drain of the second transistor is connected to the second bit line, the gate of the second transistor is connected to the first word line, and the source of the second transistor is connected to the output terminal of the first inverter, the input terminal of the second inverter, and the drain of the third transistor. The gate of the third transistor is connected to the second word line, and the source of the third transistor is connected to the drain of the fourth transistor. The gate of the fourth transistor is connected to the third word line, the source of the fourth transistor is connected to the fourth word line, and the drain of the fourth transistor is connected to the source of the third transistor.

2. The memory according to claim 1, characterized in that, Controlling the transistors in the switching unit and the backup / reload unit to perform at least one of the static random access operation, the data backup operation, and the data reload operation includes: The second word line controls the gate voltage of the third transistor to a preset voltage, the third word line controls the fourth transistor to be in a turned-off state, the memory cell is powered normally, and the first word line, the first bit line, and the second bit line control the switching unit to perform the static random access operation on the memory cell.

3. The memory according to claim 1, characterized in that, Controlling the transistors in the switching unit and the backup / reload unit to perform at least one of the static random access operation, the data backup operation, and the data reload operation includes: The second word line controls the gate voltage of the third transistor to a preset voltage, the third word line controls the fourth transistor to be in a turned-off state, and the fourth word line controls the source of the fourth transistor to be at a low level. The second word line controls the gate voltage of the third transistor to remain at a low level and a high level for a period of time, and then controls the gate voltage of the third transistor to the preset voltage to perform the data backup operation.

4. The memory according to claim 1, characterized in that, Controlling the transistors in the switching unit and the backup / reload unit to perform at least one of the static random access operation, the data backup operation, and the data reload operation includes: The second word line controls the gate voltage of the third transistor to a preset voltage, the third word line controls the fourth transistor to be in a conducting state, and the fourth word line controls the source of the fourth transistor to be at a high level. The power supplies for the second inverter and the first inverter are turned on in sequence to perform the data reload operation.

5. The memory according to any one of claims 2 to 4, characterized in that, The preset voltage is less than or equal to half of the power supply voltage of the memory.

6. The memory according to claim 1, characterized in that, The storage modules are electrically connected to form a layout of at least one row and at least one column. In the same row, the first word line of the storage modules is connected, the second word line is connected, the third word line is connected, and the fourth word line is connected. In the same column, the first word line of the storage modules is connected and the second word line is connected.

7. The memory according to claim 1, characterized in that, The control module includes a word line driving circuit and a bit line driving circuit. The word line driving circuit is used to drive the first word line, the second word line, the third word line and the fourth word line of each memory module. The bit line driving circuit is used to drive the first bit line and the second bit line of each memory module.

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