Non-volatile storage using step-wise writes

Abstract

A non-volatile storage system includes control circuitry connected to non-volatile memory cells, the non-volatile storage system providing step-wise writing of data. That is, overwriting existing data with new data without performing a traditional erase operation that changes the threshold voltage of the memory cells back to a traditional or original erased state. In one example, new data is written over old data using shifted threshold voltage distributions. Some embodiments include writing MLC data on SLC data, using intermediate erase threshold voltage distributions, and / or automatically detecting which threshold voltage distributions are currently being used to store data.

Description

Background Technology

[0001] Semiconductor memories are widely used in a variety of electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memories can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when not connected to a power source (e.g., a battery). An example of non-volatile memory is flash memory (e.g., NAND and NOR flash memory).

[0002] Users of non-volatile memory can program (e.g., write) data to the non-volatile memory and later read the data back. For example, a digital camera can take a photo and store it in non-volatile memory. Later, the user of the digital camera can view the photo by having the digital camera read the photo from the non-volatile memory.

[0003] It is also possible to erase all or part of the non-volatile memory. For example, if data becomes outdated or needs to be rewritten, a portion of the non-volatile memory storing the data can be erased, making that portion of the non-volatile memory available for storing new data. In a non-volatile memory, a conventional erase operation involves lowering the threshold voltage of the non-volatile memory cell from one or more programming states to an erase state.

[0004] In a non-volatile memory, memory cells that have stored valid data must be erased before they can be reprogrammed. However, the erasure process is typically performed at the block level, while programming is performed at the page or subpage level, where a block comprises many pages. Therefore, when rewriting data in a specific page of a specific block, all valid data in the pages of that specific block except for that specific page is moved and reprogrammed into a new block, the new data is programmed into the new block, and then the specific block is erased and made available for future programming. Moving and reprogramming valid data within a block slows down the programming process and consumes additional space in memory (because there must be areas in memory available for moving and reprogramming data). Attached Figure Description

[0005] Elements with similar numbers refer to common components in different diagrams.

[0006] Figure 1A This is a block diagram of one embodiment of a storage system connected to a host.

[0007] Figure 1B This is a block diagram of one embodiment of a front-end processor circuit.

[0008] Figure 1C This is a block diagram of one embodiment of the back-end processor circuit.

[0009] Figure 1D This is a block diagram of one embodiment of memory packaging.

[0010] Figure 2A This is a functional block diagram of a memory die embodiment.

[0011] Figure 2B This is a functional block diagram of an embodiment of an integrated memory component.

[0012] Figure 2C An embodiment of an integrated memory component is depicted.

[0013] Figure 3A -D plots a curve depicting the threshold voltage distribution.

[0014] Figure 4 This is a flowchart describing one embodiment of the programming / writing data process.

[0015] Figure 5 and 6 A graph depicting the threshold voltage distribution.

[0016] Figure 7 This is a flowchart of an embodiment describing a process of incrementally writing data so that existing data is rewritten with new data without performing a conventional erase operation that changes the threshold voltage of the non-volatile memory cell back to the conventional or original erase state.

[0017] Figure 8 and 9 A graph depicting the threshold voltage distribution.

[0018] Figure 10 This is a flowchart of an embodiment describing a process of incrementally writing data so that existing data is rewritten with new data without performing a conventional erase operation that changes the threshold voltage of the non-volatile memory cell back to the conventional or original erase state.

[0019] Figure 11 This is a flowchart of an embodiment describing a process of incrementally writing data so that existing data is rewritten with new data without performing a conventional erase operation that changes the threshold voltage of the non-volatile memory cell back to the conventional or original erase state.

[0020] Figure 12 This is a flowchart of an embodiment describing a process of incrementally writing data so that existing data is rewritten with new data without performing a conventional erase operation that changes the threshold voltage of the non-volatile memory cell back to the conventional or original erase state.

[0021] Figure 13This is a flowchart of an embodiment describing a process of incrementally writing data so that existing data is rewritten with new data without performing a conventional erase operation that changes the threshold voltage of the non-volatile memory cell back to the conventional or original erase state.

[0022] Figure 14 This is a flowchart illustrating an embodiment of the process of automatically detecting the current state set among multiple state sets used by non-volatile memory cells to store existing data.

[0023] Figure 15 This is a flowchart illustrating one embodiment of the process for automatically detecting whether a non-volatile memory cell is in a common new (intermediate) erase state. Detailed Implementation

[0024] A non-volatile memory system for performing incremental data writes is proposed. That is, existing data is rewritten with new data without performing a conventional erase operation that reverts the threshold voltage of the non-volatile memory cell to a traditional or pristine erase state. In one example, a shifted threshold voltage distribution is used to write new data onto old data. Some embodiments include writing MLC data onto SLC data, using intermediate erase threshold voltage distributions, and / or automatically detecting which threshold voltage distributions are currently being used to store data. By performing incremental data writes without performing a conventional erase operation that reverts the threshold voltage of the non-volatile memory cell to a traditional or pristine erase state, the programming / writing process is faster and requires less space in memory.

[0025] Figure 1AThis is a block diagram of one embodiment of a storage system 100 connected to a host system 120. The storage system 100 may implement the techniques disclosed herein. Many different types of storage systems may be used with the techniques disclosed herein. Example storage systems include SD cards or solid-state drives (“SSDs”); however, other types of storage systems may also be used. The storage system 100 includes a memory controller 102, one or more memory packages 104 for storing data, and local memory (e.g., DRAM / ReRAM) 106. The memory controller 102 includes a front-end processor circuitry (FEP) 110 and one or more back-end processor circuitry (BEP) 112. In one embodiment, the FEP 110 circuitry is implemented on an ASIC. In one embodiment, each BEP circuit 112 is implemented on a separate ASIC. In one embodiment, the ASICs for each of the BEP circuitry 112 and the FEP circuitry 110 are implemented on the same semiconductor, such that the memory controller 102 is fabricated as a system-on-a-chip (“SoC”). Both the FEP 110 and the BEP 112 include their own processors. In one embodiment, FEP 110 and BEP 112 act as a master-slave configuration, where FEP 110 is the master and each BEP 112 is a slave. For example, FEP circuit 110 implements a flash translation layer that performs memory management (e.g., garbage collection, wear leveling, etc.), logic-to-physical address translation, communication with the host, management of DRAM (local volatile memory), and overall management of the operation of SSD (or other non-volatile memory systems). BEP circuit 112 manages memory operations within memory package 104 upon request from FEP circuit 110. For example, BEP circuit 112 can perform read, erase, and program processes. Additionally, BEP circuit 112 can perform buffer management, set the required voltage levels for FEP circuit 110, perform error correction (ECC), control the switching mode interface with the memory package, etc. In one embodiment, each BEP circuit 112 is responsible for its own set of memory packages. Memory controller 102 is an example of control circuitry.

[0026] In one embodiment, there are multiple memory packages 104. Each memory package 104 may contain one or more memory dies. In one embodiment, each memory die in the memory package 104 utilizes NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory package 104 may contain other types of memory; for example, the memory package may contain phase-change memory (PCM) memory or magnetoresistive random access memory (MRAM).

[0027] In one embodiment, memory controller 102 communicates with host system 120 using interface 130. For use of storage system 100, host system 120 includes host processor 122, host memory 124, and interface 126 communicating via bus 128. Host memory 124 is the physical memory of the host and may be DRAM, SRAM, non-volatile memory, or other types of storage devices. Host 120 may also include a hard disk drive connected to bus 128 and / or a USB drive communicating with bus 128. Software (code) for programming host processor 122 may be stored in host memory 124, the hard disk drive connected to bus 128, or the USB drive. Host memory 124, the hard disk drive connected to bus 128, and the USB drive are examples of non-transitory, processor-readable storage media storing processor-readable code that, when executed on host processor 122, causes host processor 122 to perform the methods described below.

[0028] The host system 120 is located outside and separate from the storage system 100. In one embodiment, the storage system 100 is embedded in or connected to the host system 120. The memory controller 102 can communicate with the host 120 via various types of communication interfaces, including, for example, an SD card interface, NVMe over PCIe, a fabricated NVMe architecture, or a cache / memory coherence architecture based on Accelerator Cache Coherent Interconnect (CCIX), Compute Passthrough Link (CXL), Open Coherent Accelerator Processor Interface (OpenCAPI), Gen-Z, etc.

[0029] Figure 1B This is a block diagram of one embodiment of the FEP circuit 110. Figure 1BA host interface 150 is shown communicating with a host system 120 and a host processor 152. The host processor 152 can be any type of processor known in the art suitable for implementation. The host processor 152 communicates with a network on-chip (NOC) 154. An NOC is a communication subsystem on an integrated circuit, typically between cores of a SoC. NOCs can span synchronous and asynchronous clock domains or use clockless asynchronous logic. NOC technology applies networking theory and methods to on-chip communication, resulting in significant improvements over conventional buses and crossbar interconnects. Compared to other designs, NOCs improve the scalability of SoCs and the power efficiency of complex SoCs. NOC lines and links are shared by multiple signals. Because all links in a NOC can operate on different data packets simultaneously, a high level of parallelism is achieved. Therefore, as the complexity of integrated subsystems increases, NOCs offer enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). NOC 154 connects to and communicates with memory processor 156, SRAM 160, and DRAM controller 162. DRAM controller 162 is used to operate and communicate with DRAM (e.g., DRAM 106, which is volatile memory). SRAM 160 is a local volatile RAM memory used by memory processor 156. Memory processor 156 is used to run FEP circuitry and perform various memory operations. NOC also communicates with two PCIe interfaces, 164 and 166. Figure 1B In one embodiment, the memory controller 102 includes two BEP circuits 112; therefore, there are two PCIe interfaces 164 / 166. Each PCIe interface 164 / 166 communicates with one of the BEP circuits 112. In other embodiments, there may be more or fewer than two BEP circuits 112; therefore, there may be more than two PCIe interfaces.

[0030] Figure 1C This is a block diagram of one embodiment of the BEP circuit 112. Figure 1C This is shown for communicating with FEP circuit 110 (e.g., with...). Figure 1B PCIe interface 200 communicates with one of PCIe interfaces 164 and 166. PCIe interface 200 communicates with two NOCs 202 and 204. In one embodiment, the two NOCs may be combined into one large NOC. Each NOC (202 / 204) is connected to SRAM (230 / 260), buffer (232 / 262), processor (220 / 250), and data path controller (222 / 252) via XOR engine (224 / 254) and ECC engine (226 / 256).

[0031] ECC engines 226 / 256 are used for error correction, as is known in the art. In this document, ECC engines 226 / 256 may be referred to as the controller ECC engine. XOR engines 224 / 254 are used to XOR data so that the data can be combined and stored in a manner recoverable in the event of programming errors. In one embodiment, XOR engines 224 / 254 can recover data that cannot be decoded using ECC engines 226 / 256.

[0032] Data path controller 222 is connected to memory interface 228 to communicate with the integrated memory component via four channels. Therefore, the top NOC 202 is associated with memory interface 228 for the four channels used to communicate with the memory package, and the bottom NOC 204 is associated with memory interface 258 for the four additional channels used to communicate with the memory package. In one embodiment, each memory interface 228 / 258 includes four switching mode interfaces (TM interfaces), four buffers, and four schedulers. One scheduler, buffer, and TM interface are present for each of the channels. The processor can be any standard processor known in the art. Data path controller 222 / 252 can be a processor, FPGA, microprocessor, or other type of controller. XOR engines 224 / 254 and ECC engines 226 / 256 are dedicated hardware circuits, referred to as hardware accelerators. In other embodiments, XOR engines 224 / 254 and ECC engines 226 / 256 may be implemented in software. The scheduler, buffers, and TM interfaces are hardware circuits. In other embodiments, the memory interface (circuit for communicating with the memory die) can be... Figure 1C The different structures depicted in the text. Additionally, it possesses... Figure 1B and 1C Controllers with different architectures can also be used with the techniques described in this article.

[0033] Figure 1D This is a block diagram of one embodiment of a memory package 104, which includes a plurality of memory dies 300 (memory die 0, memory die 1, memory die 2, ..., memory die M) connected to a memory bus (data line and chip enable line) 318. The memory bus 318 is connected to a switching mode interface 270 for communication with the TM interface of the BEP circuit 112 (see example...). Figure 1CIn some embodiments, the memory package may include a small controller connected to the memory bus 318 and the TM interface 270. Generally, the memory package 104 may have eight or 16 memory dies; however, other numbers of memory dies may also be implemented. The techniques described herein are not limited to any particular number of memory dies. In some embodiments, the memory package may also include a processor, a CPU device (e.g., a RISC-V CPU), and a amount of RAM to help implement some of the capabilities described below. The techniques described herein are not limited to any particular number of memory dies.

[0034] Figure 2A This is a block diagram depicting an example of a memory die 300 capable of implementing the techniques described herein. It may correspond to... Figure 1D One of the memory dies 300 includes a non-volatile memory array 302. The array terminal lines of the memory array 302 include various layers of word lines organized into rows and various layers of bit lines organized into columns. However, other orientations may also be implemented. The memory die 300 includes a row control circuitry system 320, whose output 308 is connected to the corresponding word lines of the memory array 302. The row control circuitry system 320 receives a set of M row address signals and one or more various control signals from system control logic circuitry 360, and may typically include circuitry such as a row decoder 322, an array terminal driver 324, and a block selection circuitry system 326 for read and write operations. The row control circuitry system 320 may also include a read / write circuitry system. The memory die 300 also includes a column control circuitry system 310, which includes a sense amplifier 330, whose input / output 306 is connected to the corresponding bit lines of the memory array 302. Although only a single block is shown for array 302, the memory die may contain multiple arrays and / or multiple planes that can be accessed individually. The column control circuitry 310 receives a set of N column address signals and one or more various control signals from the system control logic 360, and may typically include circuitry such as a column decoder 312, an array terminal receiver or driver 314, a block selection circuitry 316, and read / write circuitry and I / O multiplexers.

[0035] System control logic 360 receives data and commands from host 120 and provides output data and status to memory controller 102. In some embodiments, system control logic 360 includes a state machine 362 that provides die-level control for memory operations. In one embodiment, state machine 362 is programmable in software. In other embodiments, state machine 362 does not use software and is implemented entirely in hardware (e.g., circuitry). In another embodiment, state machine 362 is replaced by a microcontroller or microprocessor on or off the memory chip. System control logic 360 may also include a power control module 364 that controls the power and voltage supplied to rows and columns of memory array 302 during memory operations, and may include charge pump and regulator circuitry for generating regulated voltages. System control logic 360 includes a storage device 366 that can be used to store parameters for operating memory array 302.

[0036] Commands and data are transmitted between memory controller 102 and memory die 300 via memory controller interface 368 (also referred to as the "communication interface"). Memory controller interface 368 is an electrical interface for communicating with memory controller 102. Examples of memory controller interface 368 include a switching mode interface and an Open NAND Flash Interface (ONFI). Other I / O interfaces may also be used. For example, memory controller interface 368 may implement a switching mode interface connected to the switching mode interface of memory interface 228 / 258 for memory controller 102. In one embodiment, memory controller interface 368 includes a set of input and / or output (I / O) pins connected to memory controller 102.

[0037] In some embodiments, all elements of the memory die 300 that include the system control logic 360 may be formed as part of a single die. In other embodiments, some or all of the system control logic 360 may be formed on different dies.

[0038] For the purposes of this document, the phrase "control circuitry" includes all or part of the memory controller 102, state machine 362, microcontroller, microprocessor, system control logic 360, row control circuitry system 320, column control circuitry system 310, and / or any or a combination of other similar circuitry for controlling non-volatile memory. One or more control circuits may comprise hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of control circuitry. Control circuitry may comprise processors, FGAs, ASICs, integrated circuits, or other types of circuitry.

[0039] In one embodiment, memory structure 302 includes a three-dimensional memory array of non-volatile memory cells, wherein multiple memory layers are formed over a single substrate, such as over a wafer. The memory structure may include any type of non-volatile memory monolithically formed in one or more physical layers of memory cells having active regions disposed over a silicon (or other type of) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge trapping layers.

[0040] In another embodiment, memory structure 302 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR flash memory) may also be used.

[0041] The exact type of memory array architecture or memory cell included in memory structure 302 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory array 302. For the purposes of the new claimed embodiments presented herein, no specific non-volatile memory technology is required. Other examples of suitable technologies for memory cells of memory array (or other types of memory structure) 302 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin-orbit torque MRAM, spin-orbit torque MRAM), FeRAM, phase-change memory (e.g., PCM), etc. Examples of suitable technologies for memory cell architecture include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bitline arrays, etc.

[0042] One example of ReRAM crosspoint memory includes reversible resistive switching elements arranged in an array of crosspoints accessed via X-lines and Y-lines (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridging memory element. The conductive bridging memory element may also be referred to as a programmable metallized cell. The conductive bridging memory element may be used as a state-changing element based on the physical migration of ions within a solid electrolyte. In some cases, the conductive bridging memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, ion mobility also increases, causing the programming threshold of the conductive bridging memory cell to decrease. Therefore, the conductive bridging memory element can have a wide range of programming thresholds that vary with temperature.

[0043] Another example is magnetoresistive random access memory (MRAM) that stores data using magnetic storage elements. The element is formed from two ferromagnetic layers separated by a thin insulating layer, each of which can remain magnetized. One of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of an external field to store the memory. The memory device is constructed from a grid of such memory cells. In one embodiment concerning programming, each memory cell is located between a pair of write lines arranged perpendicular to each other, parallel to the cell, with one above and one below the cell. When current flows through the pair of write lines, an induced magnetic field is generated. MRAM-based memory embodiments will be discussed in more detail below.

[0044] Phase-change memories (PCMs) utilize the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve a non-thermal phase transition simply by changing the coordinated state of germanium atoms with a laser pulse (or a light pulse from another source). Therefore, the programming dose is a laser pulse. Memory cells can be disabled by preventing them from receiving light. In other PCM embodiments, memory cells are programmed by current pulses. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes (continuous or discontinuous) vibrations or bursts of sound, current, voltage, light, or other waves. These memory elements within individual optional memory cells or bits may include another cascaded element as a selector, such as a bidirectional threshold switch or a metallic insulator substrate.

[0045] Those skilled in the art will recognize that the techniques described herein are not limited to a single particular memory structure, memory construction, or material composition, but rather encompass many related memory structures within the spirit and scope of the techniques described herein and as understood by those skilled in the art.

[0046] Figure 2A The components can be divided into two parts: the structure of the memory array 302 and the peripheral circuitry, which (in some embodiments) includes all the structures 310, 320, and 360 other than the memory array 302. A key characteristic of the memory circuitry is its capacity, which can be increased by increasing the area of ​​the memory die of the memory system 100 given above the memory structure 302; however, this reduces the area of ​​the memory die available for the peripheral circuitry. This imposes considerable limitations on these peripheral components. For example, the need to mount sense amplifier circuitry within the available area is a significant limitation on sense amplifier design architectures. Regarding system control logic 360, the reduced area availability limits the available functionality that can be implemented on the chip. Therefore, the fundamental trade-off in the design of the memory die for the memory system 100 is the amount of area dedicated to the memory structure 302 versus the amount of area dedicated to the peripheral circuitry.

[0047] Another area where the memory array 302 and the peripheral circuitry often differ is the processing involved in forming these areas, as these areas typically involve different processing techniques, resulting in trade-offs between different technologies on a single die. For example, when the memory array 302 is NAND flash memory, it is an NMOS structure, while the peripheral circuitry is typically CMOS-based. Components such as sense amplifier circuitry, charge pumps, logic elements in state machines, and other peripheral circuitry in system control logic 360 typically employ PMOS devices. The processing operations used to fabricate CMOS dies will differ in many ways from those optimized for NMOS flash NAND memory or other memory cell technologies.

[0048] To improve upon these limitations, the embodiments described below can... Figure 2A The components are separated onto separately formed dies, which are then bonded together. More specifically, the memory array 302 can be formed on a single die (the memory die), and some or all of the peripheral circuitry system components, including one or more control circuits, can be formed on separate dies (the control die). For example, the memory die can be formed solely of memory elements, such as NAND flash memory, MRAM memory, PCM memory, ReRAM memory, or other memory cell arrays of other memory types. Some or all of the peripheral circuitry system components (even those including components such as decoders and sense amplifiers) can then be moved to separate control dies. This allows each of the memory dies to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without worrying about CMOS components that are now moved to separate peripheral circuitry system dies that can be optimized for CMOS processing. This provides more space for peripheral components that can now incorporate additional functionality that would not be easily incorporated if confined to the edges of the same die housing the memory cell array. The two dies can then be joined together in a multi-die memory circuit, with an array on one die connected to peripheral components on the other memory circuit. Although the following will focus on a memory die and a memory circuit that controls the joining of the dies, other embodiments may use more dies, such as two memory dies and a peripheral circuit system die.

[0049] Figure 2B Show Figure 2A An alternative arrangement, which can be implemented using wafer-to-wafer bonding to provide bonded die pairs, is known as an integrated memory assembly. Figure 2BA functional block diagram depicting one embodiment of an integrated memory component 307 is shown. One or more integrated memory components 307 may be used in a memory package 104 in a memory system 100. The integrated memory component 307 includes two types of semiconductor dies (or more simply referred to as "dies"). Memory die 301 includes a memory array 302. Memory array 302 may include non-volatile memory cells. A portion of memory array 302 is used to store boot code 350. As described above, host processor 124 uses boot code 350 to perform a boot process.

[0050] The control die 311 includes control circuitry systems 310, 320, and 360 (details of which have been discussed above). In some embodiments, the control die 311 is configured to be connected to a memory array 302 in the memory die 301. Figure 2B An example of a peripheral circuit system formed in a peripheral circuit or control die 311 is shown, including control circuitry coupled to a memory array 302 formed in a memory die 301. Common components are similar to... Figure 2A The system control logic 360, row control circuitry 320, and column control circuitry 310 are located in the control die 311. In some embodiments, all or a portion of the column control circuitry 310 and all or a portion of the row control circuitry 320 are located on the memory die 301. In some embodiments, some circuitry in the system control logic 360 is located on the memory die 301.

[0051] System control logic 360, row control circuitry system 320, and column control circuitry system 310 can be formed using a common process (e.g., CMOS process), such that adding components and functions more commonly found on memory controller 102, such as ECC, may require few or no additional process steps (i.e., the same process steps used to manufacture memory controller 102 can also be used to manufacture system control logic 360, row control circuitry system 320, and column control circuitry system 310). Therefore, when moving such circuitry from a die such as memory die 301 reduces the number of steps required to manufacture such a die, adding such circuitry to a die such as control die 311 may also require few additional process steps.

[0052] Figure 2BA column control circuitry system 310, including a sense amplifier 350, is shown on a control die 311. This column control circuitry system is coupled to a memory array 302 on a memory die 301 via an electrical path 306. For example, electrical path 306 may provide electrical connections between a column decoder 312, a driver circuitry system 314, a block select 316, and bit lines of the memory array (or structure) 302. The electrical path may extend from the column control circuitry system 310 in the control die 311 through pads on the control die 311 that engage with corresponding pads on the memory die 301, which are connected to bit lines of the memory structure 302. Each bit line of the memory structure 302 may have a corresponding electrical path in electrical path 306, including a pair of pads connected to the column control circuitry system 310. Similarly, a row control circuitry system 320, including a row decoder 322, an array driver 324, and a block select 326, is coupled to the memory array 302 via an electrical path 308. Each of the electrical paths 308 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 311 and the memory structure die 301.

[0053] In some embodiments, the integrated memory component 307 contains more than one control die 311 and / or more than one memory die 301. In some embodiments, the integrated memory component 307 comprises a stack of multiple control dies 311 and multiple memory dies 301. In some embodiments, each control die 311 is fixed (e.g., bonded) to at least one of the memory structure dies 301.

[0054] As mentioned herein, the integrated memory component 307 may contain more than one control die 311 and more than one memory die 301. In some embodiments, the integrated memory component 307 comprises a stack of multiple control dies 311 and multiple memory dies 301. Figure 2C A side view depicting one embodiment of an integrated memory assembly 307 stacked on a substrate 400 is shown. The integrated memory assembly 307 has three control dies 311 and three memory dies 301. Each control die 311 is bonded to one of the memory dies 301. Bonding pads 402, 404 are depicted. More bonding pads may be present. The space between two bondsed dies 301, 311 is filled with a solid layer 406, which may be formed of epoxy, other resins, or polymers. This solid layer 406 protects the electrical connection between the dies 301 and 311 and further holds the dies together. Various materials can be used as the solid layer 406, but in this embodiment, the solid layer may be Hysol epoxy from Henkel, Inc., which has offices in California, USA.

[0055] The integrated memory assembly 307 can be stacked in a stepped offset manner, such that the bonding pads 410 of each level are uncovered and accessible from the levels above. Wire connections 412, attached to the bonding pads 410, connect the control die 311 to the substrate 400. This connection can span the width of each control die 311 (i.e., into...). Figure 2C The pages form many such wire connections.

[0056] A through-silicon via (TSV) 414 can be used to route signals through a control die 311. A through-silicon via (TSV) 416 can be used to route signals through a memory die 301. TSVs 414 and 416 can be formed before, during, or after the formation of the integrated circuit in the semiconductor dies 301 and 311. TSVs can be formed by etching through the holes in the wafer. A barrier layer can then be used to back the holes to prevent metal diffusion. The barrier layer can then be backed with a seed layer, and the seed layer can be plated with an electrical conductor such as copper, but other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and their alloys or combinations can also be used.

[0057] about Figure 2C In one embodiment of the implementation described herein, various depicted TSVs 414 and 416 connected to the bonding pad 410 and the wire bonding 412 can be used to enable multiple control dies 311 to communicate with each other and to transfer data between the multiple control dies 311. For example, a first control die can read data from a memory die to which it is bonded, transfer the data (after some optional processing) to a second control die, and the second control die can program the data into a memory die to which it is bonded.

[0058] Solder balls 418 may optionally be attached to contact pads 420 on the lower surface of substrate 400. Solder balls 418 may be used to electrically and mechanically couple integrated memory component 307 to a printed circuit board. Solder balls 418 may be omitted when integrated memory component 307 is used as an LGA package. Solder balls 418 may form part of the interface between integrated memory component 307 and memory controller 102.

[0059] exist Figure 2C In one embodiment, memory dies 301 and control dies 311 are arranged in pairs. That is, each memory die 301 is coupled to and communicates with a corresponding / matched / paired control die 311. In other embodiments, the control die may be coupled (or otherwise connected) to more than one memory die.

[0060] At the end of a successful programming process, the threshold voltage of the memory cell should, as needed, be within one or more threshold voltage distributions of the programmed memory cell or within the threshold voltage distribution of the erased memory cell. Figure 3AThis is a graph comparing the threshold voltage to the number of memory cells, showing an example threshold voltage distribution for a memory array where each memory cell stores one data bit of data. A memory cell that stores one data bit of data per memory cell is called a single-level cell (“SLC”). The data stored in an SLC memory cell is called SLC data; therefore, SLC data consists of one bit per memory cell. Data stored as one bit per memory cell is SLC data. Figure 3A Two threshold voltage distributions are shown: E and P. Threshold voltage distribution E corresponds to the erase data state. Threshold voltage distribution P corresponds to the program data state. Therefore, memory cells with threshold voltages in threshold voltage distribution E are in the erase data state (e.g., they have been erased). Therefore, memory cells with threshold voltages in threshold voltage distribution P are in the program data state (e.g., they have been programmed). In one embodiment, erase memory cells store data "1" and program memory cells store data "0". Figure 3A Describe the read reference voltage Vr. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is higher or lower than Vr, the system can determine whether the memory cell has been erased (state E) or programmed (state P). Figure 3A The verification reference voltage Vv is also described. In some embodiments, when memory cells are programmed to data state P, the system tests whether those memory cells have a threshold voltage greater than or equal to Vv.

[0061] Figure 3B -D illustrates an example threshold voltage distribution for a memory array when each memory cell stores multiple data bits per memory cell. A memory cell that stores multiple data bits per memory cell is called a multilevel cell (“MLC”). The data stored in an MLC memory cell is called MLC data; therefore, MLC data comprises multiple bits per memory cell. Data stored as multiple data bits per memory cell is MLC data. Figure 3B In the example embodiment, each memory cell stores two data bits. Other embodiments may use different data capacities per memory cell (e.g., three, four, or five data bits per memory cell).

[0062] Figure 3B The first threshold voltage distribution E for erasing memory cells is shown. Three threshold voltage distributions A, B, and C for programming memory cells are also depicted. In one embodiment, the threshold voltage in distribution E is negative, while the threshold voltages in distributions A, B, and C are positive. Figure 3BEach distinct threshold voltage distribution corresponds to a predetermined value in the data bit set. The specific relationship between the data programmed into the memory cell and the cell's threshold voltage level depends on the data encoding scheme employed by the cell. Table 1 provides example encoding schemes.

[0063] Table 1

[0064] E A B C LP 1 0 0 1 UP 1 1 0 0

[0065] Figure 3B An example of a two-pass technique for programming MLC data to two different pages (the next page and the previous page) is shown. Four states are described: state E (11), state A (10), state B (00), and state C (01). For state E, both pages store "1". For state A, the next page stores "0" and the previous page stores "1". For state B, both pages store "0". For state C, the next page stores "1" and the previous page stores "0". It should be noted that although a specific bit pattern has been assigned to each of the states, different bit patterns can also be assigned. In the first programming pass, the threshold voltage level of the memory cell is set according to the bit to be programmed to the next logical page. If the bit is logic "1", the threshold voltage does not change because it is in the appropriate state due to being previously erased. However, if the bit to be programmed is logic "0", the threshold level of the cell increases to state A, as indicated by arrow 530. The first programming pass ends here.

[0066] In the second programming pass, the threshold voltage level of the memory cell is set according to the bit to be programmed to the upper logical page. If the upper logical page bit will store a logic "1", the cell is in either state E or A without programming, depending on the programming of the lower page bit, both of which carry the upper page bit "1". If the upper page bit is a logic "0", the threshold voltage is shifted. If the first pass leaves the cell in the erase state E, then in the second stage, the memory cell is programmed such that the threshold voltage increases to state C, as depicted by arrow 534. If the memory cell has already been programmed to state A due to the first programming pass, then in the second pass, the memory cell is further programmed such that the threshold voltage increases to state B, as depicted by arrow 532. The result of the second pass is to program the memory cell to a state that specifies storing the upper page's logic "0" without changing the data on the lower page.

[0067] Figure 3C The example threshold voltage distribution of the memory cell is depicted, where each memory cell stores three data bits per memory cell (another instance of MLC data). Figure 3CEight threshold voltage distributions are shown, corresponding to eight data states. The first threshold voltage distribution (data state) Er represents an erased memory cell. The other seven threshold voltage distributions (data states) A ​​to G represent programmed memory cells and are therefore also called programming states. Each threshold voltage distribution (data state) corresponds to a predetermined value for a set of data bits. The specific relationship between the data programmed into a memory cell and the cell's threshold voltage level depends on the data encoding scheme used by the cell. In one embodiment, Gray code is used to assign data values ​​to a range of threshold voltages, such that if the memory's threshold voltage is erroneously shifted to its adjacent physical state, only one bit will be affected. Table 2 provides examples of encoding schemes.

[0068] Table 2

[0069] Er A B C D E F G UP 1 1 1 0 0 0 0 1 MP 1 1 0 0 1 1 0 0 LP 1 0 0 0 0 1 1 1

[0070] Figure 3C Seven read reference voltages, VrA, VrB, VrC, VrD, VrE, VrF, and VrG, are shown for reading data from memory cells. By testing (e.g., performing a sensing operation) whether a threshold voltage for a given memory cell is higher or lower than the seven read reference voltages, the system can determine which data state the memory cell is in (i.e., A, B, C, D, ...).

[0071] Figure 3C Seven verification reference voltages, VvA, VvB, VvC, VvD, VvE, VvF, and VvG, are also shown. In some embodiments, when a memory cell is programmed to data state A, the system tests whether those memory cells have a threshold voltage greater than or equal to VvA. When a memory cell is programmed to data state B, the system tests whether the memory cell has a threshold voltage greater than or equal to VvB. When a memory cell is programmed to data state C, the system determines whether the memory cell has a threshold voltage greater than or equal to VvC. When a memory cell is programmed to data state D, the system tests whether those memory cells have a threshold voltage greater than or equal to VvD. When a memory cell is programmed to data state E, the system tests whether those memory cells have a threshold voltage greater than or equal to VvE. When a memory cell is programmed to data state F, the system tests whether those memory cells have a threshold voltage greater than or equal to VvF. When a memory cell is programmed to data state G, the system tests whether those memory cells have a threshold voltage greater than or equal to VvG. Figure 3C It also shows Vev, which is the voltage level used to test whether the memory cell has been properly erased.

[0072] In one embodiment known as full-sequence programming, the following can be used (discussed below). Figure 4 The process directly programs memory cells from the erased data state Er to any of the programmed data states A through G. For example, a group of memory cells to be programmed can be erased first, so that all memory cells in the group are in the erased data state Er. Then, the programming process directly programs the memory cells to data states A, B, C, D, E, F, and / or G. For example, while some memory cells are programmed from data state Er to data state A, other memory cells are programmed from data state Er to data state B and / or from data state Er to data state C, etc. Figure 3C The arrows indicate full-sequence programming. In some embodiments, data states A through G may overlap, where control of die 311 and / or memory controller 102 relies on error correction to identify the correct data being stored.

[0073] Generally, during verification and read operations, the selected word line is connected to a voltage (an example of a reference signal), and the level of said voltage is specified for each read operation (see, for example, see...). Figure 3C The read comparison levels VrA, VrB, VrC, VrD, VrE, VrF, and VrG) or the levels of the voltages specified for the verification operation (e.g., see [link to documentation]). Figure 3C Verification target levels (VvA, VvB, VvC, VvD, VvE, VvF, and VvG) are used to determine whether the threshold voltage of the relevant memory cell has reached such levels. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell is turned on (conducting current) in response to the voltage applied to the word line. If the measured conduction current is greater than a certain value, the memory cell is assumed to be turned on, and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the measured conduction current is not greater than the certain value, the memory cell is assumed to be not turned on, and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During the read or verification process, unselected memory cells have one or more read pass voltages (also known as bypass voltages) at their control gate, causing these memory cells to operate as on gates (e.g., conducting current regardless of whether these memory cells are programmed or erased).

[0074] There are many ways to measure the conduction current of a memory cell during a read or verification operation. In one example, the conduction current of a memory cell is measured by the rate at which the conduction current discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) the NAND string containing that memory cell to discharge to the corresponding bit line. The voltage on the bit line is measured after a period of time to see if the bit line has discharged. It should be noted that the techniques described herein can be used with various methods known in the art for verification / reading. Other read and verification techniques known in the art may also be used.

[0075] Figure 3D Depicts the threshold voltage distribution when each memory cell stores four data bits (another instance of MLC data). Figure 3D There may be some overlap between the threshold voltage distribution (data states) S0 and S15. This overlap may occur due to factors such as memory cell charge loss (and therefore a decrease in threshold voltage). Programming interference may unintentionally increase the threshold voltage of a memory cell. Similarly, read interference may unintentionally increase the threshold voltage of a memory cell. The position of the threshold voltage distribution can change over time. Such changes can increase the bit error rate, thereby prolonging decoding time or even making decoding impossible. Changing the read reference voltage can help mitigate these effects. Using ECC during the read process can correct errors and ambiguities. When using four bits per memory cell, the memory can be programmed using the full-sequence programming discussed above or the multi-pass programming process known in the field. Figure 3D Each threshold voltage distribution (data state) corresponds to a predetermined value in the data bit set. The specific relationship between the data programmed into the memory cell and the cell's threshold voltage level depends on the data encoding scheme used by the cell. Table 3 provides examples of encoding schemes.

[0076] Table 3

[0077]

[0078]

[0079] Where TP = top page, UP = previous page, MP = middle page, and LP = next page

[0080] Figure 4 This is a flowchart illustrating one embodiment of the process of programming memory cells. For the purposes of this document, the terms programming and programming are synonymous with writing and writing. In one example embodiment, the memory array 302 is executed using the control circuitry system 310 discussed above. Figure 4The process. For example, it can be executed in the direction of state machine 362. Figure 4 The process. In one embodiment, using Figure 4 The process programs codewords into memory array 302. In some embodiments, this is performed by control die 311. Figure 4 The process of programming memory cells on the memory die.

[0081] exist Figure 11 In step 602, the programming voltage signal (Vpgm) is initialized to an initial amplitude (e.g., approximately 12 to 16V or another suitable level), and the programming counter PC maintained by state machine 362 is initialized to 1. In one embodiment, a group of memory cells selected for programming (referred to herein as selected memory cells) are programmed in parallel and are all connected to the same word line (selected word line). Other memory cells not selected for programming (unselected memory cells) may also be connected to the selected word line. That is, the selected word line will also be connected to memory cells that should be disabled for programming. Furthermore, as a memory cell reaches its expected target data state, further programming of that memory cell is disabled. NAND strings containing memory cells connected to the selected word line that should be disabled for programming (e.g., unselected NAND strings) boost their channels to disable programming. When the channels have boosted voltage, the voltage difference between the channels and the word line is not large enough to induce programming. To assist boosting, in step 604, the die is controlled to precharge the channels of the NAND strings containing memory cells connected to the selected word line that should be disabled for programming. In step 606, the NAND strings containing memory cells connected to the selected word lines that should be disabled for programming boost their channels to suppress programming. Such NAND strings are referred to herein as "unselected NAND strings". In one embodiment, the unselected word lines receive one or more boosted voltages (e.g., about 7 to 11 volts) to perform a boosting scheme. A programming disable voltage is applied to the bit lines coupled to the unselected NAND strings.

[0082] In step 608, a programming pulse of the programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming) by controlling the die. If memory cells on the NAND string are to be programmed, the corresponding bit line is biased at the programming enable voltage. In step 608, the programming pulse is simultaneously applied to all memory cells connected to the selected word line, such that all memory cells connected to the selected word line are programmed simultaneously (unless programming of the memory cells is disabled). That is, the memory cells are programmed simultaneously or during the overlap time (both are considered parallel). In this way, unless programming of all memory cells connected to the selected word line is disabled, the memory cells will change their threshold voltage simultaneously.

[0083] In step 610, the memory cell that has reached its target state is locked by controlling the die to prevent further programming. Step 610 may include performing verification at one or more verification reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltage of the selected memory cell for programming has reached the appropriate verification reference voltage. In step 610, the memory cell may be locked after the verified memory cell (by testing Vt) has determined that the memory cell has reached its target state.

[0084] If it is determined in step 612 that all memory cells have reached their target threshold voltage (pass), the programming process is complete and successful because all selected memory cells have been programmed and verified to their target state. In step 614, a "PASS" status is reported. Otherwise, if it is determined in step 612 that not all memory cells have reached their target threshold voltage (fail), the programming process continues to step 616.

[0085] In step 616, the number of memory cells that have not yet reached their corresponding target threshold voltage distribution is counted. That is, the number of memory cells that have failed to reach their target state so far is counted. This counting can be performed by state machine 362, memory controller 102, or other logic. In one embodiment, each of the sensing blocks stores the state (pass / fail) of its corresponding cell. In one embodiment, there is a total count reflecting the total number of currently programmed memory cells that failed the last verification step. In another embodiment, a separate count is maintained for each data state.

[0086] In step 618, it is determined whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during the read process of a memory cell page. If the number of failed cells is less than or equal to the predetermined limit, the programming process can stop and a "pass" status is reported in step 614. In this case, enough memory cells have been correctly programmed so that the few remaining memory cells that have not yet been fully programmed can be corrected by ECC during the read process. In some embodiments, the predetermined limit used in step 618 is lower than the number of bits that can be corrected by an error correction code (ECC) during the read process, thereby allowing for future / additional errors. When programming less than all memory cells of a page, or comparing counts for only one data state (or less than all states), the predetermined limit may be a portion (proportional or disproportionate) of the number of bits that can be corrected by ECC during the read process of a memory cell page. In some embodiments, no predetermined limit is set. Instead, the limit is varied based on the number of errors counted against the page count, the number of program-erase cycles performed, or other criteria.

[0087] If the number of failed memory cells is not less than a predetermined limit, the programming process continues in step 620, and the programming counter PC is checked against the programming limit (PL). Examples of programming limits include 6, 12, 16, 19, and 30; however, other values ​​can be used. If the programming counter PC is not less than the programming limit PL, the programming process is considered failed, and a failure (FAIL) status is reported in step 624. If the programming counter PC is less than the programming limit PL, the process continues in step 626, during which the programming counter PC is incremented by 1 and the programming voltage signal Vpgm is stepped to the next amplitude. For example, the next pulse will have an amplitude that is one step larger than the previous pulse (e.g., a step of 0.1 to 1.0 volts). After step 626, the process loops back to step 604, and (by controlling the die) another programming pulse is applied to the selected word line, causing execution to... Figure 4 Another iteration of the programming process (steps 604 to 626).

[0088] Figure 4 The programming process can be used to... Figure 3A Programming SLC data according to Figure 3B Each iteration programs the MLC data according to... Figure 3C The entire sequence of programming and each pass of another multi-pass programming process programs the MLC data.

[0089] In one embodiment, erasure is the process of changing the threshold voltage of one or more memory cells from a programmed data state to an erased data state. For example, changing the threshold voltage of one or more memory cells from... Figure 3A The state P changes to the state E, from Figure 3B The state changes from A / B / C to E. Figure 3C The state changes from A to G to state Er, or from S1 to S15 to state S0.

[0090] Erasure is typically performed at the block level. Programming, on the other hand, is performed at the page or subpage level (a block comprises many pages). Therefore, when a conventional non-volatile memory system rewrites data in a specific page of a specific block, all valid data in all pages of that block except for that specific page is moved and reprogrammed into the new block. New data is also programmed into the new block. After moving and reprogramming into the new block, the specific block is then erased and made available for future programming. Moving and reprogramming valid data slows down the programming process and consumes additional space in memory (because there must be areas in memory available for moving and reprogramming data).

[0091] To address these issues, a method called incremental data writing is proposed. This means rewriting existing data with new data without performing a traditional erase operation that reverts the threshold voltage of the non-volatile memory cell to a conventional or pristine erase state. In one example, a shifted threshold voltage distribution is used to write new data over old data. By performing incremental data writing without the need for a traditional erase operation that reverts the threshold voltage of the non-volatile memory cell to a conventional or pristine erase state, the programming / writing process is faster and requires less space in memory.

[0092] Figure 5 This describes an example of a process where incrementally writing data allows existing data to be rewritten with new data without performing a conventional erase operation that reverts the threshold voltage of the non-volatile memory cell to its traditional or original erase state. Figure 5 In one embodiment, existing SLC data is rewritten with new SLC data instead of performing a traditional erase operation. Figure 5 Three graphs, 720, 722, and 724, are shown, each plotting the number of memory cells against a threshold voltage. Initially, all data is in an initial erase state, corresponding to threshold voltage distribution 702 (also referred to as state 702). A first write process, writing the first data, causes the memory cells to be distributed between state 702 and state 704, both of which are threshold voltage distributions. For example, those memory cells storing data "1" will remain in state 702, while those memory cells storing data "0" will move to state 704 through a write (e.g., programming) process.

[0093] After the first write operation is performed, second data is received for the second write operation. The purpose is to rewrite the first data with the second data. For the purposes of this document, rewriting existing data means erasing and replacing existing data. In the past, this meant first erasing the memory cells, returning all memory cells to the initial erase state 702, and then writing the second data to the memory cells. However, Figure 5The embodiment illustrates a second write (from graph 720 to graph 722) comprising rewriting the first data with the second data, causing the first data to disappear, without the memory cells returning to the initial erase state 702. The second write is performed using shifted threshold voltage distributions 704 and 706. For example, those memory cells storing data "1" will be in state 704, while those storing data "0" will be in state 706. More specifically, those memory cells in state 702 due to the first write and being rewritten by data "1" move to state 704. Those memory cells in state 702 due to the first write and being rewritten by data "0" move to state 706. Those memory cells in state 704 due to the first write and being rewritten by data "1" remain in state 704. Those memory cells in state 704 due to the first write and being rewritten by data "0" move to state 706. At the end of the second write, these memory cells are no longer in use in state 702.

[0094] After the second write operation, third data is received for the third write. The purpose is to rewrite the second data with the third data. The third write operation (from graphs 722 to 724) involves rewriting the second data with the third data so that the second data is erased, but the memory cells do not return to the initial erase state 702. The third write is performed using shifted threshold voltage distributions 706 and 708. For example, those memory cells storing data "1" will be in state 706, while those memory cells storing data "0" will be in state 708. More specifically, those memory cells that were in state 704 due to the second write and are being rewritten by data "1" move to state 706. Those memory cells that were in state 704 due to the second write and are being rewritten by data "0" move to state 708. Those memory cells that were in state 706 due to the second write and are being rewritten by data "1" remain in state 706. Those memory cells that were in state 706 due to the second write and are being rewritten by data "0" move to state 708. At the end of the third write, these memory cells are no longer in use in states 702 and 704.

[0095] In some embodiments, the memory can be kept writing to progressively higher states. In some embodiments, the number of states is limited to a finite number (e.g., 3, 4, 5, 8, 16). After data has been written to the highest allowed state, when new data is needed again, the memory will first erase back to the initial erase state (e.g., state 702) and then program the new data.

[0096] It should be noted that the second write uses one of the states of the first write, namely state 704. In another embodiment, consecutive writes use a new set of states. For example, in one embodiment, the second write will place the memory cell in states 706 and 708, and the third write will use a state with a voltage amplitude higher than the threshold voltage range of state 708.

[0097] Figure 6 This describes another example of a process where incrementally writing data allows existing data to be rewritten with new data without performing a conventional erase operation that reverts the threshold voltage of the non-volatile memory cell back to its traditional or original erase state. Figure 6 This shows a graph plotting the number of memory cells against a threshold voltage. Figure 6 In this embodiment, existing SLC data is rewritten with new MLC data without performing a conventional erase operation. Before being written to the memory cells, the memory cells are in an initial erase state 702. A first write process, writing the first data, distributes the memory cells between states 702 and 704, both of which have threshold voltage distributions. For example, those memory cells storing data "1" will remain in state 702, while those storing data "0" will move to state 704 via a write (e.g., programming) process. Other data-to-state encodings can also be used.

[0098] After the first write operation, second data is received for the second write. The purpose is to rewrite the first data with the second data, causing the first data to disappear, without the memory cell returning to the initial erase state 702. The second write is performed using shifted threshold voltage distributions 704, 706, 708, and 710. Figure 6 In one example, the second data comprises two data bits per memory cell; therefore, four data states are used. In other embodiments, the second data comprises more than two data bits per memory cell, such that the second data can be programmed with more than four states.

[0099] exist Figure 6In one example, the memory cells storing data "11" are in state 704, the memory cells storing data "10" are in state 706, the memory cells storing data "00" are in state 708, and the memory cells storing data "01" are in state 710. More specifically, those memory cells that were in state 702 due to the first write and were being rewritten by data "11" move to state 704; those memory cells that were in state 702 due to the first write and were being rewritten by data "10" move to state 706; those memory cells that were in state 702 due to the first write and were being rewritten by data "00" move to state 708; those memory cells that were in state 702 due to the first write and were being rewritten by data "01" move to state 710; those memory cells that were in state 704 due to the first write and were being rewritten by data "11" remain in state 704; those memory cells that were in state 704 due to the first write and were being rewritten by data "10" move to state 706; those memory cells that were in state 704 due to the first write and were being rewritten by data "00" move to state 708; and those memory cells that were in state 704 due to the first write and were being rewritten by data "01" move to state 710. In the embodiment shown in Figure 6, existing SLC data is rewritten with new MLC data. In other embodiments, existing MLC data can be rewritten with SLC data.

[0100] Figure 7 This is a flowchart of an embodiment describing a process of incrementally writing data so that existing data is rewritten with new data without performing a conventional erase operation that changes the threshold voltage of the non-volatile memory cell back to the conventional or original erase state. Figure 7 The process description outlines an embodiment of rewriting existing SLC data with new MLC data without performing a traditional erase operation. Therefore, Figure 7 The process can be used to implement Figure 6 The technology described in the text. Figure 7 The process can be implemented using any of the control circuits described above. For example, Figure 7 The process can be executed by or under the control of the memory controller 102 and / or the state machine 362 (or the processor on the memory die).

[0101] exist Figure 7Step 750 places the non-volatile memory cells in an initial erase state. For example, a group of memory cells may be erased, leaving them all in state 702. Step 752 includes writing first data as SLC data to the set of non-volatile memory cells, causing at least a subset of the non-volatile memory cells to exit the initial erase state (e.g., 702), and each corresponding non-volatile memory cell in the set of non-volatile memory cells is assigned a corresponding state in a first set of states based on the first corresponding data value to be stored in the corresponding non-volatile memory cell. That is, a subset of non-volatile memory cells exits the initial erase state (e.g., 702) to be in state 704, and each memory cell is assigned one of state 702 or 704 based on the data to be stored.

[0102] Step 754 involves writing second data as MLC data into the non-volatile memory cell set by rewriting the first data without restoring any subset of non-volatile memory cells to their initial erased state, such that each corresponding non-volatile memory cell in the set is assigned a corresponding state in a second state set based on the second corresponding data value to be stored in that non-volatile memory cell. For example, memory cells are reassigned from states 702 / 704 (storing SLC data 0 or 1) to states 704 / 706 / 708 / 710 (storing MLC data of 11, 10, 00, or 01). The second state set (704 / 706 / 708 / 710) contains more states than the first state set (702 / 704). Rewriting the first data involves clearing the first data and replacing it with the second data.

[0103] exist Figure 7 In one example implementation, each state in a first state set (e.g., 702 / 704) is associated with a corresponding threshold voltage range. The first state set includes a lowest state (e.g., 702) associated with the lowest threshold voltage range of the first state set and a highest state (e.g., 704) associated with the highest threshold voltage range of the first state set. Each state in a second state set (704 / 706 / 708 / 710) is associated with a corresponding threshold voltage range such that all threshold voltages in the second state set are higher in voltage magnitude than the threshold voltage of the lowest state (e.g., 704 / 706 / 708 / 710 are higher in voltage magnitude than 702), and at least one subset of the threshold voltages of the second state set (e.g., associated with 706 / 708 / 710) are higher in voltage magnitude than all threshold voltages of the first state set.

[0104] exist Figure 7In one example implementation, the control circuitry is configured to rewrite first data in the set of non-volatile memory cells by increasing the threshold voltage of at least one subset of the set of non-volatile memory cells without decreasing the threshold voltage of any single non-volatile memory cell in the set of non-volatile memory cells. That is, during incremental writes, the threshold voltage will increase or remain constant, but will not be intentionally decreased.

[0105] exist Figure 7 In one example implementation, the control circuitry is configured to write first data as SLC data to the non-volatile memory cell set by storing one data bit in any of two states 702 / 704 of a first state set, and the control circuitry is configured to rewrite the first data by storing two or more data bits in any of four or more states 704 / 706 / 708 / 710 of a second state set (e.g., as shown in the example implementation). Figure 6 (As depicted).

[0106] Figure 8 This describes another example of a process where incrementally writing data allows existing data to be rewritten with new data without performing a conventional erase operation that reverts the threshold voltage of the non-volatile memory cell to its traditional or original erase state. Figure 8 In one embodiment, the SLC data is rewritten with new SLC data instead of performing a traditional erase operation. Figure 8 Three graphs, 820, 822, and 824, are shown, each plotting the number of memory cells against a threshold voltage. Initially, all data is in an initial erase state, corresponding to threshold voltage distribution 802 (also referred to as state 802). A first write process, writing the first data, causes the memory cells to be distributed between state 802 and state 804, both of which are threshold voltage distributions. For example, those memory cells storing data "1" will remain in state 802, while those storing data "0" will move to state 804 through a write (e.g., programming) process. That is, the write process causes some of the multiple non-volatile memory cells to move from the initial erase state 802 to the programming state 804 in the current state set (802 and 804).

[0107] After the first write operation is performed, second data is received for the second write. The second write (from graph 820 to graph 822) involves rewriting the first data with the second data without first returning the memory cell that exited the initial erase state to the initial erase state 802. The second write is performed using threshold voltage distributions 802, 804, and 806. Figure 8In this embodiment, the write process only changes the threshold voltage of the memory cell to be written with data "0". The threshold voltage of the memory cell to be written with data "1" remains unchanged. That is, existing data in the non-volatile memory cell is rewritten with new data by keeping a subset of the non-volatile memory cells in the initial erase state 802 while moving a subset of the non-volatile memory cells to the programming state 806 in the new state set. For example, those memory cells that are in state 802 due to the first write and are being rewritten with data "1" remain in state 802, while those memory cells that are in state 804 due to the first write and are being rewritten with data "1" remain in state 804. Those memory cells that are in state 802 due to the first write and are being rewritten with data "0" move to state 806. Those memory cells that are in state 804 due to the first write and are being rewritten with data "0" move to state 806. At the end of the second write operation, those memory cells storing data "1" will be in state 802 or 804, while those storing data "0" will be in state 806. It should be noted that after the second write operation, there are three valid states: 802, 804, and 806. Therefore, the technique disclosed herein is not fixed to a number of states that are powers of 2. This provides greater flexibility and efficiency in the use of the threshold voltage space.

[0108] After the second write operation, third data is received for the third write. The purpose is to rewrite the second data with the third data. The third write operation (from curves 822 to 824) involves rewriting the second data with the third data without returning the memory cells in states 804 and 806 to the initial erase state 802. Similar to the second write, the third write only changes the threshold voltage of the memory cells being rewritten with data "0". For example, those memory cells in state 802 due to the second write and being rewritten with data "1" remain in state 802, those memory cells in state 804 due to the second write and being rewritten with data "1" remain in state 804, and those memory cells in state 806 due to the second write and being rewritten with data "1" remain in state 806. Those memory cells in state 804 due to the second write and being rewritten with data "0" move to state 808. Those memory cells in state 806 due to the second write and being rewritten with data "0" move to state 808. At the end of the third write, the memory cells that stored data "1" will be in state 802, 804, or 806, while the memory cells that stored data "0" will be in state 808.

[0109] although Figure 8The concept of rewriting SLC data, but only changing the memory cell storing "0", can also be applied to MLC data. In such embodiments, the initial erase state stores "11", and if the new data used to rewrite existing data is "11", the memory cell does not change its threshold voltage.

[0110] Figure 9 This describes another example of a process where incrementally writing data allows existing data to be rewritten with new data without performing a conventional erase operation that reverts the threshold voltage of the non-volatile memory cell to its traditional or original erase state. Figure 9 In one embodiment, the SLC data is rewritten with new SLC data instead of performing a traditional erase operation. Figure 9 Three graphs, 850, 852, and 854, are shown, each plotting the number of memory cells against a threshold voltage. Initially, all data is in an initial erase state, corresponding to threshold voltage distribution 860 (also referred to as state 860). A first write process, writing the first data, causes the memory cells to be distributed between state 860 and state 862, both of which are threshold voltage distributions. For example, those memory cells storing data "1" will remain in state 860, while those storing data "0" will move to state 862 through a write (e.g., programming) process. That is, the write process causes some of the multiple non-volatile memory cells to move from the initial erase state 860 to the programming state 862 in the current state set (860 and 862).

[0111] After the first write operation is performed, second data is received for the second write operation. The purpose is to rewrite the first data with the second data. Figure 9 In this embodiment, subsequent writes are performed by first programming / writing all memory cells to the same intermediate state to make the memory cells appear to have been erased. This intermediate state is called the common new erase state, and it differs from the initial erase state 860. After all memory cells are in the common new erase state, all or a subset of the memory cells are programmed / written to one or more new sets of states. For example, Figure 9 This illustrates that when the second write is performed, all memory cells are programmed into a common new erase state 864. In one embodiment, the common new erase state 864 is the same as the highest state 862 in the first state set. In another embodiment, the common new erase state 864 partially overlaps with state 862, such that a portion of the common new erase state 864 has a higher threshold voltage than state 862. In yet another embodiment, all common new erase states 864 have a higher voltage amplitude than state 862.

[0112] After all memory cells are in a common new erase state 864, they are programmed such that the memory cells are distributed between states 866 and 868. That is, those memory cells rewritten with data "1" move to state 866, while those rewritten with data "0" move to state 868. In one embodiment, state 866 is identical to common new erase state 864. In another embodiment, state 866 partially overlaps with common new erase state 864, such that a portion of state 866 has a higher threshold voltage than common new erase state 864. In yet another embodiment, all states 866 have a higher voltage amplitude than common new erase state 864.

[0113] Figure 9 Only the first and second writes are shown. The technique of using a common new erase state can also be used for the third, fourth, and so on. For example, when performing a third write, the common new erase state may have the same threshold voltage distribution as state 868 (or may have a higher voltage amplitude).

[0114] although Figure 9 This illustrates SLC data rewriting, but the concept of a common new erase state can also be used for MLC data. For example, starting from common new erase state 864, memory cells can be programmed to three or more states where the threshold voltage is higher than common new erase state 864.

[0115] Figure 10 This is a flowchart of an embodiment describing a process of incrementally writing data so that existing data is rewritten with new data without performing a conventional erase operation that changes the threshold voltage of the non-volatile memory cell back to the conventional or original erase state. Figure 10 The process description outlines an embodiment of programming / writing memory cells to a common new erase state, and then programming / writing all or a subset of the memory cells from the common new erase state to one or more new sets of states. Therefore, Figure 10 The process can be used to implement Figure 9 The system described in the text. Figure 10 The process can be implemented using any of the control circuits described above. For example, Figure 10 The process can be executed by or under the control of the memory controller 102 and / or the state machine 362 (or the processor on the memory die). Figure 10 The process can be used for SLC data or MLC data.

[0116] Figure 10 Step 890 includes writing first data into a set of non-volatile memory cells, such that each non-volatile memory cell in the set is assigned a corresponding state from a first set of states (e.g., ...). Figure 9The first state set includes states 860 and 862. Each state in the first state set is associated with a corresponding threshold voltage range. The first state set contains the lowest state (e.g., state 860) associated with the lowest threshold voltage range of the first state set and the highest state (e.g., state 862) associated with the highest threshold voltage range of the first state set. Step 892 includes rewriting the first data in the non-volatile memory cell set with the second data, such that each non-volatile memory cell in the non-volatile memory cell set is assigned a corresponding state in the second state set (e.g., states 866 and 868). Each state in the second state set is associated with a corresponding threshold voltage range.

[0117] In one embodiment, step 892, rewriting the first data in the non-volatile memory cell set with the second data includes increasing the threshold voltage of at least one subset of the non-volatile memory cell set (e.g., curves 850 to 852) such that all non-volatile memory cells in the non-volatile memory cell set are in a common new erase state (step 892a). The common new erase state (e.g., Figure 9 State 864 is associated with a threshold voltage range that is equal to or higher than the threshold voltage of the highest data state in terms of voltage amplitude. After all non-volatile memory cells in the non-volatile memory cell set are in a common new erase state, the threshold voltage of at least some non-volatile memory cells in the non-volatile memory cell set (e.g., curves 852 to 854) is raised from the common new erase state to one or more states in a second state set that have a higher threshold voltage than the common new erase state (step 892b).

[0118] Figure 11 This is a flowchart of an embodiment describing a process of incrementally writing data so that existing data is rewritten with new data without performing a conventional erase operation that changes the threshold voltage of the non-volatile memory cell back to the conventional or original erase state. Figure 11 The process description outlines an embodiment of programming / writing memory cells to a common new erase state, and then programming / writing all or a subset of the memory cells from the common new erase state to one or more new sets of states. Therefore, Figure 11 The process can be used to implement Figure 9 The system described in [the text]. Additionally... Figure 11 The process is Figure 10 Example implementation of the process. Figure 11 The process can be implemented using any of the control circuits described above. For example, Figure 11 The process can be executed by or under the control of the memory controller 102 and / or the state machine 362 (or the processor on the memory die). Figure 10 The process can be used for SLC data or MLC data.

[0119] exist Figure 11 In step 902, the system detects the current state set among multiple state sets used by the non-volatile memory cells to store the current data. For example, reviewing... Figure 5 Curve 720 contains the first state set, curve 722 contains the second state set, and curve 724 contains the third state set. Therefore, regarding Figure 5 Multiple state sets include a first state set, a second state set, and a third state set. (As mentioned above...) Figure 5 The discussion focuses on the fact that at any given time, a memory cell can be in a first state set, a second state set, or a third state set. Figure 11 Step 902 includes, for example, determining whether the memory cell is in a first state set, a second state set, or a third state set. In step 904, the system determines whether the memory cell is already in the highest supported state set. For example, regarding... Figure 5 The third set of states associated with graph 724 (e.g., states 706 and 708) represents the highest supported state set. If a memory cell is already in the highest supported state set, then... Figure 11 The programming operation is aborted during this process (step 906). That is, in one embodiment, if the memory cell is already in the highest supported state set, it needs to be erased to the initial erased state before performing additional programming. If it is determined in step 904 that the memory cell is not yet in the highest supported state set, then in step 908, the system will begin programming the new data to rewrite the existing data. It should be noted that steps 904 and 908 represent instances where an additional state set is determined to be available for storing new data in the set of non-volatile memory cells.

[0120] In step 908, the system senses data from memory cells that will be used to store new data. The sensing in step 908 determines what the current data is in those memory cells. In step 910, the sensed data is inverted. That is, any data that is "1" is changed to "0", and any data that is "0" is changed to "1". In step 912, the data will be used for programming (see...). Figure 4 The verification target (e.g., verifying the reference voltage Vv) is set to the voltage magnitude of the current highest state (or higher). In one embodiment, the verification target is set to the lowest voltage magnitude of the current highest state. For example, reviewing... Figure 9If the data is currently in states 860 and 862, step 912 includes setting the verification target to the lowest voltage of state 862. In step 914, the system performs an SLC programming process on the inverted sensed data using the verification target set in step 912. This causes the memory cell in state 860 to move to state 864, and the memory cell in state 862 to remain in states 862 / 864 (note that in this embodiment, state 864 is the same as state 862).

[0121] In step 916, it is determined whether the SLC programming process has completed successfully. If not, the process proceeds to step 906 to abort the current programming operation and perform an erase, then proceed with subsequent programming. However, if the SLC programming process in step 914 has completed successfully, all memory cells are in a common newly erased state. In step 918, the system updates one or more verification targets and performs programming on the new data. The programming of the new data can be for SLC data or MLC data. In one embodiment, using Figure 4 The process executes the SLC programming process of Figure 914, which may include applying multiple programming pulses (e.g., multiple iterations of steps 604-626). In another embodiment, the process of step 914 may include applying only one programming pulse (e.g., one iteration of steps 604-626). In an embodiment, when using only one programming pulse, the amplitude of the programming pulse must be set such that all memory cells can raise their threshold voltage to a common new erase state. Furthermore, disabling and not performing (e.g., in...) Figure 4 The programming verification is performed during step 610.

[0122] In one embodiment, when executed at the system level (e.g., under the control of memory controller 102) Figure 11 During the process, Figure 11 Step 902 may cause data currently stored in the memory cell (e.g., existing data) to be read out to the memory controller. If so, then in step 908, the memory controller does not need to request the memory die to send data. In embodiments, this is performed at the memory die level (e.g., by state machine 362 or another processor on the memory die, or under its control). Figure 11 During the process, step 902 may involve sensing data and storing the sensed data in a latch on the memory die. If the data is stored in a latch, then a second sensing of data is not required in step 908.

[0123] Figure 12This is a flowchart of an embodiment describing a process of incrementally writing data so that existing data is rewritten with new data without performing a conventional erase operation that changes the threshold voltage of the non-volatile memory cell back to the conventional or original erase state. Figure 12 The process is Figure 5-11 Example implementation of any process. Figure 12 The process can be implemented using any of the control circuits described above. For example, Figure 12 The process can be executed by or under the control of the memory controller 102 and / or the state machine 362 (or the processor on the memory die). Figure 12 The process can be used for SLC data or MLC data.

[0124] exist Figure 12 Step 1002 involves receiving new data. This new data will be used to rewrite the existing data stored in the set of non-volatile memory cells. Step 1004 involves performing one or more sensing operations on the non-volatile memory cells to automatically detect the current state set among multiple state sets used by the non-volatile memory cells to store existing data. Step 1004 is... Figure 11 An example implementation of step 902. In step 1006, it is determined whether the memory cell is already in the highest supported state set. If so, the current programming operation is aborted in step 1008, allowing the memory cell to be erased before subsequent programming. If the memory cell is not in the highest supported state set, in step 1010, a new state set is determined from a plurality of state sets based on performing one or more sensing operations to automatically detect the current state set in step 1004. The new state set contains at least one state not included in the current state set. For example, recall... Figure 5 If the current state set contains states 704 / 706, then the new state set contains states 706 / 708 (step 708 is not included in the current state set). In step 1012, the existing data in the non-volatile memory cells is rewritten with new data, such that each non-volatile memory cell is assigned the corresponding state in the new state set. For example, step 1004 can determine that the memory cell is in a certain state. Figure 5 In states 704 / 706, step 1010 can determine that the new state set includes steps 706 / 708, and step 1012 can include programming the memory cells by performing a third write, which rewrites the second data with third data (transitioning from graph 722 to graph 724), such that the memory cells are distributed between states 706 and 708. Therefore, Figure 12 The process determines which of the multiple state sets the currently stored data belongs to, so that it can identify which new state set can be used for new data that will be rewritten on top of the old data using a shifted threshold voltage distribution, as discussed above.

[0125] Figure 13 This is a flowchart of an embodiment describing a process of incrementally writing data so that existing data is rewritten with new data without performing a conventional erase operation that changes the threshold voltage of the non-volatile memory cell back to the conventional or original erase state. Figure 13 The process is Figure 5 Example implementation of the process described in the document. Figure 13 The process can also be used as an example implementation of step 1012 in Figure 12. Figure 13 The process can be implemented using any of the control circuits described above. For example, Figure 13 The process can be executed by or under the control of the memory controller 102 and / or state machine 362 (or processor on the memory die). In one example embodiment, the execution... Figure 13 The process involves rewriting the SLC data on top of the SLC data. In other embodiments, Figure 13 The process can be applied to MLC data.

[0126] exist Figure 13 In step 1050, existing data is sensed. For example, a read operation is performed, and the data can be stored in a latch on the memory die. If the process is performed at the system level, the data is sent back to the memory controller. In step 1052, a first verification level (e.g., for subsequent programming) is used. Figure 3A The verification reference voltage (-C) is set to the threshold voltage of the first state in the new state set. In one example, the first verification level is set to the lowest threshold voltage of the lowest state in the new state set. For example, recall... Figure 5 If the data is currently stored in state 704 / 706, then in one instance of step 1052, the first verification level is set to the lowest threshold voltage of data state 706. In step 1054, the system sets the second verification level to the threshold voltage of the second state of the new state. The second state corresponds to a higher threshold voltage than the first state. For example, see... Figure 5 Considering the above example, the second verification level can be set to the lowest threshold voltage of state 708 in step 1054. Figure 13In step 1056, the system performs an MLC programming operation to write new data as SLC data to a non-volatile memory cell using a first verification level and a second verification level. For example, the memory cell stored in states 704 and 706 is programmed to be in states 706 and 708. In one embodiment, the memory cell is programmed from states 704 and 706 to two states where the voltage amplitude is higher than that of state 706. It should be noted that step 1056 includes performing an MLC programming operation because the memory cell is programmed to two or more data states. In one instance, the memory cell may store data in states 702 and 704, and step 1056 programs the memory cell to states 706 and 708. In implementation... Figure 8 In another embodiment of the scheme, step 1056 may include programming the memory cell from data state 802 / 804 to state 802 / 804 / 806; or from state 802 / 804 to state 804 / 806 / 808; or other variations.

[0127] Figure 14 This is a flowchart illustrating one embodiment of the process of automatically detecting the current state set among multiple state sets used by non-volatile memory cells to store existing data. Therefore, Figure 14 The process is Figure 12 Example implementation of step 1004. Figure 14 The process can be implemented using any of the control circuits described above. For example, Figure 14 The process can be executed by or under the control of the memory controller 102 and / or the state machine 362 (or the processor on the memory die). Figure 14 The process can be used for SLC data, or is suitable for MLC data.

[0128] exist Figure 14 In step 1100, the system selects an intermediate read level that has not yet been eliminated from the remaining set of read levels. In one embodiment, there is a read level between each pair of adjacent states. The system can perform reads at those read levels to determine in what state each memory cell stores data. Figure 3A , 3BExamples of read levels are shown in Figure 3C (e.g., read reference voltages Vr, Vra). In step 1102, data / information from non-volatile memory cells is sensed using the selected read level. In step 1104, the number of memory cells with a threshold voltage below the selected read level is counted. Additionally, the number of memory cells with a threshold voltage above the selected read level is counted. If the number of memory cells with a threshold voltage (Vt) above the selected read level exceeds a first amount (e.g., approximately 50%) (step 1106), then in step 1120, the system eliminates read levels below the selected read level from the plurality of read levels. If the number of memory cells with a threshold voltage above the read level does not exceed the first amount, then in step 1108, it is tested whether the number of memory cells with a threshold voltage below the selected read level exceeds a second amount (e.g., approximately 50%) (step 1108). If so, then in step 1124, the system eliminates read levels above the selected read level from the plurality of read levels. After steps 1120 and 1124, the process proceeds to step 1122 to determine if there are any remaining valid levels. If so, the process continues to step 1100 and is executed. Figure 14 This is another iteration of the process. If no more valid read levels remain, an error exists, and in step 1130, the process will abort and return to a failed state.

[0129] If, in step 1108, it is determined that no more than a second amount of memory cells have a threshold voltage lower than the selected read level, then in step 1110, the selected read level is the read level of the current state set. Once the system understands the read level in step 1110, it can identify states below the read level and states above the read level, and these two identified states are used... Figure 14 The process automatically detects the current state set.

[0130] Figure 14 The process is an example of performing a binary search across multiple read levels, comprising sensing operations at one or more read levels to identify the current read level, for which at least a predetermined number of non-volatile memory cells have a threshold voltage higher than the identified current level and a predetermined number of non-volatile memory cells have a threshold voltage lower than the identified current level. In some embodiments, the system will likely limit the search by restricting the increment of writes between various physical locations. For example, after a maximum write, no location will be written more than four times, thus the range to be searched for the hierarchy will be smaller. This is analogous to balancing a binary tree in programming for performance / consistency reasons.

[0131] Figure 15 This is a flowchart illustrating one embodiment of the process for detecting whether a set of non-volatile memory cells is in a common new erase state. Figure 15 The process can be implemented using any of the control circuits described above. For example, Figure 15 The process can be executed by or under the control of the memory controller 102 and / or the state machine 362 (or the processor on the memory die). Figure 15 The process can be used for SLC data or MLC data.

[0132] exist Figure 15 In step 1202, the system selects the intermediate read level that has not yet been eliminated from the set of remaining read levels. Figure 15 Step 1202 is similar to Figure 14 Step 1100. In step 1204, the system uses the selected read level to sense data from the memory cell. Figure 15 Step 1204 is similar to Figure 14 Step 1102. In step 1206, the system counts the number of memory cells with a threshold voltage lower than the selected read level and the number of memory cells with a threshold voltage higher than the selected read level. Step 1206 is similar to... Figure 14 Step 1104. In Figure 15 In step 1208, the system determines whether approximately 100% of the memory cells have a threshold voltage higher than the selected read level. In other embodiments, a percentage less than 100% may be used. If the number of memory cells with a threshold voltage higher than the selected level is 100% or close to 100%, the system eliminates read levels below the selected read level and records the current read level as the lower limit. Otherwise, in step 1210, the system determines whether 100% (or close to 100%) of the memory cells have a threshold voltage lower than the selected read level. If so, in step 1216, the system eliminates read levels above the selected read level and notifies the current read level of the upper limit.

[0133] If, in step 1210, it is determined that the threshold voltage of 100% (or close to 100%) of the memory cells is not lower than the selected read level, then in step 1212, contention for the selected read level is resolved, and the process continues to step 1222. After steps 1214 and 1216, the process continues in step 1222, at which point the system determines whether there are any remaining valid read levels. As mentioned above, read level is a synonym for read reference voltage, as discussed above. If there are any remaining valid read levels (step 1222), the process continues in step 1202 to execute. Figure 15 Another iteration of the process. If there are no remaining valid read levels (step 1222), then in step 1224, the system determines whether the upper and lower limits (see steps 1214 / 1216) are adjacent. If so, then Figure 15The process is successful (passes), and the memory cell is in a common new erase state. If the upper and lower limits are not adjacent, then in step 1228, the system determines... Figure 15 The process failed, and not all memory cells were in a common new erase state.

[0134] In one embodiment, depending on memory usage, it may be advantageous to note that further programming may not yield good results. This can be performed by the memory controller at the system level or by the state machine at the die level. One reason to determine that further programming may not yield good results is if too many memory cells exceed their expected threshold voltage distribution. Over-increment can result from rapidly programming memory cells, which is not a problem in single-pass programming but becomes problematic in multi-pass programming because data may have been programmed high enough to corrupt future data programming. To check for over-increment, a sensing process at a level above the highest state will provide the number of bits above said state. The allowed bit threshold may need to be determined empirically, but needs to be well below the damage tolerance of the error correction engine.

[0135] In one embodiment, when programming on an MLC, an SLC read level search can be used to find the 50% point. Once the point is known, the highest MLC state can be a data state with one (or more) read / verify voltage levels above that point. This highest MLC state will then become the new erase state for the new distribution programmed on it.

[0136] In some embodiments, reads and writes are performed on pages. In other embodiments, reads and writes can be performed on portions of pages. A portion of a page is a subset of a page. In one instance, a page contains 16 kilobytes of data, and a portion of a page contains 4 kilobytes of data bits. To perform a read operation on a portion of a page, the sampling range becomes processing only the portion of the page that needs to be read. The read search algorithm discussed above forms the basis of the programming operation, but in order to properly prevent other memory cells from being programmed, mathematics needs to be applied to the corresponding sense amplifier circuit (otherwise, the algorithm would be similar).

[0137] If the system tracks the memory page hierarchy, there's no need to search the current state set. The memory die can receive commands with a set of parameters / features to determine where the data is currently located and where the system wants to read or program it. In the case of programming, the parameters are provided. This eliminates the need for searching. Additionally, this provides the added benefit of being able to program any data to any level of read data without knowing the underlying architecture.

[0138] In one instance, data might be stored on a solid-state drive for an extended period, so programming it to a higher threshold voltage (which would take longer) might be worthwhile. For this, it would be ideal to leave more space between the programming and erasing states. Consider an instance where data can be stored in eight states, such as... Figure 3C As depicted. The memory controller can distinguish which data states the state machine should use for data erasure and which data states should use for data programming. For example, the memory controller can instruct the state machine to use state B for data "1" and state F for data "0". In this case, the memory controller 102 can instruct the state machine 3621 to program using the verification level VrF and perform a read using VrD. Other instances of states to be used for data 1 and data 0 may also be used.

[0139] After programming a memory cell to a common new erase state, writing new data may not be recommended. The system may use features to determine this at the expense of performance. One example is that data is erased as requested, but it requires more pulses than it should, or if too many bits are not successfully programmed. This could be due to a programming verification failure. In another instance, the system may be rapidly checking the verification / read levels at locations above and below the threshold voltage distribution of the common new erase state. Unless 100% (or close to 100%) of the memory cells are within these two levels, it is best to be aware that this is an issue in the state transfer from the memory die back to the memory controller. This will involve verification above the distribution and verification below the distribution, and applying an OR'ing solution to the results to obtain the state. For debugging purposes, it is best to verify the results simultaneously in different bits and registers.

[0140] In some embodiments, the memory cell should be in a data state that is relatively close to the threshold voltage of the adjacent memory cell. For example, see Figure 3D Ideally, the memory cell should not be in state S1, while its adjacent memory cells should be in states S14 and S15.

[0141] Tables 1, 2, and 3 (see above) provide examples of encoding schemes for mapping data to states. Other encoding schemes may also be used. In some embodiments, the encoding scheme may be changed when rewriting existing data with new data using the various processes discussed above.

[0142] A nonvolatile memory system that provides incremental data writing is disclosed. That is, existing data can be rewritten with new data without performing a conventional erase operation that reverts the threshold voltage of the nonvolatile memory cell to its initial erase state. In one example, a shifted threshold voltage distribution is used to write new data onto old data.

[0143] One embodiment includes a set of non-volatile memory cells and control circuitry connected to the non-volatile memory cells. The control circuit is configured to: place the set of non-volatile memory cells in an initial erase state; write first data as SLC data into the set of non-volatile memory cells, such that at least one subset of the non-volatile memory cells exits the initial erase state, and each corresponding non-volatile memory cell in the set of non-volatile memory cells is assigned a corresponding state in a first state set based on a first corresponding data value to be stored in the corresponding non-volatile memory cell; and write second data as Multi-Level Cell (“MLC”) data into the set of non-volatile memory cells by rewriting the first data in the set of non-volatile memory cells without restoring any subset of the non-volatile memory cells back to the initial erase state, such that each corresponding non-volatile memory cell in the set of non-volatile memory cells is assigned a corresponding state in a second state set based on a second corresponding data value to be stored in the corresponding non-volatile memory cell, the second state set containing more states than the first state set, wherein rewriting the first data includes clearing the first data and replacing it with the second data.

[0144] In one example implementation, each state in the first state set is associated with a corresponding threshold voltage range, the first state set comprising a lowest state associated with the lowest threshold voltage range of the first state set and a highest state associated with the highest threshold voltage range of the first state set; and each state in the second state set is associated with a corresponding threshold voltage range such that all threshold voltages in the second state set are higher in voltage magnitude than the threshold voltage of the lowest state, and at least one subset of the threshold voltages in the second state set are higher in voltage magnitude than all threshold voltages in the first state set.

[0145] In one example implementation, the control circuitry is configured to rewrite the first data in the non-volatile memory cell set by increasing the threshold voltage of at least one subset of the non-volatile memory cell set without decreasing the threshold voltage of any non-volatile memory cell in the non-volatile memory cell set.

[0146] In one example implementation, the control circuitry is configured to write the first data as SLC data into the non-volatile memory cell set by storing one data bit in any one of two states in the first state set; and the control circuitry is configured to rewrite the first data by storing two or more data bits in any one of four or more states in the second state set.

[0147] In one example implementation, each state in the first state set is associated with a corresponding threshold voltage range, the first state set containing a highest state associated with the highest threshold voltage range of the first state set; each state in the second state set is associated with a corresponding threshold voltage range; the first state set contains at least one state not included in the second state set; and the control circuitry is configured to rewrite the first data by: increasing the threshold voltage of at least one subset of the non-volatile memory cell set such that all non-volatile memory cells in the non-volatile memory cell set are in a common new erase state, the common new erase state being associated with a threshold voltage range that is equal to or higher than the threshold voltage of the highest data state in terms of voltage magnitude; and after all non-volatile memory cells in the non-volatile memory cell set are in the common new erase state, increasing the threshold voltage of at least some of the non-volatile memory cells in the non-volatile memory cell set from the common new erase state to one or more states in the second state set having a higher threshold voltage than the common new erase state.

[0148] In one example implementation, the control circuitry is configured to detect whether the set of non-volatile memory cells is in the common new erase state.

[0149] In one example implementation, the control circuitry is configured to rewrite the first data by: sensing the first data from the set of non-volatile memory cells; inverting the sensed data; setting a verification target to the voltage amplitude of the highest state in the first state set; performing an SLC programming process on the inverted sensed data and the verification target; and performing an MLC programming process on the second data.

[0150] In one example implementation, the set of non-volatile memory cells is configured to store data in multiple state sets including the first state set and the second state set. Additionally, the control circuitry is configured to: perform one or more sensing operations on the set of non-volatile memory cells to automatically detect a current state set among the multiple state sets used by the non-volatile memory cells to store current data; and determine a new state set among the multiple state sets based on the automatic detection of the current state set by performing the one or more sensing operations, the new state set containing at least one state not included in the current state set, and to use the new state set for subsequent rewriting.

[0151] In one example implementation, the non-volatile memory cell set is configured to store data in multiple state sets including the first state set and the second state set. Additionally, the control circuitry is configured to: determine whether the non-volatile memory cell set is currently storing data in the highest supported state, and if the non-volatile memory cell set is currently storing data in the highest supported state, cause an erase operation to be performed on the non-volatile memory cell set.

[0152] In one example implementation, the non-volatile memory cell set is configured to store data in multiple state sets comprising the first state set and the second state set, the multiple state sets comprising multiple read levels. The control circuitry is configured to perform a binary search on the multiple read levels, including a sensing operation at one or more of the multiple read levels to identify a current read level, wherein for the current read level, at least a predetermined number of non-volatile memory cells have a threshold voltage higher than the identified current level and a predetermined number of non-volatile memory cells have a threshold voltage lower than the identified current level.

[0153] One embodiment includes a method comprising: writing first data to a set of nonvolatile memory cells such that each nonvolatile memory cell in the set is assigned a corresponding state in a first set of states, each state in the first set of states being associated with a corresponding threshold voltage range, the first set of states including a lowest state associated with a lowest threshold voltage range of the first set of states and a highest state associated with a highest threshold voltage range of the first set of states; and writing second data to the set of nonvolatile memory cells by rewriting the first data in the set of nonvolatile memory cells with second data such that each nonvolatile memory cell in the set of nonvolatile memory cells is assigned a corresponding state in a second set of states, each state in the second set of states being associated with a corresponding threshold voltage range. Rewriting the first data in the set of non-volatile memory cells with the second data includes: increasing the threshold voltage of at least one subset of the set of non-volatile memory cells such that all non-volatile memory cells in the set of non-volatile memory cells are in a common new erase state, the common new erase state being associated with a threshold voltage range that is equal to or higher than the threshold voltage of the highest data state in terms of voltage magnitude; and after all non-volatile memory cells in the set of non-volatile memory cells are in the common new erase state, increasing the threshold voltage of at least some of the non-volatile memory cells in the set of non-volatile memory cells from the common new erase state to one or more states in a second set of states having a higher threshold voltage than the common new erase state.

[0154] In one example implementation, writing the first data causes a first subset of the non-volatile memory cells to be in the lowest state, and a second subset of the non-volatile memory cells to be in the highest state.

[0155] In one example implementation, the method further includes placing the set of non-volatile memory cells in an initial erase state before writing the first data; and performing the rewriting of the first data in the set of non-volatile memory cells with the second data, without restoring any non-volatile memory cell in the set of non-volatile memory cells in the highest state back to the initial erase state.

[0156] In one example implementation, the method further includes automatically detecting whether all non-volatile memory cells in the set of non-volatile memory cells are in the common new erase state.

[0157] In one example implementation, rewriting the first data further includes: determining that the non-volatile memory cell set stores data in the first state set; determining that an additional state set can be used to store data in the non-volatile memory cell set, the additional state set being the second state set; sensing the first data from the non-volatile memory cell set; inverting the sensed first data; setting a verification target to the voltage amplitude in the highest state; performing an SLC programming process on the inverted sensed data using the verification target; updating the verification target to the voltage of the state in the second state set; and performing an SLC programming process on the second data using the updated verification target.

[0158] One embodiment includes an apparatus comprising: a plurality of non-volatile memory cells configured to store data in a plurality of state sets; and control circuitry connected to the non-volatile memory cells. The control circuitry is configured to: receive new data to rewrite existing data already stored in the non-volatile memory cells; perform one or more sensing operations on the non-volatile memory cells to automatically detect a current state set in the plurality of state sets used by the non-volatile memory cells to store the existing data; determine a new state set in the plurality of state sets based on the execution of the one or more sensing operations to automatically detect the current state set, the new state set including at least one state not included in the current state set; and rewrite the existing data in the non-volatile memory cells with the new data such that each non-volatile memory cell is assigned a corresponding state in the new state set.

[0159] In one example implementation, each state in the first state set is associated with a corresponding threshold voltage range, the first state set comprising a lowest state associated with the lowest threshold voltage range of the first state set and a highest state associated with the highest threshold voltage range of the first state set; each state in the second state set is associated with a corresponding threshold voltage range; the control circuitry is further configured to increase the threshold voltage of at least one subset of the non-volatile memory cell set such that all non-volatile memory cells in the non-volatile memory cell set are in a common new erase state, the common new erase state being associated with a threshold voltage range that is equal to or higher than the threshold voltage of the highest data state in terms of voltage magnitude; the control circuitry is further configured to, after all non-volatile memory cells in the non-volatile memory cell set are in the common new erase state, rewrite the existing data with the new data by increasing the threshold voltage of at least some of the non-volatile memory cells in the non-volatile memory cell set from the common new erase state to one or more states in the new state set having a higher threshold voltage than the common new erase state.

[0160] In one example implementation, the control circuitry is configured to: place the plurality of non-volatile memory cells in an initial erase state; write existing data into the plurality of non-volatile memory cells by moving some of the plurality of non-volatile memory cells from the initial erase state to a programming state in the current state set; and rewrite the existing data in the non-volatile memory cells with the new data by moving a subset of the non-volatile memory cells to a programming state in the new state set while maintaining a subset of the non-volatile memory cells in the initial erase state.

[0161] In one implementation, the existing data and the new data are SLC data. Furthermore, the control circuitry is further configured to rewrite the existing data with the new data by: setting a first verification level to a threshold voltage of a first state in the new state set; setting a second verification level to a threshold voltage of a second state in the new state set, the second state corresponding to a higher threshold voltage than the first state; and performing an MLC programming operation to write the new data as SLC data into the non-volatile memory cell using the first verification level and the second verification level.

[0162] In one example implementation, the plurality of state sets are associated with a plurality of read levels. Additionally, the control circuitry is configured to perform one or more sensing operations on the non-volatile memory cell to automatically detect the current state set by: (a) selecting one of the plurality of read levels that has not yet been eliminated; (b) Sensing data from the non-volatile memory cells using a selected read level; (c) If a first predetermined number of non-volatile memory cells have a threshold voltage greater than the selected read level, eliminating read levels below the selected read level among the plurality of read levels; (d) If a second predetermined number of non-volatile memory cells have a threshold voltage less than the selected read level, eliminating read levels above the selected read level among the plurality of read levels; (e) If the amount of non-volatile memory cells having a threshold voltage greater than the selected read level is less than the first predetermined number and the amount of non-volatile memory cells having a threshold voltage less than the selected read level is less than the second predetermined number, determining that the current state set is a state set among the plurality of state sets having the highest state corresponding to the selected read level; (f) If the amount of non-volatile memory cells having a threshold voltage greater than the selected read level is greater than the first predetermined number or the amount of non-volatile memory cells having a threshold voltage less than the selected read level is greater than the second predetermined number, repeating (a)-(e).

[0163] For the purposes of this document, references to “embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” in the specification may be used to describe different or the same embodiments.

[0164] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intermediate element. When an element is referred to as being directly connected to another element, there is no intermediate element between the element and the other element. If two devices are directly or indirectly connected such that the two devices can transmit electronic signals between them, then the two devices are "communicating".

[0165] For the purposes of this document, the term “based on” may be understood as “at least partially based on”.

[0166] For the purposes of this document, the use of numerical terms such as “first” object, “second” object, and “third” object, without additional context, may not imply an order of objects, but may be used for identification purposes to distinguish different objects.

[0167] For the purposes of this document, the term "set" of objects may refer to a "set" of one or more objects within an object.

[0168] The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the foregoing teachings. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize the technology in various embodiments and various modifications suitable for the intended particular use. The intended scope is defined by the appended claims.

Claims

1. A non-volatile storage device, comprising: Non-volatile memory cell set; as well as A control circuit, connected to the non-volatile memory cell, is configured to: The non-volatile memory cell set is placed in an initial erase state; The first data is written as single-level cell (SLC) data to the set of non-volatile memory cells, such that at least a subset of the non-volatile memory cells exit the initial erase state, and each corresponding non-volatile memory cell in the set of non-volatile memory cells is assigned a corresponding state in the first state set based on the first corresponding data value to be stored in the corresponding non-volatile memory cell. as well as By rewriting the first data in the set of nonvolatile memory cells without restoring any nonvolatile memory cells in a subset of the nonvolatile memory cells to the initial erase state, the second data is written as multilevel unit (MLC) data into the set of nonvolatile memory cells, such that each corresponding nonvolatile memory cell in the set of nonvolatile memory cells is assigned a corresponding state in a second state set based on the second corresponding data value to be stored in the corresponding nonvolatile memory cell, the second state set containing more states than the first state set, and the rewriting of the first data includes clearing the first data and replacing it with the second data.

2. The non-volatile storage device according to claim 1, wherein: Each state in the first state set is associated with a corresponding threshold voltage range, and the first state set includes a lowest state associated with the lowest threshold voltage range of the first state set and a highest state associated with the highest threshold voltage range of the first state set. and Each state in the second state set is associated with a corresponding threshold voltage range such that all threshold voltages in the second state set are higher in voltage magnitude than the threshold voltage of the lowest state, and at least one subset of the threshold voltages in the second state set are higher in voltage magnitude than all threshold voltages in the first state set.

3. The non-volatile storage device according to claim 1, wherein: The control circuit is configured to rewrite the first data in the non-volatile memory cell set by increasing the threshold voltage of at least a subset of the non-volatile memory cell set without decreasing the threshold voltage of any non-volatile memory cell in the non-volatile memory cell set.

4. The non-volatile storage device according to claim 1, wherein: The control circuit is configured to write the first data as SLC data into the non-volatile memory cell set by causing the non-volatile memory cell set to store a data bit in either of the two states in the first state set; and The control circuit is configured to rewrite the first data by causing the set of non-volatile memory cells to store two or more data bits in any of four or more states in the second state set.

5. The non-volatile storage device according to claim 1, wherein: Each state in the first state set is associated with a corresponding threshold voltage range, and the first state set includes the highest state associated with the highest threshold voltage range of the first state set; Each state in the second state set is associated with a corresponding threshold voltage range; The first state set includes at least one state that is not included in the second state set; and The control circuit is configured to rewrite the first data by the following operation: Increase the threshold voltage of at least one subset of the non-volatile memory cell set such that all non-volatile memory cells in the set are in a common new erase state, the common new erase state being associated with a range of threshold voltages that are equal to or higher than the threshold voltage of the highest data state in terms of voltage amplitude. After all non-volatile memory cells in the set of non-volatile memory cells are in the common new erase state, the threshold voltage of at least some of the non-volatile memory cells in the set of non-volatile memory cells is raised from the common new erase state to one or more states in the second set of states that have a higher threshold voltage than the common new erase state.

6. The non-volatile storage device according to claim 5, wherein: The control circuit is configured to detect whether the set of non-volatile memory cells is in the common new erase state.

7. The non-volatile storage device of claim 1, wherein the control circuitry is configured to rewrite the first data by: Sensing the first data from the set of non-volatile memory cells; Reverse the sensed data; The verification target is set to the voltage amplitude of the highest state in the first state set; Perform an SLC programming process on the inverted sensed data and the verification target; as well as Perform an MLC programming process on the second data.

8. The non-volatile storage device according to claim 1, wherein: The non-volatile memory cell set is configured to store data in multiple state sets, including the first state set and the second state set; and The control circuit is configured to: Perform one or more sensing operations on the set of non-volatile memory cells to automatically detect the current state set of the plurality of state sets used by the non-volatile memory cells to store current data, and Based on the execution of one or more sensing operations to automatically detect the current state set, a new state set is determined from the plurality of state sets. The new state set contains at least one state not included in the current state set, and the new state set will be used to perform subsequent rewriting.

9. The non-volatile storage device according to claim 1, wherein: The non-volatile memory cell set is configured to store data in multiple state sets, including the first state set and the second state set; and The control circuit is configured to: Determine whether the non-volatile memory cell set is currently storing data in the highest supported state, and If the set of non-volatile memory cells is currently storing data in the highest supported state, then an erase operation is performed on the set of non-volatile memory cells.

10. The non-volatile storage device according to claim 1, wherein: The non-volatile memory cell set is configured to store data in a plurality of state sets including the first state set and the second state set, the plurality of state sets including a plurality of read levels; and The control circuit is configured to perform a binary search on the plurality of read levels, including a sensing operation at one or more of the plurality of read levels to identify the current read level, wherein for the current read level, at least a predetermined number of non-volatile memory cells have a threshold voltage higher than the identified current level and a predetermined number of non-volatile memory cells have a threshold voltage lower than the identified current level.

11. A method for incremental writing of non-volatile memory cells, comprising: First data is written to a set of non-volatile memory cells such that each non-volatile memory cell in the set of non-volatile memory cells is assigned a corresponding state in a first state set, each state in the first state set being associated with a corresponding threshold voltage range, the first state set containing a lowest state associated with the lowest threshold voltage range of the first state set and a highest state associated with the highest threshold voltage range of the first state set. as well as By rewriting the first data in the set of non-volatile memory cells with the second data, the second data is written into the set of non-volatile memory cells, such that each non-volatile memory cell in the set of non-volatile memory cells is assigned a corresponding state in a second state set, each state in the second state set being associated with a corresponding threshold voltage range. Rewriting the first data in the set of non-volatile memory cells with the second data includes: Increase the threshold voltage of at least one subset of the non-volatile memory cell set such that all non-volatile memory cells in the set are in a common new erase state, the common new erase state being associated with a threshold voltage range that is equal to or higher than the threshold voltage of the highest data state in terms of voltage amplitude. After all non-volatile memory cells in the set of non-volatile memory cells are in the common new erase state, the threshold voltage of at least some of the non-volatile memory cells in the set of non-volatile memory cells is raised from the common new erase state to one or more states in the second set of states that have a higher threshold voltage than the common new erase state.

12. The method according to claim 11, wherein: The writing of the first data causes a first subset of the non-volatile memory cells to be in the lowest state, and a second subset of the non-volatile memory cells to be in the highest state.

13. The method of claim 11, further comprising: This ensures that the set of non-volatile memory cells is in an initial erase state before the first data is written. as well as The process involves rewriting the first data in the set of non-volatile memory cells with the second data, without restoring any non-volatile memory cell in the set of non-volatile memory cells that is in the highest state back to the initial erase state.

14. The method of claim 11, further comprising: Automatically detect whether all non-volatile memory cells in the non-volatile memory cell set are in the common new erase state.

15. The method of claim 11, wherein rewriting the first data further comprises: Determine that the set of non-volatile memory cells stores data in the first state set; An additional state set is determined to be available for storing data in the set of non-volatile memory cells, and the additional state set is the second state set; Sensing the first data from the set of non-volatile memory cells; Reverse the sensed first data; Set the verification target to the voltage amplitude at the highest state; The verification target is used to perform an SLC programming process on the inverted sensed data; Update the verification target to the voltage of the state in the second state set; as well as Perform the SLC programming process on the second data using the updated verification target.

16. A non-volatile storage device, comprising: Multiple non-volatile memory cells configured to store data in multiple state sets; as well as A control circuit, connected to the non-volatile memory cell, is configured to: Receive new data to rewrite the existing data already stored in the non-volatile memory cell; Perform one or more sensing operations on the non-volatile memory cell to automatically detect the current state set of the plurality of state sets used by the non-volatile memory cell to store the existing data; Based on the execution of one or more sensing operations to automatically detect the current state set, a new state set is determined from the plurality of state sets, the new state set containing at least one state not included in the current state set; as well as The existing data in the non-volatile memory cell is rewritten with the new data, such that each non-volatile memory cell is assigned a corresponding state from the new state set.

17. The non-volatile storage device according to claim 16, wherein: Each state in the current state set is associated with a corresponding threshold voltage range, and the current state set includes the lowest state associated with the lowest threshold voltage range of the current state set and the highest state associated with the highest threshold voltage range of the current state set. Each state in the new state set is associated with a corresponding threshold voltage range; The control circuit is further configured to increase the threshold voltage of at least one subset of the non-volatile memory cell set, such that all non-volatile memory cells in the non-volatile memory cell set are in a common new erase state, the common new erase state being associated with a threshold voltage range that is equal to or higher than the threshold voltage of the highest data state in terms of voltage amplitude. and The control circuit is further configured to, after all non-volatile memory cells in the non-volatile memory cell set are in the common new erase state, rewrite the existing data with the new data by raising the threshold voltage of at least some of the non-volatile memory cells in the non-volatile memory cell set from the common new erase state to one or more states in the new state set having a higher threshold voltage than the common new erase state.

18. The non-volatile storage device of claim 16, wherein the control circuitry is configured to: This puts the plurality of non-volatile memory cells into an initial erase state; The existing data is written to the plurality of non-volatile memory cells by moving some of the plurality of non-volatile memory cells from the initial erase state to the programming state in the current state set; and The existing data in the non-volatile memory cells is rewritten with the new data by moving a subset of the non-volatile memory cells to a programming state in the new state set while maintaining a subset of the non-volatile memory cells in the initial erase state.

19. The non-volatile storage device according to claim 16, wherein: The existing data and the new data are SLC data; The control circuit is further configured to rewrite the existing data with the new data by the following operations: Set the first verification level to the threshold voltage of the first state in the new state set; The second verification level is set to the threshold voltage of the second state in the new state, which corresponds to a higher threshold voltage than the first state; as well as Perform an MLC programming operation to write the new data as SLC data into the non-volatile memory cell using the first verification level and the second verification level.

20. The non-volatile storage device according to claim 16, wherein: The multiple state sets are associated with multiple read levels; and The control circuit is configured to perform one or more sensing operations on the non-volatile memory cell to automatically detect the current state set by: (a) Select one of the plurality of read levels that has not yet been eliminated; (b) Sensing data from the non-volatile memory cell using the selected read level; (c) If a first predetermined number of non-volatile memory cells have a threshold voltage greater than the selected read level, then eliminate the read levels that are lower than the selected read level among the plurality of read levels; (d) If the second predetermined number of non-volatile memory cells have a threshold voltage lower than the selected read level, then eliminate the read level higher than the selected read level among the plurality of read levels; (e) If the amount of non-volatile memory cells having a threshold voltage greater than the selected read level is less than the first predetermined amount and the amount of non-volatile memory cells having a threshold voltage less than the selected read level is less than the second predetermined amount, then the current state set is determined to be a state set in the plurality of state sets having the highest state corresponding to the selected read level. (f) If the amount of the non-volatile memory cell having a threshold voltage greater than the selected read level is greater than the first predetermined amount, or the amount of the non-volatile memory cell having a threshold voltage less than the selected read level is greater than the second predetermined amount, then repeat (a)-(e).

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