Memory device and operating method thereof, memory system

Abstract

Embodiments of the present disclosure provide a memory device and an operating method thereof, a memory system, the memory device comprising: a memory cell array and a peripheral circuit coupled with the memory cell array; the memory cell array comprises a plurality of memory strings; the peripheral circuit is configured to program a plurality of memory cells coupled to a first word line from an initial state to one of a plurality of target states simultaneously; bias unselected memory cell corresponding bit lines to a program inhibit level, and selected memory cell corresponding bit lines to a low power supply level; raise the first word line from the low power supply level to a first voltage level; during the first word line level raising, raise the voltage on the selected memory cell corresponding bit lines from the low power supply level to a second or third voltage level, the third voltage level being greater than an off level of a corresponding selection transistor, and the second voltage level being between the low power supply level and the third voltage level; and apply a program pulse to the first word line.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular, to a memory device and an operating method thereof, and a memory system. BACKGROUND

[0002] A memory device is a memory apparatus used for saving information in modern information technology. As a typical non-volatile semiconductor memory, a NAND (Not-And) flash memory has become a mainstream product in the memory market due to its high storage density, controllable production cost, suitable programming and erasing speed, and data retention characteristics.

[0003] However, as the requirements for memory devices continue to increase, there are still many problems in the execution of programming operations of memory devices. SUMMARY

[0004] Embodiments of the present disclosure provide a memory device and an operating method thereof, and a memory system.

[0005] In one aspect, the present disclosure provides a memory device, comprising: a memory cell array and a peripheral circuit coupled to the memory cell array; wherein,

[0006] The memory cell array comprises a plurality of memory strings, each memory string comprising a plurality of memory cells, each memory cell in the plurality of memory cells being coupled to a respective word line, each memory string being coupled to a respective bit line through a respective select transistor;

[0007] The peripheral circuit is configured to simultaneously program a plurality of memory cells coupled to a first word line from an initial state to a respective one of a plurality of target states;

[0008] biasing bit lines corresponding to unselected memory cells along the first word line to a program inhibit level, and biasing bit lines corresponding to selected memory cells along the first word line to a low power supply level;

[0009] increasing a voltage of the first word line from a low power supply level to a first voltage level; wherein, in the process of increasing the voltage of the first word line from the low power supply level to the first voltage level, the bit line biasing circuit is further configured to increase a voltage on the bit lines corresponding to the selected memory cells from the low power supply level to a second voltage level or a third voltage level according to a program verification result of the selected memory cells, a starting time of the second voltage level and the third voltage level being related to a target state of the selected memory cells, the third voltage level being greater than an off level of the respective select transistor, and the second voltage level being between the low power supply level and the third voltage level; and

[0010] Apply a programming pulse to the first word line.

[0011] In the above scheme, the second voltage level is half of the programming disable level.

[0012] In the above scheme, the third voltage level is less than or equal to the programming disable level.

[0013] In the above scheme, the peripheral circuit is configured to raise the voltage on the first word line from the low power supply level to the first voltage level using a ladder waveform, wherein the ladder waveform has multiple steps between the low power supply level and the first voltage level; and

[0014] The peripheral circuit is configured to apply a pulse corresponding to the second voltage level to the bit line corresponding to the selected memory cell when the target state of the selected memory cell begins to enter a steady state at one step.

[0015] In the above scheme, the peripheral circuit is configured to apply a pulse corresponding to the third voltage level to the bit line corresponding to the selected memory cell from the target state of the selected memory cell to the end of the steady state, and stabilize at the third voltage level when the steady state ends.

[0016] In the above scheme, the programming pulse is one of a series of programming pulses, and the programming also includes programming verification before biasing the bit line, and the unselected memory cells along the first word line include memory cells that have been verified to be programmed to the corresponding target state.

[0017] In the above scheme, the number of steps is the same as the number of target states.

[0018] In the above scheme, during the process of increasing the voltage of the first word line from the low power supply level to the first voltage level, the peripheral circuit is further configured to increase the voltage on word lines other than the first word line from the low power supply level to the first voltage level using the ladder waveform, wherein the ladder waveform has multiple steps between the low power supply level and the first voltage level; and

[0019] The peripheral circuitry is also configured to subsequently apply a conduction voltage to word lines other than the first word line.

[0020] In the above scheme, the peripheral circuit is further configured to unload the programming pulse after the programming pulse has been applied to the first word line for a certain period of time;

[0021] After the programming pulse is unloaded, the peripheral circuit is also configured to unload the pulses corresponding to the second voltage level and the third voltage level.

[0022] In the above scheme, the memory device includes a three-dimensional NAND type memory.

[0023] In one aspect, embodiments of this disclosure provide a memory system, including:

[0024] One or more memory devices as described in the above embodiments of this disclosure; and

[0025] A memory controller, which is coupled to and controls the memory device.

[0026] On one hand, embodiments of this disclosure provide an operation method for a memory device, the memory device comprising: a memory cell array and peripheral circuitry coupled to the memory cell array; wherein,

[0027] The memory cell array includes multiple memory strings, each memory string includes multiple memory cells, each memory cell is coupled to a corresponding word line, and each memory string is coupled to a corresponding bit line through a corresponding selection transistor; the operation method includes:

[0028] Upon receiving a programming instruction, the programming instruction instructs to simultaneously program multiple memory cells coupled to the first word line from an initial state to a corresponding target state among multiple target states;

[0029] In response to the programming instruction, the bit line corresponding to the selected memory cell along the first word line is set to a low power level, and the bit line corresponding to the unselected memory cell along the first word line is set to a programming disable level.

[0030] The voltage of the first word line is increased from a low power supply level to a first voltage level; wherein, during the process of increasing the voltage of the first word line from the low power supply level to the first voltage level, according to the programming verification result of the selected memory cell, the voltage on the bit line corresponding to the selected memory cell is increased from the low power supply level to a second voltage level or a third voltage level, the start time of the second voltage level and the third voltage level are both related to the target state of the selected memory cell, the third voltage level is greater than the cutoff level of the corresponding selection transistor, and the second voltage level is between the low power supply level and the third voltage level;

[0031] Apply a programming pulse to the first word line.

[0032] In the above scheme, raising the voltage of the first word line from a low power supply level to a first voltage level includes:

[0033] The voltage on the first word line is increased from the low power supply level to the first voltage level using a ladder waveform, wherein the ladder waveform has multiple steps between the low power supply level and the first voltage level.

[0034] In the above scheme, increasing the voltage on the bit line corresponding to the selected memory cell from the low power supply level to a second voltage level or a third voltage level includes:

[0035] When the target state of the selected memory cell begins to enter a steady state at one step, a pulse corresponding to the second voltage level is applied to the bit line corresponding to the selected memory cell.

[0036] or,

[0037] During the period from the entry into a steady state to the end of the steady state in the target state of the selected memory cell, a pulse corresponding to the third voltage level is applied to the bit line corresponding to the selected memory cell, and the steady state is stabilized at the third voltage level at the end of the steady state.

[0038] In the above scheme, raising the voltage of the first word line from a low power supply level to a first voltage level includes:

[0039] During the process of increasing the first word line voltage from the low power supply level to the first voltage level, the voltage on word lines other than the first word line is increased from the low power supply level to the first voltage level using the ladder waveform, wherein the ladder waveform has multiple steps between the low power supply level and the first voltage level;

[0040] The method further includes:

[0041] Apply the turn-on voltage to all word lines except the first word line.

[0042] The method in the above scheme further includes:

[0043] The programming pulse is unloaded after being applied to the first word line for a certain period of time; and

[0044] After unloading the programming pulse, the pulses corresponding to the second voltage level and the third voltage level are unloaded.

[0045] This disclosure provides a memory device and its operation method, as well as a memory system. In various embodiments of this disclosure, during a full-sequence programming operation, when the peripheral circuit raises the first word line voltage from a low power supply level to a first voltage level, based on the programming verification result of the selected memory cell, the peripheral circuit raises the voltage on the bit line corresponding to the selected memory cell from a low power supply level to a second voltage level or a third voltage level. The third voltage level can turn off the selection transistor of the corresponding bit line, thereby causing the channel voltage of the corresponding memory string to rise almost entirely with the rise of the word line. The second voltage level, between the low power supply level and the third voltage level, can weakly turn off the selection transistor of the corresponding bit line, thereby causing the channel voltage of the corresponding memory string to rise partially with the rise of the word line. In other words, the second and third voltages can cause a difference in the rise level of the channel voltage, thus causing a difference in the effective programming voltage (the difference between the programming level and the channel voltage). In this way, memory cells at different programming levels can be programmed into a narrower threshold voltage distribution range based on the programming verification result, thereby reducing the probability of overlapping threshold voltage distributions of adjacent memory states and improving the accuracy of read operations. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0047] Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0048] Figure 2b This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0049] Figure 3a This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0050] Figure 3b This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present disclosure;

[0051] Figure 3c This is a schematic diagram of the voltage timing on each component at different stages of programming in another embodiment of this disclosure;

[0052] Figure 4 This is a schematic cross-sectional view of a memory array including NAND flash memory strings according to an embodiment of the present disclosure;

[0053] Figure 5 This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure;

[0054] Figure 6This is a schematic diagram of full-sequence programming in one embodiment of the present disclosure;

[0055] Figure 7 This is a schematic diagram of the word line voltage applied to the memory cell during programming operations using a step-pulse programming method according to an embodiment of the present disclosure;

[0056] Figure 8a This is a schematic diagram showing the correspondence between the threshold voltage distribution in different states and the initial reference voltage and the verification voltage in one embodiment of this disclosure;

[0057] Figure 8b This is a schematic diagram illustrating the relationship between the initial reference voltage, the verification voltage, and the bit line voltage in one embodiment of this disclosure;

[0058] Figure 9 This is a schematic diagram showing the correspondence between channel voltage and different target states in one embodiment of the present disclosure;

[0059] Figure 10 This is a table showing the number of programming loops for the target state when combined with channel boost in one embodiment of the present disclosure;

[0060] Figure 11 This is a schematic diagram illustrating the implementation flow of an operation method for a memory device according to an embodiment of the present disclosure.

[0061] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0062] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0063] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0064] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0065] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0066] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0067] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0068] In the following description, "selected" and "selected" have the same meaning; "not selected," "not chosen," "not selected," and "not selected" have the same meaning. "Voltage" and "potential" have the same meaning.

[0069] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0070] The memory devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0071] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0072] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0073] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0074] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2a In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108. In such a way... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0075] Figure 3a An exemplary schematic diagram of the distribution of storage cells in a three-dimensional NAND flash memory is provided, such as... Figure 3a As shown, the memory array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered rows of memory cells parallel to the gate isolation structure. Each two rows of memory cells are separated by a gate isolation structure and an up-select gate isolation structure. Each row of memory cells includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory array into multiple blocks. Multiple second gate isolation structures can divide the blocks into multiple finger regions. An up-select gate isolation structure located in the middle of each finger region can divide the finger region into two parts, thus dividing the finger region into two strings. Figure 3a The memory block shown contains 6 memory chips; however, in practical applications, the number of memory chips in a memory block is not limited to this. A memory cell in a memory block coupled to a word line can be called a memory page.

[0076] It should be noted that, Figure 3a The number of cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0077] Figure 3b A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND-type memory array, memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0078] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0079] like Figure 3b As shown, each NAND memory string 308 may include a lower select gate (BSG) 310 at its source end and an upper select gate (TSG) 312 at its drain end. BSG 310 and TSG 312 may be configured to activate the selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0080] like Figure 3bAs shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of memory cell 306, where page 320 is the basic data unit used for programming operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, as well as gate lines coupling the control gates. (This is in conjunction with the preceding...) Figure 3a A page 320 contains multiple memory cells 306, which are separated by an up-select gate isolation structure and a gate isolation structure. The memory cells between the up-select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each of which is parallel to the gate isolation structure and the up-select gate isolation structure. The memory cells in the memory chip that share the same word line form a programmable (read / write) page.

[0081] Figure 4 A schematic cross-sectional view of an exemplary memory array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 can determine the number of memory cells included in the memory array 401.

[0082] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select transistor gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select transistor gate line, and the gate layer 411 extending laterally between the upper and lower select transistor gate lines may serve as a word line layer.

[0083] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0084] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high K) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0085] Return to reference Figure 3bThe peripheral circuitry 302 can be coupled to the memory array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0086] Page buffer / sensor amplifier 504 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0087] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of memory array 301 and select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0088] In some specific embodiments, the programming operation is full-sequence programming (including but not limited to multi-state programming (MSP) / multi-phase programming). Taking QLC as an example, in a full-sequence programming operation, the storage unit can be directly programmed from the erase data state S0 to any one of the programmed data states S1-S15.

[0089] Here, the full-sequence programming can include multiple loops, each loop including multiple stages. For example, each loop can include a bit line voltage setting stage, a channel boost stage, a programming pulse stage, a recovery stage, and a programming verification stage. In the bit line voltage setting stage, the bit line corresponding to an unselected memory cell can be set to a programming disable level, such as VDD, and the bit line corresponding to a selected memory cell can be set to a low power supply level, such as ground (GND). In the channel boost stage, the channel voltage can be boosted through the coordinated application of bit line and word line voltages. In the programming pulse stage, a programming voltage can be applied to the selected word line, and a pass voltage can be applied to the unselected word line. In the recovery stage, the voltage can be reduced to a low power supply level for both the unselected and selected word lines. In the programming verification stage, a verification voltage Vvf can be applied to the selected word line, and a pass voltage Vpass can be applied to the unselected word line to determine whether the corresponding memory cell has been programmed to the desired state.

[0090] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0091] This disclosure provides another memory device, the memory device comprising: a memory cell array and peripheral circuitry coupled to the memory cell array; wherein,

[0092] The memory cell array includes multiple memory strings, each memory string includes multiple memory cells, each memory cell is coupled to a corresponding word line, and each memory string is coupled to a corresponding bit line through a corresponding selection transistor.

[0093] The peripheral circuitry is configured to simultaneously program multiple memory cells coupled to the first word line from an initial state to a corresponding target state among multiple target states.

[0094] The bit line corresponding to the unselected memory cell along the first word line is biased to the programming disable level, and the bit line corresponding to the selected memory cell along the first word line is biased to the low power supply level.

[0095] The voltage of the first word line is increased from a low power supply level to a first voltage level; wherein, when the peripheral circuit increases the voltage of the first word line from the low power supply level to the first voltage level, the peripheral circuit is further configured to increase the voltage on the bit line corresponding to the selected memory cell from the low power supply level to a second voltage level or a third voltage level based on the verification result of the selected memory cell, wherein the start time of the second voltage level and the third voltage level are both related to the target state of the selected memory cell, the second voltage level is greater than the cutoff level of the corresponding selection transistor, and the third voltage level is between the low power supply level and the third voltage level; and

[0096] Apply a programming pulse to the first word line.

[0097] Here, referring to the aforementioned Figure 3a, Figure 3b , Figure 3c Each memory cell 306 in the multiple memory cells is coupled to the corresponding word line 318, and each memory string 308 is coupled to the corresponding bit line 316 through the corresponding selection transistor (such as the above selection transistor (TSG) 312).

[0098] Specifically, the memory device may include a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array and peripheral circuitry have been described previously and will not be repeated here.

[0099] refer to Figure 3c The storage cell array may include one or more storage strings (reference). Figure 3c As shown by the middle arrow, each memory string may include an upper selection transistor SST corresponding to the upper selection transistor gate line SSL, a ground selection transistor GST corresponding to the lower selection transistor gate line GSL, and multiple memory cells located between the upper selection transistor and the ground selection transistor. Each memory string is connected to the corresponding bit line BL and a unified common source line.

[0100] Here, for reference Figure 3c The first word line is the selected word line (Sel.WL), which can be any word line among multiple word lines in the memory device. The other word lines are unselected word lines (Usel.WL) or dummy word lines (Dummy WL). The bit lines BL in the memory device are divided into two parts. One part of the bit lines is connected to the memory cell in the lowest state (i.e., erase state) corresponding to the selected word line, and is denoted as the first bit line (BL_min). The other part of the bit lines is connected to the memory cells in the memory cells corresponding to the selected word line, except for those in the lowest state (i.e. erase state) and those that have reached the target state, and is denoted as the second bit line (BL_other). In actual operation, a target memory cell among multiple memory cells can be selected by selecting the corresponding word line and bit line to perform the corresponding read and program operations.

[0101] It should be noted that the programming operation in this embodiment is full-sequence programming. Here and below, QLC is used as an example. Figure 6 This illustrates an example threshold voltage distribution for a memory cell array when each memory cell stores four bits of data (i.e., QLC). Figure 6 The arrows in the diagram indicate full-sequence programming. (See reference) Figure 6Storage cells can be directly programmed from an erase state S0 to any of the programming data states S1-S15. For example, a group of storage cells to be programmed, such as a block, can be erased first, so that all storage cells in the group are in the erase data state S0. Then, the programming process is used to directly program the storage cells to data states S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, or S15. For example, while some storage cells are being programmed from data state S0 to data state S1, other storage cells are being programmed from data state S0 to data state S2 and / or from data state S0 to data state S3, etc.

[0102] Here, the control logic can be referred to in the foregoing. Figure 5 Let's understand the control logic 512. Taking QLC as an example, the initial state of the memory cell is data erase state S0, and the target states are programming data states S1-S15. After receiving a programming operation (write) instruction, the control logic responds to the instruction and executes it. During the programming operation, according to the instruction, multiple memory cells coupled to the selected word line are simultaneously programmed from their initial data states to a corresponding target state among multiple target states. That is, refer to... Figure 6 The storage unit is directly programmed from the erased data state S0 to one of the programmed data states S1-S15.

[0103] It should be noted that during the programming operation, a verification operation is required after each programming pulse to determine whether the selected memory cell has been programmed to the desired state. When the read result in the verification operation is consistent with the write data in the programming operation, it indicates that the programming has reached the desired state. Subsequently, the corresponding bit line coupled to the memory cell that has been programmed to the desired state is pulled to the specified programming disabled state.

[0104] Here, the selected memory cell along the first word line can be understood as a memory cell among the memory cells coupled to the first word line that has not reached the target state. Specifically, when the programming operation includes multiple loops, at the beginning of the loop, the selected memory cell along the first word line can be understood as a memory cell among the memory cells coupled to the first word line whose written state is non-erasable; during the loop, the selected memory cell along the first word line can be understood as a memory cell among the memory cells coupled to the first word line that is not erased and whose written state has reached the target state.

[0105] Here, the unselected memory cells along the first word line can be understood as memory cells in the memory cells coupled to the low-voltage word line that have reached the target state. Specifically, when the programming operation includes multiple loops, at the beginning of the loop, the unselected memory cells along the first word line can be understood as memory cells in the memory cells coupled to the first word line whose state is erased; during the loop, the unselected memory cells along the first word line can be understood as memory cells in the memory cells coupled to the first word line whose state is erased and whose state has reached the target state.

[0106] Here, the peripheral circuitry sets the bit line corresponding to the selected memory cell along the first word line (i.e., the first bit line, BL_min) to a low power supply level. In some specific examples, this low voltage level can be ground, and it can also be referred to as the low inhibit voltage VBL_inhibit_Low. Simultaneously, the peripheral circuitry sets the bit line corresponding to the unselected memory cell along the first word line (i.e., the second bit line, BL_other) to a programming inhibit level (VBL_inhibit) to turn off the selection transistor connected to the corresponding bit line. Here, the programming inhibit voltage level is greater than the low power supply level, i.e., VBL_inhibit > VBL_inhibit_Low. For example, the programming inhibit level (VBL_inhibit) is VDD.

[0107] refer to Figure 7 , Figure 7 The diagram shows the voltage application timing during programming operations for the selected word line (first word line), the unselected word line, the bit line corresponding to the selected memory cell (first bit line), and the bit line corresponding to the unselected memory cell (second bit line), where the horizontal axis represents time and the vertical axis represents the voltage values ​​applied to the selected word line, the unselected word line, the bit line corresponding to the selected memory cell, and the bit line corresponding to the unselected memory cell.

[0108] Here, the peripheral circuitry boosts the voltage of the first word line (Sel.WL) from a low supply level to a first voltage level; the first voltage level is a pass voltage Vpass. Subsequently, the peripheral circuitry applies a rising waveform to the selected first word line and one or more additional word lines, including word lines adjacent to the first word line. Here, the peripheral circuitry boosts the voltage on the first word line from the low supply level to the first voltage level (e.g., Vpass) using a ladder waveform, wherein the ladder waveform has multiple steps between the low supply level and the first voltage level.

[0109] In some embodiments, the number of steps is the same as the number of target states.

[0110] refer to Figure 7 When the target state is S1-S15, the corresponding number of steps is 15. Specifically, for target states S1-S15, the steps include vpass_s1, vpass_s2, vpass_s3, vpass_s4, ..., vpass_s14, vpass_s15. It should be noted that... Figure 7 The S0* shown can be the erase state.

[0111] Here, the programming also includes programming verification before biasing the bit line, and during the process of the peripheral circuitry raising the first word line voltage from the low power supply level to the first voltage level, the peripheral circuitry is also configured to raise the voltage on the bit line corresponding to the selected memory cell from the low power supply level to a second voltage level or a third voltage level based on the programming verification result of the selected memory cell.

[0112] Here, the third voltage level (VBL_inhibit) is greater than the cutoff level of the corresponding select transistor. The function of this third voltage level is to cut off the corresponding bit line, preparing for subsequent channel boost. It should be noted that when the bit line is cut off, the channel can follow the word line boost to a significant extent. In some embodiments, the third voltage level is less than or equal to the programming inhibit level. It is understood that when the third voltage level is less than the programming inhibit level, power consumption can be reduced.

[0113] Here, the second voltage level (VBL_inhibit_Mid) is between the low power supply level (VBL_inhibit_Low) and the third voltage level (VBL_inhibit). The function of the second voltage level is to weakly cut off the corresponding bit line, preparing for subsequent channel boosting. It should be noted that when the bit line is weakly cut off, the channel can follow the word line boosting to a certain extent. This "certain extent" is smaller than the aforementioned "larger extent".

[0114] In some embodiments, the second voltage level is half of the programming disable level.

[0115] Here, the programming verification result is the comparison between the programming voltage applied to the selected memory cell and the initial reference voltage and verification voltage of the target state of each selected memory cell during the programming operation. Specifically, when the programming voltage is greater than the initial reference voltage and less than the verification voltage, the voltage on the bit line corresponding to the selected memory cell is increased from the low power supply level to a second voltage level. When both the programming voltage and the verification voltage are greater than the initial reference voltage and the verification voltage, the voltage on the bit line corresponding to the selected memory cell is increased from the low power supply level to a third voltage level.

[0116] Here, the start time of both the second and third voltage levels is related to the target state of the selected memory cell.

[0117] For example, refer to Figure 8a , Figure 8b When the threshold voltage of a memory cell is less than the maximum value of the threshold voltage distribution of the Sn state, i.e., the initial reference voltage (Vvi), it indicates that the Vvi verification result is "Fail". At this time, the threshold voltage of the memory cell will also be less than the minimum value of the threshold voltage distribution of the Sn+1 state, i.e., the verification voltage (Vvf), and the corresponding Vvf verification result is "Fail". In this case, it indicates that the memory cell is far from the Sn+1 state and a larger adjustment of the threshold voltage is required. Based on this, the voltage on the bit line corresponding to the selected memory cell is set to a low power supply level (VBL_inhibit_Low).

[0118] When the threshold voltage of the memory cell is greater than the maximum value of the threshold voltage distribution of the Sn state, i.e., the initial reference voltage (Vvi), it indicates that the Vvi verification is passed ("Pass"). When the threshold voltage of the memory cell is less than the minimum value of the threshold voltage distribution of the Sn+1 state, i.e., the verification voltage (Vvf), it indicates that the Vvf verification result is failed ("Fail"). In this case, it indicates that the memory cell is relatively close to the Sn+1 state and requires a small adjustment of the threshold voltage. Based on this, the voltage on the bit line corresponding to the selected memory cell is increased from the low power supply level to the second voltage level (VBL_inhibit_Mid).

[0119] When the threshold voltage of the memory cell is greater than the maximum value of the threshold voltage distribution in the Sn state, i.e., the initial reference voltage (Vvi), it indicates that the Vvi verification has passed. Similarly, when the threshold voltage of the memory cell is greater than the minimum value of the threshold voltage distribution in the Sn+1 state, i.e., the verification voltage (Vvf), it indicates that the Vvf verification has passed. In this case, it means that the memory cell is in the Sn+1 state, and no adjustment of the threshold voltage is required. Based on this, the voltage on the bit line corresponding to the selected memory cell is increased from the low power supply level to the third voltage level (VBL_inhibit).

[0120] It should be noted that, Figure 8a , Figure 8b The Vrd shown is the read voltage of the memory cell corresponding to the selected word line.

[0121] In some embodiments, during the process of increasing the first word line voltage from the low power supply level to the first voltage level, the peripheral circuitry is further configured to increase the voltage on word lines other than the first word line from the low power supply level to the first voltage level using the ladder waveform, wherein the ladder waveform has multiple steps between the low power supply level and the first voltage level; and

[0122] The peripheral circuitry is also configured to subsequently apply a turn-on voltage to word lines other than the first word line.

[0123] For example, refer to Figure 7 The number of steps for the memory cell corresponding to the unselected word line is also 15. Specifically, the steps include vpass_s1, vpass_s2, vpass_s3, vpass_s4, ... vpass_s14, vpass_s15, and an on-state voltage Vpass is applied to the unselected word line.

[0124] It should be noted that each step of the ladder waveform on the selected and unselected word lines can be slightly larger than the difference between the final channel voltage (i.e., the channel boost value) corresponding to each target state.

[0125] Therefore, in this embodiment of the present disclosure, during the execution of the full sequence programming operation, when the peripheral circuit raises the first word line voltage from a low power supply level to a first voltage level, according to the programming verification result of the selected memory cell, the peripheral circuit will also raise the voltage on the bit line corresponding to the selected memory cell from a low power supply level to a second voltage level or a third voltage level. The third voltage level can turn off the selection transistor of the corresponding bit line, so that the channel voltage of the corresponding memory string is basically raised as the word line is raised. The second voltage level is between the low power supply level and the third voltage level, and can weakly turn off the selection transistor of the corresponding bit line, so that the channel voltage of the corresponding memory string is partially raised as the word line is raised. That is to say, the second voltage and the third voltage can make the channel voltage rise level different, thereby making the effective programming voltage (the difference between the programming level and the channel voltage) different.

[0126] It should be noted that the multi-state programming (also known as multi-level programming) is achieved by identifying multiple different effective programming threshold voltage ranges. Each different threshold voltage range corresponds to a predetermined value for a group of data bits encoded in the memory device.

[0127] For example, during a programming operation, the programming voltage VPGM to be applied to the selected word line is applied as a series of pulses with increasing amplitude over time. The amplitude of the pulses increases with each consecutive pulse by a predetermined step size, applying the programming voltage VPGM to the corresponding memory cell. A verification operation is performed after each programming pulse. For multi-state programming, a verification step can be performed for each state of the selected memory cell to determine whether the corresponding memory cell has reached the corresponding target state.

[0128] Figure 9 The diagram illustrates the relationship between two channel voltages and the effective programming voltage Vpgm for different target states of the selected memory cell. Here, the effective programming voltage Vpgm is the difference between the actual programming voltage VPGM and the channel voltage (Vchannel, channel boost value).

[0129] Figure 9 The diagram shows the channel boost values ​​and their corresponding different target states, where S0* refers to cells belonging to the erase state and any locked cells from other target states. The bottom row shows the actual programming voltage value of 20V being applied to the selected word line, resulting in the effective programming voltage value. Figure 9As shown, the cell targeting the highest S15 target state can see the full actual programming voltage VPGM value, while the effective programming voltage Vpgm for other states decreases, resulting in relatively less programming per pulse. This allows cells being programmed to different target states to program at approximately the same rate, such that for the same effective programming voltage Vpgm pulse, each state has its corresponding threshold voltage (Vt), and as the programming cycle count increases, all states are programmed more or less simultaneously.

[0130] Furthermore, in multi-state programming operations, the channel associated with the memory cell is raised to a potential (Vch) that is a function of the cell's target programming state. Thus, lower states receive a higher channel voltage, while higher states receive a lower channel voltage. Since the same actual programming voltage VPGM pulse is applied to all cells on the word line, lower states actually experience a slower programming of their lower effective programming voltage Vpgm. Therefore, the rates at which multiple states are programmed simultaneously are approximately the same.

[0131] For example, such as Figure 9 As shown, by applying different inhibit voltages to the bit lines corresponding to the selected memory cells, such as the second voltage level (VBL_inhibit_Mid) and the third voltage level (VBL_inhibit), the threshold voltage distribution corresponding to each selected memory cell can be divided into two sub-threshold voltage distributions, and the effective programming voltage corresponding to each selected memory cell is also different. For example, if the actual programming voltage (VPGM) is 20V, the two effective programming voltages in the S1 state of the selected memory cell are: one effective programming voltage (Vpgm) is 14.2V, corresponding to a channel boost value of 5.8V; the other effective programming voltage (Vpgm) is 14.4V, corresponding to a channel boost value of 5.6V, and so on. In this way, memory cells at different programming levels can be programmed into a narrower threshold voltage distribution range by combining the programming verification results, thereby reducing the probability of overlapping threshold voltage distributions of adjacent memory states and improving the accuracy of read operations.

[0132] In some embodiments, the ladder waveform has multiple steps between the low power supply level and the first voltage level, and the peripheral circuitry begins to enter a steady state at one step of the target state of the selected memory cell (see reference). Figure 7 At time t1, the pulse corresponding to the second voltage level (VBL_inhibit_Mid) is applied to the bit line corresponding to the selected memory cell.

[0133] In some embodiments, the peripheral circuitry during a step from the entry into a steady state to the end of a steady state in the target state of the selected memory cell (refer to...) Figure 7At time t2, the pulse corresponding to the third voltage level (VBL_inhibit) is applied to the bit line corresponding to the selected memory cell, and the pulse is stabilized at the third voltage level (VBL_inhibit) at the end of the steady state.

[0134] For example, such as Figure 7 For the memory cell with target state S1, according to the voltage application timing curve of BLs:S1, when vpass_s1 reaches steady state (refer to...), Figure 7 At time t1, the pulse corresponding to the second voltage level (VBL_inhibit_Mid) is applied, and during the period from when vpass_s1 enters steady state to when it ends (refer to...). Figure 7 At time t2, the pulse corresponding to the third voltage level (VBL_inhibit) is applied. Compared to S2-S15, the channel voltage of state S1 starts to rise with the word line voltage increase first. Finally, the channel voltage (Vchannel) corresponding to state S1 is the highest among S1-S15. Similarly, for memory cells with target state S15, according to the voltage application timing curve of BLs:S15, the pulse corresponding to the second voltage level (VBL_inhibit_Mid) is applied when vpass_s15 reaches stability. During the period from vpass_s15 entering the steady state to the end of the steady state, the pulse corresponding to the third voltage level (VBL_inhibit) is applied. Compared to S1-S14, the channel voltage of state S15 rises last with the word line voltage increase. Finally, the channel voltage (Vchannel) corresponding to state S15 is the lowest among S1-S15.

[0135] Here, the target state of the selected memory cell is raised from the low power supply level at the level of the rising waveform, where the bit line is raised to a voltage sufficient to turn off the corresponding selection transistor.

[0136] The peripheral circuitry is used to apply the programming pulse VPGM to the first word line to perform the corresponding programming operation.

[0137] In some embodiments, the peripheral circuitry is further configured to unload the programming pulse after a programming pulse has been applied to the first word line for a period of time.

[0138] After the peripheral circuit unloads the programming pulse, the peripheral circuit is also configured to unload the pulses corresponding to the second voltage level and the third voltage level.

[0139] Here, the pulses corresponding to the second and third voltage levels need to be unloaded after the programming pulse is unloaded.

[0140] For example, such asFigure 7 The channel voltage increases according to the voltage on the corresponding word line and remains constant during the programming operation. Additionally, after the programming pulse is applied to the first word line, the second and third voltage levels applied to the corresponding bit lines remain continuous; after a certain period, the programming pulse applied to the first word line is unloaded; after the programming pulse applied to the first word line is completely unloaded, the second and third voltage levels applied to the corresponding bit lines are also unloaded.

[0141] In some embodiments, the programming pulse is one of a series of programming pulses, and the programming further includes programming verification prior to biasing the bit line, and the unselected memory cells along the first word line include memory cells that have been verified to be programmed to the corresponding target state.

[0142] For example, refer to Figure 6 , Figure 10 During the programming operation, each programming pulse is followed by a verification operation to determine whether the selected memory cell has been programmed to the desired state. In practice, when the read result in the verification operation matches the write data in the programming operation, it indicates that the programming operation is correct. At this time, the corresponding bit line is pulled to the specified programming disabled state.

[0143] Figure 6 Fifteen read reference voltages, Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, Vr7, Vr8, Vr9, Vr10, Vr11, Vr12, Vr13, Vr14, and Vr15, are also shown for reading data from memory cells. By testing whether the threshold voltage of a given memory cell is higher or lower than the fifteen read reference voltages, the system can determine the data state (i.e., S0, S1, S2, S3, ...) of the memory cell. Fifteen verification reference voltages, Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, Vv7, Vv8, Vv9, Vv10, Vv11, Vv12, Vv13, Vv14, and Vv15, are also shown. When memory cells are programmed to data states S1 (S2, S3, S4, ...), the system will test whether those memory cells have a threshold voltage greater than or equal to Vv1 (Vv2, Vv3, Vv4, ...).

[0144] Next, the appropriate target level is used to verify the appropriate memory cell to perform one or more verification operations. Here, the verification process is performed by testing whether the threshold voltage of the selected memory cell has reached the corresponding verification reference voltage (Vv1, Vv2, Vv3, ...). If the target state has been reached, the corresponding memory cell is programmed and no further programming operations can be performed.

[0145] It should be noted that, in this embodiment of the disclosure, a target state is plotted for the number of programming cycles. The shaded squares correspond to the state verified after the programming pulse of each cycle, wherein a "smart verification" arrangement is used to check only the programming state of units that may still be defect-free.

[0146] For example, such as Figure 10 As shown, all cells programmed to state S1 may be verified within twelve cycles, while state S15 may require up to 40 cycles. Based on a typical cell group and programming parameters, the corresponding operations are performed using 38 programming pulses and 150 verification operations (10 for each of the 15 states). To reduce the number of pulses and verifications, embodiments of this disclosure also provide a scheme for selectively increasing the channel voltage based on the target state of the memory cell.

[0147] In some embodiments, the memory device includes a three-dimensional NAND type memory.

[0148] In this embodiment of the disclosure, during the programming operation, when the peripheral circuit raises the first word line voltage from the low power supply level to the first voltage level, based on the verification result of the selected memory cell, the peripheral circuit raises the voltage on the bit line corresponding to the selected memory cell from the low power supply level to a second voltage level or a third voltage level, wherein the second voltage level and the third voltage level are different; in this way, the threshold voltage distribution corresponding to each selected memory cell can be divided into two sub-threshold voltage distributions, thereby reducing the threshold voltage distribution width of each memory state, reducing the probability that the threshold voltage distributions of adjacent memory states may overlap, and improving the accuracy of read operations.

[0149] This disclosure also provides a memory system, the memory system comprising:

[0150] One or more memory devices as described in the above embodiments of this disclosure; and

[0151] A memory controller, which is coupled to and controls the memory device.

[0152] For details regarding the specific structure and composition of the memory system, please refer to the preceding text. Figure 1 , Figure 2a , Figure 2b The relevant structure and composition of the memory system 102 are described below. For the sake of brevity, they will not be elaborated here.

[0153] In some embodiments, the memory system includes a memory card or a solid-state drive.

[0154] Based on the above-described memory device, this disclosure also provides an operation method for the memory device, the memory device comprising: a memory cell array and peripheral circuitry coupled to the memory cell array; wherein,

[0155] The memory cell array includes multiple memory strings, each memory string includes multiple memory cells, each memory cell is coupled to a corresponding word line, and each memory string is coupled to a corresponding bit line through a corresponding selection transistor; for example Figure 11 As shown, the operation method includes:

[0156] Step S1101: Receive a programming instruction, which instructs to simultaneously program multiple memory cells coupled to the first word line from an initial state to a corresponding target state among multiple target states;

[0157] Step S1102: In response to the programming instruction, set the bit line corresponding to the selected memory cell along the first word line to a low power level, and set the bit line corresponding to the unselected memory cell along the first word line to a programming disable level;

[0158] Step S1103: Increase the voltage of the first word line from a low power supply level to a first voltage level; wherein, during the process of increasing the voltage of the first word line from the low power supply level to the first voltage level, according to the programming verification result of the selected memory cell, increase the voltage on the bit line corresponding to the selected memory cell from the low power supply level to a second voltage level or a third voltage level, the start time of the second voltage level and the third voltage level are both related to the target state of the selected memory cell, the third voltage level is greater than the cutoff level of the corresponding selection transistor, and the second voltage level is between the low power supply level and the third voltage level;

[0159] Step S1104: Apply a programming pulse to the first word line.

[0160] It should be understood that Figure 11 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 11 The steps shown can be adjusted in order according to actual needs.

[0161] In some embodiments, raising the voltage of the first word line from a low power supply level to a first voltage level includes:

[0162] The voltage on the first word line is increased from the low power supply level to the first voltage level using a ladder waveform, wherein the ladder waveform has multiple steps between the low power supply level and the first voltage level.

[0163] In some embodiments, increasing the voltage on the bit line corresponding to the selected memory cell from the low power supply level to a second voltage level or a third voltage level includes:

[0164] When the target state of the selected memory cell begins to enter a steady state at one step, a pulse corresponding to the second voltage level is applied to the bit line corresponding to the selected memory cell.

[0165] or,

[0166] During the period from the entry into a steady state to the end of the steady state in the target state of the selected memory cell, a pulse corresponding to the third voltage level is applied to the bit line corresponding to the selected memory cell, and the steady state is stabilized at the third voltage level at the end of the steady state.

[0167] In some embodiments, raising the voltage of the first word line from a low power supply level to a first voltage level includes:

[0168] During the process of increasing the first word line voltage from the low power supply level to the first voltage level, the voltage on word lines other than the first word line is increased from the low power supply level to the first voltage level using the ladder waveform, wherein the ladder waveform has multiple steps between the low power supply level and the first voltage level;

[0169] The method further includes:

[0170] Apply the turn-on voltage to all word lines except the first word line.

[0171] In some embodiments, the method further includes:

[0172] The programming pulse is unloaded after being applied to the first word line for a certain period of time; and

[0173] After unloading the programming pulse, the pulses corresponding to the second voltage level and the third voltage level are unloaded.

[0174] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0175] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0176] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory device, comprising: The memory device includes: a memory cell array and a peripheral circuit coupled to the memory cell array; wherein The memory cell array includes a plurality of memory strings, each memory string including a plurality of memory cells, each memory cell of the plurality of memory cells coupled to a respective word line, each memory string coupled to a respective bit line through a respective select transistor; The peripheral circuit is configured to program a plurality of memory cells coupled to a first word line from an initial state to a respective one of a plurality of target states simultaneously; biasing bit lines corresponding to unselected memory cells along the first word line to a program inhibit level, and biasing bit lines corresponding to selected memory cells along the first word line to a low power supply level; applying a programming voltage corresponding to a programming pulse on the first word line to raise a voltage of the first word line from the low power supply level to a first voltage level; wherein, in the process of raising the first word line voltage from the low power supply level to the first voltage level, the peripheral circuit is further configured to: bias a voltage on the bit line corresponding to the selected memory cell to the low power supply level when the programming voltage is less than an initial reference voltage; raise the voltage on the bit line corresponding to the selected memory cell from the low power supply level to a second voltage level when the programming voltage is greater than the initial reference voltage and less than a verify voltage; raise the voltage on the bit line corresponding to the selected memory cell from the low power supply level to a third voltage level when the programming voltage is greater than the verify voltage; the second voltage level and the third voltage level each have a start time related to a target state of the selected memory cell, the third voltage level is greater than an off level of the respective select transistor, and the second voltage level is between the low power supply level and the third voltage level; the initial reference voltage is a maximum value of a threshold voltage distribution of an Snth target state of the plurality of target states corresponding to the selected memory cell; the verify voltage is a minimum value of a threshold voltage distribution of an Sn+1th target state of the plurality of target states corresponding to the selected memory cell; and n is an integer greater than 0.

2. The memory device of claim 1, wherein, The second voltage level is half of the program inhibit level.

3. The memory device of claim 1, wherein, The third voltage level is less than or equal to the program inhibit level.

4. The memory device of claim 1, wherein the peripheral circuit is configured to raise the voltage on the first word line from the low power supply level to the first voltage level in a staircase waveform, wherein the staircase waveform has a plurality of steps between the low power supply level and the first voltage level; and the peripheral circuit is configured to apply the second voltage level to the bit line corresponding to the selected memory cell when a step of the target state of the selected memory cell begins to enter a steady state. ​ 5. The memory device of claim 4, wherein, The peripheral circuit is configured to, during one step of the target state of the selected memory cell entering steady state to steady state end, start applying a pulse corresponding to the third voltage level to the bit line corresponding to the selected memory cell, and stabilize at the third voltage level at the steady state end.

6. The memory device of claim 4, wherein, The programming pulse is one of a series of programming pulses, and the programming further comprises a program verify before biasing the bit line, and the unselected memory cells along the first word line comprise memory cells that have been verified to be programmed to respective target states.

7. The memory device of claim 4, wherein, The number of steps is the same as the number of target states.

8. The memory device of claim 4, wherein, During the process of the first word line voltage increasing from the low power supply level to the first voltage level, the peripheral circuit is further configured to increase the voltage on word lines other than the first word line from the low power supply level to the first voltage level with the stepped waveform, wherein the stepped waveform has a plurality of steps between the low power supply level and the first voltage level; and The peripheral circuit is further configured to subsequently apply a pass voltage to the word lines other than the first word line.

9. The memory device of claim 1, wherein, The peripheral circuit is further configured to unload the programming pulse after a duration of the programming pulse being applied to the first word line; After unloading the programming pulse, the peripheral circuit is further configured to unload the pulses corresponding to the second voltage level and the third voltage level.

10. The memory device of claim 1, wherein, The memory device comprises a three-dimensional NAND type memory.

11. A memory system, characterized by comprising: Comprising: one or more memory devices as claimed in any of claims 1 to 10; and a memory controller coupled to the memory device and controlling the memory device.

12. A method of operating a memory device, comprising: The memory device comprises a memory cell array and a peripheral circuit coupled to the memory cell array; wherein, The memory cell array comprises a plurality of memory strings, each memory string comprising a plurality of memory cells, each memory cell of the plurality of memory cells being coupled to a respective word line, each memory string being coupled to a respective bit line through a respective select transistor; the method of operation comprising: receiving a program instruction, the program instruction indicating to program a plurality of memory cells coupled to a first word line from an initial state to a respective one of a plurality of target states simultaneously; in response to the program instruction, setting bit lines corresponding to selected memory cells along the first word line to a low power supply level, and setting bit lines corresponding to unselected memory cells along the first word line to a program inhibit level; applying a programming voltage corresponding to a programming pulse on the first word line to raise a voltage of the first word line from a low power supply level to a first voltage level; wherein during the raising of the first word line voltage from the low power supply level to the first voltage level, when the programming voltage is less than an initial reference voltage, biasing a voltage on a bit line corresponding to the selected memory cell to the low power supply level; when the programming voltage is greater than the initial reference voltage and less than a verify voltage, raising the voltage on the bit line corresponding to the selected memory cell from the low power supply level to a second voltage level; when the programming voltage is greater than the verify voltage, raising the voltage on the bit line corresponding to the selected memory cell from the low power supply level to a third voltage level; the second voltage level and the third voltage level each have a start time related to a target state of the selected memory cell, the third voltage level is greater than an off level of a corresponding select transistor, and the second voltage level is between the low power supply level and the third voltage level; the initial reference voltage is a maximum value of a threshold voltage distribution of an Snth target state of the selected memory cell; the verify voltage is a minimum value of a threshold voltage distribution of an Sn+1th target state of the selected memory cell; and n is an integer greater than 0.

13. The operating method of a memory device according to claim 12, wherein, The raising of the voltage of the first word line from the low power supply level to the first voltage level includes: raising the voltage on the first word line from the low power supply level to the first voltage level in a staircase waveform having a plurality of steps between the low power supply level and the first voltage level.

14. The operating method of a memory device according to claim 13, wherein, The raising of the voltage on the bit line corresponding to the selected memory cell from the low power supply level to the second voltage level or the third voltage level includes: applying a pulse corresponding to the second voltage level to the bit line corresponding to the selected memory cell when a step of the target state of the selected memory cell begins to enter a steady state; or, applying a pulse corresponding to the third voltage level to the bit line corresponding to the selected memory cell during a period from when a step of the target state of the selected memory cell enters the steady state to when the steady state ends, and stabilizing at the third voltage level at the end of the steady state.

15. The operating method of a memory device according to claim 13, wherein, The raising of the voltage of the first word line from the low power supply level to the first voltage level includes: raising the voltage on word lines other than the first word line from the low power supply level to the first voltage level in the staircase waveform having the plurality of steps between the low power supply level and the first voltage level during the raising of the first word line voltage from the low power supply level to the first voltage level; The method further includes: applying an on voltage to the word lines other than the first word line.

16. The operating method of a memory device according to claim 12, wherein, The method further includes: unloading the programming pulse after the programming pulse is applied to the first word line for a duration; and unloading the pulses corresponding to the second voltage level and the third voltage level after the programming pulse is unloaded.

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