Impedance calibration and related methods, apparatus and systems

Abstract

This invention relates to impedance calibration and related methods, apparatus, and systems. A semiconductor device may include an input / output (I / O) interface region. The semiconductor device may also include a plurality of ZQ calibration circuits, each of which is positioned adjacent to an associated portion of the I / O interface region. The semiconductor device may also include a plurality of interpolation circuits, each of which is positioned adjacent to an associated portion of the I / O interface region and configured to generate calibration codes based on a plurality of other calibration codes. Further, the portion of the I / O interface region associated with the plurality of interpolation circuits is at least partially located between the portions of the I / O interface region associated with the plurality of ZQ calibration circuits.

Description

[0001] Divisional application information

[0002] This application is a divisional application of the invention patent application filed on April 6, 2021, with application number 202110366812.8 and entitled "Impedance calibration and related methods, apparatus and systems".

[0003] Priority requirements

[0004] This application claims the benefit of U.S. Patent Application Serial No. 16 / 848,093, filed April 14, 2020, for the subject of “Impedance Calibration, and Associated Methods, Devices, and Systems”. Technical Field

[0005] The embodiments of this disclosure generally relate to impedance calibration of semiconductor devices. More specifically, the various embodiments relate to performing ZQ calibration and to related methods, apparatus, and systems. Background Technology

[0006] Semiconductor memory devices are typically housed in computers or other electronic systems as internal semiconductor integrated circuits. There are many different types of memory, including, for example, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive random access memory (RRAM), dual data rate memory (DDR), low-power dual data rate memory (LPDDR), phase-change memory (PCM), and flash memory.

[0007] Semiconductor memory devices typically comprise a number of memory cells capable of holding charges representing data bits. These memory cells are usually arranged in a memory array. Data can be written to or retrieved from a memory cell by selectively activating the memory cell via an associated word line driver. Summary of the Invention

[0008] Various embodiments of this disclosure may include a semiconductor device. The semiconductor device may include an input / output (I / O) interface region. The semiconductor device may also include a plurality of ZQ calibration circuits, each of which is positioned adjacent to an associated portion of the I / O interface region. The device may also include a plurality of interpolation circuits, each of which is positioned adjacent to an associated portion of the I / O interface region and configured to generate calibration codes based on a plurality of other calibration codes. Further, each of the plurality of interpolation circuits may be coupled to one or more of the other interpolation circuits, one or more of the ZQ calibration circuits, or any combination thereof. Furthermore, the portion of the I / O interface region associated with the plurality of interpolation circuits is at least partially located between the portions of the I / O interface region associated with the plurality of ZQ calibration circuits.

[0009] In another embodiment, an apparatus may include an input / output (I / O) interface region. The apparatus may further include a first ZQ calibration circuit configured to generate a first calibration code for a first portion of the I / O interface region. The apparatus may also include a second ZQ calibration circuit configured to generate a second calibration code for a second portion of the I / O interface region.

[0010] According to another embodiment of this disclosure, a method may include determining a first calibration code for a first portion of an input / output (I / O) interface region of a semiconductor device via a first ZQ calibration circuit. The method may further include determining a second calibration code for a second portion of the I / O interface region of the semiconductor device via a second ZQ calibration circuit associated with a second portion of the I / O interface region. Further, the method may include determining a third calibration code for a third portion of the I / O interface region of the semiconductor device based on the first calibration code and the second calibration code, wherein the third portion is at least partially located between the first portion and the second portion.

[0011] According to another embodiment of this disclosure, a method may include determining a first calibration code for a first portion of an input / output (I / O) interface region of a semiconductor device via a first ZQ calibration circuit. Further, the method may include determining a second calibration code for a second portion of the I / O interface region of the semiconductor device via a second ZQ calibration circuit. The method may also include adjusting the first portion of the I / O interface region based on the first calibration code. Furthermore, the method may include adjusting the second portion of the I / O interface region based on the second calibration code.

[0012] Further embodiments of this disclosure include an electronic system. The electronic system may include at least one input device, at least one output device, and at least one processor device operatively coupled to the input device and the output device. The electronic system may also include at least one memory device operatively coupled to the at least one processor device. The at least one memory device may include an input / output (I / O) interface comprising a plurality of regions. The at least one memory device may also include a first ZQ calibration circuit positioned adjacent to a first region of the plurality of regions of the I / O interface. The at least one memory device may also include a second ZQ calibration circuit positioned adjacent to a second region of the plurality of regions of the I / O interface. Additionally, the at least one memory device may include a first interpolation circuit coupled to each of the first and second ZQ calibration circuits and positioned adjacent to a third region of the plurality of regions of the I / O interface, wherein the third region is at least partially located between the second region and the first region. Attached Figure Description

[0013] Figure 1 This is a block diagram of an example semiconductor memory device according to at least one embodiment of the present disclosure.

[0014] Figure 2 A simplified diagram of the example ZQ calibration circuit is depicted.

[0015] Figure 3 This is a layout diagram of an example memory device.

[0016] Figure 4 This is a layout diagram of another example memory device containing a ZQ coverage area with a ZQ calibration unit.

[0017] Figure 5This is a layout diagram of another example memory device containing multiple ZQ calibration circuits.

[0018] Figure 6 This is a layout diagram of yet another example memory device containing multiple ZQ calibration circuits.

[0019] Figure 7 This is a layout diagram of an example memory device including multiple ZQ calibration circuits and multiple interpolation circuits according to various embodiments of the present disclosure.

[0020] Figure 8 This is a layout diagram of another example memory device including multiple ZQ calibration circuits and multiple interpolation circuits according to various embodiments of the present disclosure.

[0021] Figure 9 This is a flowchart of an example method of operating a semiconductor device according to various embodiments of the present disclosure.

[0022] Figure 10 This is a simplified block diagram of a memory system according to various embodiments of the present disclosure.

[0023] Figure 11 This is a simplified block diagram of an electronic system according to various embodiments of the present disclosure. Detailed Implementation

[0024] Semiconductor memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and so on. Information is stored by programming different states of the memory device. For example, a binary device has two states, typically represented by logic "1" or logic "0". In other systems, more than two states can be stored. To access the stored information, the electronic device can read or retrieve the information stored in the memory device. To store information, the electronic device can write or program states into the memory device.

[0025] Semiconductor memory devices can be volatile or non-volatile. Non-volatile memory devices (e.g., flash memory) can store data for extended periods of time, even without an external power source. Volatile memory devices (e.g., DRAM) may lose their stored state over time unless periodically refreshed by an external power source. Binary memory devices may, for example, include charging or discharging capacitors.

[0026] Semiconductor devices such as microcomputers, memories, and gate arrays can include input / output (I / O) pins and output circuitry for transmitting data to other devices via buses, on-board transmission lines, etc. Semiconductor devices can include circuitry for controlling data transmission and can include, for example, output buffers and drivers. To ensure consistent and accurate data transmission, the impedance of the semiconductor device can be matched to the impedance of the transmission network and / or the receiving device.

[0027] Semiconductor devices such as low-power dynamic random-access memory (LPDRAM) devices (and other similar semiconductor devices) can use a ZQ calibration process to adjust certain components of the semiconductor device, such as input / output (I / O) drivers, on-die termination components, and / or other components, across process, voltage, and / or temperature (PVT) variations. Specifically, the ZQ calibration process can use periodic calibration (e.g., as commanded by the memory controller) to compare components to reference values ​​to maintain consistent impedance across process, voltage, and / or temperature (PVT). However, if, for example, the process variation effect in one region of the semiconductor device differs from the process variation effect in another region of the semiconductor device, the ZQ calibration process may lose accuracy.

[0028] As described more fully below, the various embodiments described herein may relate to performing ZQ calibration of a semiconductor device via a plurality of ZQ calibration circuits and at least one interpolation circuit. More specifically, as described more fully below, various embodiments of this disclosure include a semiconductor device that includes an input / output (I / O) interface region (e.g., including a plurality of I / O buffers). Further, the semiconductor device may include a plurality of ZQ calibration circuits, wherein each of the plurality of ZQ calibration circuits is positioned adjacent to an associated portion of the I / O interface region. The semiconductor may further include a plurality of interpolation circuits, wherein each of the plurality of interpolation circuits is positioned adjacent to an associated portion of the I / O interface region. According to some embodiments, at least some portions of the I / O interface region associated with the plurality of interpolation circuits are at least partially located between at least some portions of the I / O interface region associated with the plurality of ZQ calibration circuits. Each interpolation circuit can be configured to perform a calibration operation based on data (e.g., multiple (e.g., two) calibration codes) received from multiple (e.g., two) other circuits (e.g., one or more other interpolation circuits and / or one or more other ZQ calibration circuits).

[0029] According to some embodiments, during the intended operation of a semiconductor device, a first calibration code for a first portion of an input / output (I / O) interface region (e.g., comprising multiple I / O buffers) of the semiconductor device can be determined by a first ZQ calibration circuit associated with (e.g., positioned adjacent to) the first portion. Further, a second calibration code for a second portion of the I / O interface region can be determined by a second ZQ calibration circuit associated with (e.g., positioned adjacent to) the second portion. Additionally, a third calibration code for a third portion of the I / O interface region can be determined based on the first and second calibration codes, wherein the third portion is at least partially located between the first and second portions. The third calibration code can be determined by an interpolation circuit associated with (e.g., positioned adjacent to) the third portion.

[0030] Although various embodiments have been described herein with reference to memory devices, this disclosure is not limited thereto, but rather the embodiments can be generally applied to microelectronic devices that may or may not include semiconductor devices and / or memory devices. Embodiments of this disclosure will now be explained with reference to the accompanying drawings.

[0031] Figure 1 This is a schematic block diagram of a semiconductor memory device 100 according to various embodiments of the present disclosure. For example, the semiconductor memory device 100 may include an integrated circuit 102 and a ZQ resistor (RZQ) 104. The integrated circuit 102 may include a clock input circuit 106, an internal clock generator 108, a timing generator 110, an address / command input circuit 112, an address decoder 114, a command decoder 116, and multiple row decoders 118. The semiconductor memory device 100 further includes a memory cell array 120, which includes a sense amplifier 122 and a transmission gate 124. The semiconductor memory device 100 also includes multiple column decoders 126, multiple read / write amplifiers 128, input / output (I / O) circuitry 130, multiple ZQ calibration circuits 132, a voltage generator circuit 134, and multiple interpolation circuits 136. As described more fully below, each ZQ calibration circuit in ZQ calibration circuit 132 and each interpolation circuit in interpolation circuit 136 may be associated with a portion of input / output circuit 130 (e.g., multiple output drivers).

[0032] The semiconductor memory device 100 may include a plurality of external terminals, including address and command terminals coupled to the command / address bus 140, clock terminals CK and / or CK, data terminals DQ, DQS, and DM, power terminals VDD, VSS, VDDQ, and VSSQ, and calibration terminal ZQ. The integrated circuit 102 may be mounted on a substrate such as a memory module substrate, motherboard, etc.

[0033] The memory cell array 120 includes multiple memory banks, each containing multiple word lines WL, multiple bit lines BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL. The selection of the word lines WL for each memory bank is performed by a corresponding row decoder 118, and the selection of the bit lines BL is performed by a corresponding column decoder 126. The multiple sense amplifiers 122 are positioned for their corresponding bit lines BL and coupled to at least one corresponding local I / O line, which is further coupled to a corresponding main I / O line pair in at least two main I / O line pairs via a transmission gate TG 124 acting as a switch.

[0034] Address / command input circuit 112 can receive address signals and bank address signals from outside the semiconductor memory device 100 at the command / address terminal via command / address bus 140, and transmit the address signals and bank address signals to address decoder 114. Address decoder 114 can decode the address signals received from address / command input circuit 112 and provide row address signal XADD to row decoder 118 and column address signal YADD to column decoder 126. Address decoder 114 can also receive bank address signals and provide bank address signal BADD to row decoder 118 and column decoder 126.

[0035] Address / command input circuit 112 can receive command signals from an external source, such as a memory controller, at the command / address terminal via command / address bus 140 and provide the command signals to command decoder 116. Command decoder 116 can decode the command signals and provide or generate various internal command signals. For example, internal command signals may include row command signals for selecting word lines, column command signals such as read or write commands for selecting bit lines, and ZQ calibration commands that can activate one or more ZQ calibration circuits in ZQ calibration circuit 132 and / or one or more interpolation circuits in interpolation circuit 136.

[0036] Therefore, when a read command is issued and the row and column addresses are supplied in a timely manner using the read command, read data is read from the memory cells specified by the row and column addresses in the memory cell array 120. The read / write amplifier 128 can receive the read data and provide the read data to the input / output circuit 130. The input / output circuit 130 can provide the read data, along with the data strobe signal at DQS and the data mask signal at DM, to the outside of the semiconductor memory device 100 via the data terminals DQ, DQS, and DM. Similarly, when a write command is issued and the row and column addresses are supplied in a timely manner using the write command, the input / output circuit 130 can receive the write data, along with the data strobe signal at DQS and the data mask signal at DM, at the data terminals DQ, DQS, and DM, and provide the write data to the memory cell array 120 via the read / write amplifier 128. Therefore, write data can be written into the memory cells specified by the row and column addresses.

[0037] Turning to the explanation of the external terminals included in the semiconductor memory device 100, the clock terminals CK and / CK can receive an external clock signal and a complementary external clock signal, respectively. The external clock signal (including the complementary external clock signal) can be supplied to the clock input circuit 106. The clock input circuit 106 can receive the external clock signal and generate an internal clock signal ICLK. The clock input circuit 106 can provide the internal clock signal ICLK to an internal clock generator 108. The internal clock generator 108 can generate a phase-controlled internal clock signal LCLK based on the received internal clock signal ICLK and the clock enable signal CKE from the address / command input circuit 112. Although not limited to this, a DLL circuit can be used as the internal clock generator 108. The internal clock generator 108 can provide the phase-controlled internal clock signal LCLK to the input / output circuit 130 and the timing generator 110. The input / output circuit 130 can use the phase-controlled internal clock signal LCLK as a timing signal to determine the output timing for read data. The timing generator 110 can receive the internal clock signal ICLK and generate various internal clock signals.

[0038] The power supply terminals can receive power supply voltages VDD and VSS. These voltages can be supplied to voltage generator circuit 134. Voltage generator circuit 134 can generate various internal voltages VPP, VOD, VARY, VPERI, etc., based on the power supply voltages VDD and VSS. Internal voltage VPP can be used in line decoder 118, internal voltages VOD and VARY can be used in sense amplifier 122 included in memory cell array 120, and internal voltage VPERI can be used in many other circuit blocks. The power supply terminals can also receive power supply voltages VDDQ and VSSQ. Input / output circuit 130 can receive power supply voltages VDDQ and VSSQ. For example, power supply voltages VDDQ and VSSQ can be the same voltages as power supply voltages VDD and VSS, respectively. However, dedicated power supply voltages VDDQ and VSSQ can be used for input / output circuit 130 and ZQ calibration circuit 132. In some embodiments, ZQ calibration circuit 132 can receive power from voltage generator 134.

[0039] The calibration terminal ZQ of the semiconductor memory device 100 can be coupled to a ZQ calibration circuit 132. Each ZQ calibration circuit 132 can perform a calibration operation with reference to the impedance of a ZQ resistor (RZQ) 104. In some instances, the ZQ resistor (RZQ) 104 can be mounted on a substrate coupled to the calibration terminal ZQ. For example, the ZQ resistor (RZQ) 104 can be coupled to a power supply voltage (VDDQ). Further, according to various embodiments, each interpolation circuit 136 can be configured to perform a calibration operation based on data (e.g., multiple (e.g., two) calibration codes) received from multiple (e.g., two) other circuits (e.g., one or more other interpolation circuits and / or one or more other ZQ calibration circuits).

[0040] As will be understood, the impedance code (ZQCODE) obtained through the calibration operation can be provided to the input / output circuit 130, and thus the impedance of the output buffer (not shown) contained in the input / output circuit 130 can be specified. In some embodiments, the ZQ latch ( Figure 1 (Not shown) can store calibration codes and transfer the calibration codes to one or more I / O buffers in response to ZQ latch commands.

[0041] Figure 2A simplified diagram of an example ZQ calibration circuit 200 is depicted. The ZQ calibration circuit 200 includes pull-up drivers 202, pull-down drivers 204 and 206, comparators 210 and 212, and a pad PAD_ZQ coupled to a supply voltage VDDQ via a resistor RZQ. In some embodiments, pull-down drivers 204 and 206 may contain the same or similar circuitry. As those skilled in the art will appreciate, the ZQ calibration circuit 200 can generate one or more codes to adjust the impedance of associated I / O circuitry (e.g., I / O buffers). More specifically, the one or more codes generated by the ZQ calibration circuit 200 can enable or disable one or more transistors in the output circuitry (e.g., ...). Figure 1 (One or more output drivers of the input / output circuit 130). Further, according to the various embodiments described more fully below, one or more codes generated by the ZQ calibration circuit 200 can be passed to one or more interpolation circuits (e.g., Figure 1 Interpolation circuit 136).

[0042] Figure 3 This is a layout diagram of an example memory device 300. The memory device 300 includes a ZQ calibration unit 302 (e.g., including ZQ calibration circuitry) located near the center of a DQ PAD region 304 (i.e., containing a plurality of DQ circuits). Because the ZQ calibration unit 302 is near the center of the DQ PAD region 304, in some instances, the coverage area of ​​the ZQ calibration unit 302 may cover each DQ circuit of the DQ PAD region 304. For example, Figure 4 A layout diagram of the coverage area 400 including the memory device 300 and the ZQ calibration unit 302. The coverage area 400 may also be referred to herein as the "ZQ coverage area," "effective ZQ calibration code area," "ZQ code area," "effective area," or some other variation thereof. For example only, the diameter of the coverage area 400 may be approximately 3200 micrometers (µm). Therefore, as will be understood, there are territorial limitations on the ZQ coverage area. In other words, depending on the size of the memory device, the ZQ coverage area of ​​the ZQ calibration unit of the memory device may or may not cover each DQ pad of the memory device.

[0043] Figure 5This is another layout diagram of an example memory device 500 containing multiple ZQ calibration circuits. For example, memory device 500 may include a high-bandwidth memory (HBM) device. In this example, memory device 500 includes an input / output (I / O) interface (also referred to herein as the PHY region) 501 and two ZQ calibration circuits 502A and 502B located on opposite edges of the I / O interface 501. For example, the I / O interface 501 may be approximately 1200 μm long and approximately 6,000 μm wide. Memory device 500 further includes regions 504 and 506, which may contain one or more data buses (e.g., high-speed data buses) and / or high-speed circuitry. As will be understood, due to the density of the PHY region, the ZQ calibration circuitry may not be located within the PHY region.

[0044] Assuming each ZQ calibration circuit 502A and 502B has a coverage area of ​​approximately 3200 μm 508 (as mentioned above) Figure 4 As indicated, a portion of the I / O interface 501 may not be included within the coverage area 508. Therefore, if the process variation in the uncovered area (e.g., at or near the center of the I / O interface 501) differs from that in the covered area (e.g., at the edge of the I / O interface 501), the output impedance of the uncovered area may not be correctly calibrated.

[0045] Figure 6 This is a layout diagram of another example memory device 600 containing multiple ZQ calibration circuits 602 (i.e., ZQ calibration circuits 602A-602E). Like memory device 500, memory device 600 includes an input / output (I / O) interface (also referred to herein as the PHY region) 601. For example, the I / O interface 601 may be approximately 1200 μm long and approximately 6,000 μm wide. Memory device 600 further includes regions 604 and 606, which may contain one or more data buses (e.g., high-speed data buses) and / or high-speed circuitry. The ZQ calibration circuits 602A-602E together form a coverage area 608.

[0046] As will be understood, the ZQ calibration circuit 602 may consume a relatively large area and may increase design complexity. Furthermore, the location of the ZQ calibration circuit 602 may interrupt data bus lines (e.g., within regions 604 and / or 606), which are critical for relatively large I / O interfaces. Therefore, simply adding multiple ZQ calibration circuits to provide sufficient coverage may not be desirable.

[0047] Figure 7This is a layout diagram of an example memory device 700 including a plurality of ZQ calibration circuits 702 and a plurality of interpolation circuits 703 according to various embodiments of the present disclosure. According to various embodiments, each interpolation circuit 703 may be coupled to one or more other interpolation circuits 703. Further, in some embodiments, each interpolation circuit 703 may be coupled to one or more other ZQ calibration circuits 702.

[0048] The memory device 700 further includes an I / O interface (PHY) 701 (e.g., including multiple I / O buffers). For example, the memory device 700 may be a high-bandwidth memory (HBM) device (e.g., an HBM1 or HBM2 device). As described more fully below, the memory device 700 is configured to interpolate ZQ calibration codes to determine interpolation codes (e.g., to compensate for process variations that may gradually occur between two locations of the memory device 700).

[0049] exist Figure 7 In the embodiment shown, ZQ calibration circuits 702A and 702B are positioned near the relative edges of I / O interface 701. More specifically, ZQ calibration circuit 702A is positioned near edge 720 of I / O interface 701, and ZQ calibration circuit 702B is positioned near edge 722 of I / O interface 701. Further, each of interpolation circuits 703A, 703B, and 703C is positioned near edge 724 of I / O interface 701, which is adjacent to each of edges 720 and 722.

[0050] According to various embodiments of this disclosure, each ZQ calibration circuit and each interpolation circuit of the memory device 700 may be associated with an associated region (also referred to herein as a “part”) of the I / O interface 701 (e.g., covering the associated region and / or being positioned adjacent to the associated region). More specifically, each ZQ calibration circuit and each interpolation circuit may be associated with multiple I / O buffers of the I / O interface 701. For example, output buffers of the I / O interface 701 in the region near edges 720 and 722 may be covered by ZQ calibration circuits, and other output buffers of the I / O interface 701 (e.g., those removed from edges 720 and 722 and / or near the middle of the I / O interface 701) may be covered by interpolation circuits. More specifically, for example, region 708 of I / O interface 701 may be associated with ZQ calibration circuit 702A (e.g., covered by and / or located adjacent to ZQ calibration circuit), region 710 of I / O interface 701 may be associated with interpolation circuit 703A (e.g., covered by and / or located adjacent to interpolation circuit), region 712 of I / O interface 701 may be associated with interpolation circuit 703B (e.g., covered by and / or located adjacent to interpolation circuit), region 714 of I / O interface 701 may be associated with interpolation circuit 703C (e.g., covered by and / or located adjacent to interpolation circuit), and region 716 of I / O interface 701 may be associated with ZQ calibration circuit 702B (e.g., covered by and / or located adjacent to ZQ calibration circuit).

[0051] As will be understood, process variations in memory device 700 can vary (e.g., gradually) between locations of I / O interface 701 (e.g., between regions 708, 710, 712, 714, and 716). More specifically, for example, process variations in memory device 700 can vary between two locations of I / O interface 701 (e.g., between regions 708 and 716, between regions 708 and 712, between regions 708 and 710, etc.). Further, according to the various embodiments disclosed herein, the amount of variation can be determined by interpolation (e.g., estimation). More specifically, for example, the calibration code of one region of I / O interface 701 can be determined by two or more other known calibration codes for other regions of I / O interface 701.

[0052] As will be understood, ZQ calibration circuits 702A and 702B can be used to determine calibration codes for regions 708 and 716, respectively. Further, after determining the calibration codes for regions 708 and 716, a calibration code for another region can be determined based on the calibration codes for regions 708 and 716 (i.e., via associated interpolation circuitry). Furthermore, a calibration code for yet another region can be determined based on at least two known calibration codes for other regions (i.e., via associated interpolation circuitry). Further, as will be understood, a calibration code for a region can be applied to one or more output drivers of said region (e.g., to turn one or more transistors of said region on or off).

[0053] More specifically, for example, the calibration code for region 712 can be determined by interpolation circuit 703B based on the calibration code determined by ZQ calibration circuit 702A and the calibration code determined by ZQ calibration circuit 702B. As another example, the calibration code for region 714 can be determined by interpolation circuit 703C based on the calibration code determined by ZQ calibration circuit 702B and the calibration code determined by interpolation circuit 703B. Further, as yet another example, the calibration code for region 710 can be determined by interpolation circuit 703A based on the calibration code determined by ZQ calibration circuit 702A and the calibration code determined by interpolation circuit 703B.

[0054] As those skilled in the art will appreciate, an interpolation circuit can be configured to receive at least two inputs and generate an output based on said at least two inputs. For example, in an embodiment that includes an interpolation circuit associated with a region that is substantially halfway between regions 708 and 716, the interpolation circuit (e.g., interpolation circuit 703B) can determine the code for said region according to the following equation:

[0055] (Code generated by ZQ calibration circuit 702A + Code generated by ZQ calibration circuit 702B) / (N+1); (1)

[0056] Where N is the number of interpolation circuits (i.e., N = 1 in this example).

[0057] In a anticipated example, the calibration code for region 708 (i.e., determined by ZQ calibration circuit 702A) could be fifteen (15), and the calibration code for region 716 (i.e., determined by ZQ calibration circuit 702B) could be five (5). Further, based on the interpolation performed by equation (1), the calibration code for region 712 (i.e., determined by interpolation circuit 703B) could be ten (10).

[0058] As another example, assuming the region of interest is not located substantially halfway between the ZQ calibration regions, the multiplier used for each ZQ calibration circuit can be determined based on the location of the interpolation circuit. More specifically, for example, assuming the region of interest is region 710, the interpolation circuit 703A can determine the calibration code based on the following equation:

[0059] [(Code generated by ZQ calibration circuit 702A * P1) + (Code generated by ZQ calibration circuit 702B * P2)] / (N+1); (2)

[0060] Where P1 represents the positioning of the interpolation circuit 703A relative to the ZQ calibration circuit 702A (in Figure 7 In the example, P1 = 3), P2 represents the positioning of the interpolation circuit 703A relative to the ZQ calibration circuit 702B (in Figure 7 In the example, P2 = 1), and N is the number of interpolation circuits (i.e., N = 3 in this example).

[0061] Furthermore, for example, assuming the region of interest is region 714, the interpolation circuit 703C can determine the calibration code based on the following equation:

[0062] [(Code generated by ZQ calibration circuit 702A * P3) + (Code generated by ZQ calibration circuit 702B * P4)] / (N+1); (3)

[0063] Where P3 represents the positioning of the interpolation circuit 703C relative to the ZQ calibration circuit 702A (in Figure 7 In the example, P3 = 1), P4 represents the positioning of the interpolation circuit 703C relative to the ZQ calibration circuit 702B (in Figure 7 In the example, P4 = 3), and N is the number of interpolation circuits (i.e., N = 3 in this example).

[0064] Therefore, in this example, the calibration code of region 710 (i.e., determined by interpolation circuit 703A) can be 12.5 (12.5), and the calibration code of region 714 (i.e., determined by interpolation circuit 703C) can be 7.5 (7.5).

[0065] As another example, interpolation can be performed based on the results generated by the ZQ calibration circuit 702A and the results generated by the interpolation circuit 703B. More specifically, for example, assuming the region of interest is region 710, and assuming the same example code values ​​provided above, the interpolation circuit 703A can determine the calibration code based on the following equation:

[0066] (Code generated by ZQ calibration circuit 702A + code generated by interpolation circuit 703B) / 2 (4)

[0067] As yet another example, interpolation can be performed based on the results generated by the ZQ calibration circuit 702B and the results generated by the interpolation circuit 703B. More specifically, for example, assuming the region of interest is region 714, and assuming the same example code values ​​provided above, the interpolation circuit 703C can determine the calibration code based on the following equation:

[0068] (Code generated by interpolation circuit 703B + code generated by ZQ calibration circuit 702B) / 2 (5)

[0069] As will be understood, interpolation circuits may require less area and / or use fewer resources compared to ZQ calibration circuits. Therefore, utilizing one or more interpolation circuits (i.e., instead of one or more ZQ calibration circuits) can save area and / or resources. Furthermore, utilizing interpolation circuits (e.g., such as...) Figure 7 (As shown in the diagram) This can reduce the likelihood of interrupting signal lines (e.g., data buses) located near the I / O interface. Furthermore, according to some embodiments, the interpolation circuit may not require a reference resistor and layout sensitivity, and therefore, utilizing one or more interpolation circuits (i.e., instead of one or more ZQ calibration circuits) can simplify the design of the semiconductor device.

[0070] For example, the various embodiments can be applied to other larger devices (e.g., HBM3 devices), which may include I / O interface areas larger than those of HBM devices. Figure 8 This is a layout diagram of another example memory device 800 including a plurality of ZQ calibration circuits 802 and a plurality of interpolation circuits 803 according to various embodiments of the present disclosure. According to various embodiments, each interpolation circuit 803 may be coupled to one or more other interpolation circuits 803. Further, in some embodiments, each interpolation circuit 803 may be coupled to one or more other ZQ calibration circuits 802. The memory device 800 further includes an I / O interface (PHY) 801. For example, the memory device 800 may include an HBM3 device.

[0071] exist Figure 8In the embodiment shown, ZQ calibration circuits 802A and 802B are positioned near the relative edges of I / O interface 801. More specifically, ZQ calibration circuit 802A is positioned near edge 821 of I / O interface 801, and ZQ calibration circuit 802B is positioned near edge 823 of I / O interface 801. Further, ZQ calibration circuit 802C may be positioned near edge 824 of I / O interface 801, said edge being adjacent to each of edges 821 and 823. Additionally, each of interpolation circuits 803A, 803B, and 803C is positioned near edge 826 of I / O interface 801, said edge being adjacent to each of edges 821 and 823. Furthermore, each of interpolation circuits 803D and 803E is positioned near edge 824.

[0072] According to various embodiments of this disclosure, each ZQ calibration circuit and each interpolation circuit of the memory device 800 may be associated with an associated region (also referred to herein as a “part”) of the I / O interface 801 (e.g., covering the associated region and / or being positioned adjacent to the associated region). More specifically, for example, region 808 of I / O interface 801 may be associated with ZQ calibration circuit 802A (e.g., covered by and / or located adjacent to ZQ calibration circuit), region 810 of I / O interface 801 may be associated with interpolation circuit 803A (e.g., covered by and / or located adjacent to interpolation circuit), region 812 of I / O interface 801 may be associated with interpolation circuit 803D (e.g., covered by and / or located adjacent to interpolation circuit), and region 814 of I / O interface 801 may be associated with interpolation circuit 803B (e.g., covered by and / or located adjacent to interpolation circuit). Region 816 of I / O interface 801 may be associated with ZQ calibration circuit 802C (e.g., covered by and / or located adjacent to ZQ calibration circuit), region 818 of I / O interface 801 may be associated with interpolation circuit 803C (e.g., covered by and / or located adjacent to interpolation circuit), region 820 of I / O interface 801 may be associated with interpolation circuit 803E (e.g., covered by and / or located adjacent to interpolation circuit), and region 822 of I / O interface 801 may be associated with ZQ calibration circuit 802B (e.g., covered by and / or located adjacent to ZQ calibration circuit).

[0073] As will be understood, ZQ calibration circuits 802A and 802B can be used to determine calibration codes for regions 808 and 822, respectively. Further, after determining the calibration codes for regions 808 and 822, a calibration code for another region can be determined based on the calibration codes for regions 808 and 822 (i.e., through associated interpolation circuitry). Furthermore, a calibration code for yet another region can be determined based on at least two known calibration codes (i.e., through associated interpolation circuitry). Further, as will be understood, the calibration code for a region can be used to adjust the I / O circuitry associated with said region (e.g., turn one or more transistors of said region on or off).

[0074] More specifically, for example, the calibration code for region 814 can be determined by interpolation circuit 803B based on the calibration code determined by ZQ calibration circuit 802A and the calibration code determined by ZQ calibration circuit 802B. As another example, the calibration code for region 818 can be determined by interpolation circuit 803C based on the calibration code determined by ZQ calibration circuit 802B and the calibration code determined by interpolation circuit 803B. Further, as yet another example, the calibration code for region 820 can be determined by interpolation circuit 803E based on the calibration code determined by ZQ calibration circuit 802C and the calibration code determined by ZQ calibration circuit 802B. As yet another example, the calibration code for region 812 can be determined by interpolation circuit 803D based on the calibration code determined by ZQ calibration circuit 802A and the calibration code determined by ZQ calibration circuit 802C. As yet another example, the calibration code for region 810 can be determined by interpolation circuit 803A based on the calibration code determined by ZQ calibration circuit 802A and the calibration code determined by interpolation circuit 803B.

[0075] In a anticipated example, the calibration code for region 808 (i.e., determined by ZQ calibration circuit 802A) could be fifteen (15), and the calibration code for region 822 (i.e., determined by ZQ calibration circuit 802B) could be five (5). Further, based on interpolation, the calibration code for region 814 (i.e., determined by interpolation circuit 803B) could be ten (10), the calibration code for region 810 (i.e., determined by interpolation circuit 803A) could be twelve point five (12.5), and the calibration code for region 818 (i.e., determined by interpolation circuit 803C) could be seven point five (7.5).

[0076] Continuing with this example (i.e., where the calibration code for region 808 is 15 (15) and the calibration code for region 822 is 5 (5)), if the calibration code for region 816 (i.e., determined by the ZQ calibration circuit 802C) is 10 (10), then the calibration code for region 812 can be substantially equal to the calibration code for region 810, and the calibration code for region 820 can be substantially equal to the calibration code for region 818. However, if the calibration code for region 816 (i.e., determined by the ZQ calibration circuit 802C) is not 10 (10), then the calibration code for region 812 (i.e., determined by the interpolation circuit 803D based on the calibration codes for regions 808 and 816) can not be substantially equal to the calibration code for region 810, and / or the calibration code for region 820 (i.e., determined by the interpolation circuit 803E based on the calibration codes for regions 816 and 822) can not be substantially equal to the calibration code for region 818.

[0077] It should be noted that Figure 7 The memory device 700 includes two (2) ZQ calibration circuits and three (3) interpolation circuits, and Figure 8 The memory device 800 includes three (3) ZQ calibration circuits and five (5) interpolation circuits. However, this disclosure is not limited to any particular number of ZQ calibration circuits and / or interpolation circuits. For example, the number of ZQ calibration circuits and / or interpolation circuits can vary (e.g., based on accuracy requirements, size requirements, power requirements, and / or any other requirements). Furthermore, according to some embodiments, the number of ZQ calibration circuits and / or interpolation circuits included in the semiconductor device and / or the positioning of the circuits can be considered to improve device efficiency and / or reduce device size.

[0078] Figure 9 This is a flowchart of an example method 900 for operating a semiconductor device according to various embodiments of the present disclosure. Method 900 can be arranged according to at least one embodiment described in this disclosure. In some embodiments, at least a portion of method 900 can be generated by, for example... Figure 1 Semiconductor memory device 100 Figure 7 Memory device 700, Figure 8 Memory device 800, Figure 10 The memory system 1000 and / or Figure 11 The method 900 may be performed by an electronic system 1100 or other means or systems. For example, in some embodiments, all or part of the method 900 may be performed during a semiconductor initialization process. Although shown as discrete blocks, the individual blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0079] Method 900 may begin at block 902, where a first calibration code for a first portion of the input / output (I / O) interface region of the semiconductor device can be determined by a first ZQ calibration circuit associated with the first portion, and method 900 may continue to block 904. In one example, for region 708 (see...) Figure 7 The calibration code can be determined using the ZQ calibration circuit 702A. As another example, for region 808 (see...),... Figure 8 The calibration code can be determined using the ZQ calibration circuit 802A.

[0080] At block 904, the second calibration code for the second portion of the I / O interface area can be determined by the second ZQ calibration circuit associated with the second portion, and method 900 can continue to block 906. In one example, for region 716 (see...) Figure 7 The calibration code can be determined using the ZQ calibration circuit 702B. As another example, for region 822 (see...),... Figure 8 The calibration code can be determined using the ZQ calibration circuit 802B. In yet another example, for region 816 (see...) Figure 8 The calibration code can be determined using the ZQ calibration circuit 802C.

[0081] At box 906, the third calibration code for the third portion of the I / O interface area can be determined based on the first and second calibration codes, wherein the third portion is at least partially located between the first and second portions. In one example, for region 712 (see...) Figure 7 The calibration code can be determined by interpolation circuit 703B based on the first calibration code and the second calibration code. As another example, for region 814 (see...),... Figure 8 The calibration code can be determined by interpolation circuit 803B based on the first calibration code and the second calibration code. In yet another example, for region 820 (see...) Figure 8 The calibration code can be determined by interpolation circuit 803E based on the first calibration code and the second calibration code.

[0082] Modifications, additions, or omissions may be made to method 900 without departing from the scope of this disclosure. For example, the operations of method 900 may be performed in a different order. Furthermore, the operations and actions outlined are provided by way of example only, and some of these operations and actions may be optional, combined into fewer operations and actions, or extended into other operations and actions without departing from the spirit of the disclosed embodiments. For example, a method may include one or more actions in which additional calibration codes for a further portion of a semiconductor device may be determined based on a first calibration code and a third calibration code, wherein said further portion is at least partially located between the first and third portions. Further, for example, a method may include one or more actions in which circuitry associated with a portion of an I / O interface region is adjusted based on an associated calibration code.

[0083] A memory system is also disclosed. According to various embodiments, the memory system may include a controller and a plurality of memory devices. Each memory device may include one or more memory cell arrays, and the one or more memory cell arrays may include a plurality of memory cells.

[0084] Figure 10 This is a simplified block diagram of a memory system 1000 implemented according to one or more embodiments described herein. The memory system 1000, which may include, for example, semiconductor devices, includes multiple memory devices 1002 and a controller 1004. For example, at least one memory device 1002 may include multiple ZQ calibration circuits and multiple interpolation circuits as described herein. The controller 1004 may be operatively coupled to the memory devices 1002 to transmit command and / or address signals to the memory devices 1002.

[0085] An electronic system is also disclosed. According to various embodiments, the electronic system may include a memory device comprising a plurality of memory dies, each memory die having an array of memory cells. Each memory cell may include an access transistor and a memory element operatively coupled to the access transistor.

[0086] Figure 11This is a simplified block diagram of an electronic system 1100 implemented according to one or more embodiments described herein. The electronic system 1100 includes at least one input device 1102, which may include, for example, a keyboard, mouse, or touchscreen. The electronic system 1100 further includes at least one output device 1104, such as a monitor, touchscreen, or speaker. The input device 1102 and the output device 1104 need not be separable from each other. The electronic system 1100 further includes a storage device 1106. The input device 1102, output device 1104, and storage device 1106 may be coupled to a processor 1108. The electronic system 1100 further includes a memory system 1110 coupled to the processor 1108. The memory system 1110 may include… Figure 10 The memory system 1000. The electronic system 1100 may include, for example, computing, processing, industrial or consumer products. The electronic system 1100 may include, for example, but not limited to, personal computers or computer hardware components, servers or other networking hardware components, database engines, intrusion prevention systems, handheld devices, tablet computers, electronic notebooks, cameras, telephones, music players, wireless devices, displays, chipsets, games, vehicles or other known systems.

[0087] Various embodiments of this disclosure may include a semiconductor device. The semiconductor device may include an input / output (I / O) interface region. The semiconductor device may also include a plurality of ZQ calibration circuits, each of which is positioned adjacent to an associated portion of the I / O interface region. The device may also include a plurality of interpolation circuits, each of which is positioned adjacent to an associated portion of the I / O interface region and configured to generate calibration codes based on a plurality of other calibration codes. Further, each of the plurality of interpolation circuits may be coupled to one or more of the other interpolation circuits, one or more of the ZQ calibration circuits, or any combination thereof. Furthermore, the portion of the I / O interface region associated with the plurality of interpolation circuits is at least partially located between the portions of the I / O interface region associated with the plurality of ZQ calibration circuits.

[0088] In another embodiment, an apparatus may include an input / output (I / O) interface region. The apparatus may further include a first ZQ calibration circuit configured to generate a first calibration code for a first portion of the I / O interface region. The apparatus may also include a second ZQ calibration circuit configured to generate a second calibration code for a second portion of the I / O interface region.

[0089] According to another embodiment of this disclosure, a method may include determining a first calibration code for a first portion of an input / output (I / O) interface region of a semiconductor device via a first ZQ calibration circuit. The method may further include determining a second calibration code for a second portion of the I / O interface region of the semiconductor device via a second ZQ calibration circuit associated with a second portion of the I / O interface region. Further, the method may include determining a third calibration code for a third portion of the I / O interface region of the semiconductor device based on the first calibration code and the second calibration code, wherein the third portion is at least partially located between the first portion and the second portion.

[0090] According to another embodiment of this disclosure, a method may include determining a first calibration code for a first portion of an input / output (I / O) interface region of a semiconductor device via a first ZQ calibration circuit. Further, the method may include determining a second calibration code for a second portion of the I / O interface region of the semiconductor device via a second ZQ calibration circuit. The method may also include adjusting the first portion of the I / O interface region based on the first calibration code. Furthermore, the method may include adjusting the second portion of the I / O interface region based on the second calibration code.

[0091] Further embodiments of this disclosure include an electronic system. The electronic system may include at least one input device, at least one output device, and at least one processor device operatively coupled to the input device and the output device. The electronic system may also include at least one memory device operatively coupled to the at least one processor device. The at least one memory device may include an input / output (I / O) interface comprising a plurality of regions. The at least one memory device may also include a first ZQ calibration circuit positioned adjacent to a first region of the plurality of regions of the I / O interface. The at least one memory device may also include a second ZQ calibration circuit positioned adjacent to a second region of the plurality of regions of the I / O interface. Additionally, the at least one memory device may include a first interpolation circuit coupled to each of the first and second ZQ calibration circuits and positioned adjacent to a third region of the plurality of regions of the I / O interface, wherein the third region is at least partially located between the second region and the first region.

[0092] As is customary, the various features shown in the accompanying drawings may not be drawn to scale. The illustrations presented in this disclosure are not intended to be actual views of any particular device (e.g., apparatus, system, etc.) or method, but are merely idealized representations used to describe various embodiments of this disclosure. Therefore, the dimensions of various features may be arbitrarily increased or decreased for clarity. Additionally, some figures in the drawings may be simplified for clarity. Consequently, the drawings may not depict all components of a given device (e.g., apparatus) or all operations of a particular method.

[0093] As used herein, the terms "apparatus" or "memory device" may include, but are not limited to, devices having only memory. For example, an apparatus or memory device may include memory, a processor, and / or other components or functions. For example, an apparatus or memory device may include a system-on-a-chip (SoC).

[0094] As used herein, unless otherwise stated, the term “semiconductor” should be interpreted broadly to include microelectronic and MEMS devices (e.g., magnetic storage, optical devices, etc.) that may or may not employ semiconductor functionality to operate.

[0095] The terms used herein, and especially in the appended claims (e.g., the body of the appended claims), are generally intended to be “open-ended” terms (e.g., the term “including” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “having at least”, the term “includes” should be interpreted as “including but not limited to”, etc.).

[0096] Furthermore, if the intent is a specific number of introduced claim statements, such intent will be explicitly stated in the claims, and where no such statements are present, such intent does not exist. For example, to aid understanding, the appended claims below may contain the use of introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that introducing claim statements with the indefinite articles “a” or “an” limits any particular claim containing such introductory claim statements to an embodiment containing only one such statement, even when the same claim contains the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and / or “an” should be interpreted as meaning “at least one” or “one or more”); the same applies to the use of definite articles used to introduce claim statements. As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0097] Furthermore, even when a specific number of the introduced claim statements are explicitly stated, it should be understood that such statements should be interpreted as referring to at least the number stated (e.g., an unmodified statement of "two statements" without other modifiers means at least two statements or two or more statements). Moreover, in cases where conventions such as "at least one of A, B, and C" or "one or more of A, B, and C" are used, this construction is generally intended to include a single A, a single B, a single C, A and B together, A and C together, B and C together, or A, B, and C together, etc. For example, the use of the term "and / or" is intended to be interpreted in this manner.

[0098] Furthermore, any separating words or phrases presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to imply the possibility of including one, any, or both of the terms. For example, the phrase "A or B" should be understood to imply the possibility of including "A" or "B" or "A and B".

[0099] Furthermore, the use of terms such as "first," "second," and "third" in this document does not necessarily imply a specific order or quantity of elements. Generally, the terms "first," "second," and "third" are used to distinguish different elements as general identifiers. Unless otherwise stated, these terms should not be construed as implying a specific order. Furthermore, unless otherwise stated, these terms should not be construed as implying a specific quantity of elements.

[0100] The embodiments of this disclosure described above and illustrated in the accompanying drawings do not limit the scope of this disclosure, which is covered by the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this disclosure. In fact, in addition to the modifications shown and described herein, various modifications to this disclosure, such as alternative and useful combinations of the described elements, will become apparent to those skilled in the art based on the description. Such modifications and embodiments also fall within the scope of the appended claims and their equivalents.

Claims

1. An apparatus for impedance calibration, comprising: Multiple impedance calibration circuits, each of which is positioned as an associated portion of the I / O interface area; as well as An interpolation circuit is configured to generate a calibration code via interpolation of two or more other calibration codes, said two or more other calibration codes being generated via a plurality of circuits including one or more impedance calibration circuits, another interpolation circuit, or a combination thereof, said interpolation circuit being positioned adjacent to an associated portion of said I / O interface region; The portion of the I / O interface region associated with the interpolation circuit is at least partially located between a first portion of the I / O interface region associated with a first circuit among the plurality of circuits and a second portion of the I / O interface region associated with a second circuit among the plurality of circuits.

2. The apparatus of claim 1, wherein each of the plurality of impedance calibration circuits is configured to generate calibration codes for a circuit system used to adjust the associated portion of the I / O interface region.

3. The apparatus of claim 1, wherein the plurality of impedance calibration circuits comprises at least two impedance calibration circuits.

4. The apparatus of claim 3, further comprising at least two additional interpolation circuits, each portion of the I / O interface region associated with the interpolation circuits and the at least two additional interpolation circuits being at least partially located between a first portion of the I / O interface region associated with a first impedance calibration circuit of the at least two impedance calibration circuits and a second portion of the I / O interface region associated with a second impedance calibration circuit of the at least two impedance calibration circuits.

5. The apparatus of claim 4, wherein the portion of the I / O interface region associated with the interpolation circuit is at least partially located between a fourth portion of the I / O interface region associated with a first interpolation circuit of the at least two additional interpolation circuits and a fifth portion of the I / O interface region associated with a second interpolation circuit of the at least two additional interpolation circuits.

6. The apparatus of claim 1, wherein each of the plurality of impedance calibration circuits is located adjacent to a first edge of the I / O interface region or a second edge of the I / O interface region, the second edge being opposite to the first edge.

7. The apparatus of claim 6, wherein the interpolation circuit is positioned adjacent to a third edge or a fourth edge of the I / O interface region, each of the third edge and the fourth edge of the I / O interface region being adjacent to each of the first edge and the second edge of the I / O interface region.

8. The apparatus of claim 1, wherein each of the plurality of impedance calibration circuits is located adjacent to a first edge, a second edge, or a third edge of the I / O interface region, the first edge being opposite to the second edge and adjacent to the third edge.

9. The apparatus of claim 8, wherein the interpolation circuit is positioned adjacent to the third edge or the fourth edge of the I / O interface region, the third edge being opposite to the fourth edge.

10. A method for impedance calibration, comprising: A first impedance calibration code and a second impedance calibration code are determined for a semiconductor device, wherein the first impedance calibration code is associated with a first portion of the I / O interface of the semiconductor device and the second impedance calibration code is associated with a second portion of the I / O interface; as well as A third calibration code for the semiconductor device is determined by interpolation of the first impedance calibration code and the second impedance calibration code. The third calibration code is associated with a third portion of the I / O interface, which is at least partially located between the first portion and the second portion of the I / O interface.

11. The method of claim 10, wherein determining the third calibration code comprises determining the third calibration code for the third portion of the I / O interface via an interpolation circuit associated with the third portion of the I / O interface.

12. The method of claim 10, further comprising determining a fourth calibration code for a fourth portion of the I / O interface based on the first impedance calibration code and the third calibration code, the fourth portion being at least partially located between the first portion associated with the first impedance calibration code and the third portion associated with the third calibration code.

13. The method of claim 12, further comprising determining a fifth calibration code for a fifth portion of the I / O interface based on the second impedance calibration code and the third calibration code, the fifth portion being at least partially located between the second portion and the third portion associated with the second impedance calibration code.

14. The method of claim 13, further comprising: The circuitry of the first portion of the I / O interface region is adjusted based on the first impedance calibration code; The circuitry of the second portion of the I / O interface area is adjusted based on the second impedance calibration code; The circuitry of the third portion of the I / O interface area is adjusted based on the third calibration code; The circuitry of the fourth portion of the I / O interface area is adjusted based on the fourth calibration code; as well as The circuitry of the fifth portion of the I / O interface area is adjusted based on the fifth calibration code.

15. The method of claim 10, further comprising: The circuitry of the first portion of the I / O interface area is adjusted based on the first impedance calibration code; The circuitry of the second portion of the I / O interface area is adjusted based on the second impedance calibration code; as well as The circuitry of the third portion of the I / O interface region is adjusted based on the third calibration code.

16. A system for impedance calibration, comprising: At least one input device; At least one output device; At least one processor device operatively coupled to the input device and the output device; as well as At least one memory device operatively coupled to the at least one processor device and comprising: A first calibration circuit is positioned in a first part adjacent to the I / O interface and configured to generate a first calibration code; A second calibration circuit, positioned adjacent to a second portion of the I / O interface and configured to generate a second calibration code; and An interpolation circuit, coupled to each of the first and second calibration circuits and positioned adjacent to a third portion of the I / O interface, is configured to generate a third calibration code via interpolation of the first and second calibration codes, the third portion of the I / O interface being at least partially located between the first and second portions of the I / O interface.

17. The system of claim 16, further comprising a second interpolation circuit configured to generate a fourth calibration code in response to receiving the third calibration code and the second calibration code.

18. The system of claim 17, further comprising a third interpolation circuit configured to generate a fifth calibration code in response to receiving the third calibration code and the first calibration code.

19. The system of claim 18, further comprising a fourth interpolation circuit configured to generate a sixth calibration code in response to receiving the first calibration code and the second calibration code, wherein the fourth interpolation circuit and the interpolation circuit are located adjacent to the relative edges of the I / O interface.

20. The system of claim 16, wherein the first calibration circuit and the second calibration circuit are located adjacent to the relative edges of the I / O interface.

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