Trench filling method and semiconductor device

Abstract

A trench filling method and a semiconductor device, the method comprising: providing a semiconductor substrate, the semiconductor substrate having a first trench and a second trench, the depth of the first trench being greater than the depth of the second trench; forming a first tungsten layer by a chemical vapor deposition process, the first tungsten layer filling the first trench; forming a second tungsten layer by a physical vapor deposition process, the second tungsten layer covering the first tungsten layer and filling a portion of the second trench. The present invention can effectively avoid affecting the flatness of the surface after metal aluminum deposition in subsequent processes, reduce the risk of defects in aluminum pads and appearance defects, reduce the risk of residual byproducts in subsequent processes, and improve the quality of semiconductor devices.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a trench filling method and a semiconductor device. Background Art

[0002] In the process of forming semiconductor devices using three-dimensional integration technology, through silicon vias are widely used as a common connection structure. With the improvement of the integration of bonded wafers, the size of through silicon vias continues to decrease, and the aspect ratio of the through silicon vias increases day by day.

[0003] In order to improve the quality of semiconductor devices, tungsten plugs are usually used to form through silicon vias, that is, tungsten material is filled in the through silicon via, and a tungsten layer is used to connect the underlying metal layer to form a complete metal interconnection circuit.

[0004] In the prior art, a chemical vapor deposition process is used to fill tungsten material in silicon through vias and metal interconnect trenches. The chemical vapor deposition process has a strong gap filling capability and can meet the aspect ratio requirements in deeper trenches.

[0005] However, the surface roughness of the tungsten layer formed by the chemical vapor deposition process is too large. In the metal interconnection groove area, the uneven surface of the tungsten layer will further affect the flatness of the surface after metal aluminum deposition in the subsequent process. The uneven surface of the metal aluminum not only increases the defect risk and appearance defects of the aluminum pad itself, but also increases the risk of residual by-products in subsequent processes, affecting the quality of semiconductor devices. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a trench filling method and a semiconductor device, which can effectively avoid affecting the flatness of the surface after metal aluminum is deposited in the subsequent process, reduce the defect risk and appearance defect risk of the aluminum pad, reduce the risk of residual by-products in the subsequent process, and improve the quality of the semiconductor device.

[0007] To solve the above technical problems, an embodiment of the present invention provides a trench filling method, comprising: providing a semiconductor substrate, the semiconductor substrate having a first trench and a second trench, the depth of the first trench being greater than the depth of the second trench; forming a first tungsten layer by a chemical vapor deposition process, the first tungsten layer filling the first trench; forming a second tungsten layer by a physical vapor deposition process, the second tungsten layer covering the first tungsten layer and filling a portion of the second trench.

[0008] Optionally, the roughness of the surface of the second tungsten layer is smaller than the roughness of the surface of the first tungsten layer.

[0009] Optionally, before forming the first tungsten layer by using the chemical vapor deposition process, the groove filling method also includes: providing a test run wafer, the test run wafer having a first detection groove and a second detection groove, and the first detection groove is consistent with the first groove in size, and the second detection groove is consistent with the second groove in size; on the surface of the test run wafer, forming a first detection tungsten layer by using the chemical vapor deposition process, the first detection tungsten layer fills the first groove and covers the bottom surface and side wall of the second groove; on the surface of the first detection tungsten layer, forming a second detection tungsten layer by using the physical vapor deposition process; using a preset roughness indication parameter to detect the test run wafer, wherein the roughness indication parameter is used to indicate the roughness of the surface of the first detection tungsten layer or the second detection tungsten layer; if the detection result of the roughness indication parameter exceeds the preset roughness indication parameter threshold, performing back etching during the process of forming the first tungsten layer by using the chemical vapor deposition process.

[0010] Optionally, the surfaces of the first detection tungsten layers formed by different chemical vapor deposition processes have respective roughnesses, and different chemical vapor deposition processes have respective roughness indication parameter thresholds.

[0011] Optionally, using a preset roughness indication parameter, the inspection of the trial run wafer includes: measuring the surface roughness of the first inspection tungsten layer and / or the second inspection tungsten layer.

[0012] Optionally, the roughness indication parameter threshold is a surface roughness threshold; wherein the surface roughness threshold Ra is an average value of the surface roughness within a range of 2um×2um, and the value of Ra is selected from 20 to 40nm.

[0013] Optionally, the preset roughness indication parameter is the total thickness of the first detection tungsten layer and the second detection tungsten layer, and the preset roughness indication parameter threshold is a preset thickness value of the first detection tungsten layer and the second detection tungsten layer.

[0014] Optionally, forming the first tungsten layer using a chemical vapor deposition process includes: forming a first initial tungsten layer using a chemical vapor deposition process, the first initial tungsten layer filling the first groove and covering the bottom surface and side wall of the second groove; etching back the first initial tungsten layer to remove the first initial tungsten layer on the bottom surface and side wall of the second groove, and obtaining the first tungsten layer.

[0015] Optionally, forming the second tungsten layer by using a physical vapor deposition process includes: forming the second tungsten layer by using a physical vapor deposition process, wherein the second tungsten layer covers the bottom surface and sidewalls of the second trench after the back etching process, and covers the first tungsten layer in the first trench.

[0016] Optionally, before forming the second tungsten layer by a physical vapor deposition process, the trench filling method also includes: forming a first barrier layer, the first barrier layer covering the bottom surface and side wall of the second trench after the back etching process, and covering the first tungsten layer in the first trench; wherein the second tungsten layer covers the first barrier layer.

[0017] Optionally, the first tungsten layer also covers the bottom surface and sidewalls of the second trench.

[0018] Optionally, before forming the second tungsten layer by a physical vapor deposition process, the trench filling method further includes: forming a second barrier layer, wherein the second barrier layer covers the first tungsten layer; wherein the second tungsten layer covers the second barrier layer.

[0019] Optionally, the first trench is a through silicon via or a non-through silicon via, and the second trench is a metal interconnect trench.

[0020] To solve the above technical problems, an embodiment of the present invention provides a semiconductor device, including: a semiconductor substrate, the semiconductor substrate having a first groove and a second groove, the depth of the first groove being greater than the depth of the second groove; a first tungsten layer, the first tungsten layer filling the first groove, wherein the first tungsten layer is formed by a chemical vapor deposition process; a second tungsten layer, the second tungsten layer covering the first tungsten layer and filling a portion of the second groove, wherein the second tungsten layer is formed by a physical vapor deposition process.

[0021] Optionally, the roughness of the surface of the second tungsten layer is smaller than the roughness of the surface of the first tungsten layer.

[0022] Optionally, the second tungsten layer covers the bottom surface and sidewalls of the second trench, and covers the first tungsten layer in the first trench.

[0023] Optionally, the semiconductor device further includes: a first barrier layer, the first barrier layer covers the bottom surface and sidewalls of the second trench and covers the first tungsten layer in the first trench; wherein the second tungsten layer covers the first barrier layer.

[0024] Optionally, the first tungsten layer also covers the bottom surface and sidewalls of the second trench.

[0025] Optionally, the semiconductor device further includes: a second barrier layer, wherein the second barrier layer covers the first tungsten layer; wherein the second tungsten layer covers the second barrier layer.

[0026] Optionally, the first trench is a through silicon via or a non-through silicon via, and the second trench is a metal interconnect trench.

[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0028] In an embodiment of the present invention, a chemical vapor deposition process is used to form a first tungsten layer that fills the first groove, and then a physical vapor deposition process is used to form a second tungsten layer. The second tungsten layer covers the first tungsten layer and fills a portion of the second groove. The chemical vapor deposition process can utilize the strong gap-filling ability to meet the aspect ratio requirements in the first groove. In addition, the tungsten layer formed by the physical vapor deposition process often has the characteristic of small surface roughness, and there is an opportunity to form a tungsten layer with small roughness and large smoothness and flatness in the second groove area, thereby effectively avoiding affecting the flatness of the surface after metal aluminum is deposited in the subsequent process, reducing the risk of defects in the aluminum pad and appearance defects, reducing the risk of residual by-products in the subsequent process, and improving the quality of semiconductor devices.

[0029] Furthermore, a trial run wafer (Tri-run Wafer) is provided, and a preset roughness indication parameter is used to detect the trial run wafer. If the detection result of the roughness indication parameter exceeds the preset roughness indication parameter threshold, a back-etching process is performed during the process of forming the first tungsten layer by a chemical vapor deposition process. After the second detection tungsten layer of the trial run wafer is formed by a physical vapor deposition process, if the roughness requirement still cannot be met, it can be set in the process of formally forming the semiconductor device, and in the process of forming the first tungsten layer by a chemical vapor deposition process, a back-etching process is performed. The tungsten material on the bottom surface and side wall of the second groove can be removed. Since the roughness of the bottom surface of the second groove is less than the roughness of the surface of the first tungsten layer, the roughness requirement can be better met after the second tungsten layer is formed by a physical vapor deposition process.

[0030] Furthermore, the surface of the first detection tungsten layer formed by different chemical vapor deposition processes has its own roughness, and different chemical vapor deposition processes have their own roughness indication parameter thresholds. Therefore, when using different chemical vapor deposition processes, appropriate roughness indication parameter thresholds can be set, which is beneficial to improving the accuracy of judging whether to set a back etching process in practical applications.

[0031] Furthermore, in the first specific embodiment, the first initial tungsten layer is etched back to remove the first initial tungsten layer on the bottom surface and side wall of the second groove, and the first tungsten layer is obtained, so that the tungsten material on the bottom surface and side wall of the second groove can be removed. Since the roughness of the bottom surface of the second groove is less than the roughness of the surface of the first tungsten layer, the roughness requirement can be better met after the second tungsten layer is formed by a physical vapor deposition process.

[0032] Furthermore, in the second specific embodiment, the first initial tungsten layer is not etched back, and the first tungsten layer also covers the bottom surface and side wall of the second groove, so that the surface roughness of the first tungsten layer is relatively small and can meet the requirements, and the second tungsten layer can be directly formed by physical vapor deposition process to improve production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of a cross-sectional structure of a device formed by a trench filling method in the prior art;

[0034] Figure 2 is a flow chart of a trench filling method according to an embodiment of the present invention;

[0035] Figures 3 to 6 is a schematic diagram of a device cross-sectional structure corresponding to each step in a trench filling method in an embodiment of the present invention;

[0036] Figures 7 and 8 is a schematic diagram of a device cross-sectional structure corresponding to each step in another trench filling method according to an embodiment of the present invention;

[0037] Fig. 9 The figure is a flow chart of a method for determining a back etching process in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In the prior art, chemical vapor deposition is used to fill tungsten materials in silicon through vias and metal interconnect trenches. The chemical vapor deposition process has the characteristic of strong gap filling ability, which can meet the aspect ratio requirements in deeper trenches. However, the surface roughness of the tungsten layer formed by the chemical vapor deposition process is too large. In the metal interconnect trench area, the uneven surface of the tungsten layer will further affect the flatness of the surface after the metal aluminum is deposited in the subsequent process. The uneven surface of the metal aluminum not only increases the defect risk of the aluminum pad itself and the appearance defect, but also increases the risk of residual byproducts in the subsequent process, affecting the quality of semiconductor devices.

[0039] Reference Figure 1 , Figure 1 The present invention is a schematic diagram of a cross-sectional structure of a device formed by a trench filling method in the prior art.

[0040] like Figure 1 As shown, a semiconductor substrate 100 is provided. The semiconductor substrate 100 has a first trench 101 and a second trench 102 . The depth of the first trench 101 is greater than the depth of the second trench 102 .

[0041] A tungsten layer 110 is formed by a chemical vapor deposition process. The tungsten layer 110 fills up the first trench 101 and a portion of the second trench 102 .

[0042] In subsequent processes, other device structures can also be formed, such as Figure 1 The aluminum pad 130 is shown in FIG.

[0043] The inventors of the present invention have found through research that in the prior art, only the chemical vapor deposition process is used, and the surface roughness of the formed tungsten layer is too large (e.g. Figure 1 The area encircled by the dotted circle in the middle is not conducive to the quality of subsequent processes in the shallow trench area. The use of the physical vapor deposition process has the problem of insufficient gap-filling ability, which is not conducive to the filling effect in the deep trench area. As a result, for semiconductor devices with two types of trenches at the same time and different aspect ratios of the two trenches, it is difficult to meet the requirements at the same time by using a single process.

[0044] In an embodiment of the present invention, a chemical vapor deposition process is used to form a first tungsten layer that fills the first groove, and then a physical vapor deposition process is used to form a second tungsten layer. The second tungsten layer covers the first tungsten layer and fills a portion of the second groove. The chemical vapor deposition process can utilize the strong gap-filling ability to meet the aspect ratio requirements in the first groove. In addition, the tungsten layer formed by the physical vapor deposition process often has the characteristic of small surface roughness, and there is an opportunity to form a tungsten layer with small roughness and large smoothness and flatness in the second groove area, thereby effectively avoiding affecting the flatness of the surface after metal aluminum is deposited in the subsequent process, reducing the risk of defects in the aluminum pad and appearance defects, reducing the risk of residual by-products in the subsequent process, and improving the quality of semiconductor devices.

[0045] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] Reference Figure 2 , Figure 2 1 is a flow chart of a trench filling method in an embodiment of the present invention. The trench filling method may include steps S21 to S23:

[0047] Step S21: providing a semiconductor substrate, wherein the semiconductor substrate has a first trench and a second trench, wherein a depth of the first trench is greater than a depth of the second trench;

[0048] Step S22: forming a first tungsten layer by a chemical vapor deposition process, wherein the first tungsten layer fills the first trench;

[0049] Step S23: forming a second tungsten layer by a physical vapor deposition process, wherein the second tungsten layer covers the first tungsten layer and fills a portion of the second trench.

[0050] The tungsten layer may be understood as a layer containing tungsten elements, such as a metal tungsten layer, an aluminum-tungsten composite layer, and the like.

[0051] Furthermore, the first trench may be, for example, a through trench, such as a through silicon via, or may be a non-through trench, such as a non-through silicon via.

[0052] Specifically, in the three-dimensional integration process, silicon vias are commonly used as a connection structure. As the integration of bonded wafers increases, the size of silicon vias will be reduced and the density will be increased. In this case, the size of the through-holes continues to decrease, and the aspect ratio of the through-holes is increasing. Tungsten plug silicon vias would be a suitable choice to connect the underlying metal and the metal tungsten in the silicon vias to achieve metal interconnection to form a complete circuit.

[0053] The second trench may be a metal interconnect trench.

[0054] In the prior art, in addition to being used for through silicon via filling, metal tungsten can also be used for metal interconnection, that is, a tungsten layer needs to be filled in the metal interconnection process.

[0055] Taking complementary metal oxide semiconductor image sensor (CMOS Image Sensors, CIS) devices as an example, due to its advantages of low power consumption and high signal-to-noise ratio, it has been widely used in various fields. In CIS products, in order to ensure that the subsequent process of forming a color filter will not be affected by the protrusions on the wafer surface, the tungsten layer (an aluminum-tungsten composite layer can also be used) used for metal interconnection must be set in a shallow groove on the back of the wafer.

[0056] Combine the following Figures 3 to 6 Each of the above steps is described below.

[0057] Figures 3 to 6 It is a schematic diagram of the device cross-sectional structure corresponding to each step in a trench filling method in an embodiment of the present invention.

[0058] Reference Figure 3 , a semiconductor substrate 200 is provided, wherein the semiconductor substrate 200 has a first trench 201 and a second trench 202 , wherein the depth of the first trench 201 is greater than the depth of the second trench 202 .

[0059] The first initial tungsten layer 210 is formed by a chemical vapor deposition process. The first initial tungsten layer 210 fills the first trench 201 and covers the bottom surface and sidewalls of the second trench 202 .

[0060] The surface roughness of the first initial tungsten layer 210 is too large (eg Figure 3 area outlined by a dotted circle).

[0061] In a specific implementation, the semiconductor substrate 200 may be a silicon substrate, or the material of the semiconductor substrate 200 may also be a suitable material for image sensors such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the semiconductor substrate 200 may also be a silicon substrate on an insulator surface or a germanium substrate on an insulator surface, or a substrate with an epitaxy layer (Epi layer) grown thereon. Preferably, the semiconductor substrate 200 may be a lightly doped semiconductor substrate, and the doping type is opposite to that of the drain region. Specifically, deep well doping (Deep Well Implant) may be achieved by performing ion implantation into the semiconductor substrate 200.

[0062] Furthermore, before forming the first initial tungsten layer 210, an underlying barrier layer (not shown) may be formed on the surface of the semiconductor substrate 200, the underlying barrier layer covering the bottom surface and sidewalls of the second trench and the bottom surface and sidewalls of the first trench. The first initial tungsten layer 210 covers the underlying barrier layer.

[0063] The bottom barrier layer has the function of improving adhesion with a subsequently formed tungsten layer and preventing the subsequently formed tungsten layer from diffusing into the semiconductor substrate 200 .

[0064] It should be noted that the bottom barrier layer may be formed by conventional processes, and its thickness is smaller than the first initial tungsten layer 210 and is insufficient to fill the first trench.

[0065] Reference Figure 4 , the first initial tungsten layer 210 is etched back to remove the first initial tungsten layer 210 on the bottom surface and sidewall of the second trench 202, and obtain the first tungsten layer 211.

[0066] It can be understood that compared to the first initial tungsten layer 210, Figure 4 The first tungsten layer 211 is shown to be located only within the first trench 201 .

[0067] Furthermore, the etch-back process may adopt a dry-etch process, and the semiconductor substrate 200 may be used as a stop layer, that is, after the etch-back process, the surface of the semiconductor substrate 200 is exposed.

[0068] For example, before forming the first initial tungsten layer 210, an underlying barrier layer (not shown) may be formed on the surface of the semiconductor substrate 200. Then, after the back etching process, the first initial tungsten layer 210 and the underlying barrier layer on the surface of the semiconductor substrate 200 may be removed, the first initial tungsten layer 210 on the bottom surface and sidewall of the second trench 202 may be removed, and the first tungsten layer 211 and the underlying barrier layer in the first trench 201 may be retained.

[0069] Reference Figure 5 The second tungsten layer 220 is formed by a physical vapor deposition process. The second tungsten layer 220 covers the bottom surface and sidewall of the second trench 202 after the back etching process, and covers the first tungsten layer 210 in the first trench 201.

[0070] Furthermore, the roughness of the surface of the second tungsten layer 220 is smaller than the roughness of the surface of the first tungsten layer 211 .

[0071] It can be understood that the roughness of the surface of the second tungsten layer 220 is less than the roughness of the surface of the first initial tungsten layer 210 .

[0072] In the embodiment of the present invention, the second tungsten layer 220 formed by the physical vapor deposition process has the characteristic of small surface roughness, and a tungsten layer with small roughness and high smoothness and flatness is formed in the second groove 202 area, which effectively avoids affecting the flatness of the surface after metal aluminum is deposited in the subsequent process, reduces the defect risk of the aluminum pad and appearance defects, reduces the risk of residual by-products in the subsequent process, and improves the quality of semiconductor devices.

[0073] Furthermore, before forming the second tungsten layer 220 by adopting a physical vapor deposition process, the trench filling method may also include: forming a first barrier layer (not shown), the first barrier layer covering the bottom surface and side wall of the second trench 202 after the back etching treatment, and covering the first tungsten layer 211 in the first trench 201; wherein the second tungsten layer 220 covers the first barrier layer.

[0074] The first barrier layer functions to improve adhesion with a subsequently formed tungsten layer and to prevent the subsequently formed tungsten layer from diffusing into other material regions (eg, the semiconductor substrate 200 and / or the first tungsten layer 211 ).

[0075] It should be noted that the first barrier layer may be formed by conventional processes, and its thickness is smaller than that of the second tungsten layer 220 .

[0076] Reference Figure 6 , a subsequent device structure, such as an aluminum pad 230 , is formed on the surface of the second tungsten layer 220 .

[0077] It should be pointed out that other appropriate structures may be formed subsequently, such as forming a CIS device, and the embodiments of the present invention do not limit the subsequent specific structures.

[0078] In a first specific implementation of an embodiment of the present invention, the first initial tungsten layer 210 is etched back to remove the first initial tungsten layer 210 on the bottom surface and side wall of the second groove 202, and the first tungsten layer 211 is obtained, so that the tungsten material on the bottom surface and side wall of the second groove 202 can be removed. Since the roughness of the bottom surface of the second groove 202 is less than the roughness of the surface of the first tungsten layer 211, the roughness requirement can be better met after the second tungsten layer 220 is formed by a physical vapor deposition process.

[0079] In an embodiment of the present invention, a chemical vapor deposition process is used to form a first tungsten layer 211 that fills the first groove 201, and then a physical vapor deposition process is used to form a second tungsten layer 220. The second tungsten layer 220 covers the first tungsten layer 211 and fills a portion of the second groove 202. The chemical vapor deposition process can utilize the strong gap-filling ability to meet the aspect ratio requirements in the first groove 201. In addition, the tungsten layer formed by the physical vapor deposition process often has the characteristic of small surface roughness, and there is an opportunity to form a tungsten layer with small roughness and large smoothness and flatness in the second groove 202 area, thereby effectively avoiding affecting the flatness of the surface after metal aluminum deposition in subsequent processes, reducing the risk of defects in the aluminum pad and appearance defects, reducing the risk of residual by-products in subsequent processes, and improving the quality of semiconductor devices.

[0080] Figures 7 and 8 FIG. 1 is a schematic diagram of a device cross-sectional structure corresponding to each step in another trench filling method according to an embodiment of the present invention. Figures 3 to 6 The trench filling method shown in FIG. 1 is described in different places.

[0081] Reference Figure 7 , a semiconductor substrate 200 is provided, wherein the semiconductor substrate 200 has a first trench 201 and a second trench 202 , wherein the depth of the first trench 201 is greater than the depth of the second trench 202 .

[0082] The first tungsten layer 310 is formed by a chemical vapor deposition process. The first tungsten layer 310 fills the first trench 201 and covers the bottom surface and sidewalls of the second trench 202 .

[0083] It should be pointed out that Figure 3 The difference is, Figure 7 The surface roughness of the first tungsten layer 310 is shown to be less than Figure 3 The surface roughness of the first initial tungsten layer 210 is shown as Figure 7In this case, the first tungsten layer 310 can be directly retained without the need for an etch-back process.

[0084] Reference Figure 8 A second tungsten layer 320 is formed on the surface of the first tungsten layer 310 by using a physical vapor deposition process.

[0085] Furthermore, before forming the second tungsten layer 320 by using a physical vapor deposition process, the trench filling method may further include: forming a second barrier layer (not shown), the second barrier layer covering the first tungsten layer 310; wherein the second tungsten layer 320 covers the second barrier layer.

[0086] The second barrier layer is used to improve adhesion with a subsequently formed tungsten layer and to prevent the subsequently formed tungsten layer from diffusing into other material regions (eg, the semiconductor substrate 200 and / or the second tungsten layer 310 ).

[0087] It should be noted that the first barrier layer may be formed by conventional processes, and its thickness is smaller than that of the second tungsten layer 320 .

[0088] It should be noted that the bottom barrier layer is formed before the first tungsten layer. Relatively speaking, the first barrier layer and the second barrier layer are both formed after the first tungsten layer. Figures 3 to 6 In the first specific embodiment shown, the second barrier layer belongs to Figures 7 and 8 The second specific embodiment is shown.

[0089] In a second specific implementation of the embodiment of the present invention, the first tungsten layer 310 is not etched back, and the first tungsten layer 310 still covers the bottom surface and side wall of the second groove 202, so that the surface roughness of the first tungsten layer 310 is small and can meet the requirements. The second tungsten layer 320 is directly formed by physical vapor deposition process to improve production efficiency.

[0090] In an embodiment of the present invention, a chemical vapor deposition process is used to form a first tungsten layer 310 that fills the first groove 201, and then a physical vapor deposition process is used to form a second tungsten layer 320. The second tungsten layer 320 covers the first tungsten layer 310 and fills a portion of the second groove 202. The chemical vapor deposition process can utilize the strong gap-filling ability to meet the aspect ratio requirements in the first groove 201. In addition, the tungsten layer formed by the physical vapor deposition process often has the characteristic of small surface roughness. There is an opportunity to form a tungsten layer with small roughness and high smoothness and flatness in the second groove 202 area, thereby effectively avoiding affecting the flatness of the surface after metal aluminum deposition in subsequent processes, reducing the risk of defects in the aluminum pad and appearance defects, reducing the risk of residual by-products in subsequent processes, and improving the quality of semiconductor devices.

[0091] In the embodiment of the present invention, a step of determining whether an etch-back process is required in the process of forming the first tungsten layer by using a chemical vapor deposition process is also disclosed.

[0092] Reference Fig. 9 , Fig. 9 is a flow chart of a method for determining a back-etching process in an embodiment of the present invention. The method for determining a back-etching process includes steps S91 to S95, and steps S91 to S95 may be located in steps Figure 1 Before step S12 shown in the figure. Each step is described below.

[0093] In step S91 , a test operation wafer is provided, wherein the test operation wafer has a first detection groove and a second detection groove, and the first detection groove has a size consistent with the first groove, and the second detection groove has a size consistent with the second groove.

[0094] The trial operation wafer may correspond to the product wafer on which the semiconductor device is formally formed. For example, the same process parameters may be used to form the first detection trench and the second detection trench.

[0095] The consistent dimensions are used to indicate that the process parameters and measurement parameters of the device are consistent, for example, the parameters such as length, width, height, depth, angle, etc. are consistent.

[0096] In step S92, a first detection tungsten layer is formed on the surface of the trial operation wafer by using the chemical vapor deposition process, and the first detection tungsten layer fills the first groove and covers the bottom surface and sidewall of the second groove.

[0097] Specifically, the first detection tungsten layer may be formed by using the same chemical vapor deposition process as that of the product wafer.

[0098] In step S93, a second detection tungsten layer is formed on the surface of the first detection tungsten layer by using the physical vapor deposition process.

[0099] Specifically, the second detection tungsten layer may be formed by adopting the same physical vapor deposition process as that of the product wafer.

[0100] Understandably, the process steps for the pilot wafers are closer to Figures 7 and 8 The illustrated embodiment does not involve any process steps for the etch-back process.

[0101] In step S94, the test wafer is inspected using a preset roughness indication parameter, wherein the roughness indication parameter is used to indicate the roughness of the surface of the first inspection tungsten layer or the second inspection tungsten layer.

[0102] In a first specific implementation of the embodiment of the present invention, a preset roughness indication parameter may be used, and the detection of the trial run wafer may include: measuring the surface roughness of the first detection tungsten layer and / or the second detection tungsten layer.

[0103] Specifically, after forming the first detection tungsten layer and / or the second detection tungsten layer, whether the roughness requirement is met can be detected, so that during the formal formation of the semiconductor device, during the process of forming the first tungsten layer using the chemical vapor deposition process, whether to perform back etching can be set.

[0104] Furthermore, the roughness indication parameter threshold is a surface roughness threshold; the surface roughness threshold Ra is an average value of the surface roughness within a range of 2um×2um, and the value of Ra is selected from 20 to 40nm.

[0105] The larger the average value of the surface roughness within the range of 2um×2um, the rougher the current surface is.

[0106] In a specific implementation, a plurality of units may be detected step-by-step with a range of 2um×2um as a unit, and then an average value of the plurality of units may be calculated.

[0107] It should be pointed out that in the embodiment of the present invention, the value range of the surface roughness threshold may be calculated proportionally with other area ranges as units, and the embodiment of the present invention does not limit the specific area range.

[0108] As a non-limiting example, when the current product has a higher requirement for roughness, Ra can be set to 20 nm; when the current product has a lower requirement for roughness, Ra can be set to 40 nm.

[0109] In a second specific implementation of the embodiment of the present invention, the preset roughness indication parameter may be the total thickness of the first detection tungsten layer and the second detection tungsten layer, and the preset roughness indication parameter threshold is the preset thickness value of the first detection tungsten layer and the second detection tungsten layer.

[0110] The inventors of the present invention have found through research that, in a specific implementation, the surface roughness of the tungsten layer formed by chemical vapor deposition process often has a corresponding relationship with the thickness of the tungsten layer. The thicker the tungsten layer, the greater the surface roughness of the tungsten layer.

[0111] Step S95: if the detection result of the roughness indication parameter exceeds the preset roughness indication parameter threshold, performing back etching during the process of forming the first tungsten layer by adopting the chemical vapor deposition process.

[0112] In a first specific implementation of the embodiment of the present invention, if the average value of the surface roughness within the range of 2um×2um is greater than the surface roughness threshold Ra, it can be determined that an etch-back process is required.

[0113] In a second specific implementation of the embodiment of the present invention, if the total thickness of the first detection tungsten layer and the second detection tungsten layer exceeds a preset thickness value, it can be determined that an etch-back process is required.

[0114] In an embodiment of the present invention, a test wafer is provided, and a preset roughness indication parameter is used to detect the test wafer. If the detection result of the roughness indication parameter exceeds the preset roughness indication parameter threshold, a back-etching process is performed during the process of forming the first tungsten layer by a chemical vapor deposition process. After the second detection tungsten layer of the test wafer is formed by a physical vapor deposition process, if the roughness requirement still cannot be met, in the process of formally forming a semiconductor device, a back-etching process is performed during the process of forming the first tungsten layer by a chemical vapor deposition process. The tungsten material on the bottom surface and side wall of the second groove can be removed. Since the roughness of the bottom surface of the second groove is less than the roughness of the surface of the first tungsten layer, the roughness requirement can be better met after the second tungsten layer is formed by a physical vapor deposition process.

[0115] Further, the surfaces of the first detection tungsten layers formed by different chemical vapor deposition processes have respective roughness, and different chemical vapor deposition processes have respective roughness indication parameter thresholds.

[0116] In an embodiment of the present invention, the surfaces of the first detection tungsten layer formed by different chemical vapor deposition processes have their own roughness, and different chemical vapor deposition processes have their own roughness indication parameter thresholds. Therefore, when different chemical vapor deposition processes are adopted, appropriate roughness indication parameter thresholds can be set, which is beneficial to improving the accuracy of judging whether to set a back etching process in practical applications.

[0117] In an embodiment of the present invention, a semiconductor device is further provided, referring to Figure 6 , may include: a semiconductor substrate 200, the semiconductor substrate 200 having a first trench 201 and a second trench 202, the depth of the first trench 201 being greater than the depth of the second trench 202; a first tungsten layer 211, the first tungsten layer 211 filling the first trench 201, wherein the first tungsten layer 211 is formed by a chemical vapor deposition process; a second tungsten layer 220, the second tungsten layer 220 covering the first tungsten layer 211 and filling a portion of the second trench 202, wherein the second tungsten layer 220 is formed by a physical vapor deposition process.

[0118] Furthermore, the roughness of the surface of the second tungsten layer 220 is smaller than the roughness of the surface of the first tungsten layer 211 .

[0119] Furthermore, the second tungsten layer 220 covers the bottom surface and sidewalls of the second trench 202 , and covers the first tungsten layer in the first trench 201 .

[0120] Furthermore, the semiconductor device also includes: a first barrier layer (not shown), the first barrier layer covers the bottom surface and sidewalls of the second trench 202, and covers the first tungsten layer 211 in the first trench 201; wherein the second tungsten layer 220 covers the first barrier layer.

[0121] In an embodiment of the present invention, another semiconductor device is provided. Figure 8 , may include: a semiconductor substrate 200, the semiconductor substrate 200 having a first trench 201 and a second trench 202, the depth of the first trench 201 being greater than the depth of the second trench 202; a first tungsten layer 310, the first tungsten layer 211 filling the first trench 201, wherein the first tungsten layer 310 is formed by a chemical vapor deposition process; a second tungsten layer 320, the second tungsten layer 320 covering the first tungsten layer 310 and filling a portion of the second trench 202, wherein the second tungsten layer 320 is formed by a physical vapor deposition process.

[0122] Furthermore, the first tungsten layer 310 also covers the bottom surface and sidewalls of the second trench 202 .

[0123] Furthermore, the semiconductor device further includes: a second barrier layer (not shown), the second barrier layer covers the first tungsten layer 310; wherein the second tungsten layer 320 covers the second barrier layer.

[0124] Further, the first trench 201 is a through silicon via or a non-through silicon via, and the second trench 202 is a metal interconnect trench.

[0125] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A trench filling method, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate having a first trench and a second trench, the depth of the first trench being greater than the depth of the second trench; forming a first tungsten layer by a chemical vapor deposition process, wherein the first tungsten layer fills the first trench; forming a second tungsten layer by a physical vapor deposition process, wherein the second tungsten layer covers the first tungsten layer and fills a portion of the second trench; Before forming the first tungsten layer by a chemical vapor deposition process, the method further comprises: Providing a test run wafer, wherein the test run wafer has a first detection groove and a second detection groove, wherein the first detection groove has the same size as the first groove, and the second detection groove has the same size as the second groove; On the surface of the trial operation wafer, a first detection tungsten layer is formed by the chemical vapor deposition process, wherein the first detection tungsten layer fills the first groove and covers the bottom surface and sidewall of the second groove; On the surface of the first detection tungsten layer, forming a second detection tungsten layer by using the physical vapor deposition process; Using a preset roughness indication parameter to inspect the test run wafer, wherein the roughness indication parameter is used to indicate the roughness of the surface of the first inspection tungsten layer or the second inspection tungsten layer; If the detection result of the roughness indication parameter exceeds the preset roughness indication parameter threshold, an etch-back process is performed during the process of forming the first tungsten layer by using a chemical vapor deposition process.

2. The trench filling method according to claim 1, characterized in that: The roughness of the surface of the second tungsten layer is smaller than the roughness of the surface of the first tungsten layer.

3. The trench filling method according to claim 1, characterized in that: The surfaces of the first detection tungsten layers formed by different chemical vapor deposition processes have respective roughnesses, and different chemical vapor deposition processes have respective roughness indication parameter thresholds.

4. The trench filling method according to claim 1, characterized in that: Using the preset roughness indication parameters, the test run wafer is inspected including: The surface roughness of the first detection tungsten layer and / or the second detection tungsten layer is measured.

5. The trench filling method according to claim 4, characterized in that: The roughness indication parameter threshold is a surface roughness threshold; The surface roughness threshold Ra is an average value of the surface roughness within a range of 2um×2um, and the value of Ra is selected from 20 to 40nm.

6. The trench filling method according to claim 1, characterized in that: The preset roughness indication parameter is the total thickness of the first detection tungsten layer and the second detection tungsten layer, and the preset roughness indication parameter threshold is the preset thickness value of the first detection tungsten layer and the second detection tungsten layer.

7. The trench filling method according to any one of claims 1 to 6, characterized in that: Forming the first tungsten layer using a chemical vapor deposition process includes: Forming a first initial tungsten layer by a chemical vapor deposition process, wherein the first initial tungsten layer fills the first trench and covers the bottom surface and sidewalls of the second trench; The first initial tungsten layer is etched back to remove the first initial tungsten layer on the bottom surface and sidewall of the second trench, and obtain the first tungsten layer.

8. The trench filling method according to claim 7, characterized in that: Forming the second tungsten layer by a physical vapor deposition process includes: The second tungsten layer is formed by a physical vapor deposition process, and the second tungsten layer covers the bottom surface and the sidewall of the second trench after the back etching process, and covers the first tungsten layer in the first trench.

9. The trench filling method according to claim 8, characterized in that: Before forming the second tungsten layer by a physical vapor deposition process, the method further comprises: forming a first barrier layer, wherein the first barrier layer covers the bottom surface and sidewalls of the second trench after the etch-back process, and covers the first tungsten layer in the first trench; Wherein, the second tungsten layer covers the first barrier layer.

10. The trench filling method according to claim 1, characterized in that: The first tungsten layer also covers the bottom surface and sidewalls of the second trench.

11. The trench filling method according to claim 10, characterized in that: Before forming the second tungsten layer by a physical vapor deposition process, the method further comprises: forming a second barrier layer, wherein the second barrier layer covers the first tungsten layer; Wherein, the second tungsten layer covers the second barrier layer.

12. The trench filling method according to claim 1, characterized in that: The first trench is a through silicon via or a non-through silicon via, and the second trench is a metal interconnect trench.

13. A semiconductor device, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate has a first trench and a second trench, wherein a depth of the first trench is greater than a depth of the second trench; A first tungsten layer, wherein the first tungsten layer fills the first groove, wherein the first tungsten layer is formed by a chemical vapor deposition process; a second tungsten layer, the second tungsten layer covers the first tungsten layer and fills a portion of the second trench, wherein the second tungsten layer is formed by a physical vapor deposition process; In the process of forming the first tungsten layer by using the chemical vapor deposition process, if the detection result of the roughness indication parameter of the test run wafer exceeds the preset roughness indication parameter threshold, back etching is performed; wherein, the roughness indication parameter is used to indicate the roughness of the surface of the first detection tungsten layer or the second detection tungsten layer, the test run wafer has a first detection groove and a second detection groove, and the first detection groove is consistent with the first groove in size, and the second detection groove is consistent with the second groove in size, the first detection tungsten layer is formed on the surface of the test run wafer by using the chemical vapor deposition process, the first detection tungsten layer fills the first groove and covers the bottom surface and side wall of the second groove, and the second detection tungsten layer is formed on the surface of the first detection tungsten layer by using the physical vapor deposition process.

14. The semiconductor device according to claim 13, characterized in that The roughness of the surface of the second tungsten layer is smaller than the roughness of the surface of the first tungsten layer.

15. The semiconductor device according to claim 13, wherein: The second tungsten layer covers the bottom surface and sidewalls of the second trench and covers the first tungsten layer in the first trench.

16. The semiconductor device according to claim 15, characterized in that Also includes: a first barrier layer, the first barrier layer covering the bottom surface and sidewalls of the second trench and covering the first tungsten layer in the first trench; Wherein, the second tungsten layer covers the first barrier layer.

17. The semiconductor device according to claim 13, characterized in that The first tungsten layer also covers the bottom surface and sidewalls of the second trench.

18. The semiconductor device according to claim 17, wherein: Also includes: a second barrier layer, the second barrier layer covering the first tungsten layer; Wherein, the second tungsten layer covers the second barrier layer.

19. The semiconductor device according to claim 13, characterized in that The first trench is a through silicon via or a non-through silicon via, and the second trench is a metal interconnect trench.

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