Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a substrate, at least one via, a liner, and a conductive layer. The substrate includes electronic circuitry. The at least one via passes through the substrate. The at least one via includes a plurality of recessed portions on a sidewall thereof. The liner fills the plurality of recessed portions of the at least one via. The conductive layer is disposed on the sidewall of the at least one via, over the liner, and extends to a surface of the substrate. A thickness of the conductive layer on the sidewall of the at least one via varies.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded several generations of ICs, each with smaller and more complex circuitry than the previous one. Throughout IC development, functional density (i.e., the number of interconnects per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. Typically, this scaling down process provides benefits through increased production efficiency and reduced associated costs. This scaling down also increases the complexity of handling and manufacturing ICs, prompting research into advancements in IC handling and manufacturing to enable these progresses. Summary of the Invention

[0003] According to one aspect of this disclosure, a semiconductor device includes a substrate, at least one via, a liner, and a conductive layer. The substrate includes electronic circuitry. At least one via extends through the substrate. The at least one via includes a plurality of recesses on its sidewalls. The liner fills the plurality of recesses of the at least one via. The conductive layer is disposed on the sidewalls of the at least one via, covers the liner, and extends to the surface of the substrate. The thickness of the conductive layer on the sidewalls of the at least one via is variable.

[0004] According to another aspect of this disclosure, a semiconductor device includes a circuit substrate, a passivation layer, at least one substrate via, a conductive layer, and an insulating liner. The circuit substrate includes a semiconductor substrate and a device layer thereon on the semiconductor substrate. The passivation layer is disposed on the device layer. At least one substrate via passes through the passivation layer, the device layer, and the semiconductor substrate. The conductive layer covers the passivation layer and the inner sidewalls of the at least one substrate via. The insulating liner is disposed between the conductive layer of the circuit substrate and the semiconductor substrate, and the insulating liner has scalloped sidewalls facing the semiconductor substrate and substantially smooth sidewalls facing the conductive layer.

[0005] According to another aspect of this disclosure, a method of forming a semiconductor device includes: forming a device layer over the front side of a first substrate; forming at least one via through the device layer and extending into the first substrate; performing a cyclic deposition and etching process to form a conductive layer on the sidewall of the at least one via; and thinning the back side of the first substrate. Attached Figure Description

[0006] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of discussion.

[0007] Figures 1A to 1J This is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0008] Figures 2A to 2F This is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an alternative embodiment of the present disclosure.

[0009] Figures 3 to 11 These are cross-sectional views of various semiconductor devices according to some embodiments of the present disclosure.

[0010] Figure 12 The illustration shows a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0011] Figure 13 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself define a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” “above,” etc., are used herein to describe the relationship or function of one component or feature with respect to another component, as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein will be interpreted accordingly.

[0014] The semiconductor device of the present invention provides a thicker metal protective layer for high aspect ratio (e.g., AR ≥ 6) vias or trenches with scalloped sidewalls. In some embodiments, the semiconductor device of the present invention is an optical element for use in a photolithographic patterning process. In some embodiments, the semiconductor device of the present disclosure is a mask for forming a pattern of a photomask or a chip. In some embodiments, the semiconductor device of the present invention may be a beam controller, such as a beam deflector, an electron beam deflector, an electromagnetic beam deflector, etc. In some embodiments, the semiconductor device of the present disclosure is used as a beam deflector through which one or more electrons or a beam of light are deflected by operation of electronic circuitry embedded in the semiconductor device.

[0015] Figures 1A to 1J This is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. It should be understood that the present disclosure is not limited to the methods described below. Additional operations may be provided before, during, and / or after the method, and for additional embodiments of the method, some operations described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0016] refer to Figure 1A A circuit substrate 20 is provided. In some embodiments, the circuit substrate 20 has a device layer 25 formed in a region of its front surface. Specifically, the circuit substrate 20 includes a semiconductor substrate 21 and a device layer 25 formed on the front surface or active side of a semiconductor substrate 21. In some embodiments, the circuit substrate 20 is provided at this stage as a wafer-type substrate. In some examples, the circuit substrate 20 is referred to as a "circuit wafer," "device wafer," "device substrate," or "substrate." The circuit substrate 20 may include multiple semiconductor device regions that are subsequently segmented to form individual semiconductor devices.

[0017] Semiconductor substrate 21 includes elemental semiconductors such as silicon and germanium, and / or compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide. For example, semiconductor substrate 21 is a silicon-on-insulator (SOI) substrate or a silicon substrate. In various embodiments, semiconductor substrate 21 may be a planar substrate, a substrate with multiple fins, nanowires, or other forms known to those skilled in the art.

[0018] Device layer 25 includes at least one transistor, such as a complementary metal-oxide-semiconductor (CMOS) transistor, a fin field-effect transistor (FinFET), a gate-all-around FET (GAA-FET), etc. Device layer 25 also includes a metallization layer on the semiconductor substrate 21 and covering the transistor. The metallization layer may include conductive features 24 embedded in the dielectric layer 22 to electrically connect different devices in and / or on the semiconductor substrate 21 to form a functional circuit. In some examples, device layer 25 is referred to as an "electronic circuit". The metallization layer can be formed by any suitable process, such as deposition, electroplating, damascene, dual damascene, etc. Dielectric layer 22 includes an interlayer dielectric (ILD) layer and one or more intermetallic dielectric (IMD) layers. Conductive features 24 may include multilayer wires and multiple conductive plugs. Conductive plugs include contact plugs and via plugs. Contact plugs are located in the ILD layer for connecting metal wires to devices. Via plugs are located in the IMD layer for connecting metal wires in different layers. The dielectric layer 22 includes silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or a combination thereof. The conductive feature 24 includes metals, metal alloys, or combinations thereof, such as tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or combinations thereof.

[0019] After forming the device layer 25, at least one passivation layer 28 is formed on the front surface of the circuit substrate 20. In some embodiments, the at least one passivation layer 28 comprises silicon oxide, silicon nitride, or an organic film. In some embodiments, the at least one passivation layer 28 comprises a polymer material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or combinations thereof. In some examples, the passivation layer 28 is considered part of the circuit substrate 20.

[0020] refer to Figure 1B One or more vias 26 are formed in the circuit substrate 20. In some embodiments, the vias 26 are formed such that no metal pattern is exposed within the vias. In some embodiments, a mask layer is formed on the passivation layer 28, and an etching process is performed using the mask layer as a mask. In some embodiments, the vias 26 are formed to pass through the passivation layer 28 and the device layer 25 and extend into the semiconductor substrate 21. The etching process includes dry etching, wet etching, and reactive ion etching such as Bosch etching. The etching process can etch from the front surface such that the vias 26 reach a depth of approximately tens to hundreds of micrometers but do not penetrate the back surface.

[0021] In some embodiments, the etching process may result in each via 26 adjacent to device layer 25 having a substantially smooth sidewall for its upper opening 26a, and a series of etched macro-scallops or concave portions 26c on the sidewall of each via 26 adjacent to semiconductor substrate 21. Alternatively, each via 26 may include an upper opening 26a, a lower opening 26b below the upper opening 26a, and concave portions 26c on the sidewall of the lower opening 26b. The upper opening 26a, lower opening 26b, and concave portions 26c are spatially connected to each other. In some examples, the concave portions 26c are considered part of the lower opening 26b.

[0022] Each of the vias 26 has a high aspect ratio of about 6 or greater (e.g., about 10 or greater). In some embodiments, the upper opening 26a has a depth a1 ranging from about 2 μm to 40 μm, and the lower opening 26b has a depth a2 ranging from about 10 μm to 200 μm. In some embodiments, the upper opening 26a has a width b1 ranging from about 3 μm to 110 μm, the lower opening 26b has a width b2 ranging from about 3 μm to 100 μm, and the difference Δb between them is greater than zero, for example, about 0.1 μm to 10 μm (e.g., 0.1 μm to 5 μm). In some embodiments, a recessed portion 26c is disposed along the sidewall of the lower opening 26b and has a width c ranging from about 0.01 μm to 0.2 μm. In some embodiments, a series of etched large scallops or recessed portions 26c may be formed only on the exposed sidewall of the semiconductor substrate 21. In some embodiments, the recessed portions 26c have substantially the same size or width, such as Figure 1B As shown. However, this disclosure is not limited thereto. In other embodiments, the recessed portion 26c may vary in size or width depending on process parameters. In some embodiments, the angle θ between the sidewall of the upper opening 26a and the bottom surface of the device layer 25 is less than about 90 degrees, for example, about 30 to 89.5 degrees. However, this disclosure is not limited thereto. In some cases, the angle θ between the sidewall of the upper opening 26a and the bottom surface of the device layer 25 is about 90 degrees, and the difference Δb between width b1 and width b2 is about 0.

[0023] In some examples, this scallop-like sidewall can be described as ripped, rough, stair-step, or wavy. In some embodiments, the large scallop or recessed portion 26c is continuously formed along the sidewall of the lower opening 26b, such as... Figure 1B As shown. In other embodiments, the large scallop-shaped or recessed portion 26c is formed discontinuously along the sidewall of the lower opening 26b; that is, adjacent recessed portions 26c are separated from each other.

[0024] refer to Figure 1C A liner 27 is formed above the circuit substrate 20. The liner 27 extends along the sidewalls and bottom of the via 26 and fills the scalloped or recessed portion 26c of the sidewalls of the via 26. Specifically, the liner 27 is formed on the surface of the passivation layer 28, on the smooth sidewalls of the upper opening 26a, and on the scalloped sidewalls and bottom of the lower opening 26b.

[0025] In some embodiments, the liner 27 comprises an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be formed by a suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. In some embodiments, a CVD method is used to form the liner 27. In some examples, the liner 27 is referred to as an "insulating liner." In some embodiments, the sidewall scallops are completely filled by the liner 27 to create a flat surface for subsequent metal film deposition. Specifically, the liner 27 has scallop-shaped sidewalls facing the semiconductor substrate 21 and substantially smooth sidewalls facing the subsequently formed conductive layer.

[0026] refer to Figure 1D A conductive layer 50a is formed on the circuit substrate 20 along the sidewalls and bottom of the via 26. In some embodiments, the conductive layer 50a is conformally formed inside the via 26 such that the inner sidewalls and bottom of each via 26 are completely covered by the conductive layer 50a. In some embodiments, a deposition process P1 is performed to form the conductive layer 50a on the circuit substrate 20 and cover the substrate 27. The conductive layer 50a may comprise one or more layers of Au, Ti, Cu, Ag, and Ni or alloys thereof. In some embodiments, the deposition process P1 includes a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process including sputtering, atomic layer deposition (ALD) processes, electroplating, or any other suitable film deposition method. In some embodiments, a sputtering method is used to form the conductive layer 50a. In some embodiments, the conductive layer 50a has substantially equal thicknesses ranging from about 0.05 μm to 0.2 μm.

[0027] refer to Figure 1E An etching process P2 is performed on the conductive layer 50a to etch a larger portion of the horizontal portion of the conductive layer 50a and a smaller portion of the vertical portion of the conductive layer 50a. In some embodiments, the etching process P2 is in-situ etching. Specifically, the deposition process P1 and the etching process P2 are performed in the same processing chamber. However, this disclosure is not limited thereto. In other embodiments, the deposition process P1 and the etching process P2 are performed in different processing chambers.

[0028] In some embodiments, during one cycle of deposition process P1 and etching process P2, the remaining conductive layer 50a is formed with different thicknesses on each via 26 and passivation layer 28. Specifically, due to the directional etching process P2, the conductive layer 50a is formed thicker on the sidewall of the lower opening 26b of the via 26.

[0029] refer to Figure 1F and Figure 1G Another cycle of deposition process P1 and etching process P2 is performed to obtain a conductive layer 50 with the desired thickness.

[0030] like Figure 1F As shown, a deposition process P1 is performed to form a conductive layer 50b on the conductive layer 50a. The conductive layer 50b may comprise one or more layers of Au, Ti, Cu, Ag, and Ni, or alloys thereof. In some embodiments, the deposition process P1 includes a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process including sputtering, atomic layer deposition (ALD) processes, electroplating, or any other suitable film deposition method. In some embodiments, a sputtering method is used to form the conductive layer 50b. In some embodiments, the conductive layer 50b has substantially equal thicknesses ranging from about 0.05 μm to 0.2 μm.

[0031] In some embodiments, conductive layer 50b and conductive layer 50a are made of the same material. However, this disclosure is not limited thereto. In some alternative embodiments, conductive layer 50b and conductive layer 50a may comprise different materials. Conductive layer 50b and conductive layer 50a are collectively referred to as conductive layer 50. In some embodiments, when conductive layer 50b and conductive layer 50a are made of the same material, the interface between them may be invisible. In other embodiments, when conductive layer 50b and conductive layer 50a are made of different materials, an interface may exist between them.

[0032] like Figure 1G As shown, an etching process P2 is performed on the conductive layer 50b to etch a larger portion of the horizontal portion of the conductive layer 50b and a smaller portion of the vertical portion of the conductive layer 50b. In some embodiments, the etching process P2 is in-situ etching. Specifically, the deposition process P1 and the etching process P2 are performed in the same processing chamber. However, this disclosure is not limited thereto. In other embodiments, the deposition process P1 and the etching process P2 are performed in different processing chambers.

[0033] From another perspective, Figure 1D The deposition process P1 and Figure 1EThe etching process P2 constitutes one cycle of the cyclic deposition and etching process. In the cyclic deposition and etching process, the deposition process P1 and the etching process P2 are performed continuously and cyclically without interruption. The above-described embodiments of the cyclic deposition and etching process, comprising two cycles of deposition and etching steps, are provided for illustrative purposes and are not to be construed as limiting this disclosure. In some embodiments, in some alternative embodiments, Figure 1D The deposition process P1 and Figure 1E The etching process P2 can be performed alternately multiple times until a conductive layer 50 with a predetermined thickness is formed. Specifically, the cyclic deposition and etching process can include m cycles of deposition and etching steps, where m is a positive integer. For example, m is an integer from 1 to 5, such as 2, 3, or 4. The cyclic deposition and etching process of the present invention is advantageous for increasing the thickness of the conductive layer 50 on the sidewall of the via 26.

[0034] In some embodiments, after the above-described cyclic deposition and etching processes, the resulting conductive layer 50 has different thicknesses. Specifically, the thickness d1 of the conductive layer 50 on the sidewall of the lower opening 26b is approximately between 0.5 μm and 4 μm, the thickness d2 of the conductive layer 50 on the sidewall of the upper opening 26a is approximately between 0.01 μm and 2 μm, and the thickness d3 of the conductive layer 50 on the surface of the circuit substrate 20 is approximately between 0.5 μm and 4 μm. In some embodiments, d1 > d3 > d2. In some embodiments, d1 > d3 = d2. Therefore, the ratio of d2 / d3 is equal to or less than 1, and the ratio of d2 / d1 is less than 1. However, this disclosure is not limited thereto. In other embodiments, d3 > d1 > d2.

[0035] In some embodiments, following the formation of conductive layer 50, one or more optional conductive layers may be further formed on conductive layer 50, depending on process requirements, to provide a multilayer conductive structure on the sidewalls of each substrate via. The optional conductive layers are formed using a different method than conductive layer 50. For example, the optional conductive layers may be formed with a uniform thickness. In some embodiments, the multilayer conductive structure includes a Ti / Al / Ti structure, a Ti / Cu / Ti structure, etc.

[0036] refer to Figure 1H Forming a filling layer 140 to fill, as Figure 1G The via 26 is shown. In some embodiments, the filler layer 140 comprises silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. In some embodiments, silicon oxide is used. In some embodiments, a blanket layer of filler material is formed over the conductive layer 50, followed by a planarization operation, such as a chemical mechanical polishing process or an etch-back process, to leave the filler material only inside the via 26, as shown. Figure 1H As shown. In other embodiments, no filler material is formed.

[0037] refer to Figure 1I The back side of the circuit substrate 20 is thinned using a grinding or polishing process P3. In some embodiments, the remaining thickness of the thinned circuit substrate 20 is in the range of about 12 μm to about 140 μm. In some embodiments, the back side of the circuit substrate 20 is thinned until the fill layer 140 is exposed from the bottom of the via 26. Specifically, the conductive layer 50 and the liner 27 at the bottom of each via 26 are removed during the polishing process P3.

[0038] refer to Figure 1J A dicing process is used to separate a semiconductor device from its adjacent counterparts by dividing the circuit substrate 20 along the dicing zone CL. Specifically, multiple semiconductor devices are formed on a wafer, and the wafer is diced into individual semiconductor devices (chips) through a sawing (dicing) operation. Figure 1J As indicated by the arrow in the image. Subsequently, an etching process is performed to remove the filler layer 140, as shown... Figure 1J As shown. In some examples, the substrate via 65 is referred to as a "through-hole" or "silicon via". Thus, the semiconductor device 1 of the present invention is completed.

[0039] In the semiconductor device of this invention, a pre-passivation liner (e.g., oxide or nitride) is applied prior to the metal sputtering process. The pre-passivation liner smoothly fills the sidewall scallops caused by the Bosch process, forming a very flat surface and resolving the problem of metal layer discontinuity caused by sidewall scallops. Furthermore, a cyclic deposition and etching process is performed to obtain a thicker metal film on the sidewalls of the TSV region. Simultaneously, through a directional etching process, the thickness of the field region metal film can be thinner than that of the TSV region sidewalls.

[0040] In some embodiments, the semiconductor device serving as a beam deflector is controllable, causing it to deflect the beam in a selectable direction. In this invention, the conductive layer 50, continuously formed along the sidewall of the via 26, is thick enough that the conductive layer 50 is not easily damaged or broken into discontinuous sections when the beam passes through the substrate of the semiconductor device.

[0041] In the above embodiments, the absence of a support substrate in the semiconductor device of the present invention is provided for illustrative purposes and does not constitute a limitation of the present invention. In other embodiments, the semiconductor device of the present invention may be bonded to a support substrate according to process requirements.

[0042] Figures 2A to 2FThis is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an alternative embodiment of the present disclosure. It should be understood that the present disclosure is not limited to the methods described below. Additional operations may be provided before, during, and / or after the method, and for additional embodiments of the method, some operations described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0043] refer to Figure 2A This provides an intermediate structure similar to that of 1H. In some embodiments, [the following is performed] Figures 1A to 1H Operations to form Figure 2A The structure, component configuration, and manufacturing methods have been described above and will not be repeated here.

[0044] refer to Figure 2B The back side of the circuit substrate 20 is thinned by a grinding or polishing process P3. In some embodiments, the remaining thickness of the thinned circuit substrate 20 is in the range of about 100 μm to about 500 μm.

[0045] refer to Figure 2C The thinned circuit substrate 20 is bonded to the support substrate 30 via a bonding layer 40. In some embodiments, the support substrate 30 comprises an elemental semiconductor such as silicon or germanium and / or a compound semiconductor such as silicon-germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide. For example, the support substrate 30 is a silicon-on-insulator (SOI) substrate or a silicon substrate. In some embodiments, the support substrate 30 does not have devices. In some examples, the support substrate 30 is referred to as a “device-free support.” In some embodiments, the support substrate 30 is provided at this stage as a wafer-type substrate. In some examples, the support substrate 30 is referred to as a “support wafer,” a “silicon support,” or a “silicon frame.”

[0046] In some embodiments, the bonding layer 40 includes silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, such as Figure 2C As shown, the bonding layer 40 is silicon oxide formed on the surface of the support substrate 30 by, for example, a thermal oxidation process or a chemical vapor deposition (CVD) process. In other embodiments, the bonding layer 40 is formed on the back side of the circuit substrate 20 by a CVD process. In some embodiments, the thickness of the bonding layer 40 is in the range of about 500 nm to about 5 μm. In other embodiments, the thickness of the bonding layer 40 is in the range of about 1 μm to 2 μm. In some embodiments, the bonding layer 40 may be omitted.

[0047] refer to Figure 2D The back side of the support substrate 30 is recessed by using one or more photolithography and etching operations. In some embodiments, the etching operation includes plasma dry etching or wet etching.

[0048] In some embodiments, wet etching utilizes tetramethylammonium hydroxide (TMAH) or KOH solution. In some embodiments, bonding layer 40 serves as an etch stop layer forming notch 35, such as... Figure 2D As shown. In some embodiments, the included angle α between the sidewall and the bottom of the notch 35 is approximately 90 degrees. However, this disclosure is not limited thereto. In other embodiments, the included angle α between the sidewall and the bottom of the notch 35 is greater than 90 degrees, for example, approximately 90.5 to 155 degrees.

[0049] refer to Figure 2E Subsequently, the bonding layer 40 exposed by the notch 35 is removed by a suitable etching operation. Then, the back side of the circuit substrate 20 is etched to expose the fill layer 140 filling the via 26. The fill layer 140 is then removed, thereby forming the substrate via 65, as shown. Figure 2E As shown.

[0050] refer to Figure 2F A dicing process is used to separate a semiconductor device from its adjacent counterparts by dividing the circuit substrate 20 and the underlying support substrate 30 along the dicing zone CL. Specifically, multiple semiconductor devices are formed on a wafer, and the wafer is diced into individual semiconductor devices (chips) through a sawing (dicing) operation. Figure 2F As indicated by the arrow in the diagram. This completes the semiconductor device 2 of the present invention.

[0051] exist Figure 1J and Figure 2F In the above embodiments, the sidewall scallops or recessed portions 26c of the substrate perforation 65 have similar dimensions. However, this disclosure is not limited thereto. In other embodiments, the dimensions of the sidewall scallops of the substrate perforation can vary, such as... Figures 3 to 6 As shown.

[0052] exist Figures 3 to 6 In semiconductor devices 3-6, the sidewall scallops or recessed portions 26c of the substrate through-hole 65 have different dimensions. For example... Figure 3 As shown, the upper recessed portion 26c has a width c1, and the lower recessed portion 26c has a width c2, where width c1 is smaller than width c2. Figure 4 As shown, the upper recessed portion 26c has a width c1, and the lower recessed portion 26c has a width c2, where width c1 is greater than width c2. Figure 5 As shown, the size or width c of the recessed portion 26c gradually increases from the front side of the circuit substrate 20. Figure 6 As shown, the size or width c of the recessed portion 26c gradually decreases from the front side of the circuit substrate 20.

[0053] exist Figure 2FIn the above embodiments, the support substrate 30 is provided as a single notch with substantially vertical sidewalls. However, this disclosure is not limited thereto. In other embodiments, the support substrate 30 may have other configurations, such as Figures 7 to 11 As shown.

[0054] exist Figure 7 In the semiconductor device 7, a support substrate 30 is provided with a single recess 35 having inclined sidewalls. Specifically, as Figure 7 As shown, the angle α between the sidewall and the bottom of the notch 35 is greater than 90 degrees.

[0055] exist Figures 8 to 11 In the semiconductor device 8-11, the support substrate 30 is provided with a plurality of recesses 35 that are spatially connected to the substrate through-holes 65.

[0056] like Figures 8 to 9 As shown, the support substrate 30 includes a first portion 30a and a second portion 30b for supporting the circuit substrate 20 above it, which has a substrate through-hole 65. The first portion 30a surrounds the second portion 30b.

[0057] exist Figure 8 In this context, each of the notches 35 has a symmetrical profile, for example, having substantially perpendicular sidewalls facing each other. Viewed from another angle, each of the first portion 30a and the second portion 30b has substantially perpendicular sidewalls opposite each other.

[0058] exist Figure 9 In the design, the notch 35 has different cross-sectional profiles. The notch 35 between the first portion 30a and the adjacent second portion 30b has an asymmetrical profile, while the notch 35 between the adjacent second portions 30b has a symmetrical profile. From another perspective, each first portion 30a has substantially perpendicular sidewalls and inclined sidewalls opposite each other, and each second portion 30b has substantially perpendicular sidewalls opposite each other.

[0059] like Figures 10 to 11 As shown, the support substrate 30 includes a first portion 30a, a second portion 30b, and a third portion 30c for supporting the circuit substrate 20 above it, which has a substrate through-hole 65. The first portion 30a surrounds the second portion 30b, and the second portion 30b surrounds the third portion 30c.

[0060] Figure 10 The semiconductor device 10 is similar to Figure 8 The semiconductor device 8, in addition to Figure 10 In the middle, the central portion (e.g., the third portion 30c) is shorter than the outer portions (e.g., the first portion 30a and the second portion 30b).

[0061] Figure 11The semiconductor device 11 is similar to Figure 9 The semiconductor device 9, in addition to Figure 11 In the middle, the central portion (e.g., the third portion 30c) is shorter than the outer portions (e.g., the first portion 30a and the second portion 30b).

[0062] The shape and configuration of the support substrate are not limited to those disclosed herein. Those skilled in the art will understand that other shapes and configurations of the support substrate are also possible. In other words, any support substrate capable of supporting the overlay circuit board including substrate through-holes of this disclosure is considered to fall within the spirit and scope of this disclosure. Furthermore, Figures 3 to 6 The substrate vias shown can be replaced according to design requirements. Figures 7 to 11 Substrate perforation of each semiconductor device 7-11.

[0063] Figure 12 The illustrations depict methods for forming a semiconductor device according to some embodiments. Although the method is illustrated and / or described as a series of actions or events, it should be understood that the method is not limited to the illustrated sequence or actions. Therefore, in some embodiments, the actions may be performed in a different order than shown, and / or may be performed simultaneously. Furthermore, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events, which may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other actions or events not illustrated may be included.

[0064] In action 102, a device layer is formed over the front side of the first substrate. Figure 1A Cross-sectional views corresponding to some embodiments of action 102 are shown.

[0065] In step 104, at least one through hole is formed, and the at least one through hole penetrates the device layer and extends into the first substrate. Figure 1B Cross-sectional views corresponding to some embodiments of action 104 are shown. In some embodiments, at least one through-hole is formed having scalloped sidewalls in a first substrate. The scalloped or recessed portion of the sidewall of at least one through-hole can have different shapes and configurations, which has been shown in Figure 1J and Figures 3 to 6 It is described in the text.

[0066] In step 106, a liner is formed on the sidewall of at least one through hole, and the liner fills the scalloped portion of at least one through hole adjacent to the first substrate. Figure 1C Cross-sectional views corresponding to some embodiments of action 106 are shown.

[0067] In step 108, a cyclic deposition and etching process is performed to form a conductive layer on the sidewall of at least one via, and the conductive layer covers the liner. Figures 1D to 1G The illustration shows cross-sectional views corresponding to some embodiments of action 108. In some embodiments, the conductive layer is formed thicker on the lower sidewall of at least one substrate through-hole and thinner on the upper sidewall of at least one substrate through-hole.

[0068] In action 110, the back side of the first substrate is thinned. Figure 1I and Figure 2B Cross-sectional views corresponding to some embodiments of action 110 are shown.

[0069] In some embodiments, at least one via is filled with a filler material prior to the thinning operation of action 110. In some embodiments, at least one substrate via is formed by removing the filler material after the thinning operation of action 110.

[0070] In action 112, the second substrate is bonded to the back side of the first substrate, with the bonding layer sandwiched between them. Figure 2C Cross-sectional views corresponding to some embodiments of action 112 are shown.

[0071] At action 114, at least one notch is formed in the second substrate to expose the bottom of at least one through hole. Figures 2D to 2E The illustration shows cross-sectional views corresponding to some embodiments of action 114. One or more notches in the second substrate can have different shapes and configurations, which has been... Figure 2F and Figures 7 to 11 As described in the text.

[0072] In some embodiments, at least one via has a filler material prior to the thinning operation of action 110, and after the notch is formed in the second substrate in action 114, the filler material is removed to form at least one substrate through-hole.

[0073] In action 116, a dicing process is performed to separate a semiconductor device from an adjacent semiconductor device. Figure 1J and Figure 2F Cross-sectional views corresponding to some embodiments of action 116 are shown.

[0074] The following is combined Figure 1J , Figure 2F and Figures 3 to 11 The structure of the semiconductor device of the present invention will be described.

[0075] In some embodiments, semiconductor device 1 / 2 / 3 / 4 / 5 / 6 / 7 / 8 / 9 / 10 / 11 includes a circuit substrate 20, at least one substrate via 65, a liner 27, and a conductive layer 50. The circuit substrate 20 includes electronic circuitry (e.g., device layer 25). At least one substrate via 65 extends through the circuit substrate 20. The at least one substrate via 65 includes a plurality of recesses 26c on its sidewalls. The liner 27 fills the plurality of recesses 26c of the at least one substrate via 65. The conductive layer 50 is disposed on the sidewall of the at least one substrate via, covers the liner 27, and extends to the surface of the circuit substrate 20. The thickness of the conductive layer 50 on the sidewall of the at least one substrate via 65 is variable. In some embodiments, the conductive layer 50 includes one or more layers of Au, Ti, Ni, Ag, and Cu, or alloys thereof.

[0076] In some embodiments, at least one substrate via 65 has a lower opening 65b and an upper opening 65a, the upper opening 65a being wider than the lower opening 65b. In some embodiments, the upper opening 65a has sloping and smooth sidewalls, and a plurality of recesses 26c are arranged along the sidewalls of the lower opening 65b. In some embodiments, electronic circuitry (e.g., device layer 25) is disposed adjacent to the upper opening 65a of at least one substrate via 65.

[0077] In some embodiments, the thickness d2 of the conductive layer 50 on the sidewall of the upper opening 65a of at least one substrate via 65 is less than the thickness d1 of the conductive layer 50 on the sidewall of the lower opening 65b. In some embodiments, the thickness d2 of the conductive layer 50 on the sidewall of the upper opening 65a is equal to or less than the thickness d3 of the conductive layer 50 on the surface of the circuit substrate 20.

[0078] In some embodiments, the semiconductor device further includes a support substrate 30 and a bonding layer 40. The support substrate 30 has at least one notch 35. The bonding layer 40 is disposed between the circuit substrate 20 and the support substrate 30, and at least one substrate via 65 is in spatial communication with the notch 35 of the support substrate 30. In some embodiments, no bonding layer is disposed in the notch 35.

[0079] In some embodiments, semiconductor device 1 / 2 / 3 / 4 / 5 / 6 / 7 / 8 / 9 / 10 / 11 includes a circuit substrate 20, a passivation layer 28, at least one substrate via 65, a conductive layer 50, and an insulating liner 27. The circuit substrate 20 includes a semiconductor substrate 21 and a device layer 25 above the semiconductor substrate 21. The passivation layer 28 is disposed above the device layer 25. At least one substrate via 65 passes through the passivation layer 28, the device layer 25, and the semiconductor substrate 21. The conductive layer 50 covers the passivation layer 28 and the inner sidewalls of the at least one substrate via 65. In some embodiments, the thickness of the conductive layer 50 on the inner sidewalls of the at least one substrate via 65 is non-uniform. The insulating liner 27 is disposed between the conductive layer 50 of the circuit substrate 20 and the semiconductor substrate 21, and the insulating liner 27 has scalloped sidewalls facing the semiconductor substrate 21 and generally smooth sidewalls facing the conductive layer 50.

[0080] In some embodiments, the scalloped sidewalls of the insulating liner 27 include a plurality of recesses 26c, the width of which is uniform, such as... Figure 1J and Figure 2F As shown. In some embodiments, the scalloped sidewalls of the insulating liner 27 include a plurality of recesses 26c, the width of which is non-uniform, such as... Figures 3 to 6 As shown.

[0081] In some embodiments, the angle θ between the upper opening 65a of the inner sidewall of at least one substrate through-hole 65 and the bottom surface of the device layer 25 is less than about 90 degrees. From another angle, the upper sidewall of at least one substrate through-hole 65 is inclined away from the top edge of at least one substrate through-hole 65.

[0082] In this invention, the conductive layer continuously formed along the sidewall of the via 26 is thick enough that the conductive layer 50 is not easily damaged or broken into discontinuous parts when the light beam passes through the substrate of the semiconductor device. The semiconductor device, as a beam deflector, is controllable, allowing it to deflect the light beam in a selectable direction.

[0083] In the above embodiments, the semiconductor device of the present invention, serving as a beam controller, is provided for illustrative purposes and does not constitute a limitation of the present invention. In other embodiments, the substrate vias of the semiconductor device of the present invention can function as heat dissipation elements, such as... Figure 13 As shown.

[0084] refer to Figure 13In the semiconductor device 12, a central substrate via is filled with conductive material 51, while peripheral substrate vias 65 remain open and serve as heat dissipation elements. One end of the central substrate via of the circuit substrate 20 is electrically connected to a first integrated circuit structure 52, and the other end of the central substrate via of the circuit substrate 20 is electrically connected to a second integrated circuit structure 56. In some embodiments, each of the first and second integrated circuit structures 52 and 56 includes an interposer substrate, a printed circuit board substrate, etc. Furthermore, each of the first and second integrated circuit structures 52 and 56 may contain devices, or may not have devices. In some embodiments, the first integrated circuit structure 52 is electrically connected to a first die structure 54, and the second integrated circuit structure 56 is electrically connected to a second die structure 58. In some embodiments, each of the first and second die structures 54 and 58 may be a single die or a die stack comprising multiple vertically stacked dies. For example, the first die structure 54 is a cube comprising multiple vertically stacked memory chips, while the second die structure 58 is a CPU chip.

[0085] In some embodiments, a heat sink 62 is disposed on the second die structure 58 to effectively dissipate heat from the semiconductor device. The heat sink 62 may be a finned heat sink or a cold plate. The heat sink 62 is adhered to the second die structure 58 directly or via a thermal interface material (TIM). In some embodiments, a bump 60 is also included in the semiconductor device 12, disposed between the heat sink 62 and the device layer 25 of the circuit substrate 20 to provide electrical conductivity and / or heat dissipation.

[0086] In some embodiments, the conductive layer 50 and the conductive material 51 are formed in the same process step. Specifically, the central substrate via is designed to be narrower than the width of the peripheral substrate vias. With this configuration, during the cyclic deposition and etching processes to form the conductive layer 50, the conductive material on the opposite sidewalls of each central substrate via merges to completely fill the central substrate via. However, this disclosure is not limited thereto. In other embodiments, when the conductive material on the opposite sidewalls of each central substrate via is insufficient to completely fill the central substrate via, an electroplating process can be further performed to form another conductive layer to completely fill the central substrate via.

[0087] The conductive layer 50 in the peripheral substrate vias is not only disposed on the sidewalls of the peripheral substrate vias, but also on the surface portion of the circuit substrate 20 to improve heat dissipation performance. Furthermore, Figures 3 to 6 The substrate vias shown can be replaced according to design requirements. Figure 13 The substrate around the semiconductor device 12 is perforated.

[0088] As described above, the various embodiments or examples described herein offer several advantages over the prior art. It should be understood that not all advantages are discussed herein, no particular advantage is required from any of the embodiments or examples, and other embodiments or examples may provide different advantages.

[0089] According to one aspect of this disclosure, a semiconductor device includes a substrate, at least one via, a liner, and a conductive layer. The substrate includes electronic circuitry. At least one via extends through the substrate. The at least one via includes a plurality of recesses on its sidewalls. The liner fills the plurality of recesses of the at least one via. The conductive layer is disposed on the sidewalls of the at least one via, covers the liner, and extends to the surface of the substrate. The thickness of the conductive layer on the sidewalls of the at least one via is variable.

[0090] In some embodiments, the at least one via has a lower opening and an upper opening, the upper opening being wider than the lower opening. In some embodiments, the upper opening has sloping and smooth sidewalls, and the plurality of recessed portions are arranged along the sidewalls of the lower opening. In some embodiments, the thickness of the conductive layer on the sidewall of the upper opening of the at least one via is less than the thickness of the conductive layer on the sidewall of the lower opening. In some embodiments, the thickness of the conductive layer on the sidewall of the upper opening is equal to or less than the thickness of the conductive layer on the surface of the substrate. In some embodiments, the electronic circuit is disposed adjacent to the upper opening of the at least one via. In some embodiments, the system further includes: a support substrate having at least one notch; and a bonding layer disposed between the substrate and the support substrate, wherein the at least one via communicates with the at least one notch space of the support substrate. In some embodiments, no bonding layer is disposed in the notch. In some embodiments, the conductive layer comprises one or more layers of Au, Ti, Ni, Ag, and Cu or alloys thereof.

[0091] According to another aspect of this disclosure, a semiconductor device includes a circuit substrate, a passivation layer, at least one substrate via, a conductive layer, and an insulating liner. The circuit substrate includes a semiconductor substrate and a device layer thereon on the semiconductor substrate. The passivation layer is disposed on the device layer. At least one substrate via passes through the passivation layer, the device layer, and the semiconductor substrate. The conductive layer covers the passivation layer and the inner sidewalls of the at least one substrate via. The insulating liner is disposed between the conductive layer of the circuit substrate and the semiconductor substrate, and the insulating liner has scalloped sidewalls facing the semiconductor substrate and substantially smooth sidewalls facing the conductive layer.

[0092] In some embodiments, the thickness of the conductive layer on the inner sidewall of the at least one substrate perforation is non-uniform. In some embodiments, the scalloped sidewall of the insulating liner includes a plurality of recessed portions, the width of which is non-uniform. In some embodiments, the angle between the inner sidewall of the upper opening of the at least one substrate perforation and the bottom surface of the device layer is less than about 90 degrees. In some embodiments, the device further includes: a support substrate having at least one notch; and a bonding layer disposed between the circuit substrate and the support substrate, wherein the at least one substrate perforation communicates with the at least one notch space of the support substrate.

[0093] According to another aspect of this disclosure, a method of forming a semiconductor device includes: forming a device layer over the front side of a first substrate; forming at least one via through the device layer and extending into the first substrate; performing a cyclic deposition and etching process to form a conductive layer on the sidewall of the at least one via; and thinning the back side of the first substrate.

[0094] In some embodiments, the method further includes forming a liner on the sidewall of the at least one via before forming the conductive layer, wherein the liner fills a scalloped portion of the at least one via adjacent to the first substrate. In some embodiments, the method further includes: filling the at least one via with a filler material before thinning; and removing the filler material after thinning to form at least one substrate through-hole. In some embodiments, the method further includes: filling the at least one via with a filler material before thinning; bonding a second substrate to the back side of the first substrate after thinning, with a bonding layer sandwiched therebetween; forming a notch in the second substrate to expose the bottom of the at least one via; and removing the filler material to form at least one substrate through-hole. In some embodiments, the at least one via in the first substrate is formed having scalloped sidewalls. In some embodiments, the cyclic deposition and etching process includes m cycles of deposition and etching steps, where m is an integer from 2 to 5.

[0095] The foregoing outlines features of several embodiments or examples to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments or examples described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: Substrates, including electronic circuits; At least one through-hole extends through the substrate, wherein the at least one through-hole includes a plurality of recessed portions on its sidewall; A liner is filled into the plurality of recessed portions of the at least one through hole; as well as A conductive layer is disposed on the sidewall of the at least one via, covers the liner, and extends to the surface of the substrate, wherein the thickness of the conductive layer on the sidewall of the at least one via is variable. The at least one through hole has a lower opening and an upper opening, wherein the upper opening is wider than the lower opening. The electronic circuitry is disposed next to the upper opening of the at least one through-hole.

2. The semiconductor device of claim 1, wherein the interface between the substrate and the conductive layer is smooth.

3. The semiconductor device of claim 2, wherein the upper opening has an inclined and smooth sidewall, and the plurality of recessed portions are arranged along the sidewall of the lower opening.

4. The semiconductor device of claim 2, wherein the thickness of the conductive layer on the sidewall of the upper opening of the at least one via is less than the thickness of the conductive layer on the sidewall of the lower opening.

5. The semiconductor device of claim 4, wherein the thickness of the conductive layer on the sidewall of the upper opening is equal to or less than the thickness of the conductive layer on the surface of the substrate.

6. The semiconductor device of claim 2, wherein the electronic circuitry comprises a complementary metal-oxide-semiconductor transistor, a fin field-effect transistor, or a gate-around FET.

7. The semiconductor device according to claim 1, further comprising: A supporting substrate having at least one notch; as well as A bonding layer is disposed between the substrate and the support substrate, wherein at least one via communicates with at least one recessed space of the support substrate.

8. The semiconductor device according to claim 7, wherein no bonding layer is provided in the recess.

9. The semiconductor device of claim 1, wherein the conductive layer comprises one or more layers of Au, Ti, Ni, Ag and Cu or alloys thereof.

10. A semiconductor device, comprising: A circuit substrate, including a semiconductor substrate and a device layer thereon on the semiconductor substrate; A passivation layer is disposed on the device layer; At least one substrate via extends through the passivation layer, the device layer, and the semiconductor substrate; A conductive layer covering the passivation layer and the inner sidewall of the at least one substrate via; An insulating liner is disposed between the conductive layer and the semiconductor substrate of the circuit substrate, wherein the insulating liner has scalloped sidewalls facing the semiconductor substrate and substantially smooth sidewalls facing the conductive layer. The at least one substrate via has a lower opening and an upper opening, wherein the upper opening is wider than the lower opening. The device layer is disposed next to the upper opening of the at least one substrate perforation.

11. The semiconductor device of claim 10, wherein the thickness of the conductive layer on the inner sidewall of the at least one substrate through-hole is non-uniform.

12. The semiconductor device of claim 10, wherein the scalloped sidewall of the insulating liner includes a plurality of recesses, the width of which is non-uniform.

13. The semiconductor device of claim 10, wherein the angle between the inner sidewall of the upper opening of the at least one substrate through-hole and the bottom surface of the device layer is less than 90 degrees.

14. The semiconductor device of claim 10, further comprising: A supporting substrate having at least one notch; as well as A bonding layer is disposed between the circuit substrate and the support substrate, wherein at least one substrate via communicates with at least one recessed space of the support substrate.

15. A method for manufacturing a semiconductor device, comprising: A device layer is formed above the front side of the first substrate; At least one via is formed, the at least one via penetrating the device layer and extending into the first substrate, wherein the at least one via has a lower opening and an upper opening, the upper opening being wider than the lower opening, and the device layer is disposed next to the upper opening of the at least one via; A cyclic deposition and etching process is performed to form a conductive layer on the sidewall of the at least one via; as well as Thin the back side of the first substrate.

16. The method of manufacturing a semiconductor device according to claim 15, further comprising forming a liner on the sidewall of the at least one via before forming the conductive layer, wherein the liner fills a scalloped portion of the at least one via adjacent to the first substrate.

17. The method for manufacturing a semiconductor device according to claim 15, further comprising: Before the thinning process, the at least one through-hole is filled with a filler material; as well as After the thinning process, the filler material is removed to form at least one substrate perforation.

18. The method of manufacturing a semiconductor device according to claim 15, further comprising: Before the thinning process, the at least one through-hole is filled with a filler material; After the thinning process, the second substrate is bonded to the back side of the first substrate, with the bonding layer sandwiched therebetween. A notch is formed in the second substrate to expose the bottom of the at least one through-hole; as well as Remove the filler material to form at least one substrate perforation.

19. The method of manufacturing a semiconductor device according to claim 15, wherein the at least one via in the first substrate is formed having scalloped sidewalls.

20. The method of manufacturing a semiconductor device according to claim 15, wherein the cyclic deposition and etching process comprises m cycles of deposition and etching steps, and m is an integer from 2 to 5.

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