Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, the substrate comprising a first conductive structure and a device structure, the substrate further comprising a first dielectric layer, a second dielectric layer, and an etch stop layer, wherein the second dielectric layer has a resistor layer; forming a first opening and a second opening in the second dielectric layer, wherein the bottom of the first opening exposes the etch stop layer on the first conductive structure, and the bottom of the second opening exposes the resistor layer; using a selective film forming process, forming an intermediate conductive film on the surface of the exposed resistor layer; after forming the intermediate conductive film, etching the exposed etch stop layer until the surface of the first conductive structure is exposed; after etching the exposed etch stop layer, forming a second conductive structure in the first opening; and after etching the exposed etch stop layer, forming a third conductive structure in the second opening. Thus, the semiconductor structure can have better performance and reliability while reducing the difficulty of the semiconductor structure manufacturing process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Currently, in the semiconductor manufacturing process, it is a widely used process to form an opening in an interlayer dielectric layer by an etching process, and then deposit a conductive material in the opening to form an electrical connection structure for electrical connection between semiconductor devices.

[0003] However, it is difficult for existing semiconductor structures to reduce the difficulty of the manufacturing process of the semiconductor structure while taking into account the performance and reliability of the semiconductor structure. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to reduce the difficulty of the manufacturing process of the semiconductor structure while improving the performance and reliability of the semiconductor structure.

[0005] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate including a first conductive structure and a device structure, the substrate also including a first dielectric layer located between the first conductive structure and the device structure, a second dielectric layer located on the first dielectric layer, and an etch stop layer located between the first dielectric layer and the second dielectric layer, the second dielectric layer having a resistance layer; a second conductive structure located in the second dielectric layer, the second conductive structure penetrates the etch stop layer, and the second conductive structure contacts with a top surface of the first conductive structure; an intermediate conductive film located in the second dielectric layer, the intermediate conductive film is also located on the top surface of the resistance layer; a third conductive structure located in the second dielectric layer, the third conductive structure is also located on the surface of the intermediate conductive film.

[0006] Optionally, the material of the intermediate conductive film includes fluorine-free tungsten.

[0007] Optionally, the thickness of the intermediate conductive film is greater than 2 nanometers.

[0008] Optionally, the material of the second conductive structure includes fluorine-containing tungsten, and the material of the third conductive structure includes fluorine-containing tungsten.

[0009] Optionally, the material of the first conductive structure includes cobalt.

[0010] Optionally, the material of the resistance layer includes titanium nitride.

[0011] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first conductive structure and a device structure, the substrate further comprising a first dielectric layer located between the first conductive structure and the device structure, a second dielectric layer located on the first dielectric layer, and an etch stop layer located between the first dielectric layer and the second dielectric layer, the second dielectric layer having a resistor layer therein; forming a first opening and a second opening in the second dielectric layer, the bottom of the first opening exposing the etch stop layer on the first conductive structure, and the bottom of the second opening exposing the resistor layer; using a selective film forming process to form an intermediate conductive film on the surface of the exposed resistor layer; after forming the intermediate conductive film, etching the exposed etch stop layer until the surface of the first conductive structure is exposed; after etching the exposed etch stop layer, forming a second conductive structure in the first opening; after etching the exposed etch stop layer, forming a third conductive structure in the second opening.

[0012] Optionally, the material of the intermediate conductive film includes fluorine-free tungsten.

[0013] Optionally, the material of the resistance layer includes titanium nitride.

[0014] Optionally, the selective film forming process for forming the fluorine-free tungsten includes a selective atomic layer deposition process.

[0015] Optionally, the reaction gas used in the selective atomic layer deposition process includes tungsten pentachloride.

[0016] Optionally, the parameters of the selective atomic layer deposition process also include: the reaction gas used also includes hydrogen; the reaction temperature is 350 degrees Celsius to 450 degrees Celsius.

[0017] Optionally, a third conductive structure is formed while the second conductive structure is formed, wherein the materials of the second conductive structure and the third conductive structure include fluorine-containing tungsten.

[0018] Optionally, the process of forming the fluorine-containing tungsten includes a selective metal deposition process.

[0019] Optionally, the reaction gas used in the selective metal deposition process includes tungsten hexafluoride.

[0020] Optionally, the thickness of the intermediate conductive film is greater than 2 nanometers, and the thickness of the intermediate conductive film is smaller than the depth of the second opening.

[0021] Optionally, the method of etching the exposed etch stop layer includes: after forming the intermediate conductive film, etching back the exposed etch stop layer until the surface of the first conductive structure is exposed.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0023] In the formation process of the semiconductor structure provided by the technical solution of the present invention, after forming the first opening and the second opening, the second conductive structure and the third conductive structure are formed. Therefore, not only can the patterns of the first opening and the second opening be transferred through a mask layer, but also the number of mask layers and the number of etching steps performed on the second dielectric layer are reduced. Moreover, the material of the second conductive structure and the material of the third conductive structure can be flattened in a flattening step to form the second conductive structure and the third conductive structure. Thus, the manufacturing process of the semiconductor structure is simplified and the difficulty of the manufacturing process of the semiconductor structure is reduced. On this basis, since there is an etching stop layer between the first dielectric layer and the second dielectric layer, and before etching the exposed etching stop layer, a selective film forming process is used to form an intermediate conductive film on the surface of the exposed resistor layer, therefore, on the one hand, it is realized that the material of the intermediate conductive film is selectively formed on the surface of the resistor layer by using a selective film forming process, thereby, the formation of the intermediate conductive film is realized with simple process steps. On the other hand, the intermediate conductive film can protect the resistance layer in the process of forming the second conductive structure, reduce the loss of the resistance layer in the process of forming the second conductive structure, and enable the resistance layer to form a good electrical connection with the third conductive structure through the intermediate conductive film, so that the performance and reliability of the semiconductor structure are good. In summary, the method for forming the semiconductor structure can reduce the difficulty of the manufacturing process of the semiconductor structure while improving the performance and reliability of the semiconductor structure.

[0024] Furthermore, since the material of the intermediate conductive film includes fluorine-free tungsten, the intermediate conductive film and the first conductive structure are both metal materials. Therefore, the second conductive structure and the third conductive structure can be formed simultaneously by the same selective metal deposition process, further simplifying the formation process of the semiconductor structure.

[0025] Furthermore, since the reaction gas used in the selective atomic layer deposition process includes tungsten pentachloride, the selective atomic layer deposition process has high selectivity for materials and is very easy to grow on the surfaces of metals such as titanium nitride and fluorine-containing tungsten, aluminum, etc. Therefore, when the material of the resistor layer includes the above materials, the selective atomic layer deposition process can be used to highly selectively form the material of the intermediate conductive film on the surface of the resistor layer, thereby forming the intermediate conductive film with fewer steps, a larger process window and easy implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 3 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure;

[0027] Figures 4 to 9 It is a cross-sectional structural schematic diagram of a semiconductor structure forming process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] As described in the background art, it is difficult for existing semiconductor structures to reduce the difficulty of the manufacturing process of the semiconductor structure while taking into account the performance and reliability of the semiconductor structure. The following is a detailed description with reference to the accompanying drawings.

[0029] Figures 1 to 3 The invention is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure.

[0030] Please refer to Figure 1 , providing a substrate (not shown), the substrate comprising a dielectric layer 100, wherein the dielectric layer 100 has a first conductive layer 110 and a resistive layer 120 respectively.

[0031] The material of the first conductive layer 110 is cobalt, and the material of the resistance layer 120 is titanium nitride.

[0032] Please continue to refer to Figure 1 , a first opening 131 and a second opening 132 are formed in the dielectric layer 100 , wherein the bottom of the first opening 131 exposes the top surface of the first conductive layer 110 , and the bottom of the second opening 132 exposes the top surface of the resistor layer 120 .

[0033] Please refer to Figure 2 A first plug 140 is formed in the first opening 131 by a selective tungsten deposition process, and the first plug 140 is in contact with the top surface of the first conductive layer 110 .

[0034] The material of the first plug 140 includes tungsten. Tungsten has low resistance and can effectively reduce the parasitic resistance of the semiconductor structure and improve the performance of the semiconductor structure.

[0035] Please refer to Figure 3 , a second plug 150 is formed in the second opening 132 .

[0036] As the process nodes are further reduced, the critical dimensions of the first conductive layer 110 and the resistance layer 120 are reduced and the device density is increased, which makes the critical dimensions of the first opening 131 and the second opening 132 reduced and the spacing between the first opening 131 and the second opening 132 reduced, resulting in a complex manufacturing process for forming the first opening 131 and the second opening 132 respectively with different mask layers, a small process window, and high process difficulty.

[0037] In the above method, in order to simplify the manufacturing process of the semiconductor structure, the patterns of multiple photolithography layers are transferred to the same mask layer, and the dielectric layer 100 is etched using the same mask layer as a mask, thereby simultaneously forming the first opening 131 and the second opening 132. Thus, on the one hand, the number of mask layers and the number of etching steps performed on the dielectric layer 100 are reduced. On the other hand, after the material of the first plug 140 and the material of the second plug 150 are filled, the material of the first plug 140 and the material of the second plug 150 can be planarized in one planarization step, so that the planarization process has fewer steps and is simpler.

[0038] However, since the first opening 131 and the second opening 132 are formed at the same time, the surface of the resistor layer 120 is exposed during the process of forming the first plug 140. Therefore, the selective tungsten deposition process damages the resistor layer 120. On the one hand, the performance of the semiconductor structure is poor. On the other hand, it causes poor contact between the resistor layer 120 and the second plug 150, which increases the risk of abnormal device connection in the semiconductor structure and causes poor reliability of the semiconductor structure. Specifically, when the top surface of the first conductive layer 110 is pretreated, the hydrogen and oxygen used in the pretreatment process will react with the material of the resistor layer 120, causing a portion of the material of the resistor layer 120 to be converted from titanium nitride to rich titanium (rich Ti). As a result, the fluorine-containing reaction gas used in the selective metal deposition process is easy to etch and wear out the resistor layer 120, causing the second opening 132 (such as Figure 2 Area A), and both sides directly below the second opening (as shown Figure 2 The resistance layer 120 (shown in region B) is worn out, resulting in poor contact between the second plug 150 and the resistance layer 120 (as shown in region B). Figure 3 As shown in area C in the middle, the performance and reliability of the semiconductor structure are poor.

[0039] In summary, it is difficult to reduce the difficulty of the manufacturing process of the semiconductor structure while taking into account the performance and reliability of the semiconductor structure.

[0040] In order to solve the technical problem, the embodiment of the present invention provides a semiconductor structure and a method for forming the same. Due to the use of a selective film forming process, an intermediate conductive film is formed on the surface of the exposed resistance layer; after the intermediate conductive film is formed, the exposed etch stop layer is etched until the surface of the first conductive structure is exposed; after the exposed etch stop layer is etched, a second conductive structure is formed in the first opening, and a third conductive structure is formed in the second opening. Thus, the performance and reliability of the semiconductor structure can be improved while reducing the difficulty of the manufacturing process of the semiconductor structure.

[0041] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figures 4 to 9 It is a cross-sectional structural schematic diagram of a semiconductor structure forming process according to an embodiment of the present invention.

[0043] Please refer to Figure 4 , providing a substrate 200, the substrate 200 includes: a first conductive structure 240 and a device structure (not shown), a first dielectric layer 210 located between the first conductive structure 240 and the device structure, a second dielectric layer 220 located on the first dielectric layer 210, and an etch stop layer 230 located between the first dielectric layer 210 and the second dielectric layer 220, wherein the second dielectric layer 220 has a resistor layer 250.

[0044] The device structure includes one or both of a PMOS transistor and an NMOS transistor.

[0045] The material of the first dielectric layer 210 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxynitride.

[0046] In this embodiment, the material of the first dielectric layer 210 includes silicon oxide.

[0047] The material of the second dielectric layer 220 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbide nitride.

[0048] In this embodiment, the material of the second dielectric layer 220 includes silicon oxide.

[0049] The function of the etch stop layer 230 is, on the one hand, to protect the first dielectric layer 210 and the first conductive structure 240 during the process of forming the resistance layer 250, thereby reducing the damage to the first dielectric layer 210 and the first conductive structure 240 caused by the process of forming the resistance layer 250. On the other hand, as an etch stop layer when the first opening is subsequently formed, the risk of over-etching the first conductive structure 240 is reduced.

[0050] Moreover, the etch stop layer 230 can also protect the first conductive structure in the subsequent process of forming the intermediate conductive film, thereby reducing the risk of damage to the first conductive structure caused by the process of forming the intermediate conductive film, thereby improving the performance of the semiconductor structure.

[0051] The material of the etch stop layer 230 is different from the material of the first dielectric layer 210 , and the material of the etch stop layer 230 is different from the material of the second dielectric layer 220 .

[0052] The material of the etch stop layer 230 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0053] In this embodiment, the material of the etch stop layer 230 includes silicon nitride.

[0054] In this embodiment, the thickness of the etch stop layer 230 is greater than 10 angstroms.

[0055] If the thickness of the etch stop layer 230 is too small, it is easy to be worn away to expose the first conductive structure 240 during the subsequent etching process of forming the first opening, causing damage to the first conductive structure 240. Therefore, the etch stop layer 230 has a suitable thickness, that is, the thickness of the etch stop layer 230 is selected to be above 10 angstroms, which can further reduce the risk of damaging the first conductive structure 240 during the etching process of forming the first opening, thereby improving the performance and reliability of the semiconductor structure.

[0056] In this embodiment, the first conductive structure 240 and the device structure are electrically interconnected.

[0057] In this embodiment, the material of the first conductive structure 240 includes cobalt.

[0058] The resistance layer 250 is located on the surface of the etch stop layer 230 .

[0059] In this embodiment, the material of the resistance layer 250 includes titanium nitride.

[0060] The projection of the first conductive structure 240 on the surface of the substrate 200 and the projection of the resistance layer 250 on the surface of the substrate do not overlap.

[0061] In this embodiment, the method for forming the first conductive structure 240 and the etch stop layer 230 includes: forming a first conductive opening (not shown) in the first dielectric layer 210; forming a first conductive film in the first conductive opening and on the surface of the first dielectric layer; planarizing the first conductive film until the surface of the first dielectric layer 210 is exposed to form the first conductive structure 240; and forming the etch stop layer 230 on the surface of the first dielectric layer 210 and the surface of the first conductive structure 240.

[0062] The process of forming the first conductive film is at least one of a metal electroplating process, a chemical vapor deposition process, an atomic layer deposition process, and a selective metal growth process.

[0063] In this embodiment, the method for forming the resistance layer 250 and the second dielectric layer 220 includes: forming a device material layer (not shown) on the surface of the etch stop layer 230; patterning the device material layer to form the resistance layer 250; and forming the second dielectric layer 220 on the surface of the etch stop layer 230 and the surface of the resistance layer 250.

[0064] Please refer to Figure 5 A first opening 261 and a second opening 262 are formed in the second dielectric layer 220 , wherein the bottom of the first opening 261 exposes the etching stop layer 230 on the first conductive structure 240 , and the bottom of the second opening 262 exposes the resistance layer 250 .

[0065] The second opening 262 provides space for subsequently forming an intermediate conductive film and a third conductive structure.

[0066] The method for forming the first opening 261 and the second opening 262 includes: forming a mask layer 263 on the surface of the second dielectric layer 220; forming a first opening photolithography layer (not shown) on the surface of the mask layer 263, wherein the first opening photolithography layer exposes at least a portion of the surface of the mask layer 263 on the first conductive structure 240; etching the mask layer 263 using the first opening photolithography layer as a mask until the surface of the second dielectric layer 220 is exposed, thereby forming a first mask opening 264 in the mask layer 263; and forming a second opening photolithography layer (not shown) on the surface of the mask layer 263. As shown in the figure, the second opening photolithography layer exposes at least part of the surface of the mask layer 263 on the resistor layer 250; the mask layer 263 is etched using the second opening photolithography layer as a mask until the surface of the second dielectric layer 220 is exposed, and a second mask opening 265 is formed in the mask layer 263; after the first mask opening 264 and the second mask opening 265 are formed, the second dielectric layer 220 is etched using the mask layer 263 as a mask until the surface of the etch stop layer 230 and the surface of the resistor layer 250 are exposed, so as to form a first opening 261 and a second opening 262.

[0067] The process of etching the second dielectric layer 220 includes: a dry etching process and a wet etching process, or a combination of the two.

[0068] In this embodiment, the second dielectric layer 220 is etched using a dry etching process, which is beneficial to improving the morphology of the formed first opening 261 and the second opening 262 , thereby improving the performance of the formed semiconductor structure.

[0069] It should be understood that, according to actual process step sequence requirements, the first mask opening 264 may be formed before the second mask opening 265 , or the first mask opening 264 may be formed before the second mask opening 265 .

[0070] In other embodiments, the method for forming the first opening and the second opening includes: forming a mask layer on the surface of the second dielectric layer; forming an opening photolithography layer on the surface of the mask layer, wherein the opening photolithography layer exposes at least a portion of the mask layer surface on the first conductive structure and the resistor layer; using the opening photolithography layer as a mask, etching the mask layer until the surface of the second dielectric layer is exposed, and forming a first mask opening and a second mask opening in the mask layer; after forming the first mask opening and the second mask opening, using the mask layer as a mask, etching the second dielectric layer until the etching stop layer and the resistor layer surface are exposed.

[0071] In this embodiment, after the first opening 261 and the second opening 262 are formed, the mask layer 263 is removed.

[0072] Please refer to Figure 6 , a selective film forming process is used to form an intermediate conductive film 270 on the exposed surface of the resistance layer 250 .

[0073] By adopting the selective film forming process, the intermediate conductive film 270 can be formed by relatively simple and convenient process steps.

[0074] The function of the intermediate conductive film 270 is to protect the resistance layer 250 during the subsequent etching of the exposed etch stop layer 230 and the process of forming the second conductive structure and the third conductive structure.

[0075] Since there is an etch stop layer 230 between the first dielectric layer 210 and the second dielectric layer 220, and before the exposed etch stop layer 230 is subsequently etched, the intermediate conductive film 270 is formed on the exposed surface of the resistance layer 250. Therefore, in the process of forming the intermediate conductive film 270, the first conductive structure 240 is covered by the etch stop layer 230, so that the material of the intermediate conductive film 270 can be selectively formed on the surface of the resistance layer 250 by a selective film forming process, and further, the formation of the intermediate conductive film 270 is realized by simple process steps.

[0076] In this embodiment, the material of the intermediate conductive film 270 includes fluorine-free tungsten (FFW, Fluorine Free W). Specifically, the material of the intermediate conductive film 270 including fluorine-free tungsten means that the material of the intermediate conductive film 270 includes tungsten, and the material of the intermediate conductive film 270 does not contain fluorine element.

[0077] Since the material of the intermediate conductive film 270 includes fluorine-free tungsten, the intermediate conductive film 270 and the first conductive structure 240 are both metal materials. Therefore, the second conductive structure and the third conductive structure can be formed simultaneously in the subsequent process by the same selective metal deposition process, further simplifying the formation process of the semiconductor structure.

[0078] In this embodiment, the selective film forming process includes a selective atomic layer deposition process. The intermediate conductive film 270 formed by the selective atomic layer deposition process has good compactness, and thus can better protect the resistance layer 250.

[0079] Specifically, the reaction gas used in the selective atomic layer deposition process includes tungsten pentachloride, thereby achieving the formation of the third conductive film 272 material including fluorine-free tungsten.

[0080] Since the reaction gas used in the selective atomic layer deposition process includes tungsten pentachloride, the selective atomic layer deposition process has high selectivity for materials and is very easy to grow on the surfaces of metals such as titanium nitride and fluorine-containing tungsten, aluminum, etc. Therefore, when the material of the resistor layer 250 includes the above-mentioned materials (titanium nitride, etc.), the selective atomic layer deposition process can be used to highly selectively form the material of the intermediate conductive film 270 on the surface of the resistor layer 250. As a result, the formation of the intermediate conductive film 270 has fewer steps, a larger process window, and is easy to implement.

[0081] In this embodiment, the thickness of the intermediate conductive film 270 is greater than 2 nanometers, and the thickness of the intermediate conductive film 270 is smaller than the depth of the second opening 262 .

[0082] On the one hand, by making the thickness of the intermediate conductive film 270 above 2 nanometers, the material continuity of the intermediate conductive film 270 is ensured, which is conducive to the intermediate conductive film 270 completely covering the surface of the resistor layer 250, so as to improve the intermediate conductive film 270's ability to protect the resistor layer 250 when the second conductive structure and the third conductive structure are subsequently formed, and reduce the risk of the resistor layer 250 being damaged by the subsequent process of forming the second conductive structure and the third conductive structure. On the other hand, the selective atomic layer deposition process has a low material deposition rate, and the excessive thickness of the intermediate conductive film 270 not only leads to material waste, but also increases the process time and reduces the process efficiency. Therefore, selecting a suitable thickness range of the intermediate conductive film 270, that is, making the thickness of the intermediate conductive film 270 less than the depth of the second opening 262, can enable the intermediate conductive film 270 to better protect the resistor layer 250 while avoiding material waste and improving process efficiency.

[0083] In this embodiment, the parameters of the selective film forming process also include: the reaction gas used also includes hydrogen; the reaction temperature is 350 degrees Celsius to 450 degrees Celsius.

[0084] In this embodiment, the parameters of the selective atomic layer deposition process also include: the gas used also includes nitrogen.

[0085] Specifically, during the selective atomic layer deposition process, tungsten pentachloride is introduced into the chamber several times, wherein each time the tungsten pentachloride is introduced, the duration of the introduction is 0.1 to 2 seconds. After each introduction of tungsten pentachloride, nitrogen is introduced for purging to discharge the unadsorbed tungsten pentachloride out of the chamber, wherein each time the nitrogen is introduced, the duration of the introduction is 0.5 to 3 seconds. After each removal of the unadsorbed tungsten pentachloride, hydrogen is continuously introduced to react with the adsorbed tungsten pentachloride to form a partially conductive protective film 250 material including fluorine-free tungsten, wherein each time the hydrogen is introduced, the duration of the introduction is 0.5 to 3 seconds.

[0086] By adopting the parameters of the selective film forming process, the thickness of the formed intermediate conductive film 270 can be within the thickness range of the intermediate conductive film 270 , thereby taking into account both the protection effect on the resistance layer 250 and the process efficiency.

[0087] Please refer to Figure 7 After forming the intermediate conductive film 270 , the exposed etch stop layer 230 is etched until the surface of the first conductive structure 240 is exposed.

[0088] Since the exposed etch stop layer 230 is etched after the intermediate conductive film 270 is formed, the intermediate conductive film 270 can protect the resistance layer 250 during the etching of the exposed etch stop layer 230, reducing the risk of damage to the resistance layer 250 caused by the etching process, thereby improving the performance and reliability of the semiconductor structure.

[0089] In this embodiment, the method for etching the exposed etch stop layer 230 includes: after forming the intermediate conductive film 270 , etching back the exposed etch stop layer 230 until the surface of the first conductive structure 240 is exposed.

[0090] Since the material of the intermediate conductive film 270 and the material of the second dielectric layer 220 are different from the material of the etch stop layer 230, during the etching of the exposed etch stop layer 230, the etching process can have a higher etching rate for the etch stop layer 230 while having a lower etching rate for the material of the intermediate conductive film 270 and the material of the second dielectric layer 220. Therefore, the exposed etch stop layer 230 can be etched back.

[0091] Since the exposed etch stop layer 230 can be etched back by etching after the intermediate conductive film 270 is formed, the photolithography layer and mask layer required in the semiconductor manufacturing process are reduced, thereby simplifying the manufacturing process of the semiconductor structure.

[0092] The process of etching the exposed etch stop layer 230 includes: a dry etching process and a wet etching process, or a combination of the two.

[0093] In this embodiment, the exposed etch stop layer 230 is etched using a dry etching process, which is beneficial to improving the morphology of the semiconductor structure, thereby improving the performance of the formed semiconductor structure.

[0094] After etching the exposed etch stop layer 230 , a second conductive structure is formed in the first opening 261 , and a third conductive structure is formed in the second opening 262 .

[0095] Since the second conductive structure and the third conductive structure are formed after the first opening 261 and the second opening 262 are formed, not only the patterns of the first opening 261 and the second opening 262 can be formed through a mask layer ( Figure 5 The mask layer 263 shown in FIG. 2 is used for pattern transfer, thereby reducing the number of mask layers and the number of etching steps performed on the second dielectric layer 220. In addition, the material of the second conductive structure and the material of the third conductive structure can be planarized in one planarization step to form the second conductive structure and the third conductive structure. Thus, the manufacturing process of the semiconductor structure is simplified and the difficulty of the manufacturing process of the semiconductor structure is reduced.

[0096] On this basis, since there is an etch stop layer 230 between the first dielectric layer 220 and the second dielectric layer 230, and before etching the exposed etch stop layer 230, a selective film forming process is used to form an intermediate conductive film 270 on the surface of the exposed resistor layer 250. Therefore, on the one hand, the selective film forming process is used to selectively form the material of the intermediate conductive film 270 on the surface of the resistor layer 250, thereby realizing the formation of the intermediate conductive film 270 with simple process steps. On the other hand, the intermediate conductive film 270 can protect the resistor layer 250 in the process of forming the second conductive structure, reduce the loss of the resistor layer 250 in the process of forming the second conductive structure, and enable the resistor layer 250 to form a good electrical connection with the third conductive structure through the intermediate conductive film 270, so that the performance and reliability of the semiconductor structure are good.

[0097] In summary, the method for forming a semiconductor structure can reduce the difficulty of the manufacturing process of the semiconductor structure while improving the performance and reliability of the semiconductor structure.

[0098] For details on the process of forming the second conductive structure and the third conductive structure, please refer to Figures 8 to 9 .

[0099] Please refer to Figure 8 After etching the exposed etch stop layer 230 , a pretreatment step is performed on the exposed surface of the first conductive structure 240 and the surface of the intermediate conductive film 270 .

[0100] Through the pretreatment step, the natural oxide film, residual pollutants, etc. on the surface of the first conductive structure 240 and the surface of the intermediate conductive film 270 can be removed to improve the performance and reliability of the semiconductor structure.

[0101] Since the pretreatment step is performed after the intermediate conductive film 270 is formed on the surface of the resistor layer 250, the intermediate conductive film 270 can protect the resistor layer 250 in the pretreatment step, avoiding the hydrogen and oxygen used in the pretreatment step from reacting with the material of the resistor layer 250, and avoiding the conversion of a part of the material of the resistor layer 250 from titanium nitride to titanium-rich, thereby improving the performance and reliability of the semiconductor structure. At the same time, it also avoids the risk of etching the titanium-rich material by the reaction gas in the subsequent process of forming the materials of the second conductive structure and the third conductive structure. Therefore, the intermediate conductive film 270 can protect the resistor layer 250 in the process of forming the second conductive structure, reduce the loss of the resistor layer 250 in the process of forming the second conductive structure, and enable the resistor layer 250 to form a good electrical connection with the third conductive structure through the intermediate conductive film 270, thereby the performance and reliability of the semiconductor structure are good.

[0102] Please refer to Fig. 9 After the pretreatment step, a selective metal deposition process is used to deposit a conductive material layer (not shown) in the first opening 261 and the second opening 262, wherein the surface of the conductive material layer is higher than the surface of the second dielectric layer 220; a sacrificial layer (not shown) is formed on the surface of the second dielectric layer 220 and the surface of the conductive material layer, wherein the surface of the sacrificial layer is higher than the surface of the conductive material layer; and the sacrificial layer and the conductive material layer are planarized until the surface of the second dielectric layer 220 is exposed, so as to form a second conductive structure 281 in the first opening 261 and a third conductive structure 282 in the second opening 262.

[0103] Specifically, in this embodiment, the third conductive structure 282 is formed while the second conductive structure 281 is formed, thereby further simplifying the manufacturing process.

[0104] In this embodiment, the material of the second conductive structure 281 includes fluorine-containing tungsten, and the material of the third conductive structure 282 includes fluorine-containing tungsten. Specifically, the material of the second conductive structure 281 and the third conductive structure 282 includes fluorine-containing tungsten means that the material of the second conductive structure 281 and the third conductive structure 282 includes tungsten, and the material of the second conductive structure 281 and the third conductive structure 282 contains fluorine element.

[0105] Specifically, the reaction gas used in the selective metal deposition process includes tungsten hexafluoride, so that the materials of the second conductive structure 281 and the third conductive structure 282 contain fluorine.

[0106] In other embodiments, the process of forming the second conductive structure and the third conductive structure includes: a metal electroplating process or a chemical vapor deposition process.

[0107] In other embodiments, the second conductive structure and the third conductive structure materials include: one or more combinations of copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0108] In this embodiment, the sacrificial layer provides sacrificial material for the planarization process. It should be understood that the sacrificial layer will be removed during the planarization process.

[0109] In this embodiment, the planarization process includes a chemical mechanical polishing process.

[0110] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method. Please continue to refer to 9. The semiconductor structure includes: a substrate 200 (such as Figure 4 As shown in the figure, the substrate 200 includes a first conductive structure 240 and a device structure (not shown), a first dielectric layer 210 located between the first conductive structure 240 and the device structure, a second dielectric layer 220 located on the first dielectric layer 210, and an etch stop layer 230 located between the first dielectric layer 210 and the second dielectric layer 220, wherein the second dielectric layer 220 has a resistor layer 250; a second conductive structure 281 located in the second dielectric layer 220, wherein the second conductive structure 281 penetrates the etch stop layer 230, and the second conductive structure 281 contacts the top surface of the first conductive structure 240; an intermediate conductive film 270 located in the second dielectric layer 220, wherein the intermediate conductive film 270 is also located on the top surface of the resistor layer 250; and a third conductive structure 282 located in the second dielectric layer 220, wherein the third conductive structure 282 is also located on the surface of the intermediate conductive film 270.

[0111] The device structure includes one or both of a PMOS transistor and an NMOS transistor.

[0112] The material of the first dielectric layer 210 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxynitride.

[0113] In this embodiment, the material of the first dielectric layer 210 includes silicon oxide.

[0114] The material of the second dielectric layer 220 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbide nitride.

[0115] In this embodiment, the material of the second dielectric layer 220 includes silicon oxide.

[0116] The material of the etch stop layer 230 is different from the material of the first dielectric layer 210 , and the material of the etch stop layer 230 is different from the material of the second dielectric layer 220 .

[0117] The material of the etch stop layer 230 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0118] In this embodiment, the material of the etch stop layer 230 includes silicon nitride.

[0119] In this embodiment, the thickness of the etch stop layer 230 is greater than 10 angstroms.

[0120] The projection of the first conductive structure 240 on the surface of the substrate 200 and the projection of the resistance layer 250 on the surface of the substrate do not overlap.

[0121] In this embodiment, the first conductive structure 240 and the device structure are electrically interconnected.

[0122] In this embodiment, the material of the first conductive structure 240 includes cobalt.

[0123] The resistance layer 250 is located on the surface of the etch stop layer 230 .

[0124] In this embodiment, the material of the resistance layer 250 includes titanium nitride.

[0125] In this embodiment, the material of the intermediate conductive film 270 includes fluorine-free tungsten.

[0126] In this embodiment, the thickness of the intermediate conductive film 270 is greater than 2 nanometers, and the thickness of the intermediate conductive film 270 is smaller than the second opening 262 (eg, Figure 6 shown) depth.

[0127] In this embodiment, the material of the second conductive structure 281 includes fluorine-containing tungsten, and the material of the third conductive structure 282 includes fluorine-containing tungsten.

[0128] In other embodiments, the second conductive structure and the third conductive structure materials include: one or more combinations of copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride and aluminum.

[0129] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a first conductive structure and a device structure, the substrate further comprising a first dielectric layer located between the first conductive structure and the device structure, a second dielectric layer located on the first dielectric layer, and an etch stop layer located between the first dielectric layer and the second dielectric layer, wherein the second dielectric layer has a resistor layer; A second conductive structure located in the second dielectric layer, the second conductive structure penetrates the etch stop layer, and the second conductive structure contacts the top surface of the first conductive structure; An intermediate conductive film located in the second dielectric layer, the intermediate conductive film also being located on the top surface of the resistance layer; A third conductive structure located in the second dielectric layer, wherein the third conductive structure is also located on the surface of the intermediate conductive film; Among them, the intermediate conductive film is formed before forming the second conductive structure, and is used to protect the resistance layer during the process of forming the second conductive structure; the material of the intermediate conductive film includes fluorine-free tungsten; the material of the resistance layer includes titanium nitride; the selective film forming process for forming the fluorine-free tungsten includes a selective atomic layer deposition process; the reaction gas used in the selective atomic layer deposition process includes tungsten pentachloride.

2. The semiconductor structure according to claim 1, wherein: The thickness of the intermediate conductive film is greater than 2 nanometers.

3. The semiconductor structure according to claim 1, wherein: The material of the second conductive structure includes fluorine-containing tungsten, and the material of the third conductive structure includes fluorine-containing tungsten.

4. The semiconductor structure according to claim 1, wherein: The material of the first conductive structure includes cobalt.

5. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first conductive structure and a device structure, the substrate further comprising: A first dielectric layer between the first conductive structure and the device structure, a second dielectric layer located on the first dielectric layer, and an etch stop layer located between the first dielectric layer and the second dielectric layer, wherein the second dielectric layer has a resistance layer; forming a first opening and a second opening in the second dielectric layer, wherein the bottom of the first opening exposes the etching stop layer on the first conductive structure, and the bottom of the second opening exposes the resistance layer; A selective film forming process is used to form an intermediate conductive film on the surface of the exposed resistor layer; After forming the intermediate conductive film, etching the exposed etch stop layer until the surface of the first conductive structure is exposed; After etching the exposed etch stop layer, forming a second conductive structure in the first opening; After etching the exposed etch stop layer, a third conductive structure is formed in the second opening.

6. The method for forming a semiconductor structure according to claim 5, wherein: The material of the intermediate conductive film includes fluorine-free tungsten.

7. The method for forming a semiconductor structure according to claim 6, wherein: The material of the resistance layer includes titanium nitride.

8. The method for forming a semiconductor structure according to claim 7, wherein: The selective film forming process for forming the fluorine-free tungsten includes a selective atomic layer deposition process.

9. The method for forming a semiconductor structure according to claim 8, wherein: The reaction gas used in the selective atomic layer deposition process includes tungsten pentachloride.

10. The method for forming a semiconductor structure according to claim 9, wherein: The parameters of the selective atomic layer deposition process also include: the reaction gas used also includes hydrogen; the reaction temperature is 350 degrees Celsius to 450 degrees Celsius.

11. The method for forming a semiconductor structure according to claim 6, wherein: While forming the second conductive structure, a third conductive structure is formed, wherein the materials of the second conductive structure and the third conductive structure include fluorine-containing tungsten.

12. The method for forming a semiconductor structure according to claim 11, wherein: The process of forming the fluorine-containing tungsten includes a selective metal deposition process.

13. The method for forming a semiconductor structure according to claim 12, wherein: The reaction gas used in the selective metal deposition process includes tungsten hexafluoride.

14. The method for forming a semiconductor structure according to claim 5, wherein: The thickness of the intermediate conductive film is greater than 2 nanometers, and the thickness of the intermediate conductive film is smaller than the depth of the second opening.

15. The method for forming a semiconductor structure according to claim 5, wherein: The method for etching the exposed etch stop layer comprises: after forming the intermediate conductive film, etching back the exposed etch stop layer until the surface of the first conductive structure is exposed.

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