Display device

Abstract

A display device is provided. The display device according to an embodiment includes a substrate including a plurality of pixel regions, and pixels respectively disposed in the plurality of pixel regions. The pixel includes a first electrode and a second electrode disposed on the substrate and disposed in the same layer, a light emitting element diode disposed on the first electrode and the second electrode, a third electrode electrically connected to the first electrode and one end portion of the light emitting element, a fourth electrode electrically connected to the second electrode and the other end portion of the light emitting element, and an electrode pattern disposed in the same layer as the third electrode and the fourth electrode.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to a display device, and more specifically, to a display device including a light-emitting element. Background Technology

[0002] With increasing interest in information display and growing demand for portable information media, the need for display devices has increased significantly, and their commercialization is underway. Summary of the Invention

[0003] Technical issues

[0004] When a sensing electrode layer is formed on the panel of a display device to form the sensing electrodes of a touch sensor, a separate process is required to form the sensing electrode layer, which increases the manufacturing cost of the display device.

[0005] Various embodiments of this disclosure relate to a display device that forms an electrode pattern disposed on the same layer as the internal lines of each pixel and uses the electrode pattern as the sensing electrode of a touch sensor.

[0006] The effects of this disclosure are not limited to those described above, and those skilled in the art will clearly understand from the appended claims other unmentioned effects.

[0007] Technical solution

[0008] According to aspects of this disclosure, a display device may include: a substrate including a plurality of pixel regions; and a pixel disposed in each of the plurality of pixel regions, wherein the pixel may include: a first electrode and a second electrode disposed on the substrate and disposed on the same layer; a light-emitting element disposed on the first electrode and the second electrode; a third electrode configured to electrically connect a first end of the first electrode and the light-emitting element; a fourth electrode configured to electrically connect a second electrode and a second end of the light-emitting element; and an electrode pattern disposed on the same layer as one of the third electrode and the fourth electrode.

[0009] The electrode pattern can be disposed on the same layer as the third electrode, and the electrode pattern can be electrically insulated from the third electrode.

[0010] The electrode pattern can be disposed on the same layer as the fourth electrode and can be electrically insulated from the fourth electrode, and the electrode pattern can be superimposed on at least a portion of the third electrode.

[0011] The display device may also include an input sensing controller electrically connected to an electrode pattern, the electrode pattern being an input sensing electrode, and the input sensing controller being able to sense input from an external device based on signals provided from the electrode pattern.

[0012] The display device may further include: a first insulating layer configured to cover at least a portion of the first electrode and the second electrode and disposed between the light-emitting element and the substrate; the first insulating layer may include a first opening configured to expose at least a portion of the first electrode and a second opening configured to expose at least a portion of the second electrode; and a third electrode may contact the first electrode through the first opening and a fourth electrode may contact the second electrode through the second opening.

[0013] The display device may further include a second insulating layer configured to cover the third electrode, and the electrode pattern may be disposed on the same layer as the fourth electrode, and the electrode pattern may be disposed on the second insulating layer.

[0014] The display device may further include a second insulating layer configured to cover a third electrode, wherein the electrode pattern may be disposed on the same layer as the third electrode and between the first insulating layer and the second insulating layer.

[0015] The electrode pattern may include a first electrode pattern and a second electrode pattern spaced apart from each other.

[0016] The display device may further include a connection pattern configured to electrically connect the first electrode pattern and the second electrode pattern, and the connection pattern may be disposed on the same layer as one of the third electrode and the fourth electrode, and the connection pattern may be disposed on a different layer from the first electrode pattern and the second electrode pattern.

[0017] The display device may also include partition walls disposed on a substrate along the boundaries of multiple pixel regions, and connecting patterns may be disposed on the partition walls.

[0018] The display device may also include partition walls disposed on a substrate along the boundaries of multiple pixel regions, and a connecting pattern may be disposed between the first insulating layer and the partition walls.

[0019] The display device may further include a second insulating layer configured to cover a third electrode, and the second insulating layer may include a first contact and a second contact formed to overlap with a connection pattern, and the electrode pattern may be connected to the connection pattern through the first contact and the second contact.

[0020] The display device may further include a second insulating layer configured to cover a third electrode and a fourth electrode, the third electrode and the fourth electrode may be disposed on the same layer, and the electrode pattern may be disposed between the first insulating layer and the second insulating layer.

[0021] The display device may also include a partition wall disposed on a substrate along the boundaries of multiple pixel regions, and an electrode pattern may be disposed between the partition wall and a second insulating layer.

[0022] Electrode patterns can be set as window shapes in a plan view.

[0023] According to another aspect of this disclosure, the display device may include: a substrate including a plurality of pixel regions; a pixel disposed in each of the plurality of pixel regions; and an input sensing controller, wherein the pixel may include: a first electrode and a second electrode disposed on the substrate and disposed in the same layer; a light-emitting element electrically connected to the first electrode and the second electrode; and a sensing electrode disposed in the same layer as the first electrode and the second electrode, and the input sensing controller may be electrically connected to the sensing electrode to sense input from an external device based on a signal provided from the sensing electrode.

[0024] The display device may further include: a first insulating layer configured to cover at least a portion of the first electrode and the second electrode and disposed between the light-emitting element and the substrate; a third electrode disposed on the first electrode and configured to contact a first end of the light-emitting element; and a fourth electrode disposed on the second electrode and configured to contact a second end of the light-emitting element. The first insulating layer may include a first opening configured to expose at least a portion of the first electrode and a second opening configured to expose at least a portion of the second electrode, and the third electrode may contact the first electrode through the first opening, and the fourth electrode may contact the second electrode through the second opening.

[0025] The sensing electrode may include a metal with a first reflectivity, and the sensing electrode may reflect light incident from the outside and emit light back to the outside.

[0026] The display device may also include a dummy electrode disposed on the same layer as the first electrode and the second electrode, and the dummy electrode may be electrically separated from the sensing electrode.

[0027] According to another aspect of this disclosure, the display device may include: a substrate including a plurality of pixel regions; a pixel disposed in each of the plurality of pixel regions; and an input sensing controller, wherein the pixel may include: a first electrode and a second electrode disposed on the substrate and disposed on the same layer; a light-emitting element disposed on the first electrode and the second electrode; a third electrode configured to electrically connect a first end of the first electrode and the light-emitting element; a fourth electrode configured to electrically connect a second electrode and a second end of the light-emitting element; a shielding electrode disposed between the first electrode and the third electrode; and a sensing electrode disposed on the same layer as the shielding electrode, and the input sensing controller may be electrically connected to the sensing electrode to sense input from an external device based on a signal provided from the sensing electrode.

[0028] The shielding electrode and the sensing electrode can be configured to be spaced apart from each other and electrically isolated from each other.

[0029] The display device may also include an insulating pattern disposed between the shielding electrode and the third electrode, wherein the shielding electrode can be electrically separated from the third electrode by the insulating pattern, and the shielding electrode and the sensing electrode can be integrally formed.

[0030] Details of various embodiments are included in the detailed description and accompanying drawings.

[0031] Beneficial effects

[0032] The display device according to embodiments of the present disclosure may include an electrode pattern that serves as a sensing electrode for a touch sensor on the same layer as any of the internal lines included in the individual pixels.

[0033] Therefore, in the display device according to the present disclosure, a separate process for forming the sensing electrodes of the touch sensor can be omitted, which simplifies the manufacturing process of the display device and reduces its manufacturing cost.

[0034] Furthermore, since the display device according to this disclosure does not include a separate sensing electrode layer for forming the sensing electrodes of the touch sensor, a thin display device can be realized.

[0035] The effects of this disclosure are not limited to the foregoing, and various other effects are anticipated herein. Attached Figure Description

[0036] Figure 1a and Figure 1b This is a perspective view showing a light-emitting element according to an embodiment of the present disclosure.

[0037] Figure 2 This is a schematic plan view of a display device according to an embodiment of the present disclosure.

[0038] Figures 3a to 3c Each of these is a circuit diagram illustrating a pixel according to an embodiment of the present disclosure.

[0039] Figure 4 This is a circuit diagram illustrating a pixel according to another embodiment of the present disclosure.

[0040] Figure 5 and Figure 6 It is a plan view of pixels according to an embodiment of the present disclosure.

[0041] Figure 7 This is a cross-sectional view of pixels according to an embodiment of the present disclosure, and is along... Figure 5 A sectional view taken by line A-A'.

[0042] Figure 8 and Figure 9 This is a diagram used to explain the touch sensing function of the display device according to the present disclosure.

[0043] Figure 10 This is a cross-sectional view showing pixels according to another embodiment of the present disclosure.

[0044] Figures 11a to 11c It is according to various embodiments corresponding to Figure 10 A cross-sectional view of the pixels of line B-B'.

[0045] Figure 12a and Figure 12b This is a plan view showing pixels according to another embodiment of the present disclosure.

[0046] Figure 13 This is a plan view showing pixels according to yet another embodiment of the present disclosure.

[0047] Figure 14 This is a plan view showing pixels according to yet another embodiment of the present disclosure.

[0048] Figures 15a to 15c It is according to various embodiments corresponding to Figure 14 A cross-sectional view of the pixels along line C-C'.

[0049] Figure 16 This is a plan view showing pixels according to yet another embodiment of the present disclosure.

[0050] Figure 17a and Figure 17b It is according to various embodiments corresponding to Figure 16 A cross-sectional view of the pixels of line D-D'.

[0051] Figure 18 This is a plan view showing pixels according to yet another embodiment of the present disclosure.

[0052] Figure 19a and Figure 19b It is according to various embodiments corresponding to Figure 18 A cross-sectional view of the pixels along line E-E'.

[0053] Figure 20 This is a plan view showing pixels according to yet another embodiment of the present disclosure.

[0054] Figure 21a and Figure 21b It is according to various embodiments corresponding to Figure 20 A cross-sectional view of the pixels of line F-F'.

[0055] Figure 22 This is a plan view showing pixels according to yet another embodiment of the present disclosure.

[0056] Figure 23 This is a plan view showing pixels according to yet another embodiment of the present disclosure.

[0057] Figure 24a and Figure 24b It is according to various embodiments corresponding to Figure 23 A cross-sectional view of the pixels of line G-G'.

[0058] Figure 25 This is a plan view showing pixels according to yet another embodiment.

[0059] Figure 26a and Figure 26b It is according to various embodiments corresponding to Figure 25 A cross-sectional view of the pixels along line H-H'. Detailed Implementation

[0060] The advantages and features of this disclosure, as well as the methods for implementing this disclosure, will become clear from the embodiments described in detail below with reference to the accompanying drawings. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art, and the invention will be defined only by the appended claims.

[0061] It will be understood that when an element or layer is referred to as being "on" another element or layer, that element or layer may be directly on, connected to, or combined with the other element or layer, or there may be one or more intervening elements or layers. The same reference numerals always denote the same element.

[0062] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure. In this disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0063] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals are used to designate the same or similar elements.

[0064] Figure 1a and Figure 1b This is a perspective view showing a light-emitting element according to an embodiment of the present disclosure.

[0065] Reference Figure 1a and Figure 1bAccording to embodiments of the present disclosure, a light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element LD may be implemented as a stack formed by continuously stacking the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0066] In embodiments of this disclosure, the light-emitting element (LD) may be arranged in the form of a rod extending in one direction. If the direction along which the light-emitting element (LD) extends is defined as the longitudinal direction, the light-emitting element (LD) may have a first end and a second end in the longitudinal direction.

[0067] In embodiments of this disclosure, one of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed on the first end of the light-emitting element, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed on the second end of the light-emitting element.

[0068] In embodiments of this disclosure, the light-emitting element (LD) may be arranged in the form of a rod. Here, the term "rod-shaped" includes rod-like and strip-like shapes such as cylindrical and prismatic shapes extending in the longitudinal direction (i.e., having an aspect ratio greater than 1). For example, the length of the light-emitting element LD may be greater than its diameter. However, this disclosure is not limited thereto. For example, the light-emitting element LD may be a core-shell structured light-emitting element.

[0069] Light-emitting diodes (LDs) can be manufactured with diameters and / or lengths corresponding to, for example, micrometer or nanometer scale dimensions. For example, the diameter of an LD can be equal to or less than 600 nm, and the length can be equal to or less than 4 μm. However, the size of the LD is not limited to these dimensions. For example, the size of the LD can be changed to meet the requirements of display devices using LDs.

[0070] The first semiconductor layer 11 may include, for example, at least one N-type semiconductor layer. For instance, the first semiconductor layer 11 may include a semiconductor layer comprising any one of the semiconductor materials InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a first dopant such as Si, Ge, or Sn. The materials forming the first semiconductor layer 11 are not limited to these, and the first semiconductor layer 11 may be formed from a variety of other materials.

[0071] The active layer 12 can be formed on the first semiconductor layer 11 and has a single quantum well structure or a multiple quantum well structure. The active layer 12 can emit light with a wavelength of 400 nm to 900 nm. In embodiments of this disclosure, a doped cladding layer (not shown) can be formed on and / or under the active layer 12. For example, the cladding layer can be formed of an AlGaN layer or an InAlGaN layer. In embodiments, materials such as AlGaN or AlInGaN can also be used to form the active layer 12, and various other materials can be used to form the active layer 12.

[0072] If an electric field with a predetermined voltage or higher is applied to the opposite ends of the light-emitting element LD, the light-emitting element LD emits light through the recombination of electron-hole pairs in the active layer 12. Because the light emission of the light-emitting element LD is controlled based on the aforementioned principle, the light-emitting element LD can be used as a light source for various light-emitting devices and as a pixel for display devices.

[0073] The second semiconductor layer 13 may be disposed on the active layer 12 and may include a semiconductor layer of a different type than the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one P-type semiconductor layer. Alternatively, the second semiconductor layer 13 may include a semiconductor layer comprising any one of the semiconductor materials InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second dopant such as Mg. The materials forming the second semiconductor layer 13 are not limited to these, and the second semiconductor layer 13 may be formed from a variety of other materials.

[0074] In the embodiments of this disclosure, the light-emitting element LD may include not only a first semiconductor layer 11, an active layer 12 and a second semiconductor layer 13, but also a fluorescent layer, another active layer, another semiconductor layer and / or an electrode layer disposed on and / or under each layer.

[0075] In embodiments, the light-emitting element LD may further include at least one electrode layer disposed on one side (e.g., the upper surface) of the second semiconductor layer 13 or on one side (e.g., the lower surface) of the first semiconductor layer 11. For example, as Figure 1b As shown, the light-emitting element LD may further include an electrode layer 15 disposed on one side of the second semiconductor layer 13. The electrode layer 15 may be an ohmic electrode, but is not limited thereto. Furthermore, the electrode layer 15 may include a metal or a metal oxide. For example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), ITO, and their oxides or alloys may be used alone or in combination with each other. However, this disclosure is not limited thereto. In embodiments, the electrode layer 15 may be substantially transparent or translucent. Therefore, light generated from the light-emitting element LD can be emitted to the outside of the light-emitting element LD after passing through the electrode layer 15.

[0076] The light-emitting element LD may also include an insulating film 14. However, in embodiments of this disclosure, the insulating film 14 may be omitted, or may be configured to cover only some of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. For example, the insulating film 14 may be disposed on a portion of the light-emitting element LD except for its opposite ends, such that the opposite ends of the light-emitting element LD are exposed.

[0077] To explain, Figure 1a and Figure 1b The insulating film 14, a portion of which has been removed, is shown. The entire side surface of the light-emitting element LD can be surrounded by the insulating film 14.

[0078] In embodiments of this disclosure, the insulating film 14 may comprise a transparent insulating material. For example, the insulating film 14 may comprise at least one or more insulating materials selected from SiO2, Si3N4, Al2O3, and TiO2, but is not limited thereto. In other words, various materials with insulating properties may be used.

[0079] The insulating film 14 prevents the active layer 12 from short-circuiting due to contact with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. The insulating film 14 minimizes surface defects on the light-emitting element (LD), thereby improving the lifespan and efficiency of the LD. In the case of multiple LDs arranged in close contact with each other, the insulating film 14 prevents unwanted short circuits between the LDs.

[0080] The type, structure, shape, etc. of the light-emitting element LD according to the embodiments of this disclosure can be changed in various ways.

[0081] Figure 2 This is a schematic plan view of a display device according to an embodiment of the present disclosure.

[0082] Reference Figures 1a to 2 The display device 1000 may include a substrate SUB and a plurality of pixels PXL disposed on the substrate SUB. Specifically, the display device 1000 may include a display area DA configured to display an image and a non-display area NDA formed in an area other than the display area DA.

[0083] The display area DA can be the area in which the pixel PXL is disposed. The non-display area NDA can be the area in which a driver for driving the pixel PXL is disposed and various lines (not shown) for binding the pixel PXL to the driver are disposed.

[0084] The display area DA can have various shapes. For example, the display area DA can be set in various forms, such as a closed polygon with sides formed by straight lines, a circle or ellipse with sides formed by curves, and a semicircle or semi-ellipse with sides formed by both straight lines and curves.

[0085] When the display area DA comprises multiple regions, each region can also be set in various shapes (such as closed polygons with straight sides, and semicircles or semi-ellipses with sides formed by curves). In addition, the surface areas of the multiple regions can be the same or different from each other.

[0086] In embodiments of this disclosure, an example will be described where the display area DA is configured with a single region having a rectangular shape including straight sides.

[0087] The non-display area NDA can be disposed on at least one side of the display area DA. In embodiments of this disclosure, the non-display area NDA can surround the display area DA.

[0088] Pixel PXL can be disposed in display area DA on substrate SUB. Each of pixels PXL may include at least one light-emitting element LD configured to be driven in response to a corresponding scan signal and a corresponding data signal.

[0089] Each pixel PXL may include a light-emitting element that emits white light and / or colored light. Each pixel PXL may emit light of any color, including red, green, and blue, and is not limited thereto. For example, each pixel PXL may emit light of any color, including cyan, magenta, yellow, and white.

[0090] Specifically, a pixel PXL may include a first pixel PXL1 configured to emit light of a first color, a second pixel PXL2 configured to emit light of a second color different from the first color, and a third pixel PXL3 configured to emit light of a third color different from the first and second colors. At least one first pixel PXL1, at least one second pixel PXL2, and at least one third pixel PXL3 arranged adjacent to each other can form a pixel unit PXU capable of emitting light of various colors.

[0091] In one embodiment, the first pixel PXL1 can be a red pixel emitting red light, the second pixel PXL2 can be a green pixel emitting green light, and the third pixel PXL3 can be a blue pixel emitting blue light. In another embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can each include a light-emitting element associated with a first color, a light-emitting element associated with a second color, and a light-emitting element associated with a third color as light sources, allowing the pixels to emit light of the first color, the second color, and the third color, respectively. In another embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can each include a light-emitting element of the same color, and light conversion layers of different colors can be disposed on the respective light-emitting elements, allowing the pixels to emit light of the first color, the second color, and the third color.

[0092] However, there are no particular restrictions on the color, type, and / or number of pixels PXL that form each pixel unit PXU.

[0093] Multiple pixels PXL can be arranged on a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The arrangement of pixels PXL is not limited to a specific arrangement. In other words, pixels can be arranged in various forms.

[0094] The driver can provide signals to pixel PXL via a line assembly (not shown), thus controlling the operation of pixel PXL. Figure 2 For the sake of explanation, the line component has been omitted.

[0095] The driver may include a scan driver SDV configured to provide scan signals to pixel PXL via scan lines, a transmit driver EDV configured to provide transmit control signals to pixel PXL via transmit control lines, a data driver DDV configured to provide data signals to pixel PXL via data lines, and a timing controller (not shown). The timing controller can control the scan driver SDV, the transmit driver EDV, and the data driver DDV. According to an embodiment, the display device 1000 may not include the transmit driver EDV.

[0096] In an embodiment, each of the pixels PXL may be formed by an active pixel. However, the type, structure, and / or driving scheme of the pixels PXL that can be applied to this disclosure are not particularly limited.

[0097] Figures 3a to 3c These are circuit diagrams illustrating pixels according to embodiments of the present disclosure. Specifically, Figures 3a to 3c An example of pixels forming an active emission display panel is shown.

[0098] Reference Figure 3aEach of the pixels PXL may include at least one light-emitting element LD and a pixel driving circuit DC, the pixel driving circuit DC being connected to the light-emitting element to drive the light-emitting element LD.

[0099] The first electrode (e.g., the anode) of the light-emitting element LD can be connected to a first driving power supply VDD via a pixel driving circuit DC. The second electrode (e.g., the cathode) of the light-emitting element LD can be connected to a second driving power supply VSS.

[0100] The first driving power supply VDD and the second driving power supply VSS can have different potentials. For example, the second driving power supply VSS can have a potential that is equal to or greater than the threshold voltage of the light-emitting element LD, which is lower than the potential of the first driving power supply VDD.

[0101] The light-emitting element (LD) can emit light with a brightness corresponding to the driving current controlled by the DC of the pixel driving circuit.

[0102] although Figure 3a An embodiment is shown in which each of the pixels PXL includes only one light-emitting element LD, but this disclosure is not limited thereto. For example, each of the pixels PXL may include multiple light-emitting elements connected in parallel and / or in series with each other.

[0103] In embodiments of this disclosure, the pixel driving circuit DC may include a first transistor M1, a second transistor M2, and a storage capacitor Cst.

[0104] The first transistor (switching transistor) M1 may include a first electrode connected to the data line DL and a second electrode connected to the first node N1. Here, the first electrode and the second electrode of the first transistor M1 may be different electrodes. For example, if the first electrode is the source electrode, then the second electrode may be the drain electrode. The gate electrode of the first transistor M1 may be connected to the scan line SL.

[0105] When a scan signal with a voltage (e.g., gate on-voltage) capable of turning on the first transistor M1 is supplied from the scan line SL, the first transistor M1 can be turned on to electrically connect the data line DL to the first node N1. Here, the data signal corresponding to the frame is supplied to the data line DL, thereby the data signal can be transmitted to the first node N1. The data signal transmitted to the first node N1 can be stored in the storage capacitor Cst.

[0106] The second transistor (driving transistor) M2 may include a first electrode connected to the first driving power supply VDD and a second electrode electrically connected to the first electrode (e.g., the anode) of the light-emitting element LD. The gate electrode of the second transistor M2 may be connected to the first node N1. The second transistor M2 may control the driving current to be supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0107] The storage capacitor Cst may include a first electrode connected to the first drive power supply VDD and a second electrode connected to the first node N1. The storage capacitor Cst may be charged with a voltage corresponding to the data signal supplied to the first node N1, and the charged voltage may be maintained until the data signal of the next frame is supplied.

[0108] To explain, Figure 3a A pixel driving circuit DC with a relatively simple structure is shown. The driving circuit includes a first transistor M1 configured to transmit a data signal to a pixel PXL, a storage capacitor Cst configured to store the data signal, and a second transistor M2 configured to supply a driving current corresponding to the data signal to a light-emitting element LD.

[0109] However, this disclosure is not limited thereto, and the structure of the pixel driving circuit DC can be changed in various ways. For example, the pixel driving circuit DC may also include at least one transistor (such as a transistor configured to compensate the threshold voltage of the second transistor M2, a transistor configured to initialize the first node N1, and / or a transistor configured to control the emission time of the light-emitting element LD), or other circuit elements (such as a boost capacitor for boosting the voltage of the first node N1).

[0110] Furthermore, despite Figure 3a In the present invention, the transistors included in the pixel driving circuit DC (e.g., the first transistor M1 and the second transistor M2) have been shown as being formed of P-type transistors, but the present disclosure is not limited thereto. In other words, at least one of the first transistor M1 and the second transistor M2 included in the pixel driving circuit DC may be changed to an N-type transistor.

[0111] For example, refer to Figure 3b In the pixel driving circuit DC, each of the first transistor M1 and the second transistor M2 can be formed by an N-type transistor. Aside from the change in the connection positions of some components due to the change in transistor type, Figure 3b The construction and operation of the pixel driving circuit DC shown can be similar to Figure 3a The construction and operation of the pixel driving circuit DC are described. Therefore, a detailed description related to this will be omitted.

[0112] Reference Figure 3c In some embodiments, each of the pixels PXL may also include a third transistor M3 (sensing transistor).

[0113] The gate electrode of the third transistor M3 can be connected to the sensing signal line SSL. The first electrode of the third transistor M3 can be connected to the sensing line SENL, and its second electrode can be connected to the anode of the light-emitting element LD. The third transistor M3 can transmit the voltage value at the anode of the light-emitting element LD to the sensing line SENL in response to a sensing signal supplied to the sensing signal line SSL. The voltage value transmitted through the sensing line SENL can be provided to external circuitry (e.g., a timing controller), and the external circuitry can compensate each pixel PXL based on the provided voltage value.

[0114] Figure 4 This is a circuit diagram illustrating a pixel according to another embodiment of the present disclosure.

[0115] Reference Figure 4 Each of the pixels PXL according to another embodiment of the present disclosure may include a light-emitting element LD, a first transistor to a seventh transistor T1, T2, T3, T4, T5, T6 and T7, and a storage capacitor Cst.

[0116] The first electrode (e.g., the anode) of the light-emitting element LD can be connected to the first transistor T1 via a sixth transistor T6. The second electrode (e.g., the cathode) of the light-emitting element LD can be connected to a second driving power supply VSS. The light-emitting element LD can emit light with a predetermined brightness corresponding to the current supplied from the first transistor T1.

[0117] The first transistor (driving transistor) T1 may include a first electrode connected to the first driving power supply VDD via a fifth transistor T5, and a second electrode connected to the first electrode of the light-emitting element LD via a sixth transistor T6. The first transistor T1 may control the current flowing from the first driving power supply VDD to the second driving power supply VSS via the light-emitting element LD in response to the voltage of the first node N1, which is its gate electrode.

[0118] A second transistor (switching transistor) T2 can be connected between the data line DL and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 can be connected to the scan line SL. When a scan signal with a gate on-state voltage is supplied to the scan line SL, the second transistor T2 can be turned on, allowing the data line DL to be electrically connected to the first electrode of the first transistor T1.

[0119] The third transistor T3 can be connected between the second electrode of the first transistor T1 and the first node N1. Furthermore, the gate electrode of the third transistor T3 can be connected to the scan line SL. When a scan signal with a gate on-state voltage is supplied to the scan line SL, the third transistor T3 can be turned on, allowing the second electrode of the first transistor T1 to be electrically connected to the first node N1.

[0120] The fourth transistor T4 can be connected between the first node N1 and the initialization power supply Vint. Furthermore, the gate electrode of the fourth transistor T4 can be connected to the scan line SL-1 of the previous stage. When a scan signal with a gate on-state voltage is supplied to the scan line SL-1 of the previous stage, the fourth transistor T4 turns on, allowing the voltage of the initialization power supply Vint to be supplied to the first node N1. The initialization power supply Vint can be set to a voltage lower than the data signal voltage.

[0121] The fifth transistor T5 can be connected between the first drive power supply VDD and the first electrode of the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to the emitter control line EL. The fifth transistor T5 can be turned on when an emitter control signal with a gate on-voltage is supplied to the emitter control line EL, and can be turned off under other conditions.

[0122] The sixth transistor T6 can be connected between the second electrode of the first transistor T1 and the first electrode of the light-emitting element LD. The gate electrode of the sixth transistor T6 can be connected to the emitter control line EL. The sixth transistor T6 can be turned on when an emitter control signal with a gate on-state voltage is supplied to the emitter control line EL, and can be turned off under other conditions.

[0123] The seventh transistor T7 can be connected between the initialization power supply Vint and the first electrode (e.g., the anode) of the light-emitting element LD. The gate electrode of the seventh transistor T7 can be connected to the scan line SL+1 of the next stage. When a scan signal with a gate on-state voltage is supplied to the scan line SL+1 of the next stage, the seventh transistor T7 can be turned on, so that the voltage of the initialization power supply Vint can be supplied to the first electrode of the light-emitting element LD.

[0124] Figure 4 The illustration shows the case where the gate electrode of the seventh transistor T7 is connected to the scan line SL+1 of the next stage. However, the spirit of this disclosure is not limited thereto. For example, in another embodiment of this disclosure, the gate electrode of the seventh transistor T7 may be connected to the scan line SL. In this case, when a scan signal of the gate on-state voltage is supplied to the scan line SL, the voltage of the initialization power supply Vint may be supplied to the anode of the light-emitting element LD via the seventh transistor T7.

[0125] The storage capacitor Cst can be connected between the first drive power supply VDD and the first node N1. The storage capacitor Cst can store the voltage corresponding to both the data signal and the threshold voltage of the first transistor T1.

[0126] Despite Figure 4In the present invention, the transistors included in the pixel driving circuit DC (e.g., the first to seventh transistors T1, T2, T3, T4, T5, T6 and T7) have been shown as being formed of P-type transistors, but the invention is not limited thereto. For example, at least one of the first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 may be changed to N-type transistors.

[0127] Figure 5 and Figure 6 It is a plan view of pixels according to an embodiment of the present disclosure. Figure 7 This is a cross-sectional view of pixels according to an embodiment of the present disclosure, and is along... Figure 5 A sectional view taken by line A-A'.

[0128] Although each electrode is simply shown as being formed of a single electrode layer for the purpose of explanation, this disclosure is not limited thereto. In embodiments of this disclosure, the expression "components are formed and / or disposed in the same layer" can mean that the components can be formed by the same process and can be formed by the same material.

[0129] Reference Figure 2 , Figures 5 to 7 The display device 1000 may include a substrate SUB comprising multiple pixel regions PA1, PA2, and PA3, and a pixel PXL disposed on the substrate SUB. The pixel PXL may include a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3. The first pixel PXL1 may be disposed in the first pixel region PA1, the second pixel PXL2 may be disposed in the second pixel region PA2, and the third pixel PXL3 may be disposed in the third pixel region PA3.

[0130] Each pixel PXL may include a first dam BNK1 and a second dam BNK2 disposed on a substrate SUB, a first electrode RFE1 and a second electrode RFE2, a first insulating layer INS1, a light-emitting element LD, a third electrode CTE1 and a fourth electrode CTE2, a second insulating layer INS2 and a third insulating layer INS3. In some embodiments, each pixel PXL may further include an anchoring layer ANCL and a partition wall (not shown) disposed along the boundary of each pixel PXL.

[0131] The substrate SUB can be a rigid substrate or a flexible substrate, and its material or properties are not particularly limited. For example, the substrate SUB can be a rigid substrate made of glass or tempered glass, or a flexible substrate formed from a thin film made of plastic or metal. Furthermore, the substrate SUB can be a transparent substrate, but is not limited to this. For example, the substrate SUB can be a translucent substrate, an opaque substrate, or a reflective substrate.

[0132] The first dam BNK1 and the second dam BNK2 can be disposed on the substrate SUB. A space can be provided between the first dam BNK1 and the second dam BNK2 for disposing of the light-emitting element LD. In an embodiment, the first dam BNK1 and the second dam BNK2 can be disposed on the substrate SUB to space the length of the light-emitting element LD from each other in a first direction DR1. Furthermore, the first dam BNK1 and the second dam BNK2 can extend in a second direction DR2 intersecting the first direction DR1.

[0133] The first dike BNK1 and the second dike BNK2 can be insulating materials including organic or inorganic materials. However, the materials of the first dike BNK1 and the second dike BNK2 are not limited to these.

[0134] Each of the first dike BNK1 and the second dike BNK2 may have a trapezoidal shape with sides inclined at a predetermined angle. The first dike BNK1 and the second dike BNK2 are not limited to the shapes described above, and may have various shapes such as semi-elliptical, circular, and square.

[0135] The first electrode RFE1 (or the first pixel electrode) and the second electrode RFE2 (or the second pixel electrode) may be disposed on the substrate SUB. Although for the sake of explanation, the first electrode RFE1 and the second electrode RFE2 are shown as being disposed directly on the substrate SUB, this disclosure is not limited thereto. For example, components (e.g., pixel circuitry) for driving the display device as a passive or active matrix may be further disposed between the substrate SUB and the first electrode RFE1 and the second electrode RFE2.

[0136] In this embodiment, the first electrode RFE1 and the second electrode RFE2 can be respectively disposed on the corresponding first dam BNK1 and second dam BNK2. For example, the first electrode RFE1 can be disposed on the first dam BNK1, and the second electrode RFE2 can be disposed on the second dam BNK2.

[0137] The first electrode RFE1 and the second electrode RFE2 can be configured to have substantially uniform thickness along the surfaces of the first embankment BNK1 and the second embankment BNK2, and the first electrode RFE1 and the second electrode RFE2 can be configured to correspond to the shapes of the first embankment BNK1 and the second embankment BNK2. For example, the first electrode RFE1 can have a shape corresponding to the inclination of the first embankment BNK1, and the second electrode RFE2 can have a shape corresponding to the inclination of the second embankment BNK2.

[0138] The first electrode RFE1 and the second electrode RFE2 can be disposed on the substrate SUB to be spaced apart from each other in the first direction DR1 and extended in the second direction DR2, and the light-emitting element LD is disposed between the first electrode RFE1 and the second electrode RFE2.

[0139] In an embodiment, the first electrode RFE1 may be configured to be adjacent to the first end of each light-emitting element LD, and may be electrically connected to each light-emitting element LD via the third electrode CTE1. The second electrode RFE2 may be configured to be adjacent to the second end of each light-emitting element LD, and may be electrically connected to each light-emitting element LD via the fourth electrode CTE2.

[0140] The first electrode RFE1 and the second electrode RFE2 can be set on the same plane and have the same height. If the first electrode RFE1 and the second electrode RFE2 have the same height, the light-emitting element LD can be connected to the first electrode RFE1 and the second electrode RFE2 more reliably.

[0141] The first electrode RFE1 and the second electrode RFE2 can be formed of a conductive material. The conductive material can include metals, such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and their alloys. However, the conductive material is not limited to these.

[0142] Furthermore, each of the first electrode RFE1 and the second electrode RFE2 may have a single-layer structure, but this disclosure is not limited thereto. Each of the first electrode RFE1 and the second electrode RFE2 may have a multi-layer structure. For example, each of the first electrode RFE1 and the second electrode RFE2 may also include a capping layer (not shown) formed of a transparent conductive material. The capping layer may be configured to cover the first electrode RFE1 and the second electrode RFE2, thereby preventing the first electrode RFE1 and the second electrode RFE2 from being damaged during the manufacturing process of the display device.

[0143] Here, the materials of the first electrode RFE1 and the second electrode RFE2 are not limited to those described above. For example, the first electrode RFE1 and the second electrode RFE2 may include conductive materials having a predetermined reflectivity. When the first electrode RFE1 and the second electrode RFE2 are made of conductive materials having a predetermined reflectivity, light emitted from opposite ends of the light-emitting element LD can be reflected by the first electrode RFE1 and the second electrode RFE2 to travel in the display direction (e.g., the third direction DR3).

[0144] Specifically, the first electrode RFE1 and the second electrode RFE2 can have shapes corresponding to the shapes of the first dam BNK1 and the second dam BNK2, and can have a predetermined angle with the substrate SUB. Light emitted from both ends of each of the light-emitting elements LD can be reflected by the first electrode RFE1 and the second electrode RFE2 to travel further in the third direction DR3. Therefore, the light output efficiency of the display device can be improved.

[0145] Either the first electrode RFE1 or the second electrode RFE2 can be a positive electrode, and the other can be a negative electrode.

[0146] like Figure 5 As shown, the first electrode RFE1 can be connected to the first connecting line CNL1, and the second electrode RFE2 can be connected to the second connecting line CNL2. In one embodiment, the first connecting line CNL1 can be integrally formed with the first electrode RFE1, and the second connecting line CNL2 can be integrally formed with the second electrode RFE2. In another embodiment, the first connecting line CNL1 and the second connecting line CNL2 can be formed separately from the first electrode RFE1 and the second electrode RFE2, so as to be electrically connected to each other through separate through holes or contact holes.

[0147] Reference Figure 3a The first electrode RFE1 and the second electrode RFE2 can be electrically connected to the pixel driving circuit DC and the second driving power supply VSS through the first connecting line CNL1 and the second connecting line CNL2, respectively.

[0148] The first electrode RFE1 and the second electrode RFE2 can be connected to the first and second terminals of the light-emitting element LD, respectively, so that a driving signal can be provided to the light-emitting element LD. The light-emitting element LD can emit light with a predetermined brightness corresponding to the driving current provided from the pixel driving circuit DC.

[0149] A first insulating layer INS1 may be disposed on the first electrode RFE1 and the second electrode RFE2. The first insulating layer INS1 may be completely disposed on the substrate SUB to cover the first dam BNK1 and the second dam BNK2, as well as the first electrode RFE1 and the second electrode RFE2, as described above. Alternatively, the first insulating layer INS1 may be disposed along the surface of the substrate SUB where the first dam BNK1 and the second dam BNK2, as well as the first electrode RFE1 and the second electrode RFE2, are not disposed.

[0150] In some embodiments, the first insulating layer INS1 may be an inorganic insulating layer formed of an inorganic material. In this case, the first insulating layer INS1 may be configured to have a substantially uniform thickness along the surfaces of the substrate SUB and the first electrode RFE1 and the second electrode RFE2, and may form at least a partially empty space between the first insulating layer INS1 and the light-emitting element LD disposed on the first insulating layer INS1. In some embodiments, the first insulating layer INS1 may include an organic insulating layer formed of an organic material. In this case, the first insulating layer INS1 may fill the space between the substrate SUB and the light-emitting element LD and reliably support the light-emitting element LD.

[0151] The first insulating layer INS1 may include a first opening OP1 and a second opening OP2. The first opening OP1 and the second opening OP2 may respectively expose at least a portion of the first electrode RFE1 and at least a portion of the second electrode RFE2.

[0152] The first opening OP1 and the second opening OP2 can be formed to be superimposed on the corresponding first electrode RFE1 and second electrode RFE2, respectively. For example, the first opening OP1 can be superimposed on the first electrode RFE1, and the second opening OP2 can be superimposed on the second electrode RFE2.

[0153] The first opening OP1 and the second opening OP2 may have a thickness and / or depth corresponding to the thickness of the first insulating layer INS1. That is, the first opening OP1 and the second opening OP2 may completely penetrate the first insulating layer INS1 in their respective regions. Therefore, the first electrode RFE1 and the second electrode RFE2 may be exposed to the outside to contact the third electrode CTE1 and the fourth electrode CTE2, which will be described later.

[0154] The light-emitting element LD can be disposed on the first insulating layer INS1. The light-emitting element LD can be disposed in the space provided by the first dike BNK1 and the second dike BNK2, and can be electrically connected between the first electrode RFE1 and the second electrode RFE2. For example, the first end of the light-emitting element LD can be electrically connected to the first electrode RFE1, and the second end of the light-emitting element LD can be electrically connected to the second electrode RFE2.

[0155] The third electrode CTE1 (or the first contact electrode) and the fourth electrode CTE2 (or the second contact electrode) can be disposed on the first insulating layer INS1 and the light-emitting element LD. In addition, the second insulating layer INS2 can be disposed between the third electrode CTE1 and the fourth electrode CTE2.

[0156] The third electrode CTE1 and the fourth electrode CTE2 can contact one of the opposite ends of each light-emitting element (LD). For example, the third electrode CTE1 can contact the first end of each light-emitting element (LD), and the fourth electrode CTE2 can contact the second end of each light-emitting element (LD).

[0157] In the plan view, the third electrode CTE1 may cover and stack with the first electrode RFE1. The third electrode CTE1 may be electrically connected to the first electrode RFE1 through the first opening OP1 of the first insulating layer INS1.

[0158] In the plan view, the fourth electrode CTE2 can cover and stack with the second electrode RFE2. The fourth electrode CTE2 can be electrically connected to the second electrode RFE2 through the second opening OP2 of the first insulating layer INS1.

[0159] Each of the third electrode CTE1 and the fourth electrode CTE2 can be formed of a transparent conductive material. For example, the transparent conductive material may include ITO, IZO, ITZO, etc. When the third electrode CTE1 and the fourth electrode CTE2 are formed of a transparent conductive material, the loss can be reduced when the light emitted from the light-emitting element LD travels along the third direction DR3. The materials of the third electrode CTE1 and the fourth electrode CTE2 are not limited to the materials described above.

[0160] The second insulating layer INS2 can be disposed between the third electrode CTE1 and the fourth electrode CTE2. Specifically, the second insulating layer INS2 can be disposed on the third electrode CTE1, and at least a portion of the fourth electrode CTE2 can be disposed on the second insulating layer INS2. The third electrode CTE1 and the fourth electrode CTE2 can be disposed on different layers and can be insulated from each other by the second insulating layer INS2.

[0161] However, the arrangement of the third electrode CTE1 and the fourth electrode CTE2 is not limited to this; the third electrode CTE1 and the fourth electrode CTE2 can be arranged in the same layer. This will be described later.

[0162] Each of the pixels PXL may include an electrode pattern TEL (or sensing electrode) disposed on a substrate SUB. The electrode pattern TEL may be disposed on the same layer as one of the various lines disposed on the substrate SUB. In an embodiment, the electrode pattern TEL may be disposed on the same layer as a fourth electrode CTE2. The arrangement of the electrode pattern TEL is not limited thereto, and various embodiments thereof will be described later.

[0163] As described above, the electrode pattern TEL can be disposed on the same layer as the fourth electrode CTE2. Furthermore, the electrode pattern TEL can be formed simultaneously with the fourth electrode CTE2, and can comprise the same material. For example, a base metal layer can be formed on the first insulating layer INS1 and the second insulating layer INS2, and the base metal layer can be patterned to simultaneously form the fourth electrode CTE2 and the electrode pattern TEL.

[0164] The electrode pattern TEL can be at least partially superimposed on the third electrode CTE1, and can be set in the area of ​​pixel regions PA1, PA2 and PA3 in the planar view that is not superimposed on the fourth electrode CTE2.

[0165] Electrode patterns TELs disposed in pixel regions PA1, PA2, and PA3 can be integrally formed and connected to each other. However, this is not a limitation; the electrode patterns can be formed separately in pixel regions PA1, PA2, and PA3. In other words, the electrode patterns TELs disposed in pixel regions PA1, PA2, and PA3 can be spaced apart from each other. In this case, the electrode patterns TELs disposed in pixel regions PA1, PA2, and PA3 can be electrically connected to each other via individual connection patterns.

[0166] Electrode pattern TELs can be used as the touch electrode layer of a touch sensor. Specifically, electrode pattern TELs can be used as the sensing electrodes of a self-capacitance type touch sensor or a mutual capacitance type touch sensor.

[0167] In this regard, further reference will be made. Figure 8 and Figure 9 This section describes in detail the touch sensing function of a display device that uses an electrode pattern TEL as the touch electrode layer.

[0168] Figure 8 and Figure 9 This diagram is used to explain the touch sensing function of the display device according to this disclosure. More specifically, Figure 8 A display device including a self-capacitive touch sensor is shown. Figure 9 A display device including a mutual capacitance type touch sensor is shown.

[0169] Reference Figure 8 and Figure 9 The display device 1000 may include multiple sensing electrode assemblies TE1, TE2, TE3, and TE4 disposed on a substrate SUB. For ease of explanation, Figure 8 and Figure 9 The diagram shows a structure in which four sensing electrode assemblies, TE1, TE2, TE3, and TE4, are mounted on a substrate SUB. However, of course, a greater number of sensing electrode assemblies can be mounted.

[0170] Each of the sensing electrode assemblies TE1, TE2, TE3, and TE4 can be configured to have a size corresponding to a plurality of pixels PXL. For example, each of the sensing electrode assemblies TE1, TE2, TE3, and TE4 can be configured to have a size corresponding to 10 to 300 pixels PXL, but is not limited thereto.

[0171] Each of the sensing electrode assemblies TE1, TE2, TE3, and TE4 can be a sensing electrode having the electrode pattern TEL described above. For example, each of the sensing electrode assemblies TE1, TE2, TE3, and TE4 can have an electrode pattern TEL integrally formed on a plurality of pixels PXL, or the electrode pattern TEL formed on each of the pixels PXL can be electrically connected to each other.

[0172] First, according to embodiments of this disclosure, when the display device 1000 includes a self-capacitance type touch sensor, such as Figure 8 As shown, each of the sensing electrode assemblies TE1, TE2, TE3 and TE4 can be connected to the touch sensing line TL, and can be electrically connected to the touch sensing controller TSC (or input sensing controller) via the touch sensing line TL.

[0173] The touch sensing controller (TSC) can be formed as one or more controllers on the substrate (SUB) to provide touch drive signals to the touch sensing line (TL) or to receive touch sensing signals from the touch sensing line (TL). The location of the touch sensing controller (TSC) is not limited to this, and the touch sensing controller (TSC) can be formed on a separate component to be connected to it via other lines.

[0174] As mentioned above, Figure 8 The sensing electrode assemblies TE1, TE2, TE3 and TE4 can be used as sensing electrodes for self-capacitive touch screen panels.

[0175] For example, if an external conductor (e.g., a user's finger) touches (or is near) the display device 1000, the self-capacitance value of at least one of the sensing electrode assemblies TE1, TE2, TE3, and TE4 may change at the touch location. This change in self-capacitance value can become a touch sensing signal for sensing the touch, and the touch sensing signal can be provided to the touch sensing controller TSC via the touch sensing line TL. The touch sensing controller TSC (or an execution processing device connected to the touch sensing controller TSC) can determine the location where the external conductor was touched based on the touch sensing signal and the change in capacitance value.

[0176] Next, according to embodiments of this disclosure, in the case where the display device 1000 includes a mutual capacitance type touch sensor, such as Figure 9 As shown, the sensing electrode assemblies TE1, TE2, TE3 and TE4 can form sensing electrode strings TES1 and TES2, and the sensing electrode strings TES1 and TES2 can be electrically connected to the touch sensing controller TSC through touch sensing lines TL1 and TL2.

[0177] Specifically, the first sensing electrode assembly TE1 can be connected to the fourth sensing electrode assembly TE4 via the first connecting line BE1. The fourth sensing electrode assembly TE4 can be connected to the second touch sensing line TL2, and can also be connected to the touch sensing controller TSC via the second touch sensing line TL2. In other words, the first sensing electrode assembly TE1, the fourth sensing electrode assembly TE4, and the first connecting line BE1 can form a first sensing electrode string TES1.

[0178] The third sensing electrode assembly TE3 can be connected to the second sensing electrode assembly TE2 via the second connecting line BE2. The second sensing electrode assembly TE2 can be connected to the first touch sensing line TL1, and can also be connected to the touch sensing controller TSC via the first touch sensing line TL1. In other words, the second sensing electrode assembly TE2, the third sensing electrode assembly TE3, and the second connecting line BE2 can form a second sensing electrode string TES2.

[0179] although Figure 9 Only one first sensing electrode string TES1 and one second sensing electrode string TES2 are shown, but multiple first sensing electrode strings TES1 and multiple second sensing electrode strings TES2 can be provided on the substrate SUB.

[0180] The first sensing electrode string TES1 and the second sensing electrode string TES2 can be configured to cross each other. In addition, a separate insulating layer or insulating pattern can be formed between the first sensing electrode string TES1 and the second sensing electrode string TES2, and the first sensing electrode string TES1 and the second sensing electrode string TES2 can be insulated from each other.

[0181] The touch sensing controller (TSC) can provide touch drive signals to either the first sensing electrode string (TES1) or the second sensing electrode string (TES2) via touch sensing lines (TL1 and TL2), and can receive touch signals generated from the remaining sensing electrode strings.

[0182] As mentioned above, Figure 9 The sensing electrode assemblies TE1, TE2, TE3 and TE4 can be used as sensing electrodes for mutual capacitance type touch screen panels.

[0183] Mutual capacitance values ​​can be formed between the first sensing electrode assembly TE1 and the fourth sensing electrode assembly TE4 in the first sensing electrode string TES1, and between the second sensing electrode assembly TE2 and the third sensing electrode assembly TE3 in the second sensing electrode string TES2. If an external conductor (e.g., a user's finger) touches (or is near) the display device 1000, the mutual capacitance values ​​formed between the respective sensing electrode assemblies TE1, TE2, TE3, and TE4 can change at the touch location. Such changes in mutual capacitance values ​​can become touch sensing signals for sensing touch, and these touch sensing signals can be provided to the touch sensing controller TSC via touch sensing lines TL1 and TL2. The touch sensing controller TSC (or an execution processing device connected to the touch sensing controller TSC) can determine the location where the external conductor is touched based on the touch sensing signal according to the given changes in mutual capacitance values.

[0184] Return to reference Figures 5 to 7The third insulating layer INS3 can be disposed on the fourth electrode CTE2 and the electrode pattern TEL. The third insulating layer INS3 can cover the fourth electrode CTE2 and the electrode pattern TEL to prevent damage to the fourth electrode CTE2 and the electrode pattern TEL. In addition, the third insulating layer INS3 can be used as an encapsulation layer to prevent oxygen and moisture from penetrating into the light-emitting element LD.

[0185] The third insulating layer INS3 may comprise an inorganic insulating layer made of inorganic materials or an organic insulating layer made of organic materials. Although the third insulating layer INS3 may have a single-layer structure as shown in the figures, this disclosure is not limited thereto. For example, the third insulating layer may have a multi-layer structure comprising organic and inorganic insulating layers.

[0186] Although not shown in the accompanying drawings, in some embodiments, a planarization layer (not shown) may also be provided on the third insulating layer INS3. The planarization layer can mitigate step differences caused by various components disposed beneath it. The planarization layer may include an organic insulating layer. However, it is not limited thereto; the planarization layer may include an inorganic insulating layer.

[0187] Although the electrode pattern TEL disclosed herein has been described as a component of each pixel PXL, it can be used as a sensing electrode that generates an electrical signal in response to an external input such as a touch. For example, the electrode pattern TEL does not involve the emission of a light-emitting element LD disposed in each of the pixels PXL, and can be a sensing electrode constituting a touch sensor.

[0188] As described above, the electrode pattern TEL can be used as the sensing electrode of a touch sensor included in a display device. The electrode pattern TEL can be formed on the same layer as the fourth electrode CTE2, and can be formed simultaneously with the fourth electrode. That is, the display device according to this disclosure can omit the separate process for forming the sensing electrode of the touch sensor, simplifying the manufacturing process of the display device and reducing its manufacturing cost. Furthermore, since the display device according to this disclosure does not include a separate sensing electrode layer for forming the sensing electrode of the touch sensor, it is effective to realize a thin display device.

[0189] In the following description, pixels and display devices including such pixels according to other embodiments will be described. In the following embodiments, components identical to those in the previously described embodiments are denoted by the same reference numerals, and their descriptions will be omitted or simplified, with differences being the primary focus.

[0190] Figure 10 This is a cross-sectional view showing pixels according to another embodiment of the present disclosure. Figures 11a to 11c It is according to various embodiments corresponding to Figure 10 A cross-sectional view of the pixels of line B-B'.

[0191] Figures 10 to 11c Implementation examples and Figures 5 to 7 The difference in the embodiment is that the electrode pattern TEL_1 is disposed in the pixel regions PA1, PA2 and PA3 spaced apart from each other, and further connection patterns BRL1 and BRL2 are formed to connect the electrode pattern TEL_1 to each other.

[0192] Reference Figures 10 to 11a Pixel PXL_1 may include electrode pattern TEL_1. Electrode pattern TEL_1 may be set in pixel regions PA1, PA2, and PA3, and may be spaced apart from each other in the planar view. Electrode pattern TEL_1 may be set on the same layer as the fourth electrode CTE2.

[0193] Connection patterns BRL1 and BRL2, configured to connect adjacent electrode patterns TEL_1, can be formed between electrode patterns TEL_1. Connection patterns BRL1 and BRL2 may include a first connection pattern BRL1 and a second connection pattern BRL2. The first connection pattern BRL1 may be a connection pattern configured to connect electrode patterns TEL_1 that are adjacent to each other in a first direction DR1, and the second connection pattern BRL2 may be a connection pattern configured to connect electrode patterns TEL_1 that are adjacent to each other in a second direction DR2.

[0194] For example, the electrode pattern TEL_1 (or the first electrode pattern) disposed in the first pixel region PA1 and the electrode pattern TEL_1 (or the second electrode pattern) disposed in the second pixel region PA2 can be configured to be spaced apart from each other, and the first connection pattern BRL1 can be electrically connected to the first electrode pattern and the second electrode pattern.

[0195] The first connection pattern BRL1 can be disposed on a different layer than the electrode pattern TEL_1. In other words, the first connection pattern BRL1 can be disposed on a different layer than the fourth electrode CTE2. In an embodiment, the first connection pattern BRL1 can be disposed on the same layer as the third electrode CTE1, and the first connection pattern BRL1 can be disposed between the first insulating layer INS1 and the second insulating layer INS2. The first connection pattern BRL1 and the third electrode CTE1 can be formed simultaneously and include the same material. For example, a base metal layer can be formed on the first insulating layer INS1, and the base metal layer can be patterned to simultaneously form the third electrode CTE1 and the first connection pattern BRL1.

[0196] The second insulating layer INS2, configured to cover the first connection pattern BRL1, may include a first contact CT1 and a second contact CT2 that expose at least a portion of the first connection pattern BRL1. Adjacent electrode patterns TEL_1 can contact the first connection pattern BRL1 through the first contact CT1 and the second contact CT2 of the second insulating layer INS2.

[0197] For example, electrode patterns TEL_1 disposed in the first pixel region PA1 and electrode patterns TEL_1 disposed in the second pixel region PA2 can be electrically connected to each other via a first connecting pattern BRL1. Electrode pattern TEL_1 disposed in the first pixel region PA1 can contact the first connecting pattern BRL1 via a first contact CT1, and electrode pattern TEL_1 disposed in the second pixel region PA2 can contact the first connecting pattern BRL1 via a second contact CT2. Furthermore, adjacent electrode patterns TEL_1 in the second direction DR2 can contact the second connecting pattern BRL2 via a third contact CT3.

[0198] like Figure 11b and Figure 11c As shown, the partition wall PW, configured to surround each of pixels PXL_1a and PXL_1b, can also be disposed on the substrate SUB along the boundary of each of pixels PXL_1a and PXL_1b. The partition wall PW can be disposed on the first insulating layer INS1, but is not limited thereto. For example, the partition wall PW can be disposed between the substrate SUB and the first insulating layer INS1.

[0199] The partition wall PW prevents light leakage between adjacent pixels PXL_1a and PXL_1b. Additionally, during the process of aligning the light-emitting elements (LDs), the partition wall PW prevents the solution containing the LDs from leaking into adjacent pixels.

[0200] The first connection pattern BRL1 can be positioned above or below the partition wall PW. For example, as shown... Figure 11b As shown, the first connection pattern BRL1a can be disposed on the separator wall PW. More specifically, the first connection pattern BRL1a can be disposed between the separator wall PW and the second insulating layer INS2. The first connection pattern BRL1a can generally be disposed along the surface of the separator wall PW. As another example, such as Figure 11c As shown, the first connection pattern BRL1b can be disposed below the partition wall PW. More specifically, the first connection pattern BRL1b can be disposed between the first insulating layer INS1 and the partition wall PW.

[0201] Since the connection relationship and structure of the second connection pattern BRL2 can be substantially the same as the connection relationship and structure of the first connection pattern BRL1, its detailed description will be omitted.

[0202] As described above, when the electrode pattern TEL_1 is set in pixel regions PA1, PA2, and PA3 spaced apart from each other, the parasitic capacitance value that may be generated between the electrode lines of pixel PXL can be reduced compared to a structure integrally formed in each of pixel regions PA1, PA2, and PA3. When the parasitic capacitance value is reduced, noise caused by parasitic capacitance can be reduced.

[0203] Figure 12a and Figure 12b This is a plan view showing pixels according to another embodiment of the present disclosure. Figure 12a and Figure 12b Various shapes of electrode patterns TELa and TELb are shown.

[0204] Reference Figure 12a The electrode pattern TELa can be configured to surround multiple third electrodes CTE1 and fourth electrodes CTE2 in a planar view. The electrode pattern TELa can have a single closed curve shape and can have a fine wiring structure. The electrode pattern TELa can include a wide opening and can have a window shape set along the edge of the opening.

[0205] In addition, refer to Figure 12b The electrode pattern TELb can be set along the edges of pixel regions PA1, PA2 and PA3 in a planar diagram, and can have a grid shape including a fine wiring structure.

[0206] The shapes of the electrode patterns TELa and TELb are not limited to this. The electrode patterns can have various shapes, as long as they can be on the same layer as other wiring included in the pixels PXLa and PXLb.

[0207] Figure 13 This is a plan view showing pixels according to yet another embodiment of the present disclosure. Figure 13 Implementation examples and Figure 5 The difference in the embodiments is that, in the planar view, each pixel includes a circular electrode.

[0208] Reference Figure 13 Each pixel PXLc may include a first electrode RFE1c, a second electrode RFE2c, a light-emitting element LD, a third electrode CTE1c, a fourth electrode CTE2c, and an electrode pattern TELc.

[0209] The first electrode RFE1c and the second electrode RFE2c can be spaced apart from each other, and the light-emitting element LD is placed between the first electrode RFE1c and the second electrode RFE2c. For example, the first electrode RFE1c and the second electrode RFE2c can be configured such that one electrode surrounds the other in a planar view. For example, the first electrode RFE1c can be surrounded by the second electrode RFE2c. More specifically, the first electrode RFE1c can be formed in a circular shape in a planar view, and the second electrode RFE2c can be formed in a shape surrounding the first electrode RFE1c (e.g., a ring shape). The shapes of the first electrode RFE1c and the second electrode RFE2c are not limited to this. For example, the first electrode RFE1c can have an elliptical shape or a polygonal shape such as a triangle or a square. Furthermore, if the second electrode RFE2c is also formed surrounding the first electrode RFE1c, its shape is not limited.

[0210] The light-emitting element (LD) can be disposed between the first electrode RFE1c and the second electrode RFE2c. A first end of the LD can be connected to the first electrode RFE1c via a third electrode CTE1c, and a second end of the LD can be connected to the second electrode RFE2c via a fourth electrode CTE2c. The third electrode CTE1c and the fourth electrode CTE2c can be at least partially superimposed on the first electrode RFE1c and the second electrode RFE2c, respectively.

[0211] The third electrode CTE1c and the fourth electrode CTE2c can also be formed similarly to the first electrode RFE1c and the second electrode RFE2c, respectively. For example, the third electrode CTE1c can be stacked on top of the first electrode RFE1c and can be formed in a circular shape in a planar view. Furthermore, the fourth electrode CTE2c can be stacked on top of the second electrode RFE2c and can be configured to surround the third electrode CTE1c (or in a ring shape). The third electrode CTE1c and the fourth electrode CTE2c are not limited to this and can have various shapes.

[0212] The electrode pattern TELc can be disposed on the same layer as any of the first electrode RFE1c, the second electrode RFE2c, the third electrode CTE1c, and the fourth electrode CTE2c. For example, the electrode pattern TELc can be disposed on the same layer as the fourth electrode CTE2c. In embodiments, the electrode pattern TELc can be disposed in a region that does not overlap with the first electrode RFE1c, the second electrode RFE2c, the third electrode CTE1c, and the fourth electrode CTE2c, but is not limited thereto. For example, the electrode pattern TELc can at least partially overlap with the first electrode RFE1c and / or the third electrode CTE1c.

[0213] Figure 14 This is a plan view showing pixels according to yet another embodiment of the present disclosure. Figures 15a to 15c It is according to various embodiments corresponding to Figure 14 A cross-sectional view of the pixels along line C-C'.

[0214] Figures 14 to 15c Implementation examples and Figures 5 to 7 The difference in this embodiment is that the electrode pattern TEL_2 and the third electrode CTE1 are disposed on the same layer.

[0215] Reference Figures 14 to 15a Each pixel PXL_2 may include an electrode pattern TEL_2. The electrode pattern TEL_2 may be disposed on the same layer as the third electrode CTE1.

[0216] Electrode pattern TEL_2 can be formed simultaneously with the third electrode CTE1, and can include the same material. For example, a base metal layer can be formed on the first insulating layer INS1, and the base metal layer can be patterned to simultaneously form the third electrode CTE1 and the electrode pattern TEL_2.

[0217] The electrode pattern TEL_2 can be set in the area of ​​pixel regions PA1, PA2 and PA3 that does not overlap with the third electrode CTE1 and the fourth electrode CTE2.

[0218] The electrode patterns TEL_2 disposed in pixel regions PA1, PA2, and PA3 can be integrally formed and connected to each other. However, this is not a limitation; the electrode patterns can be formed separately in pixel regions PA1, PA2, and PA3.

[0219] like Figure 15b and Figure 15c As shown, the separator wall PW can be set along the boundary of pixels PXL_2a and PXL_2b, and the electrode pattern TEL_2 can be set above or below the separator wall PW. For example, as Figure 15b As shown, the electrode pattern TEL_2a can be disposed on the separator wall PW. More specifically, the electrode pattern TEL_2a can be disposed between the separator wall PW and the second insulating layer INS2. As another example, as Figure 15c As shown, the electrode pattern TEL_2b can be disposed below the separator wall PW. More specifically, the electrode pattern TEL_2b can be disposed between the first insulating layer INS1 and the separator wall PW.

[0220] Figure 16 This is a plan view showing pixels according to yet another embodiment of the present disclosure. Figure 17a and Figure 17b It is according to various embodiments corresponding to Figure 16 A cross-sectional view of the pixels of line D-D'.

[0221] Figures 16 to 17bImplementation examples and Figures 10 to 11c The difference in the embodiment is that the electrode pattern TEL_3 and the third electrode CTE1 are disposed on the same layer, and the connecting patterns BRL1_3 and BRL2_3 are disposed on the same layer as the fourth electrode CTE2.

[0222] Reference Figures 16 to 17a Pixel PXL_3 may include electrode pattern TEL_3. Electrode pattern TEL_3 may be set in pixel regions PA1, PA2, and PA3, and may be spaced apart from each other in the planar view. Electrode pattern TEL_3 may be set on the same layer as the third electrode CTE1.

[0223] Connection patterns BRL1_3 and BRL2_3, configured to connect adjacent electrode patterns TEL_3, can be formed between electrode patterns TEL_3. Connection patterns BRL1_3 and BRL2_3 may include a first connection pattern BRL1_3 and a second connection pattern BRL2_3. The first connection pattern BRL1_3 may be a connection pattern configured to connect electrode patterns TEL_3 that are adjacent to each other in the first direction DR1, and the second connection pattern BRL2_3 may be a connection pattern configured to connect electrode patterns TEL_3 that are adjacent to each other in the second direction DR2.

[0224] The first connection pattern BRL1_3 can be disposed on a different layer than the electrode pattern TEL_3. In other words, the first connection pattern BRL1_3 can be disposed on a different layer than the third electrode CTE1. In an embodiment, the first connection pattern BRL1_3 can be disposed on the same layer as the fourth electrode CTE2, and the first connection pattern BRL1_3 can be disposed between the second insulating layer INS2 and the third insulating layer INS3. The first connection pattern BRL1_3 and the fourth electrode CTE2 can be formed simultaneously and comprise the same material.

[0225] The second insulating layer INS2, configured to cover the electrode pattern TEL_3, may include a first contact CT1 and a second contact CT2 that expose at least a portion of the electrode pattern TEL_3. Adjacent electrode patterns TEL_3 may contact the first connection pattern BRL1_3 through the first contact CT1 and the second contact CT2 of the second insulating layer INS2.

[0226] like Figure 17b As shown, a partition wall PW can be further provided on the substrate SUB to surround each pixel PXL_3a along the boundary of each pixel PXL_3a, and a first connection pattern BRL1_3a can be provided above the partition wall PW. More specifically, the first connection pattern BRL1_3a can be provided between the third insulating layer INS3 and the second insulating layer INS2 provided on the partition wall PW.

[0227] Since the connection relationship and structure of the second connection pattern BRL2_3 can be substantially the same as the connection relationship and structure of the first connection pattern BRL1_3, its detailed description will be omitted.

[0228] Figure 18 This is a plan view showing pixels according to yet another embodiment of the present disclosure. Figure 19a and Figure 19b It is according to various embodiments corresponding to Figure 18 A cross-sectional view of the pixels along line E-E'.

[0229] Figures 18 to 19b Implementation examples and Figures 5 to 7 The difference in the embodiment is that the third electrode CTE1_4 and the fourth electrode CTE2_4 are disposed on the same layer, and the electrode pattern TEL_4 is disposed on the same layer as the third electrode CTE1_4 and the fourth electrode CTE2_4.

[0230] Reference Figures 18 to 19a Each pixel PXL_4 may include an electrode pattern TEL_4. The third electrode CTE1_4 and the fourth electrode CTE2_4 may be disposed on the same layer, and the electrode pattern TEL_4 may be disposed on the same layer as the third electrode CTE1_4 and the fourth electrode CTE2_4. In other words, the electrode pattern TEL_4, the third electrode CTE1_4, and the fourth electrode CTE2_4 may be formed simultaneously and may include the same material.

[0231] Therefore, unlike the embodiments described above, a separate insulating layer may not be required between the third electrode CTE1_4 and the fourth electrode CTE2_4 (e.g., Figure 7 The second insulating layer (INS2).

[0232] The electrode pattern TEL_4 can be set in the pixel areas PA1, PA2 and PA3 in a region that does not overlap with the third electrode CTE1_4 and the fourth electrode CTE2_4.

[0233] The electrode patterns TEL_4 disposed in pixel regions PA1, PA2, and PA3 can be integrally formed and connected to each other. However, this is not a limitation; the electrode patterns can be formed separately in pixel regions PA1, PA2, and PA3.

[0234] like Figure 19b As shown, the separator wall PW can be set along the boundary of each pixel PXL_4a, and the electrode pattern TEL_4a can be set above the separator wall PW. More specifically, the electrode pattern TEL_4a can be set between the separator wall PW and the third insulating layer INS3.

[0235] Figure 20This is a plan view showing pixels according to yet another embodiment of the present disclosure. Figure 21a and Figure 21b It is according to various embodiments corresponding to Figure 20 A cross-sectional view of the pixels of line F-F'. Figure 22 This is a plan view showing pixels according to yet another embodiment of the present disclosure.

[0236] Figures 20 to 22 Implementation examples and Figures 5 to 7 The difference in the embodiment is that the electrode pattern TEL_5 is disposed on the same layer as the first electrode RFE1 and the second electrode RFE2.

[0237] Reference Figures 20 to 21a Each pixel PXL_5 may include an electrode pattern TEL_5. The electrode pattern TEL_5 may be disposed on the same layer as the first electrode RFE1 and the second electrode RFE2.

[0238] The electrode pattern TEL_5 can be formed simultaneously with the first electrode RFE1 and the second electrode RFE2. For example, a base metal layer can be formed on the substrate SUB, and the base metal layer can be patterned to simultaneously form the first electrode RFE1, the second electrode RFE2, and the electrode pattern TEL_5.

[0239] Furthermore, the electrode pattern TEL_5 may include the same material as the first electrode RFE1 and the second electrode RFE2. That is, the electrode pattern TEL_5 may include a conductive material with a predetermined reflectivity. Therefore, the electrode pattern TEL_5 can reflect light incident on it from the outside and emit the light to the outside, and can provide a mirror function to reflect the image of an object positioned in front of the display device.

[0240] Electrode pattern TEL_5 can be set in the pixel regions PA1, PA2, and PA3 in areas that do not overlap with the first electrode RFE1 and the second electrode RFE2. Furthermore, electrode pattern TEL_5 may not overlap with the third electrode CTE1 and the fourth electrode CTE2.

[0241] Electrode patterns TEL_5 disposed in pixel regions PA1, PA2, and PA3 can be formed in pixel regions PA1, PA2, and PA3, respectively. Connecting patterns BRL1_5 and BRL2_5 configured to connect adjacent electrode patterns TEL_5 can be formed between electrode patterns TEL_5. Connecting patterns BRL1_5 and BRL2_5 can be formed on the same layer as either the third electrode CTE1 or the fourth electrode CTE2, but this disclosure is not limited thereto.

[0242] like Figure 21bAs shown, a partition wall PW can be set along the boundary of each pixel PXL_5a, and an electrode pattern TEL_5a can be set below the partition wall PW. More specifically, the electrode pattern TEL_5a can be set between the first insulating layer INS1 and the substrate SUB.

[0243] Each of the pixels PXL_5 may also include a first dummy pattern DMP1 (or a first dummy electrode) formed in a portion of each of the pixel regions PA1, PA2, and PA3. Furthermore, as... Figure 22 As shown, each of the pixels PXL_5b may also include a second dummy pattern DMP2 (or a second dummy electrode) located at the boundary of each of the pixels PXL_5b.

[0244] The first dummy pattern DMP1 and the second dummy pattern DMP2 can be disposed on the same layer as the electrode pattern TEL_5, and can be formed simultaneously with it. The first dummy pattern DMP1 and the second dummy pattern DMP2 can be electrically separated from the electrode pattern TEL_5. The first dummy pattern DMP1 and the second dummy pattern DMP2 can be electrodes in a floating state, but are not limited thereto. For example, a voltage or signal different from the voltage or signal of the electrode pattern TEL_5 can be applied to the first dummy pattern DMP1 and the second dummy pattern DMP2. Furthermore, different voltages or signals can be applied to the first dummy pattern DMP1 and the second dummy pattern DMP2 respectively.

[0245] The first dummy pattern DMP1 and the second dummy pattern DMP2 can reduce the parasitic capacitance values ​​that may be excessively generated between the electrode pattern TEL_5 and the electrode lines of pixels PXL_5 and PXL_5b, and can reduce the noise phenomenon of the touch sensor caused by parasitic capacitance.

[0246] Furthermore, the first dummy pattern DMP1 and the second dummy pattern DMP2 may include a conductive material having a predetermined reflectivity, as in the electrode pattern TEL_5. Therefore, the first dummy pattern DMP1 and the second dummy pattern DMP2 can provide a mirror function for reflecting an image of an object positioned in front of the display device.

[0247] Figure 23 This is a plan view showing pixels according to yet another embodiment of the present disclosure. Figure 24a and Figure 24b It is according to various embodiments corresponding to Figure 23 A cross-sectional view of the pixels of line G-G'.

[0248] Figures 23 to 24b Implementation examples and Figures 5 to 7The difference in this embodiment is that it also includes a shielding electrode SML disposed between the first electrode RFE1 and the third electrode CTE1, and the electrode pattern TEL_6 and the shielding electrode SML are disposed on the same layer.

[0249] Reference Figures 23 to 24a Each pixel PXL_6 may include a shielding electrode SML and an electrode pattern TEL_6. The shielding electrode SML may be disposed between the first electrode RFE1 and the third electrode CTE1, and the electrode pattern TEL_6 may be disposed on the same layer as the shielding electrode SML. The electrode pattern TEL_6 may be formed simultaneously with the shielding electrode SML and may include the same material.

[0250] For example, a substrate shielding electrode layer can be formed on the first insulating layer INS1 to surround the area in which each light-emitting element LD is aligned. The light-emitting element LD can be aligned, and then the substrate shielding electrode layer can be patterned to form the electrode pattern TEL_6.

[0251] The electrode pattern TEL_6 can be set in the pixel areas PA1, PA2 and PA3 in areas that do not overlap with the third electrode CTE1 and the fourth electrode CTE2, and can be electrically separated from the third electrode CTE1 and the fourth electrode CTE2.

[0252] Electrode patterns TEL_6 disposed in pixel regions PA1, PA2, and PA3 can be formed in pixel regions PA1, PA2, and PA3, respectively. Connecting patterns BRL1_6 and BRL2_6, configured to connect adjacent electrode patterns TEL_6, can be formed between electrode patterns TEL_6. Connecting patterns BRL1_6 and BRL2_6 can be formed on the same layer as either the third electrode CTE1 or the fourth electrode CTE2, but this disclosure is not limited thereto.

[0253] like Figure 24b As shown, the separator wall PW can be set along the boundary of each pixel PXL_6a, and the electrode pattern TEL_6a can be set below the separator wall PW. More specifically, the electrode pattern TEL_6a can be set between the separator wall PW and the first insulating layer INS1.

[0254] Figure 25 This is a plan view showing pixels according to yet another embodiment. Figure 26a and Figure 26b It is according to various embodiments corresponding to Figure 25 A cross-sectional view of the pixels along line H-H'.

[0255] Figures 25 to 26b Implementation examples and Figures 23 to 24bThe difference in the embodiment is that the shielding electrode SML and the electrode pattern TEL_7 are integral with each other, and an insulating pattern INSP is also included to insulate the third electrode CTE1 from the electrode pattern TEL_7.

[0256] Reference Figures 25 to 26a Each pixel PXL_7 may include an electrode pattern TEL_7 and an insulating pattern INSP.

[0257] Electrode pattern TEL_7 can be disposed between the first electrode RFE1 and the third electrode CTE1, and can be formed to surround the area where the light-emitting element LD is aligned. During the process of arranging the light-emitting element LD, electrode pattern TEL_7 can be in a floating state. In other words, electrode pattern TEL_7 can be used as a shielding electrode SML, and the light-emitting element LD can be reliably aligned between the first electrode RFE1 and the second electrode RFE2.

[0258] Electrode patterns TEL_7 disposed in pixel regions PA1, PA2, and PA3 can be formed in pixel regions PA1, PA2, and PA3, respectively. Connecting patterns BRL1_7 and BRL2_7, configured to connect adjacent electrode patterns TEL_7, can be formed between electrode patterns TEL_7. Connecting patterns BRL1_7 and BRL2_7 can be formed on the same layer as either the third electrode CTE1 or the fourth electrode CTE2, but this disclosure is not limited thereto.

[0259] Furthermore, the arrangement of the electrode pattern TEL_7 is not limited to this; the electrode patterns TEL_7 set in the pixel areas PA1, PA2 and PA3 can be integrally formed to connect with each other.

[0260] like Figure 26b As shown, the separator wall PW can be set along the boundary of each pixel PXL_7a, and the electrode pattern TEL_7a can be set below the separator wall PW. More specifically, the electrode pattern TEL_7a can be set between the separator wall PW and the first insulating layer INS1.

[0261] Although embodiments of the present disclosure have been disclosed, those skilled in the art will understand that the present disclosure may be implemented in other specific forms without departing from the scope and spirit of the present disclosure as disclosed in the appended claims. Therefore, it should be understood that the exemplary embodiments are for illustrative purposes only and do not limit the scope of the invention.

Claims

1. A display device, the display device comprising: The substrate comprises multiple pixel regions; as well as A pixel, set in each of the plurality of pixel regions. The pixel includes: a first electrode and a second electrode disposed on the substrate and in the same layer; a light-emitting element disposed on the first electrode and the second electrode; a third electrode configured to electrically connect a first end of the first electrode and the light-emitting element; a fourth electrode configured to electrically connect a second end of the second electrode and the light-emitting element; and an electrode pattern disposed in the same layer as one of the third electrode and the fourth electrode.

2. The display device according to claim 1, wherein, The electrode pattern is disposed on the same layer as the third electrode, and the electrode pattern is electrically insulated from the third electrode.

3. The display device according to claim 1, wherein, The electrode pattern is disposed on the same layer as the fourth electrode, and the electrode pattern is electrically insulated from the fourth electrode. The electrode pattern is superimposed on at least a portion of the third electrode.

4. The display device according to claim 1, further comprising an input sensing controller electrically connected to the electrode pattern. in, The electrode pattern is an input sensing electrode, and The input sensing controller senses input from an external device based on signals provided from the electrode pattern.

5. The display device of claim 4, further comprising a first insulating layer, the first insulating layer being configured to cover at least a portion of the first electrode and the second electrode and disposed between the light-emitting element and the substrate. in, The first insulating layer includes a first opening configured to expose at least a portion of the first electrode and a second opening configured to expose at least a portion of the second electrode. The third electrode contacts the first electrode through the first opening, and the fourth electrode contacts the second electrode through the second opening.

6. The display device of claim 5, further comprising a second insulating layer configured to cover the third electrode. in, The electrode pattern is disposed on the same layer as the fourth electrode, and the electrode pattern is disposed on the second insulating layer.

7. The display device according to claim 5, further comprising a second insulating layer configured to cover the third electrode. in, The electrode pattern is disposed on the same layer as the third electrode, and the electrode pattern is disposed between the first insulating layer and the second insulating layer.

8. The display device according to claim 5, wherein, The electrode pattern includes a first electrode pattern and a second electrode pattern spaced apart from each other.

9. The display device according to claim 8, further comprising a connection pattern configured to electrically connect the first electrode pattern and the second electrode pattern. in, The connection pattern is disposed on the same layer as one of the third electrode and the fourth electrode, and the connection pattern is disposed on a different layer from the first electrode pattern and the second electrode pattern.

10. The display device according to claim 9, further comprising a partition wall disposed on the substrate along the boundaries of the plurality of pixel regions. in, The connection pattern is set on the partition wall.

11. The display device according to claim 9, further comprising a partition wall disposed on the substrate along the boundaries of the plurality of pixel regions. in, The connection pattern is disposed between the first insulating layer and the partition wall.

12. The display device of claim 9, further comprising a second insulating layer configured to cover the third electrode. in, The second insulating layer includes a first contact and a second contact formed to overlap with the connection pattern, and The electrode pattern is connected to the connection pattern via the first contact and the second contact.

13. The display device of claim 5, further comprising a second insulating layer configured to cover the third electrode and the fourth electrode. in, The third electrode and the fourth electrode are disposed on the same layer, and The electrode pattern is disposed between the first insulating layer and the second insulating layer.

14. The display device of claim 13, further comprising a partition wall disposed on the substrate along the boundaries of the plurality of pixel regions, and in, The electrode pattern is disposed between the partition wall and the second insulating layer.

15. The display device according to claim 4, wherein, The electrode pattern is set in the shape of a window in the plan view.

16. A display device, the display device comprising: The substrate comprises multiple pixel regions; Pixels, set in each of the plurality of pixel regions; as well as Input sensing controller, The pixel includes: a first electrode and a second electrode disposed on the substrate and in the same layer; a light-emitting element electrically connected to the first electrode and the second electrode; and a sensing electrode disposed in the same layer as the first electrode and the second electrode, wherein the input sensing controller is electrically connected to the sensing electrode to sense input from an external device based on a signal provided from the sensing electrode.

17. The display device according to claim 16, further comprising: A first insulating layer is configured to cover at least a portion of the first electrode and the second electrode, and is disposed between the light-emitting element and the substrate; A third electrode is disposed on the first electrode and configured to contact the first end of the light-emitting element; as well as A fourth electrode is disposed on the second electrode and configured to contact the second end of the light-emitting element, and The first insulating layer includes a first opening configured to expose at least a portion of the first electrode and a second opening configured to expose at least a portion of the second electrode. The third electrode contacts the first electrode through the first opening, and the fourth electrode contacts the second electrode through the second opening.

18. The display device according to claim 16, in, The sensing electrode comprises a metal having a first reflectivity, and The sensing electrode reflects light incident from the outside and emits the light back to the outside.

19. The display device according to claim 16, further comprising a dummy electrode disposed on the same layer as the first electrode and the second electrode. in, The dummy electrode is electrically separated from the sensing electrode.

20. A display device, the display device comprising: The substrate comprises multiple pixel regions; Pixels, set in each of the plurality of pixel regions; as well as Input sensing controller, The pixel includes: a first electrode and a second electrode disposed on the substrate and on the same layer; a light-emitting element disposed on the first electrode and the second electrode; a third electrode configured to electrically connect a first end of the first electrode and the light-emitting element; a fourth electrode configured to electrically connect a second end of the second electrode and the light-emitting element; a shielding electrode disposed between the first electrode and the third electrode; and a sensing electrode disposed on the same layer as the shielding electrode. The input sensing controller is electrically connected to the sensing electrode to sense input from an external device based on signals provided from the sensing electrode.

21. The display device according to claim 20, wherein, The shielding electrode and the sensing electrode are configured to be spaced apart from each other and electrically isolated from each other.

22. The display device according to claim 20, further comprising an insulating pattern disposed between the shielding electrode and the third electrode. in, The shielding electrode is electrically separated from the third electrode by the insulating pattern, and The shielding electrode and the sensing electrode are integrally formed.

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