Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a fourth nitride semiconductor layer, a fifth nitride semiconductor layer and a sixth nitride semiconductor layer. The first nitride semiconductor layer and the second nitride semiconductor layer are stacked on the substrate. The third nitride semiconductor layer and the fourth nitride semiconductor layer are arranged above the second nitride semiconductor layer and between a source electrode and a drain electrode, and have a first P-type doping. The fifth nitride semiconductor layer is arranged above the fourth nitride semiconductor layer and has a band gap higher than that of the fourth nitride semiconductor layer. The sixth nitride semiconductor layer is arranged above the fifth nitride semiconductor layer and coupled to the drain electrode, and has a second P-type doping. The semiconductor structure provided by the application can effectively reduce the production cost and time.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and its fabrication method, specifically to an enhancement-mode high electron mobility transistor (HEMT) structure and its fabrication method. Background Technology

[0002] GaN materials, due to their wide bandgap and high-speed electron mobility, are widely used in high-power semiconductor structures, especially in radio frequency and power applications. Traditionally, High Electron Mobility Transistors (HEMTs) utilize stacked group III-V semiconductors, forming a heterojunction at their interface. Due to the band bending at the heterojunction, a potential well is formed deep within the conduction band bend, and a two-dimensional electron gas (2DEG) is formed within the potential well.

[0003] However, high electron mobility transistors are typically normally-on (i.e., depletion-mode) devices. Therefore, an additional negative bias is required to turn them off, which is not only relatively inconvenient but also limits their application range. To address this issue, enhancement-mode high electron mobility transistors have been proposed. These transistors utilize methods such as bombarding the aluminum gallium nitride (ANH3) layer with fluorine ions to disrupt its lattice structure before forming the metal gate; or etching recesses into the ANH3 layer to form recesses, followed by epitaxial gallium nitride (HNH3) layers with P-type impurities at the bottom of the recesses to create a gate stack structure that allows the two-dimensional electron gas to be turned off without the need for an additional bias.

[0004] However, all of the above methods have their technical bottlenecks. For example, when using etching processes to form recessed structures to improve the breakdown voltage of high electron mobility transistors (HEMs), the etching precision is difficult to control, making it difficult to regulate the thickness of the aluminum gallium nitride (GaN) layer at the bottom of the recess within a specific range. This often results in significant variations in the pinch-off voltage between identical HEMs. Furthermore, epitaxially generating a GaN layer with P-type impurities at the bottom of the recess requires specialized epitaxial techniques and is very time-consuming. Moreover, due to the small atomic size of fluorine, under long-term high-temperature and high-pressure operation, fluorine ions bombarding HEMs can easily diffuse out of the GaN layer, causing enhancement-mode HEMs to invert into depletion-mode devices, leading to overall circuit failure.

[0005] Therefore, there is a need to provide an advanced enhanced high electron mobility transistor and its fabrication method to solve the problems faced by the existing technology. Summary of the Invention

[0006] This invention proposes a semiconductor structure for forming enhancement-mode high electron mobility transistors (EMTs). By adjusting the thickness, concentration, and aluminum content ratio of the first, second, and third top nitride semiconductor layers, the on-state voltage of the carrier channel can be effectively controlled while simultaneously improving the dynamic on-resistance. Furthermore, compared to the high etching precision required to create the recess and the special epitaxial techniques needed to epitaxially form a gallium nitride layer with P-type impurities at the bottom of the recess in existing technologies, the semiconductor structure manufacturing method proposed in this invention uses conventional epitaxial and etching processes, effectively reducing production costs and time. Compared to the problem of enhancement-mode devices turning into depletion-mode devices in existing EMTs bombarded with fluoride ions, this problem is easily eliminated because the semiconductor structure and its manufacturing method do not use fluoride ions.

[0007] In view of this, the present invention provides a semiconductor structure, comprising a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a fourth nitride semiconductor layer, a fifth nitride semiconductor layer, and a sixth nitride semiconductor layer. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer, wherein the bandgap of the second nitride semiconductor layer is higher than that of the first nitride semiconductor layer. The third nitride semiconductor layer is disposed on the second nitride semiconductor layer between a source electrode and a drain electrode, and has a first P-type doping. The fourth nitride semiconductor layer is disposed on the second nitride semiconductor layer and between the third nitride semiconductor layer and the drain electrode, and has the first P-type doping. The fifth nitride semiconductor layer is disposed on the fourth nitride semiconductor layer, wherein the bandgap of the fifth nitride semiconductor layer is higher than those of the third nitride semiconductor layer and the fourth nitride semiconductor layer. The sixth nitride semiconductor layer is disposed on the fifth nitride semiconductor layer and coupled to the drain electrode, and has a second P-type doping.

[0008] According to some embodiments of the present invention, the semiconductor structure further includes a gate electrode and a second drain electrode. The gate electrode is disposed on the third nitride semiconductor layer and in direct contact with the third nitride semiconductor layer. The second drain electrode is disposed on the sixth nitride semiconductor layer and in direct contact with the sixth nitride semiconductor layer, wherein the second drain electrode is adjacent to and electrically connected to the drain electrode, and wherein the source electrode and the drain electrode are in direct contact with the second nitride semiconductor layer.

[0009] According to some embodiments of the present invention, the concentration of the first P-type doping is greater than that of the second P-type doping.

[0010] According to some embodiments of the present invention, the third nitride semiconductor layer and the fourth nitride semiconductor layer have the same thickness, and the thickness of the sixth nitride semiconductor layer is greater than those of the third nitride semiconductor layer and the fourth nitride semiconductor layer.

[0011] According to some embodiments of the present invention, the thickness of the second nitride semiconductor layer is less than that of the fourth nitride semiconductor layer. The second nitride semiconductor layer includes AlxGa1-xN with 0 < x < 1, and the fourth nitride semiconductor layer includes AlyGa1-yN with 0 < y < 1, wherein y > x.

[0012] According to some embodiments of the present invention, the first nitride semiconductor layer comprises GaN, the third nitride semiconductor layer and the fourth nitride semiconductor layer comprise GaN having the first P-type doping, and the sixth nitride semiconductor layer comprises GaN having the second P-type doping.

[0013] The present invention also proposes a method for manufacturing a semiconductor structure, comprising providing a substrate; forming a first nitride semiconductor layer on the substrate; forming a second nitride semiconductor layer on the first nitride semiconductor layer, wherein the band gap of the second nitride semiconductor layer is higher than the band gap of the first nitride semiconductor layer; forming a first top nitride semiconductor layer on the second nitride semiconductor layer, wherein the first top nitride semiconductor layer has a first p-type doping; forming a second top nitride semiconductor layer on the first top nitride semiconductor layer, wherein the band gap of the second top nitride semiconductor layer is higher than the band gap of the first top nitride semiconductor layer; and forming a third top nitride semiconductor layer on the second top nitride semiconductor layer, wherein the third top nitride semiconductor layer has a second p-type doping. The process involves: doping the third top nitride semiconductor layer; forming a second drain electrode on top of the third top nitride semiconductor layer; using the second drain electrode as an etching mask to etch the third top nitride semiconductor layer to form a sixth nitride semiconductor layer, wherein the second drain electrode and the sixth nitride semiconductor layer form an ohmic contact; etching the second top nitride semiconductor layer to form a fifth nitride semiconductor layer, exposing the first top nitride semiconductor layer, wherein the sixth nitride layer is stacked on top of the fifth nitride semiconductor layer; and etching the first top nitride semiconductor layer to expose the second nitride semiconductor layer, forming a third nitride semiconductor layer and a fourth nitride semiconductor layer, wherein the fifth nitride semiconductor layer and the sixth nitride semiconductor layer are stacked on top of the fourth nitride semiconductor layer.

[0014] According to some embodiments of the present invention, the manufacturing method further includes forming a source electrode and a drain electrode on the second nitride semiconductor layer, wherein the source electrode and the drain electrode are located on opposite sides of the third nitride semiconductor layer and the fourth nitride semiconductor layer, wherein the drain electrode and the second drain electrode are adjacent to each other and electrically connected; and after forming the source electrode and the drain electrode, forming a gate electrode on the third nitride semiconductor layer, wherein the gate electrode is in direct contact with the third nitride semiconductor layer.

[0015] According to some embodiments of the present invention, the concentration of the first P-type doping is greater than the concentration of the second P-type doping, the first nitride semiconductor layer includes GaN, the second nitride semiconductor layer includes AlxGa1-xN, 0 < x < 1, the first top nitride semiconductor layer includes GaN with the first P-type doping, the second top nitride semiconductor layer includes AlyGa1-yN, 0 < y < 1 and y > x, and the third top nitride semiconductor layer includes GaN with the second P-type doping.

[0016] According to some embodiments of the present invention, the thickness of the third top nitride semiconductor layer is greater than the thickness of the first top nitride semiconductor layer, and the thickness of the second nitride semiconductor layer is less than the thickness of the second top nitride semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0018] Figure 1 FIG. is a cross-sectional view of the semiconductor structure shown according to an embodiment of the present invention; and

[0019] Figures 2A to 2D FIG. is a schematic cross-sectional view of a manufacturing method of the semiconductor structure shown according to an embodiment of the present invention.

[0020] DESCRIPTION OF REFERENCE NUMERALS:

[0021] 100: Semiconductor structure

[0022] 110: Substrate <00000​​​​​​​​​​​​​​​​​​​​​160: Second top nitride semiconductor layer

[0031] 161: Fifth nitride semiconductor layer

[0032] 170: Third top nitride semiconductor layer

[0033] 171: Sixth nitride semiconductor layer

[0034] 181: Drain electrode

[0035] 182: Second drain electrode

[0036] 183: Source Electrode

[0037] 184: Gate electrode

[0038] D1: First thickness

[0039] D2: Second thickness

[0040] D3: Third Thickness

[0041] D4: Fourth Thickness Detailed Implementation

[0042] The following provides a detailed description of the component substrate, semiconductor structure, and manufacturing method of the semiconductor structure according to some embodiments of the present invention. It should be understood that the following description provides many different embodiments or examples to implement different variations of some embodiments of the present invention. The specific components and arrangements described below are merely for simple and clear description of some embodiments of the present invention. Of course, these are merely examples and not limitations of the present invention. Furthermore, repeated reference numerals or designations may be used in different embodiments. These repetitions are only for simple and clear description of some embodiments of the present invention and do not represent any association between the different embodiments and / or structures discussed. Moreover, when referring to a first material layer located on or above a second material layer, it includes the case where the first material layer and the second material layer are in direct contact. Alternatively, there may be a case where one or more other material layers are spaced apart, in which case the first material layer and the second material layer may not be in direct contact.

[0043] Furthermore, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the arrangement of the diagram is flipped so that it is upside down, the element depicted on the "lower" side will become the element on the "higher" side.

[0044] Here, the terms "about," "approximately," and "roughly" generally indicate within 20%, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%, of a given value or range. The quantities given here are approximate quantities, meaning that the meaning of "about," "approximately," or "roughly" may be implied even without specific mention of them.

[0045] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or portions. Therefore, a first element, component, region, layer, and / or portion discussed below may be referred to as a second element, component, region, layer, and / or portion without departing from the teachings of some embodiments of the present invention.

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of the invention.

[0047] Some embodiments of the present invention can be understood in conjunction with the accompanying drawings, which are also considered part of the description of the embodiments of the present invention. It should be understood that the drawings of the embodiments of the present invention are not drawn to scale with actual devices and components. The shape and thickness of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present invention. Furthermore, the structures and devices in the drawings are illustrated schematically to clearly show the features of the embodiments of the present invention.

[0048] In some embodiments of the present invention, relative terms such as "down," "up," "horizontal," "vertical," "below," "above," "top," "bottom," etc., should be understood as the orientation shown in the paragraph and related figures. These relative terms are for illustrative purposes only and do not imply that the described device must be manufactured or operated in a specific orientation. Terms relating to joining or connecting, such as "connection" or "interconnection," unless specifically defined, may refer to two structures in direct contact, or to two structures not in direct contact, with other structures disposed between them. Furthermore, these terms relating to joining or connecting may include cases where both structures are movable or both structures are fixed.

[0049] Figure 1 This is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention. Figure 1 As shown, the semiconductor structure 100 includes a substrate 110. In some embodiments, the substrate 110 may be a bulk semiconductor substrate or a composite substrate formed of different materials, and the substrate 110 may be doped (e.g., using P-type or N-type doping) or undoped. In some embodiments, the substrate 110 may include a semiconductor substrate, a glass substrate, or a ceramic substrate, such as a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, an aluminum nitride substrate, a sapphire substrate, a combination thereof, or similar materials, but the embodiments of the present invention are not limited thereto. In some embodiments, the substrate 110 may include a semiconductor-on-insulator (SOI) substrate, which is formed by depositing a semiconductor material on an insulating layer.

[0050] like Figure 1 As shown, the semiconductor structure 100 also includes a buffer layer 120. In some embodiments, the buffer layer 120 is disposed above the substrate 110. The function of the buffer layer 120 is to reduce the strain generated between the substrate 110 and the subsequently formed nitride semiconductor layer. The buffer layer 120 may be, for example, a combination of an AlN nucleation layer and an AlGaN transition layer. The buffer layer 120 can reduce defects caused by lattice misalignments between the substrate 110 and the subsequently formed nitride semiconductor layer.

[0051] like Figure 1 As shown, the semiconductor structure 100 also includes a first nitride semiconductor layer 130 and a second nitride semiconductor layer 140 formed above the first nitride semiconductor layer 130, wherein the second nitride semiconductor layer 140 has a first thickness D1. According to an embodiment of the present invention, the first nitride semiconductor layer 130 and the second nitride semiconductor layer 140 are material layers with different band gaps, and the band gap of the second nitride semiconductor layer 140 is higher than that of the first nitride semiconductor layer 130.

[0052] According to some embodiments of the present invention, the first nitride semiconductor layer 130 and the second nitride semiconductor layer 140 are composed of compounds formed by elements in Group III-V of the periodic table. However, the first nitride semiconductor layer 130 and the second nitride semiconductor layer 140 are different in composition from each other. According to some embodiments of the present invention, the first nitride semiconductor layer 130 includes a GaN layer, and the second nitride semiconductor layer 140 includes an AlxGa1-xN layer, where 0 < x < 1. The first nitride semiconductor layer 130 and the second nitride semiconductor layer 140 are in direct contact with each other. Since the first nitride semiconductor layer 130 and the second nitride semiconductor layer 140 have different band gaps, a heterojunction is formed at the interface between the first nitride semiconductor layer 130 and the second nitride semiconductor layer 140.

[0053] The first nitride semiconductor layer 130 can be grown epitaxially using a gallium-containing precursor and a nitrogen-containing precursor by Metal-organic Chemical Vapor Deposition (MOCVD). The gallium-containing precursor may include trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemicals; the nitrogen-containing precursor includes ammonia (NH3), tertiarybutylamine (TBAm), phenyl hydrazine, or other suitable chemicals. However, the embodiments of the present invention are not limited thereto.

[0054] As Figure 1 shown, the second nitride semiconductor layer 140 is grown epitaxially above the first nitride semiconductor layer 130. The second nitride semiconductor layer 140 can be formed by a deposition process, such as Metal-organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), other suitable methods, or a combination of the foregoing. For example, the second nitride semiconductor layer 140 can be grown epitaxially by Metal-organic Vapor Phase Epitaxy (MOCVD) using an aluminum-containing precursor, a gallium-containing precursor, and a nitrogen-containing precursor. The aluminum-containing precursor includes trimethylaluminum (TMA), triethylaluminum (TEA), or other suitable chemicals; the gallium-containing precursor includes trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemicals; the nitrogen-containing precursor includes ammonia (NH3), tertiarybutylamine (TBAm), phenylhydrazine, or other suitable chemicals. However, the embodiments of the present invention are not limited thereto.

[0055] The bandgap discontinuity and piezo-electric effect between the first nitride semiconductor layer 130 and the second nitride semiconductor layer 140 generate a carrier channel 130A with highly mobile conductive electrons near the interface between the first nitride semiconductor layer 130 and the second nitride semiconductor layer 140. This carrier channel 130A is called a two-dimensional electron gas (2-DEG), which forms a carrier channel on the interface between the first nitride semiconductor layer 130 and the second nitride semiconductor layer 140. According to some embodiments of the present invention, since the semiconductor structure 100 is an enhancement-mode transistor, the carrier channel 130A is discontinuous.

[0056] According to some embodiments of the present invention, as Figure 1 shown, the semiconductor structure 100 further includes a third nitride semiconductor layer 151 and a fourth nitride semiconductor layer 152 formed by using the first top nitride semiconductor layer 150. The third nitride semiconductor layer and the fourth nitride semiconductor layer 152 are both disposed on the second nitride semiconductor layer 140, wherein the first top nitride semiconductor layer 150 has a first P-type doping and a second thickness D2. In other words, both the third nitride semiconductor layer 151 and the fourth nitride semiconductor layer 152 have the first P-type doping and the second thickness D2. According to some embodiments of the present invention, the first P-type doping includes Mg, Be, Ca, Zn, etc. that can form P-type nitride materials. According to an embodiment of the present invention, the first top nitride semiconductor layer 150 includes a P-type gallium nitride layer.

[0057] According to some embodiments of the present invention, as Figure 1 shown, the semiconductor structure 100 further includes a fifth nitride semiconductor layer 161 formed by using the second top nitride semiconductor layer 160, and the fifth nitride semiconductor layer 161 is disposed on the fourth nitride semiconductor layer 152, wherein the second top nitride semiconductor layer 160 has a third thickness D3. According to an embodiment of the present invention, the second top nitride semiconductor layer 160 includes an AlyGa1-yN layer, where 0 < y < 1. According to an embodiment of the present invention, y > x and the third thickness D3 is greater than the first thickness D1. In other words, the proportion of the aluminum content in the second top nitride semiconductor layer 160 is higher than the proportion of the aluminum content in the second nitride semiconductor layer 140, and the third thickness D3 of the second top nitride semiconductor layer 160 is greater than the first thickness D1 of the second nitride semiconductor layer 140.

[0058] According to some embodiments of the present invention, as Figure 1As shown, the semiconductor structure 100 further includes a sixth nitride semiconductor layer 171 formed using a third top nitride semiconductor layer 170. The sixth nitride semiconductor layer 171 is disposed above the fifth nitride semiconductor layer 161, and the third top nitride semiconductor layer 170 has a fourth thickness D4 and a second P-type dopant. According to an embodiment of the present invention, the concentration of the second P-type dopant is less than the concentration of the first P-type dopant, and the fourth thickness D4 exceeds the second thickness D2. In other words, the concentration of the second P-type dopant in the third top nitride semiconductor layer 170 is less than the concentration of the first P-type dopant in the first top nitride semiconductor layer 150, and the fourth thickness D4 of the third top nitride semiconductor layer 170 exceeds the second thickness D2 of the first top nitride semiconductor layer 150.

[0059] According to some embodiments of the present invention, such as Figure 1 As shown, the semiconductor structure 100 further includes a drain electrode 181, a second drain electrode 182, and a source electrode 183. The drain electrode 181 and the source electrode 183 are disposed on the second nitride semiconductor layer 140 and are located on opposite sides of the third nitride semiconductor layer 151 and the fourth nitride semiconductor layer 152, respectively, wherein the drain electrode 181 and the source electrode 183 are in direct contact with the second nitride semiconductor layer 140. The second drain electrode 182 is formed on the sixth nitride semiconductor layer 171, and the drain electrode 181 and the second drain electrode 182 are adjacent to each other and electrically connected.

[0060] According to some embodiments of the present invention, the materials of the drain electrode 181, the second drain electrode 182, and the source electrode 183 may include conductive materials, such as metals, metal silicides, other suitable materials, or combinations thereof. Metals may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), combinations thereof, alloys thereof, or multilayers thereof. However, the embodiments of the present invention are not limited thereto. According to some embodiments of the present invention, the drain electrode 181 and the source electrode 183 form an ohmic contact with the second nitride semiconductor layer 140, and the second drain electrode 182 forms an ohmic contact with the sixth nitride semiconductor layer 171.

[0061] According to some embodiments of the present invention, such as Figure 1As shown, the semiconductor structure 100 further includes a gate electrode 184. The gate electrode 184 is disposed on the third nitride semiconductor layer 151. In some embodiments, the material of the gate electrode 184 may be the same as or similar to the materials of the drain electrode 181, the second drain electrode 182, and the source electrode 183, which will not be elaborated further here. According to one embodiment of the present invention, the gate electrode 184 and the third nitride semiconductor layer 151 form a Schottky contact. According to another embodiment of the present invention, the gate electrode 184 and the third nitride semiconductor layer 151 form an ohmic contact.

[0062] According to some embodiments of the present invention, such as Figure 1 As shown, semiconductor structure 100 forms an enhancement-high electron mobility transistor (EHMT). A third nitride semiconductor layer 151 and gate electrode 184 form the gate stack structure of the EHMT. A fourth nitride semiconductor layer 152, a fifth nitride semiconductor layer 161, a sixth nitride semiconductor layer 171, a drain electrode 181, and a second drain electrode 182 form the drain terminal of the EHMT, and a source electrode 183 forms the source terminal of the EHMT. The drain electrode 181 and the source electrode 183 are located on opposite sides of the gate electrode 184 and the second drain electrode 182, respectively, and the drain electrode 181 and the second drain electrode 182 are adjacent to each other. According to some embodiments of the present invention, the fourth nitride semiconductor layer 152, the fifth nitride semiconductor layer 161, the sixth nitride semiconductor layer 171, and the second drain electrode 182 are used to improve the dynamic on-resistance characteristics of the EHMT.

[0063] According to some embodiments of the present invention, the second thickness D2 of the third nitride semiconductor layer 151 and the concentration of the first P-type doping are used to increase the on-state voltage of the carrier channel 130A below the third nitride semiconductor layer 151 (i.e., below the gate stack structure of the high electron mobility transistor), so that the carrier channel 130A below the third nitride semiconductor layer 151 can be fully depleted without the application of voltage, thereby completely shutting down the carrier channel 130A. According to some embodiments of the present invention, the third thickness D3 of the fifth nitride semiconductor layer 161, the aluminum content ratio (i.e., y) of the second top nitride semiconductor layer 160, the fourth thickness D4 of the sixth nitride semiconductor layer 171, and the concentration of the second P-type doping are used to adjust the on-state voltage of the carrier channel 130A below the fourth nitride semiconductor layer 152 (i.e., below the drain terminal of the high electron mobility transistor), so that the carrier channel 130A below the fourth nitride semiconductor layer 152 can achieve partial depletion, thereby improving the device characteristics of the enhancement high electron mobility transistor formed by the semiconductor structure 100.

[0064] Figures 2A to 2D This is a schematic cross-sectional view of a method for manufacturing a semiconductor structure according to an embodiment of the present invention. (Refer to...) Figure 2A A substrate 110 is provided. Next, a buffer layer 120 may be formed over the substrate 110 to mitigate lattice differences between the film layers on the substrate 110 and the buffer layer 120, thereby improving crystal quality. In some embodiments, the material of the buffer layer 120 may include a III-V compound semiconductor material, such as a III-nitride. For example, the material of the buffer layer 14 may include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), similar materials, or combinations thereof, but the embodiments of the present invention are not limited thereto. In some embodiments, the buffer layer 120 may be formed by a deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), similar processes, or combinations thereof, but the embodiments of the present invention are not limited thereto. In some embodiments, the buffer layer 120 may include doped carbon.

[0065] like Figure 2AAs shown, a first nitride semiconductor layer 130 may be formed over the buffer layer 120. In some embodiments, the material of the first nitride semiconductor layer 130 may include one or more III-V compound semiconductor materials, such as group III nitrides. In some embodiments, the material of the first nitride semiconductor layer 130 may include gallium nitride (GaN). The first nitride semiconductor layer 130 may be formed by a deposition process, such as metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods, or combinations thereof. For example, the first nitride semiconductor layer 130 may be epitaxially formed by metal-organic chemical vapor deposition (MOCVD) using gallium-containing precursors and nitrogen-containing precursors. Gallium-containing precursors may include trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemicals; nitrogen-containing precursors may include ammonia (NH3), tertiary butylamine (TBAm), phenyl hydrazine, or other suitable chemicals. However, the embodiments of the present invention are not limited thereto.

[0066] like Figure 2A As shown, a second nitride semiconductor layer 140 may be formed over the first nitride semiconductor layer 130. In some embodiments, the material of the second nitride semiconductor layer 140 may include one or more III-V compound semiconductors, such as group III nitrides. In some embodiments, the material of the second nitride semiconductor layer 140 may include aluminum gallium nitride (AlGaN). In some embodiments, the second nitride semiconductor layer 140 may have dopants, such as N-type doping or P-type doping. The second nitride semiconductor layer 140 may be formed by a deposition process, such as metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods, or combinations thereof. For example, the second nitride semiconductor layer 140 may be epitaxially formed using aluminum-containing precursors, gallium-containing precursors, and nitrogen-containing precursors via metal-organic vapor phase epitaxy (MOCVD). Aluminum-containing precursors include trimethylaluminum (TMA), triethylaluminum (TEA), or other suitable chemicals; gallium-containing precursors include trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemicals; nitrogen-containing precursors include ammonia (NH3), tert-butylamine (TBAm), phenylhydrazine, or other suitable chemicals. However, the embodiments of the present invention are not limited thereto.

[0067] According to some embodiments of the present invention, the first nitride semiconductor layer 130 includes a GaN layer, and the second nitride semiconductor layer 140 includes an AlxGa1-xN layer, where 0 < x < 1, and the second nitride semiconductor layer 140 has a first thickness Dl.

[0068] In some embodiments, as Figure 2A shown, a first top nitride semiconductor layer 150 may be formed over the second nitride semiconductor layer 140. In some embodiments, the material of the first top nitride semiconductor layer 150 includes p-type doped gallium nitride (GaN). The first top nitride semiconductor layer 150 may be formed, for example, by depositing a doped compound semiconductor material on the second nitride semiconductor layer 140 through an epitaxial growth process, but the embodiments of the present invention are not limited thereto. According to an embodiment of the present invention, the first top nitride semiconductor layer 150 has a second thickness D2 and a first p-type doping.

[0069] In some embodiments, as Figure 2A shown, a second top nitride semiconductor layer 160 may be formed over the first top nitride semiconductor layer 150. In some embodiments, the material of the second top nitride semiconductor layer 160 includes an AlyGa1-yN layer, where 0 < y < 1 and y > x. In other words, the proportion of the aluminum content in the second top nitride semiconductor layer 160 is higher than that in the second nitride semiconductor layer 140. The second top nitride semiconductor layer 160 may be formed, for example, by depositing a compound semiconductor material on the first top nitride semiconductor layer 150 through an epitaxial growth process, but the embodiments of the present invention are not limited thereto. According to an embodiment of the present invention, the second top nitride semiconductor layer 160 has a third thickness D3, where the third thickness D3 is greater than the first thickness D1. That is, the third thickness D3 of the second top nitride semiconductor layer 160 is greater than the first thickness D1 of the second nitride semiconductor layer 140.

[0070] In some embodiments, as Figure 2A shown, a third top nitride semiconductor layer 170 may be formed over the second top nitride semiconductor layer 160. In some embodiments, the material of the third top nitride semiconductor layer 170 includes p-type doped gallium nitride (GaN). The third top nitride semiconductor layer 170 may be formed, for example, by depositing a doped compound semiconductor material on the second top nitride semiconductor layer 160 through an epitaxial growth process, but the embodiments of the present invention are not limited thereto.

[0071] According to one embodiment of the present invention, the third top nitride semiconductor layer 170 has a fourth thickness D4 and a second P-type dopant, wherein the concentration of the second P-type dopant is less than the concentration of the first P-type dopant, and the fourth thickness D4 exceeds the second thickness D2. In other words, according to some embodiments of the invention, the P-type dopant of the third top nitride semiconductor layer 170 includes magnesium (Mg), beryllium (Be), calcium (Ca), zinc (Zn), and other materials capable of forming P-type nitrides. According to one embodiment of the present invention, the third nitride semiconductor layer 150 includes a P-type gallium nitride layer.

[0072] The doping concentration is less than the P-type doping concentration of the first top nitride semiconductor layer 150, and the fourth thickness D4 of the third top nitride semiconductor layer 170 is greater than the second thickness D2 of the first top nitride semiconductor layer 150.

[0073] According to other embodiments of the present invention, in addition to sequentially forming the buffer layer 120, the first nitride semiconductor layer 130, the second nitride semiconductor layer 140, the first top nitride semiconductor layer 150, the second top nitride semiconductor layer 160 and the third top nitride semiconductor layer 170 on the substrate 110, an epitaxial wafer having the above semiconductor layers can also be provided to shorten the manufacturing process steps.

[0074] Next, as Figure 2B As shown, a second drain electrode 182 is formed above the third top nitride semiconductor layer 170. Using the second drain electrode 182 as an etching mask and the first top nitride semiconductor layer 150 as an etching stop layer, a fifth nitride semiconductor layer 161 and a sixth nitride semiconductor layer 171 are formed below the second drain electrode 182 by patterning the second top nitride semiconductor layer 160 and the third top nitride semiconductor layer 170, respectively. Furthermore, the first top nitride semiconductor layer 150 is thus exposed.

[0075] Next, as Figure 2C As shown, the first top nitride semiconductor layer 150 is patterned, and the second nitride semiconductor layer 140 is used as an etch stop layer to form the third nitride semiconductor layer 151. A fourth nitride semiconductor layer 152 is formed below the second drain electrode 182, the fifth nitride semiconductor layer 161, and the sixth nitride semiconductor layer 171.

[0076] Subsequently, as Figure 2DAs shown, a drain electrode 181 and a source electrode 183 are formed on opposite sides of the third nitride semiconductor layer 151 and the fourth nitride semiconductor layer 152, wherein the drain electrode 181 and the source electrode 183 are in direct contact with the second nitride semiconductor layer 140, and the drain electrode 181 and the second drain electrode 182 are adjacent and electrically connected to each other. According to an embodiment of the present invention, the drain electrode 181 and the source electrode 183 form an ohmic contact with the second nitride semiconductor layer 140.

[0077] According to some embodiments of the present invention, such as Figure 2D As shown, after forming the second drain electrode 182, drain electrode 181, and source electrode 183, a gate electrode 184 is formed above the third nitride semiconductor layer 151. According to one embodiment of the invention, the gate electrode 184 forms a Schottky contact with the third nitride semiconductor layer 151. According to another embodiment of the invention, the gate electrode 184 may also form an ohmic contact with the third nitride semiconductor layer 151. According to some embodiments of the invention, the materials of the drain electrode 181, the second drain electrode 182, the source electrode 183, and the gate electrode 184 may include conductive materials, such as metals, metal silicides, other suitable materials, or combinations thereof. Metals may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), combinations thereof, alloys thereof, or multilayers thereof. However, the embodiments of the invention are not limited thereto.

[0078] like Figure 2D As shown, a carrier channel 130A is formed on the heterogeneous interface between the first nitride semiconductor layer 130 and the second nitride semiconductor layer 140 through spontaneous polarization and piezoelectric polarization effects caused by the different energy bands between them. Furthermore, the carrier channel 130A is cut off below the third nitride semiconductor layer 151 when no voltage is applied.

[0079] According to some embodiments of the present invention, semiconductor structure 100 forms an enhancement-high electron mobility transistor (EHMT). A third nitride semiconductor layer 151 and gate electrode 184 form a gate stack structure for the EHMT. A fourth nitride semiconductor layer 152, a fifth nitride semiconductor layer 161, a sixth nitride semiconductor layer 171, a drain electrode 181, and a second drain electrode 182 form the drain terminal of the EHMT, and a source electrode 183 forms the source terminal of the EHMT. According to some embodiments of the present invention, the fourth nitride semiconductor layer 152, the fifth nitride semiconductor layer 161, the sixth nitride semiconductor layer 171, and the second drain electrode 182 are used to improve the dynamic on-resistance characteristics of the EHMT.

[0080] This invention proposes a semiconductor structure for forming enhancement-mode high electron mobility transistors (EMTs). By adjusting the thickness, concentration, and aluminum content ratio of the first, second, and third top nitride semiconductor layers, the on-state voltage of the carrier channel can be effectively controlled while simultaneously improving the dynamic on-resistance. Furthermore, compared to the high etching precision required to create the recess and the special epitaxial techniques needed to epitaxially form a gallium nitride layer with P-type impurities at the bottom of the recess in existing technologies, the semiconductor structure manufacturing method proposed in this invention uses conventional epitaxial and etching processes, effectively reducing production costs and time. Compared to the problem of enhancement-mode devices turning into depletion-mode devices in existing EMTs bombarded with fluoride ions, this problem is easily eliminated because the semiconductor structure and its manufacturing method do not use fluoride ions.

[0081] While the embodiments and advantages of the present invention have been disclosed above, it should be understood that any person skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of the present invention. Furthermore, the scope of protection of the present invention is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Any person skilled in the art can understand from the disclosure of some embodiments of the present invention how current or future processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps can be used according to some embodiments of the present invention, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of the present invention includes the above-described processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of the present invention also includes combinations of various claim claims and embodiments.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A first nitride semiconductor layer disposed on the substrate; A second nitride semiconductor layer disposed on the first nitride semiconductor layer, wherein the bandgap of the second nitride semiconductor layer is higher than that of the first nitride semiconductor layer, and a carrier channel is formed between the first nitride semiconductor layer and the second nitride semiconductor layer; A third nitride semiconductor layer disposed on the second nitride semiconductor layer and between a source electrode and a drain electrode, having a first P-type doping; A fourth nitride semiconductor layer disposed on the second nitride semiconductor layer and between the third nitride semiconductor layer and the drain electrode, having the first P-type doping; A fifth nitride semiconductor layer disposed on the fourth nitride semiconductor layer, wherein the bandgap of the fifth nitride semiconductor layer is higher than those of the third nitride semiconductor layer and the fourth nitride semiconductor layer; And A sixth nitride semiconductor layer disposed on the fifth nitride semiconductor layer and coupled to the drain electrode, having a second P-type doping, wherein the on-voltage of the carrier channel is determined by the thickness of the fifth nitride semiconductor layer, the thickness of the sixth nitride semiconductor layer, and the concentration of the second P-type doping, so that the carrier channel below the fourth nitride semiconductor layer reaches partial depletion.

2. The semiconductor structure as described in claim 1, characterized in that, Further comprising: A gate electrode disposed on the third nitride semiconductor layer and in direct contact with the third nitride semiconductor layer; And A second drain electrode disposed on the sixth nitride semiconductor layer and in direct contact with the sixth nitride semiconductor layer, wherein the second drain electrode is adjacent to and electrically connected to the drain electrode, and the source electrode and the drain electrode are in direct contact with the second nitride semiconductor layer.

3. The semiconductor structure as described in claim 1, characterized in that, Wherein the concentration of the first P-type doping is greater than that of the second P-type doping.

4. The semiconductor structure as described in claim 1, characterized in that, Wherein the third nitride semiconductor layer and the fourth nitride semiconductor layer have the same thickness, and the thickness of the sixth nitride semiconductor layer is greater than those of the third nitride semiconductor layer and the fourth nitride semiconductor layer.

5. The semiconductor structure as described in claim 1, characterized in that, Wherein the thickness of the second nitride semiconductor layer is less than that of the fourth nitride semiconductor layer, the second nitride semiconductor layer includes AlxGa1-xN with 0 < x < 1, the fourth nitride semiconductor layer includes AlyGa1-yN with 0 < y < 1, and y > x, and the on-voltage of the carrier channel is further determined by y.

6. The semiconductor structure as described in claim 1, characterized in that, Wherein the first nitride semiconductor layer includes GaN, the third nitride semiconductor layer and the fourth nitride semiconductor layer include GaN with the first P-type doping, and the sixth nitride semiconductor layer includes GaN with the second P-type doping.

7. A method for manufacturing a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a first nitride semiconductor layer on the substrate; A second nitride semiconductor layer is formed on the first nitride semiconductor layer, wherein the band gap of the second nitride semiconductor layer is higher than the band gap of the first nitride semiconductor layer, and a carrier channel is formed between the first nitride semiconductor layer and the second nitride semiconductor layer; A first top nitride semiconductor layer is formed on the second nitride semiconductor layer, wherein the first top nitride semiconductor layer has a first P-type doping; A second top nitride semiconductor layer is formed on top of the first top nitride semiconductor layer, wherein the band gap of the second top nitride semiconductor layer is higher than the band gap of the first top nitride semiconductor layer; A third top nitride semiconductor layer is formed on the second top nitride semiconductor layer, wherein the third top nitride semiconductor layer has a second P-type doping; A second drain electrode is formed on the third top nitride semiconductor layer; Using the second drain electrode as an etching mask, the third top nitride semiconductor layer is etched to form a sixth nitride semiconductor layer, wherein the second drain electrode and the sixth nitride semiconductor layer form an ohmic contact; A fifth nitride semiconductor layer is formed by etching the second top nitride semiconductor layer, exposing the first top nitride semiconductor layer, wherein a sixth nitride layer is stacked on top of the fifth nitride semiconductor layer; and The first top nitride semiconductor layer is etched to expose the second nitride semiconductor layer, and a third nitride semiconductor layer and a fourth nitride semiconductor layer are formed. The fifth nitride semiconductor layer and the sixth nitride semiconductor layer are stacked on the fourth nitride semiconductor layer. The on-state voltage of the carrier channel is determined by the thickness of the fifth nitride semiconductor layer, the thickness of the sixth nitride semiconductor layer and the concentration of the second P-type doping, so that the carrier channel below the fourth nitride semiconductor layer is partially depleted.

8. The manufacturing method as described in claim 7, characterized in that, Also includes: A source electrode and a drain electrode are formed on the second nitride semiconductor layer, wherein the source electrode and the drain electrode are located on opposite sides of the third nitride semiconductor layer and the fourth nitride semiconductor layer, and wherein the drain electrode and the second drain electrode are adjacent to each other and electrically connected; and After the source electrode and the drain electrode are formed, a gate electrode is formed on the third nitride semiconductor layer, wherein the gate electrode is in direct contact with the third nitride semiconductor layer.

9. The manufacturing method as described in claim 7, characterized in that, Where the concentration of the first P-type doping is greater than the concentration of the second P-type doping, and where the first nitride semiconductor layer includes GaN, the second nitride semiconductor layer includes AlxGa1-xN, 0 < x < 1, the first top nitride semiconductor layer includes GaN having the first P-type doping, the second top nitride semiconductor layer includes AlyGa1-yN, 0 < y < 1 and y > x, the third top nitride semiconductor layer includes GaN having the second P-type doping, and where the on-voltage of the carrier channel is also determined by y.

10. The manufacturing method as described in claim 7, characterized in that, Where the thickness of the third top nitride semiconductor layer is greater than the thickness of the first top nitride semiconductor layer, and where the thickness of the second nitride semiconductor layer is less than the thickness of the second top nitride semiconductor layer.

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