Semiconductor structure and method of forming the same

Abstract

The structure includes a substrate comprising a first semiconductor material; a dielectric feature embedded in the substrate; and a second semiconductor material embedded in the substrate, the second semiconductor material having a lattice mismatch with the first semiconductor material, the second semiconductor material having two upper sidewalls and two lower sidewalls, the two upper sidewalls being in contact with the dielectric feature, the two lower sidewalls being in contact with the substrate, the two lower sidewalls being non-perpendicular to a top surface of the substrate, a bottommost portion of the dielectric feature being lower than a topmost portion of the two lower sidewalls. Embodiments of the invention also relate to semiconductor structures and methods of forming the same.

Description

[0001] This application is a divisional application of the invention patent application filed on December 8, 2017, with application number 201711290808.8 entitled "Semiconductor Structure and Method for Forming the Same". Technical Field

[0002] Embodiments of the present invention relate to semiconductor structures and methods for forming the same. Background Technology

[0003] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each with smaller and more complex circuitry than the previous one. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be produced using manufacturing processes) decreases. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down has also increased the complexity of handling and manufacturing ICs, and similar advancements in IC handling and manufacturing are needed to realize these progresses.

[0004] Heterogeneous integration of different semiconductor materials (e.g., III-V materials epitaxially grown on silicon or silicon-germanium substrates) has been introduced to improve the functionality and performance of field-effect transistors (FETs). However, the performance of devices fabricated using combinations of different semiconductor materials depends on the quality of the resulting structure. Specifically, confining dislocation defects is important in various semiconductor devices and processes because dislocation defects fragment monolithic crystal structures and cause undesirable and abrupt changes in electrical properties, leading to poor material quality and limited performance. Therefore, semiconductor structures and methods that address these issues are needed to enhance performance and reduce dislocation defects. Summary of the Invention

[0005] An embodiment of the present invention provides a semiconductor structure comprising: a substrate including a first semiconductor material; a dielectric component embedded in the substrate; and a second semiconductor material embedded in the substrate, wherein the second semiconductor material has a lattice mismatch with the first semiconductor material, the second semiconductor material having two upper sidewalls and two lower sidewalls, the two upper sidewalls contacting the dielectric component, the two lower sidewalls contacting the substrate, the two lower sidewalls not perpendicular to the top surface of the substrate, and the bottom portion of the dielectric component being lower than the top portion of the two lower sidewalls.

[0006] Another embodiment of the present invention provides a semiconductor structure comprising: a substrate including a first semiconductor material, the substrate having a groove, the bottom of the groove having a first sidewall and a second sidewall intersecting the second sidewall; an isolation member surrounding the groove; and a second semiconductor material disposed in the groove and in contact with the first semiconductor material, the second semiconductor material having a lattice mismatch with the first semiconductor material, wherein dislocations in the lattice mismatched second semiconductor material propagate from the first sidewall to the second sidewall in a direction parallel to the top surface of the substrate.

[0007] Another embodiment of the present invention provides a method for forming a semiconductor structure, comprising: receiving a semiconductor substrate; forming a first isolation member surrounding a portion of the semiconductor substrate; recessing the portion of the semiconductor substrate to form an opening in the semiconductor substrate, the opening extending longitudinally in a first direction, the bottom of the opening having a V-shape in a plane perpendicular to the first direction; epitaxially growing a crystalline semiconductor material in the opening; patterning the crystalline semiconductor material to form a plurality of fins, each of the plurality of fins extending longitudinally in the first direction; and forming a second isolation member surrounding each of the plurality of fins, the second isolation member being surrounded by the first isolation member. Attached Figure Description

[0008] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0009] Figure 1A , Figure 1B and Figure 1C This is a diagram showing the three types of crystal orientations of silicon.

[0010] Figure 2A This is a perspective view of a semiconductor structure having a semiconductor material according to various aspects of the present invention, wherein the semiconductor material fills a groove having a V-shaped groove.

[0011] Figure 2B and Figure 2C It is according to various aspects of the present invention Figure 2A A cross-sectional view of the semiconductor structure in the image.

[0012] Figure 3A and Figure 3B This is a top view of a semiconductor wafer according to various aspects of the present invention, showing the geometric placement of a groove with a V-shaped groove relative to the crystal orientation of the semiconductor wafer.

[0013] Figure 4This is a flowchart of a method for forming a semiconductor structure having a semiconductor material according to various aspects of the present invention, wherein the semiconductor material fills a groove having a V-shaped groove.

[0014] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Figure 5F Based on some embodiments Figure 4 Cross-sectional views of semiconductor structures at various manufacturing stages constructed using the methods described in the paper.

[0015] Figure 6 These are example diagrams of temperature and time parameters for epitaxial growth processes according to some embodiments. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or above a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various embodiments. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another (or other) element or component as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] The increasing speed and computing power of microelectronic devices have recently necessitated a demand for greater complexity and functionality in semiconductor structures, from which these devices are fabricated. Heterogeneous integration of different semiconductor materials (e.g., III-V materials such as gallium arsenide, gallium nitride, indium aluminum arsenide, and / or germanium) and silicon or silicon-germanium substrates) is an attractive avenue for enhancing the functionality and performance of semiconductor devices. However, when a crystalline material is epitaxially grown on substrates of different kinds of materials, dislocation defects—often referred to as “heterogeneous structures”—are commonly introduced due to the different crystal lattice sizes of the two materials (called “lattice mismatch”). This lattice mismatch between the initial substrate and subsequent layers generates stress during material deposition, which in turn generates dislocation defects in the semiconductor structure. These dislocation defects (or, for simplicity, “dislocations”) form at the mismatched interfaces to mitigate mismatch strain. Dislocations can have vertical assemblies that continuously extend through all the semiconductor layers subsequently added to the heterostructure, terminating at the surface. When forming semiconductor devices such as diodes, lasers, and transistors on such heterostructures, dislocations in the active region can significantly degrade device performance.

[0019] Therefore, there is a need in the art for a general and efficient method for fabricating semiconductor heterostructures that would limit dislocations in materials with various lattice mismatches. There is also a need in the art for semiconductor devices utilizing combinations of integrated lattice mismatched materials (with reduced dislocation levels) to improve functionality and performance.

[0020] According to various embodiments, the present invention generally relates to the fabrication of lattice-mismatched semiconductor heterostructures and the fabrication of semiconductor devices based on such lattice-mismatched heterostructures, wherein certain regions of the semiconductor heterostructure have an upper portion that is substantially free of dislocations.

[0021] Figures 1A to 1C Three orientations of silicon crystal planes are shown. Silicon is widely used as a semiconductor material in the electronics industry. Most silicon used to form silicon wafers is formed from single-crystal silicon. Silicon wafers are used as substrates on which field-effect transistor (FET) devices are formed. Although described in conjunction with silicon substrates, the use of substrates comprising or substantially composed of other semiconductor materials is contemplated within the scope of this invention.

[0022] In crystalline silicon, the atoms that make up the solid are arranged in a periodic manner. If a periodic arrangement exists throughout the solid, the material is defined as being formed from a single crystal. If the solid consists of numerous single-crystal regions, the solid is called a polycrystalline material. The periodic arrangement of atoms in a crystal is commonly referred to as a “lattice.” The crystal lattice also contains a volume representing the entire lattice and is called a unit cell, which repeats regularly throughout the crystal. For example, silicon has a rhombic cubic lattice structure, which can be represented as two intersecting face-centered cubic lattices. Therefore, the simplification of analyzing and visualizing cubic lattices can be extended to the characterization of silicon crystals. In the description herein, reference is made to the various crystal planes in silicon crystals, particularly the (100), (110), and (111) planes. These planes define the orientation of the silicon atoms relative to the theoretical crystal axes. The numbers (xys) are called Miller indices and are determined by the reciprocals of the points where the silicon crystal planes intersect the theoretical crystal axes. Figure 1A In this configuration, the silicon crystal plane intersects the x-axis at point 1, but not the y-axis or z-axis. Therefore, the orientation of this type of crystalline silicon is represented as (100). Similarly, Figure 1B (110) crystalline silicon is shown and Figure 1C Silicon (111) is shown. Notably, for any given face in a cubic crystal, there are five other equivalent faces. Thus, all six faces of a cube, which comprises the basic unit cell of the crystal, are considered to be (100) faces. The symbol {xyz} refers to all six equivalent (xyz) faces. Throughout the specification, crystal orientations such as

[100] ,

[110] , and

[111] will be referenced. These are defined as the normal directions of the corresponding faces. Thus, the

[100] direction is the direction perpendicular to the (100) face. Similarly, for any given crystal orientation, there are five other equivalent directions. Symbols <xyz>This refers to all six equivalent directions.

[0023] Figure 2A This is a perspective view of a semiconductor structure 200 (or structure 200) according to various aspects of the present invention. Structure 200 may be an intermediate device manufactured during the processing of an integrated circuit (IC) or a portion thereof, which may include static random access memory (SRAM) and / or other logic circuits, passive components (such as resistors, capacitors, inductors) and active components (such as p-type FETs, n-type FETs, dual-gate FETs, tri-gate FETs, FinFETs, MOSFETs, CMOS transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells) and combinations thereof.

[0024] Figure 2A The design has been simplified to more clearly and better illustrate the concept of the invention. Additional components may be incorporated into structure 200, and for other embodiments of structure 200, some components described below may be replaced or eliminated. Figure 2A The structure 200 has multiple grooves 202, each groove 202 having a V-shaped groove (also called an inverted triangular groove) located at its bottom. Figure 2B and Figure 2C This relates to cross-sections taken along the transverse direction of the groove 202 (e.g., along line A-A') and along the longitudinal direction of the groove 202 (e.g., along line B-B'). These are described together herein. Figure 2A , Figure 2B and Figure 2C .

[0025] Structure 200 includes a substrate 204 and various components formed therein or on it. Substrate 204 includes a first semiconductor material (e.g., a group IV element) or other suitable semiconductor material, such as germanium or silicon. The first semiconductor material may be crystalline. For example, substrate 204 may be a bulk silicon wafer, a bulk germanium wafer, a semiconductor-on-insulator (SOI) substrate, or a strained semiconductor-on-insulator (SSOI) substrate. In the illustrated embodiment, substrate 204 comprises or is substantially composed of (001) silicon. Substrate 204 may include a material having a first conductivity type (such as n-type or p-type).

[0026] Structure 200 also includes an isolation member 206 surrounding a portion of substrate 204. Isolation member 206 may be formed of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. Isolation member 206 may be a shallow trench isolation (STI) member. In one embodiment, the depth h1 of isolation member 206 is in the range of about 30 nm to about 250 nm. In another embodiment, the depth h1 of isolation member 206 is in the range of about 200 nm to about 300 nm. Isolation member 206 has generally vertical sidewalls 210, i.e., disposed at about 80° to about 100° relative to the top surface of substrate 204, and in a particular embodiment, substantially perpendicular to the top surface of substrate 204. In yet another embodiment, sidewalls 210 may be non-vertical, for example, along the shown inclined dashed line 212, such as about 60° to about 80° or about 100° to about 120° relative to the top surface of substrate 204. The non-vertical sidewalls 210 can be generated by different etch rates at different depths during the trench formation process used to fill the isolation component 206. The isolation component 206 defines individual semiconductor regions 208.

[0027] In the illustrated embodiment, each semiconductor region 208 includes a recess 202 formed therein. The recess 202 has a V-shaped (or, generally considered, inverted triangular) lower portion (represented as V-groove 214) surrounded by a substrate 204 and a generally rectangular upper portion (represented as R-groove 216) surrounded by an isolation member 206. In the illustrated embodiment, the depth of the recess 202 is represented as h2, the depth of the R-groove 216 as h3, and the widths of the V-groove 214 and the R-groove 216 as w. In some embodiments, the depth h2 of the recess 202 is in the range of about 200 nm to about 700 nm. In some embodiments, the depth h3 of the R-groove 216 is about 5 nm to about 50 nm smaller than the depth h1 of the isolation member 206. The recesses 202 are separated and isolated from each other by the isolation member 206.

[0028] In the illustrated embodiment, the two sidewalls 218 of the V-groove 214 intersect each other at their apex, defining a V-shape in the cross-sectional view of the V-groove 214. In various embodiments, the V-groove 214 and the R-groove 216 are formed by recessing the top surface of the substrate 204 in one or more etching processes. Typically, the forming solution of the V-groove 214 may also expose the (111) crystal planes of the substrate 204 in the sidewalls 218 and 220. For example, the V-groove 214 can be formed by applying an etchant selective to the (111) crystal planes of silicon (such as by using a potassium hydroxide (KOH) solution) to the substrate 204. Silicon atoms exhibit a hexagonal arrangement in the (111) crystal planes. In the silicon lattice, the (111) and (001) crystal planes form an angle of 54.7°. The sidewalls 218 form an angle α relative to the top surface of the substrate 204. Due to process variations during etching, the angle α is about 54.7°, such as from about 45° to about 59°. In some embodiments, angle α is equal to or less than 54.7°. In some embodiments, the two sidewalls 218 form an angle β equal to or greater than 70.5°. (Cross-sectional view along the longitudinal direction of groove 202) Figure 2C In this embodiment, the sidewall 220 of the V-groove 214 can form an angle γ relative to the top surface of the substrate 204, the angle γ being substantially the same as the angle α. In some embodiments, the dimensions of the V-groove 214 (such as the depth (h2-h3), width w, and length s of the sidewall 220) have the following relationship:

[0029]

[0030] The sidewall 218 of the V-groove 214 also intersects with the sidewall 210 of the isolation member 206. In the illustrated embodiment, the bottom portion of the isolation member 206 is located below the top portion of the sidewall 218 and above the bottom portion of the V-groove 214. In some embodiments, the bottom portion of the isolation member 206 also extends into the substrate 204 and is also located below the bottom portion of the V-groove 214.

[0031] The isolation member 206 surrounds an R-groove 216 above the V-groove 214. The R-groove 216 is typically a rectangle having a width w and a length l. The width w may be less than the length l. In some embodiments, w ranges from about 50 nm to about 1000 nm. In some embodiments, w ranges from about 100 nm to about 500 nm. In a specific example, w is about 400 nm. The length l can extend from about tens of nanometers to about several thousand nanometers.

[0032] A regenerated layer 230, comprising a second semiconductor material, fills the groove 202. The second semiconductor material may be a crystalline semiconductor material. In some embodiments, the second semiconductor material exhibits a lattice mismatch with the first semiconductor material in the substrate 204. In various embodiments, the first semiconductor material may include or be composed of silicon, germanium, or a silicon-germanium alloy. The second semiconductor material may include or be composed of Group II, III, IV, V, and / or VI elements and / or combinations thereof, for example, selected from the group consisting of germanium, silicon-germanium, gallium arsenide, aluminum antimony, indium aluminum antimony, indium antimony, indium arsenide, indium phosphide, and gallium nitride. In a specific embodiment, the first semiconductor material comprises germanium, and the second semiconductor material comprises indium arsenide.

[0033] Since the interface between the first and second semiconductor materials is essentially a (111) crystal plane, dislocations 240 are generated from the (111) crystal plane due to lattice mismatch. The inventors of this invention have observed that dislocations originating from the (111) crystal plane primarily follow... <110> The direction (such as [-110] or

[110] direction) propagates through the second semiconductor material and terminates at another (111) crystal plane. <110> The orientation is parallel to the crystal orientation of the top surface of the (001) semiconductor substrate. This dislocation propagation mode is called the "Taylor mode". The Taylor mode helps to release the strain between lattice-mismatched semiconductor layers and confine dislocations to the region between the two (111) crystal planes. In the illustrated embodiment, as Figure 2B As shown, dislocation 240 originates from a sidewall 218 on one side of the V-groove 214 and propagates in a direction substantially parallel to the top surface of the substrate 204, terminating on a sidewall 218 on the other side of the V-groove 214. Due to the geometry of the groove 202, dislocation 240 is confined to the bottom of the groove 202 and does not propagate to the R-groove 216 above. Therefore, the upper portion of the regrown layer 230 is substantially dislocation-free, allowing the semiconductor device formed therein to have enhanced performance. This substantially dislocation-free region of the regrown layer 230 has substantially the same dimensions as the R-groove 216, having a width w and a length l. As discussed above, w and l can be hundreds or thousands of nanometers, thus providing space for a relatively large number of transistors, such as FinFETs formed therein.

[0034] Figure 3A and Figure 3B Some exemplary orientations of the recess 202 relative to a crystal orientation on a semiconductor wafer are shown. The semiconductor wafer 300 has a crystal orientation 302 located on its top surface, such as an

[110] orientation or a

[100] orientation. In some embodiments, the semiconductor wafer 300 has a notch 304 located at its edge to mark the crystal orientation 302. In the illustrated embodiment, a plurality of fins 306 are formed on a second semiconductor material in the recess 202. In some embodiments, the fins 306 include a channel region disposed between a pair of opposing source / drain components. The flow of carriers (electrons for an n-channel FinFET, holes for a p-channel FinFET) through the channel region is controlled by applying a voltage to a gate stack adjacent to and overlapping the fins 306 in the channel region. The fins 306 and their channel regions are oriented in the same direction as the longitudinal direction of the recess 202. Therefore, the orientation of the recess 202 determines the orientation of the channel region relative to the crystal orientation 302. Some orientations of the recess 202 provide better carrier mobility in the channel region than others. For example, as shown... Figure 3A As shown, in one embodiment, crystal orientation 302 is in the

[110] direction, and the longitudinal orientation of groove 202 is parallel or perpendicular to the

[110] direction. Figure 3B As shown, in another embodiment, the crystal orientation 302 is the

[100] direction, and the longitudinal orientation of the groove 202 is at an angle of 45° or 135° relative to the

[100] direction.

[0035] Figure 4 A flowchart is shown of a method 400 for manufacturing a semiconductor device 500 (or structure 500) having a V-groove 214 according to various aspects of the present invention. Structure 500 may be substantially similar in many respects to Figure 2A Structure 200. Additional steps may be added before, during, and after method 400, and some described operations may be replaced or eliminated for other embodiments of method 400. The following is in conjunction with... Figures 5A to 5F and Figure 6 Description method 400. Figures 5A to 5F A cross-sectional view of structure 500 at various stages of method 400 according to some embodiments is shown. Figure 6 The temperature and time parameters used in the exemplary epitaxial growth process are shown.

[0036] First refer to Figure 4 Box 402 and Figure 5A The receiving structure 500 includes a substrate 204 on which a recess 202 will be formed. In various examples, the substrate 204 includes elemental semiconductors, such as silicon or germanium with a crystalline structure; compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; non-semiconductor materials, such as soda-lime glass, fused silica, and / or calcium fluoride (CaF2); and / or combinations thereof.

[0037] Substrate 204 may be homogeneous in composition or may comprise multiple layers, some of which may be selectively etched to form recesses 202. The layers may have similar or different compositions, and in various embodiments, some substrate layers have non-uniform compositions to induce device strain and thus modulate device performance. Examples of multilayer substrates include silicon-on-insulator (SOI) substrates. In some such examples, the layers of substrate 204 may comprise insulators, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and / or other suitable insulating materials. In the illustrated embodiment, substrate 204 comprises or is substantially composed of (001) silicon. Substrate 204 may also be doped to have a first conductivity type such as n-type or p-type.

[0038] Reference Figure 4 The box 404 and Figure 5B An isolation member 206 is formed in substrate 204. In one embodiment, forming the isolation member 206 includes: forming a hard mask having openings (defining a region for the isolation member 206), etching the substrate 204 through the openings of the hard mask to form trenches, and depositing a dielectric material to fill the trenches. Suitable dielectric materials for the isolation member 206 include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-k dielectric materials, and / or other suitable dielectric materials. The isolation member 206 may be an STI member. The sidewalls of the isolation member 206 may be non-perpendicular to the top surface of the substrate 204. Frame 404 may also include a chemical mechanical polishing (CMP) process to remove excess dielectric material.

[0039] Reference Figure 4 Box 406 and Figure 5C The substrate 204 is etched to form a recess 202 between the isolation members 206. In various embodiments, the recess 202 comprises two parts: a V-groove 214 at the bottom and an R-groove 216 at the top. The V-groove 214 may have a maximum depth corresponding to the deepest point furthest from the substrate surface and exhibit a V-shaped profile. In one embodiment, the sidewalls 218 of the V-groove 214 are characterized as non-(001) crystal planes of a first semiconductor material in the substrate 204, such as (111) crystal planes (e.g., (111) silicon surfaces). To etch the substrate 204, the etching process may include any suitable etching technique such as wet etching, dry etching, reactive ion etching (RIE), ashing, and / or other etching methods. For example, dry etching processes may employ oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or plasma and / or combinations thereof. For example, wet etching processes may include etching with diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchants. The etchant 510 used in the etching process does not (or minimally) etch the isolation component 206. Therefore, the isolation component 206 is substantially retained after etching the substrate 204. In some embodiments, the etching process includes multiple etching steps with different etching chemicals, each targeting a specific portion of the substrate 204, and each chemical is selected not to etch the isolation component 206. For example, the etching process may include isotropic etching to first form R-groove 216, followed by wet etching using KOH or NaOH to form V-groove 214, wherein KOH or NaOH is selective for the (111) crystal plane of the first semiconductor material.

[0040] Reference Figure 4 Box 408 and Figure 5D A regenerated layer 230 comprising a second semiconductor material is formed within the groove 202, thereby filling the V-groove 214 and the R-groove 216. The second semiconductor material may comprise a III-V material (such as GaAs, InAs, or InP), a type IV material (such as Ge or SiGe), or an alloy or mixture comprising any of these materials (such as InGaP). The second semiconductor material is compositionally different from the first semiconductor material. Therefore, the epitaxial growth is heteroepitaxial growth. Specifically, the first semiconductor material has a first lattice constant, and the second semiconductor material has a second lattice constant different from the first lattice constant. Therefore, a lattice mismatch exists at the interface between the first and second semiconductor materials. In one example, the lattice mismatch is 4% or greater. Dislocations due to the lattice mismatch are generated from a sidewall 218, along... <110> The dislocations propagate in the direction of growth and terminate at the other sidewall 218, forming a Taylor pattern. Therefore, the upper part of the regenerated layer 230 in the region of R-groove 216 is essentially free of dislocations.

[0041] The regenerated layer 230 can be formed in the groove 202 by epitaxial growth in any suitable epitaxial deposition system (including but not limited to atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), ultra-high vacuum CVD (UHVCVD)), molecular beam epitaxy (MBE), or atomic layer deposition (ALD). In CVD processes, epitaxial growth typically involves introducing a source gas into the chamber. The source gas may include at least one precursor gas and a carrier gas (such as hydrogen). The reaction chamber may be heated, for example, by RF heating. Depending on the composition of the regenerated layer 230, the growth temperature in the chamber ranges from about 300°C to about 900°C. The epitaxial growth system may also utilize low-energy plasma to enhance layer growth kinetics. The epitaxial growth system may be a single-wafer or multi-wafer batch reactor.

[0042] In one embodiment, the first semiconductor material in the substrate 204 is silicon, and the second semiconductor material in the regenerated layer 230 is indium arsenide (InAs). Figure 6 The diagram illustrates exemplary epitaxial growth parameters used in a CVD process. Epitaxial growth can begin by preheating the silicon substrate to a temperature Temp4 for a duration of t1. As an example, t1 can be approximately 9 to 11 minutes, such as 10 minutes, and Temp4 can be in the range of approximately 600°C to approximately 800°C, such as 720°C. In the next step, a tert-butylarsine (TBA) pre-flow gas is introduced at a temperature Temp3 for a duration of t2. Temp3 can be in the range of approximately 500°C to approximately 600°C, and t2 can be in the range of approximately 3 to 7 minutes, such as 5 minutes. Then, an InAs buffer gas is introduced at a relatively low temperature Temp1 for a duration of t3. Temp1 can be in the range of approximately 300°C to approximately 350°C, and t1 can be in the range of approximately 8 to 12 minutes, such as 10 minutes. Epitaxial growth then continues at a temperature Temp2 for a duration of t4. Temp2 can be in the range of about 400°C to about 550°C, and t4 can be in the range of about 8 minutes to 12 minutes, such as 10 minutes. During the CVD process, the V / III ratio process parameters are in the range of about 50 to about 150, the gas pressure is in the range of about 50 Torr to 200 Torr, and the total gas flow is in the range of about 6000 sccm to about 9000 sccm.

[0043] Epitaxial growth selectively grows a second semiconductor material over the first semiconductor material in the trench 202. To ensure complete filling of the V-groove 214 and R-groove 216, the second semiconductor material is overgrown to a considerable extent, resulting in an excess portion of the second semiconductor material over the isolation member 206. In one example, the overgrown portion of the second semiconductor material over the isolation member 206 has a thickness between about 100 nm and about 1000 nm. In another example, the overgrown portion has a thickness of about 500 nm. After the epitaxial growth of the second semiconductor material, a polishing process such as CMP can be performed to remove the overgrown portion and planarize the top surface of the structure 500.

[0044] Reference Figure 4 Box 410 and Figure 5E The second semiconductor material in the upper portion of the regrown layer 230 is patterned to form a plurality of fins 306. This may include forming a hard mask on the regrown layer 230 and patterning the regrown layer 230 to define the fins 306. The hard mask may include a dielectric, such as silicon oxide, silicon nitride, silicon oxynitride, and / or silicon carbide. The hard mask may be formed to any suitable thickness and by any suitable process, including thermal growth, chemical vapor deposition (CVD), high-density plasma CVD (HDP-CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other suitable deposition processes. To pattern the hard mask, frame 408 may include various processes such as photolithography and etching. The photolithography process may include forming a photoresist over the structure 500. Exemplary photoresist includes a radiation-sensitive photosensitive material that radiates light such as UV light, deep ultraviolet (DUV) radiation, and / or EUV radiation. Photolithographic exposure is performed on the structure 500, exposing selected portions of the photoresist to radiation. Exposure causes a chemical reaction in the exposed areas of the photoresist. After exposure, a developer is applied to the photoresist. The developer dissolves or removes the exposed areas (in the case of a positive photoresist development process) or the unexposed areas (in the case of a negative photoresist development process). Suitable positive developers include TMAH (tetramethylammonium hydroxide), KOH, and NaOH, and suitable negative developers include solvents such as n-butyl acetate, ethanol, hexane, benzene, and toluene. After developing the photoresist, the exposed portions of the hard mask can be removed by etching processes such as wet etching, dry etching, RIE, ashing, and / or other etching methods, resulting in a patterned hard mask. After etching, the photoresist can be removed.

[0045] Subsequently, the regenerated layer 230 is etched using a patterned hard mask to define the fin 306. The etching process may include any suitable etching technique such as wet etching, dry etching, RIE, ashing, and / or other etching methods. The remainder of the regenerated layer 230 becomes the fin 306, defining a trench 518 located between the fin 306 and the isolation member 206.

[0046] Reference Figure 4 Box 412 and Figure 5F The trench 518 is filled with a dielectric material to form an isolation (STI) component 520. The STI component 520 is surrounded by an isolation component 206. The STI component 520 also surrounds each fin 306 to isolate them. Suitable dielectric materials for the STI component 520 include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-k dielectric materials, and / or other suitable dielectric materials. The dielectric material can be deposited by any suitable technique including thermal growth, CVD, HDP-CVD, PVD, ALD, and / or spin coating. The formation of the STI component 520 may also include the steps of planarizing the top surface of the structure 500 and removing excess dielectric material, and recessing the STI component 520 by selective etching. In some embodiments, selective etching may also recess the isolation component 206. In some embodiments, the isolation member 206 has etch selectivity towards the STI member 520, and the selective etching includes multiple etching steps, each targeting a different material composition, such as recessing the STI member 520 in one step and recessing the isolation member 206 in another step. In some embodiments, the top surface of the substrate 204 is also recessed during selective etching. After selective etching, in an embodiment, the top of the fin 306 extends outward from the STI member 520, while the bottom of the fin 306 remains surrounded by the STI member 520.

[0047] Although Figure 4 As not shown, method 400 may involve further processes to complete the fabrication of structure 500. For example, method 400 may form a FinFET on fin 306, including forming a gate stack, source / drain (S / D) regions and S / D contacts that are bonded to the top of the fin, as well as a multilayer interconnect structure that connects the gate stack and S / D contacts to other portions of structure 500 to form a complete IC.

[0048] While not intended to be limiting, one or more embodiments of the present invention provide numerous benefits for semiconductor devices (including FinFETs) and their fabrication. For example, embodiments of the present invention provide semiconductor heterostructures with significantly minimized interface defects and methods for fabricating them, overcoming limitations of known techniques. In various embodiments, the present invention produces regions with relatively large areas in the hundreds or thousands of nanometers to have upper portions that are substantially free of dislocations. Therefore, the present invention contemplates the fabrication of semiconductor devices based on monolithic lattice mismatch heterostructures, which has long been sought in the art but has been impractical to date due to dislocation defects.

[0049] In one exemplary aspect, the invention relates to a structure. The structure includes: a substrate comprising a first semiconductor material; a dielectric component embedded in the substrate; and a second semiconductor material embedded in the substrate, the second semiconductor material having a lattice mismatch with the first semiconductor material, the second semiconductor material having two upper sidewalls and two lower sidewalls, the two upper sidewalls contacting the dielectric component, the two lower sidewalls contacting the substrate, the two lower sidewalls not perpendicular to the top surface of the substrate, and the lowest portion of the dielectric component being lower than the highest portion of the two lower sidewalls. In an embodiment, one of the two lower sidewalls defines a first angle relative to the top surface of the substrate, the first angle being in the range of 45° to 59°. In an embodiment, the lowest portion of the dielectric component is lower than the lowest portion of the two lower sidewalls. In an embodiment, one of the two lower sidewalls includes a hexagonal crystal plane. In an embodiment, one of the two lower sidewalls includes a (111) crystal plane defined by the first semiconductor material. In an embodiment, the second semiconductor material includes dislocations due to lattice mismatch, the dislocations originating from one of the two lower sidewalls and terminating at the other of the two lower sidewalls. In this embodiment, dislocations propagate in a crystal orientation parallel to the top surface of the substrate. In this embodiment, the substrate is (001) silicon, and the crystal orientation is defined by (001) silicon. <110> Direction. In one embodiment, the two lower sidewalls intersect at the apex, thereby defining an inverted triangular groove between the two lower sidewalls, the top width of which is at least [amount missing] of the depth of the inverted triangular groove. The width of the top of the inverted triangular trench is at least 50 nm. In one embodiment, the two upper sidewalls are not perpendicular to the top surface of the substrate. In another embodiment, the second semiconductor material includes a plurality of fins, and the structure further includes shallow trench isolation (STI) components surrounding each of the plurality of fins.

[0050] In another exemplary aspect, the invention relates to a structure. This structure includes: a substrate comprising a first semiconductor material, the substrate having a recess, the bottom of the recess having a first sidewall and a second sidewall intersecting the second sidewall; an isolation member surrounding the recess; and a second semiconductor material disposed in the recess and in contact with the first semiconductor material, the second semiconductor material having a lattice mismatch with the first semiconductor material, dislocations in the lattice mismatched second semiconductor material propagating from the first sidewall to the second sidewall in a direction parallel to the top surface of the substrate. In an embodiment, the first semiconductor material is (001) silicon, and the direction is defined by the (001) silicon. <110> Crystal orientation. In an embodiment, the first sidewall includes a (111) crystal plane defined by (001) silicon. In an embodiment, the first sidewall and the second sidewall intersect at a vertex to define a V-groove between the first sidewall and the second sidewall, the V-groove having a top opening having a width, and a distance from the vertex to the top opening, the width being at least a fraction of the distance. times.

[0051] In another exemplary aspect, the invention relates to a method. The method includes: receiving a semiconductor substrate; forming a first isolation member surrounding a portion of the semiconductor substrate; recessing a portion of the semiconductor substrate to form an opening in the semiconductor substrate, the opening extending longitudinally in a first direction, the bottom of the opening having a V-shape in a plane perpendicular to the first direction; epitaxially growing a crystalline semiconductor material in the opening; patterning the crystalline semiconductor material to form a plurality of fins, each of the plurality of fins extending longitudinally in the first direction; and forming a second isolation member surrounding each of the plurality of fins, the second isolation member being surrounded by the first isolation member. In an embodiment, the semiconductor substrate is a crystal structure defining a

[110] direction along the top surface of the semiconductor substrate; and the first direction is substantially parallel to or substantially perpendicular to the

[110] direction. In an embodiment, the lowest portion of the first isolation member is lower than the lowest portion of the opening. In an embodiment, the crystalline semiconductor material includes indium.

[0052] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the invention.< / xyz>

Claims

1. A semiconductor structure, comprising: Substrate, comprising a first semiconductor material; Dielectric components are embedded in the substrate; A second semiconductor material is embedded in the substrate and disposed in a groove of the substrate, wherein, in a cross-sectional view along the transverse direction of the groove, the groove has a V-shaped groove surrounded by the substrate and a rectangular R-groove surrounded by the dielectric member, the second semiconductor material having a lattice mismatch with the first semiconductor material, the second semiconductor material having two upper sidewalls and two lower sidewalls, the two upper sidewalls contacting the dielectric member and defining the R-groove, the two lower sidewalls contacting the substrate and intersecting at their apexes to define the V-groove, the two lower sidewalls not perpendicular to the top surface of the substrate, the bottom portion of the dielectric member being lower than the top portion of the two lower sidewalls, wherein, in a cross-sectional view along the transverse direction of the groove and in a cross-sectional view along the longitudinal direction of the groove, the sidewalls of the V-groove form an angle of 45° to 59° relative to the top surface of the substrate; Multiple fins, formed of the second semiconductor material and located on the second semiconductor material disposed in the same groove; and Shallow groove isolation components, surrounding each of the plurality of fins, The shallow trench isolation member and the dielectric member surround the lower portion of the plurality of fins, while the upper portion of the plurality of fins protrudes from the shallow trench isolation member and the dielectric member. The dielectric member extends from the top surface of the shallow trench isolation member to a position below the bottom surface of the shallow trench isolation member. The shallow trench isolation member is disposed within the lateral range enclosed by the dielectric member. The second semiconductor material includes dislocations due to lattice mismatch, which originate from a sidewall on one side of the V-groove and propagate in a direction substantially parallel to the top surface of the substrate, terminating on a sidewall on the other side of the V-groove. The dislocations are confined within the V-groove and do not propagate to the R-groove above. The semiconductor wafer with the groove formed has a notch located at the edge of the semiconductor wafer, thereby representing a first crystal orientation in the [110] direction or the [100] direction, and wherein the longitudinal orientation of the groove is parallel or perpendicular to the first crystal orientation, or the longitudinal orientation of the groove is at an angle of 45° or 135° relative to the first crystal orientation. The two upper sidewalls are not perpendicular to the top surface of the substrate, and the two upper sidewalls are inclined toward the bottommost part of the two lower sidewalls. In the top view, the dielectric component surrounds the second semiconductor material beneath the plurality of fins from four sides, and the dielectric component is further surrounded by the substrate, wherein the top surface of the dielectric component is higher than the top surface of the second semiconductor material beneath the plurality of fins and flush with the top surface of the substrate.

2. The semiconductor structure according to claim 1, wherein, The first semiconductor material includes germanium, and the second semiconductor material includes indium arsenide.

3. The semiconductor structure according to claim 2, wherein, The lowest portion of the dielectric component is lower than the lowest portion of the two lower sidewalls.

4. The semiconductor structure according to claim 1, wherein, One of the two lower sidewalls includes a hexagonal crystal facet.

5. The semiconductor structure according to claim 1, wherein, One of the two lower sidewalls includes a (111) crystal plane defined by the first semiconductor material.

6. The semiconductor structure according to claim 1, wherein, The width of the R-groove in the transverse direction is less than its length in the longitudinal direction.

7. The semiconductor structure according to claim 6, wherein, The width of the R-groove is in the range of 50nm to 1000nm.

8. The semiconductor structure according to claim 1, wherein, The substrate is (001) silicon, and the first crystal orientation is defined by the (001) silicon. <110> direction.

9. The semiconductor structure according to claim 1, wherein, The top width of the V-groove is at least [amount missing] of the depth of the V-groove. times.

10. The semiconductor structure according to claim 9, wherein, The top width of the V-groove is at least 50 nm.

11. The semiconductor structure according to claim 1, wherein, The two lower sidewalls form an angle equal to or greater than 70.5°.

12. The semiconductor structure according to claim 1, wherein, The second semiconductor material includes indium.

13. A semiconductor structure comprising: A substrate, comprising a first semiconductor material, said substrate having a groove; A dielectric component surrounds the groove, wherein, in a cross-sectional view along the transverse direction of the groove, the groove has a V-shaped V-groove surrounded by the substrate and a rectangular R-groove surrounded by the dielectric component, the V-groove having a first sidewall and a second sidewall intersecting the second sidewall, wherein, in a cross-sectional view along the transverse direction of the groove and in a cross-sectional view along the longitudinal direction of the groove, the sidewalls of the V-groove form an angle of 45° to 59° relative to the top surface of the substrate; A second semiconductor material is disposed in the groove and in contact with the first semiconductor material. The second semiconductor material has a lattice mismatch with the first semiconductor material. Dislocations in the lattice mismatched second semiconductor material propagate from the first sidewall of the V-groove to the second sidewall in a direction parallel to the top surface of the substrate. The dislocations are confined in the V-groove and do not propagate to the R-groove above. Multiple fins, formed of the second semiconductor material and located on the second semiconductor material disposed in the same groove; and Shallow groove isolation components, surrounding each of the plurality of fins, The shallow trench isolation member and the dielectric member surround the lower part of the plurality of fins, while the upper part of the plurality of fins protrudes from the shallow trench isolation member and the dielectric member. The dielectric member extends from the top surface of the shallow trench isolation member to a position below the bottom surface of the shallow trench isolation member, and the shallow trench isolation member is disposed within the lateral range enclosed by the dielectric member. The second semiconductor material further comprises a third sidewall and a fourth sidewall in contact with the dielectric component. The third and fourth sidewalls are not perpendicular to the top surface of the substrate, and are inclined toward the bottommost portions of the first and second sidewalls. The semiconductor wafer with the groove formed has a notch located at the edge of the semiconductor wafer, thereby representing a first crystal orientation in the [110] direction or the [100] direction, and wherein the longitudinal orientation of the groove is parallel or perpendicular to the first crystal orientation, or the longitudinal orientation of the groove is at an angle of 45° or 135° relative to the first crystal orientation. In the top view, the dielectric component surrounds the second semiconductor material beneath the plurality of fins from four sides, and the dielectric component is further surrounded by the substrate, wherein the top surface of the dielectric component is higher than the top surface of the second semiconductor material beneath the plurality of fins and flush with the top surface of the substrate.

14. The semiconductor structure according to claim 13, wherein, The first semiconductor material is (001) silicon, and the direction is defined by the (001) silicon. <110> Crystal orientation.

15. The semiconductor structure according to claim 14, wherein, The first sidewall includes a (111) crystal plane defined by the (001) silicon.

16. The semiconductor structure according to claim 13, wherein, The first sidewall and the second sidewall intersect at a vertex, thereby defining a V-groove between the first sidewall and the second sidewall. The V-groove has a top opening with a width, and the vertex is at a distance from the top opening, the width being at least a fraction of the distance. times.

17. A method for forming a semiconductor structure, comprising: Receive semiconductor substrate; Forming a first isolation component surrounding a portion of the semiconductor substrate; The portion of the semiconductor substrate is recessed to form an opening in the semiconductor substrate, the opening extending longitudinally in a first direction, the bottom of the opening surrounded by the semiconductor substrate having a V-shape in a plane perpendicular to the first direction, thereby forming a V-groove at the bottom of the opening, and the opening also having a rectangular R-groove surrounded by the first isolation member, wherein, in a cross-sectional view along the first direction and in a plane perpendicular to the first direction, the sidewalls of the V-groove all form an angle of 45° to 59° relative to the top surface of the semiconductor substrate; A crystalline semiconductor material is epitaxially grown in the opening; The crystalline semiconductor material is patterned to form a plurality of fins, each of the plurality of fins extending longitudinally in the first direction, wherein the top surface of the plurality of fins is flush with the top surface of the first isolation member; and A second isolation member is formed around each of the plurality of fins, the second isolation member being surrounded by the first isolation member, wherein forming the second isolation member further includes making the first isolation member and the second isolation member recessed such that the top surface of the plurality of fins is higher than the top surface of the recessed first isolation member. The plurality of fins are disposed on the crystalline semiconductor material within the same V-groove. The crystalline semiconductor material includes dislocations due to lattice mismatch, which originate from a sidewall on one side of the V-groove and propagate in a direction substantially parallel to the top surface of the substrate, terminating on a sidewall on the other side of the V-groove. The dislocations are confined within the V-groove and do not propagate to the R-groove above. The recessing of the first isolation component and the second isolation component includes: The second isolation component is recessed using a first etching step with a first material composition; and A second etching step using a second material composition causes the first isolation member to be recessed, wherein the first material composition is different from the second material composition, and both the recessed first isolation member and the recessed second isolation member surround the bottom of the plurality of fins, while the tops of the plurality of fins protrude from the recessed first isolation member and the recessed second isolation member, wherein the recessed first isolation member extends from the top surface of the recessed second isolation member to a position below the bottom surface of the recessed second isolation member, and the recessed second isolation member is disposed within the lateral range enclosed by the recessed first isolation member. The epitaxial growth of the crystalline semiconductor material in the opening includes: The semiconductor substrate is heated to a first temperature; Pre-flow gas is introduced at the second temperature; Introducing a buffer precursor gas at the third temperature; and Continue epitaxial growth at the fourth temperature The relationship between the first temperature and the fourth temperature is: first temperature > second temperature > fourth temperature > third temperature.

18. The method of claim 17, wherein: The semiconductor substrate is a crystal structure defining a [110] direction, the [110] direction being along the top surface of the semiconductor substrate; and The first direction is parallel or perpendicular to the [110] direction.

19. The method of claim 17, wherein, The bottom portion of the first isolation component is lower than the bottom portion of the opening.

20. The method of claim 17, wherein, The crystalline semiconductor material includes indium.

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