Low power oscillator circuit

Abstract

The embodiment of the present disclosure discloses a low-power-consumption oscillator circuit, which comprises a voltage parameter generation module, a comparator, a digital auxiliary module, a latch and an oscillator, the voltage parameter generation module outputs a reference voltage and an actual voltage to the comparator; the comparator generates and outputs a first digital signal based on the proportional relationship between the actual voltage and the reference voltage; the digital auxiliary control module, in response to the actual voltage being equal to the reference voltage, sends a first indication signal for indicating turning off to the voltage parameter generation module and the comparator, outputs a second indication signal for indicating that the frequency range is unchanged, and controls the digital auxiliary module to turn off; the latch saves and continuously outputs the second indication signal; and the oscillator generates and outputs a first clock signal based on the second indication signal. By setting the digital auxiliary module, when the actual voltage is equal to the reference voltage, part of the devices is turned off, the frequency stability of the oscillator is ensured, and the power consumption of the oscillator circuit is reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of oscillators, and particularly relates to a low-power-consumption oscillator circuit. BACKGROUND

[0002] An oscillator is a frequency generating device that converts direct current power into alternating current power with a certain frequency, and the frequency of the oscillator can determine the size of the actual voltage generated by the oscillator circuit.

[0003] At present, the frequency of the oscillator is usually determined by an analog circuit module deployed in the oscillator circuit. When the actual voltage generated by the oscillator circuit does not reach the reference voltage, the analog circuit module can adjust the frequency of the oscillator by changing the size of the voltage output to the oscillator. When the actual voltage generated by the oscillator circuit is equal to the reference voltage, in order to keep the actual voltage generated by the oscillator circuit always equal to the reference voltage, the frequency of the oscillator needs to be kept in a stable state, and the analog circuit module needs to continuously output a stable size of voltage to the oscillator, which is easy to cause the power consumption of the oscillator circuit to be large.

[0004] Therefore, how to reduce the power consumption of the oscillator circuit while ensuring the stability of the frequency of the oscillator has become a technical problem to be solved. SUMMARY

[0005] In order to solve the problems in the related art, the present disclosure provides a low-power-consumption oscillator circuit.

[0006] In a first aspect, the present disclosure provides an oscillator circuit.

[0007] Specifically, the oscillator circuit comprises a voltage parameter generation module, a comparator, a digital auxiliary module, a latch and an oscillator, wherein

[0008] The first end of the voltage parameter generation module is connected with the first input end of the comparator, and the second end of the voltage parameter generation module is connected with the second input end of the comparator, the first end of the voltage parameter generation module is configured to output a reference voltage, and the second end of the voltage parameter generation module is configured to output an actual voltage.

[0009] The output end of the comparator is connected with the input end of the digital auxiliary module, and the comparator is configured to generate a first digital signal based on the proportional relationship between the actual voltage and the reference voltage, and output the first digital signal through the output end of the comparator.

[0010] An output terminal of the digital auxiliary module is connected with an input terminal of the latch, and the digital auxiliary module is configured to send a first instruction signal to the voltage parameter generation module and the comparator and output a second instruction signal, and control the digital auxiliary module to be turned off, in response to the fact that the first digital signals at a plurality of continuous time points before a current time point are the same, and the first digital signal at the current time point adjacent to the plurality of continuous time points is different from the plurality of continuous time points, wherein the first instruction signal is used to instruct the voltage parameter generation module and the comparator to be turned off, and the second instruction signal is used to instruct the frequency range of the oscillator to be unchanged;

[0011] An output terminal of the latch is connected with an input terminal of the oscillator, and the latch is configured to save and continuously output the second instruction signal through the output terminal of the latch;

[0012] The oscillator is configured to generate and output the first clock signal based on the received second instruction signal.

[0013] In an implementation manner of the present disclosure, the comparator is specifically configured to generate the first digital signal used to indicate that the judgment result is 0 through the output terminal of the comparator, in response to the fact that the proportional relationship between the actual voltage and the reference voltage is less than 1; or generate the first digital signal used to indicate that the judgment result is 1 through the output terminal of the comparator, in response to the fact that the proportional relationship between the actual voltage and the reference voltage is greater than 1.

[0014] In an implementation manner of the present disclosure, the digital auxiliary module is specifically configured to send the first instruction signal to the voltage parameter generation module and the comparator and output the second instruction signal, and control the digital auxiliary module to be turned off, in response to the fact that the first digital signals at a plurality of continuous time points before a current time point are all used to indicate that the judgment result is 0, and the first digital signal at the current time point adjacent to the plurality of continuous time points is used to indicate that the judgment result is 1, or in response to the fact that the first digital signals at a plurality of continuous time points before a current time point are all used to indicate that the judgment result is 1, and the first digital signal at the current time point adjacent to the plurality of continuous time points is used to indicate that the judgment result is 0.

[0015] In an implementation manner of the present disclosure, the digital auxiliary module is further configured to generate a third instruction signal based on a first preset algorithm and the current frequency range of the oscillator, and output the third instruction signal through the output terminal of the digital auxiliary module, in response to the fact that the first digital signals at a plurality of continuous time points before a current time point are the same, and the first digital signal at the current time point adjacent to the plurality of continuous time points is the same as the plurality of continuous time points, wherein the third instruction signal is used to indicate the first target frequency range of the oscillator.

[0016] In an implementation form of the present disclosure, the digital auxiliary module is further configured to, in response to the continuous multiple first digital signals before the current time all indicating the judgment result as 0, and the first digital signal at the current time adjacent to the multiple continuous first digital signals indicating the judgment result as 0, generate a third indication signal based on the first preset algorithm and the current frequency range of the oscillator, and output the third indication signal through the output end of the digital auxiliary module, where the third indication signal is used to instruct the oscillator to increase from the current frequency range to a first target frequency range.

[0017] Or, in response to the continuous multiple first digital signals before the current time all indicating the judgment result as 1, and the first digital signal at the current time adjacent to the multiple continuous first digital signals indicating the judgment result as 1, generate a third indication signal based on the first preset algorithm and the current frequency range of the oscillator, and output the third indication signal through the output end of the digital auxiliary module, where the third indication signal is used to instruct the oscillator to decrease from the current frequency range to a first target frequency range.

[0018] In an implementation form of the present disclosure, the latch is further configured to output the third indication signal through the output end of the latch.

[0019] In an implementation form of the present disclosure, the output end of the oscillator is connected with a third end of the voltage parameter generation module, and the oscillator is further configured to generate and output a second clock signal to the voltage parameter generation module based on the received third indication signal.

[0020] In an implementation form of the present disclosure, the voltage parameter generation module is further configured to adjust the size of the actual voltage based on the second clock signal.

[0021] In an implementation form of the present disclosure, the digital auxiliary module is further configured to, in response to the time difference between the time of sending the first indication signal, the second indication signal and the time of controlling the digital auxiliary module to turn off and the current time being greater than or equal to a preset time threshold, send a fourth indication signal to the voltage parameter generation module and the comparator respectively, and control the digital auxiliary module to turn on, where the fourth indication signal is used to instruct the voltage parameter generation module and the comparator to turn on.

[0022] In an implementation form of the present disclosure, the digital auxiliary module is further configured to, after sending the fourth indication signal and controlling the digital auxiliary module to turn on, in response to the continuous multiple first digital signals before the current time being the same, and the first digital signal at the current time adjacent to the multiple continuous first digital signals being the same as the multiple continuous first digital signals, generate a fifth indication signal based on a second preset algorithm and the current frequency range of the oscillator, and output the fifth indication signal through the output end of the digital auxiliary module, where the fifth indication signal is used to instruct a second target frequency range of the oscillator.

[0023] In an implementation form of the present disclosure, the latch is further configured to output a fifth indication signal through an output terminal of the latch.

[0024] In an implementation form of the present disclosure, the oscillator is further configured to generate and output a third clock signal to the voltage parameter generation module based on the received fifth indication signal.

[0025] In an implementation form of the present disclosure, the voltage parameter generation module is further configured to adjust the magnitude of the actual voltage based on the third clock signal.

[0026] In an implementation form of the present disclosure, the oscillator circuit further comprises a frequency divider, an input terminal of the frequency divider is connected with an output terminal of the oscillator, an output terminal of the frequency divider is connected with a third terminal of the voltage parameter generation module, the frequency divider is configured to generate and output a fourth clock signal based on a preset frequency reduction ratio and the second clock signal, or generate and output a fifth clock signal based on a preset frequency reduction ratio and the third clock signal.

[0027] In an implementation form of the present disclosure, the first preset algorithm is a successive approximation algorithm, and the second preset algorithm is a gradual algorithm.

[0028] The technical effects provided by the embodiments of the present disclosure can include the following beneficial effects:

[0029] The above technical solution, the voltage parameter generation module can output the reference voltage and the actual voltage to the comparator through the first terminal and the second terminal of the voltage parameter generation module respectively; the comparator can generate the first digital signal based on the proportional relationship between the actual voltage and the reference voltage, and output the first digital signal to the digital auxiliary module through the output terminal of the comparator; the digital auxiliary module, in response to the fact that the continuous multiple first digital signals before the current time are the same, and the first digital signal of the current time adjacent to the continuous multiple first digital signals is different from the continuous multiple first digital signals, indicates that the actual voltage is equal to the reference voltage, then sends the first indication signal for indicating turning off to the voltage parameter generation module and the comparator respectively, and outputs the second indication signal for indicating that the frequency grade of the oscillator is unchanged, and controls the digital auxiliary module to turn off; the latch can save and continuously output the received second indication signal to the oscillator; the oscillator can generate and output the first clock signal of the corresponding frequency based on the received second indication signal. Since the digital auxiliary module is used in the oscillator circuit, when it is judged that the actual voltage is equal to the reference voltage, the voltage parameter generation module, the comparator and the digital auxiliary module can be turned off, only the latch and the oscillator work, and the latch can continuously output the second indication signal for indicating that the frequency grade is unchanged to the oscillator, therefore, the power consumption of the oscillator circuit is reduced on the premise of ensuring the frequency stability of the oscillator.

[0030] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0031] Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description when read in connection with the accompanying drawings. In the drawings, a

[0032] Figure 1 A schematic diagram of an oscillator circuit according to an embodiment of the present disclosure is shown.

[0033] Figure 2 Another schematic diagram of an oscillator circuit according to an embodiment of the present disclosure is shown.

[0034] Figure 3 Another schematic diagram of an oscillator circuit according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0035] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so as to be easily implemented by those skilled in the art. Also, parts irrelevant to the description of the exemplary embodiments are omitted in the drawings for the sake of clarity.

[0036] In the present disclosure, it is to be understood that terms such as "include" or "have" are intended to indicate that there are constituents, numbers, steps, actions, parts, or combinations thereof disclosed in the specification, and are not intended to exclude the possibility of additional one or more other constituents, numbers, steps, actions, parts, or combinations thereof.

[0037] It is further noted that the embodiments and features of the present disclosure can be combined with each other, if not contrary. Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0038] As mentioned above, the frequency of the oscillator is usually determined by an analog circuit module provided in the oscillator circuit. When the actual voltage generated by the oscillator circuit does not reach the reference voltage, the analog circuit module can adjust the frequency of the oscillator by changing the size of the voltage output to the oscillator. When the size of the actual voltage generated by the oscillator circuit is equal to the reference voltage, in order to keep the actual voltage generated by the oscillator circuit always equal to the reference voltage, the frequency of the oscillator needs to be kept in a stable state, and the analog circuit module needs to continuously output a stable size of voltage to the oscillator, which is easy to cause the power consumption of the oscillator circuit to be large.

[0039] In view of the above defects, the embodiment of the present disclosure provides a low-power-consumption oscillator circuit, which comprises a voltage parameter generation module, a comparator, a digital auxiliary module, a latch and an oscillator. The voltage parameter generation module can output a reference voltage and an actual voltage to the comparator through the first end and the second end of the voltage parameter generation module, respectively; the comparator can generate a first digital signal based on the proportional relationship between the actual voltage and the reference voltage, and output the first digital signal to the digital auxiliary module through the output end of the comparator; the digital auxiliary module, in response to the fact that the continuous multiple first digital signals before the current time are the same, and the first digital signal of the current time adjacent to the continuous multiple first digital signals is different from the continuous multiple first digital signals, indicates that the actual voltage is equal to the reference voltage, then sends a first indication signal for indicating turning off to the voltage parameter generation module and the comparator, respectively, and outputs a second indication signal for indicating that the frequency grade of the oscillator is unchanged, and controls the digital auxiliary module to turn off; the latch can save and continuously output the received second indication signal to the oscillator, and the oscillator can generate and output a first clock signal of a corresponding frequency based on the received second indication signal. Since the oscillator circuit of the present disclosure adopts the digital auxiliary module, when it is judged that the actual voltage is equal to the reference voltage, the voltage parameter generation module, the comparator and the digital auxiliary module can be turned off, only leaving the latch and the oscillator to work, and the latch can continuously output the second indication signal for indicating that the frequency grade is unchanged to the oscillator, so that the power consumption of the oscillator circuit is reduced on the premise of ensuring the frequency stability of the oscillator.

[0040] Figure 1 A schematic diagram of an oscillator circuit according to an embodiment of the present disclosure is shown.

[0041] As shown in Figure 1 , the oscillator circuit comprises a voltage parameter generation module, a comparator, a digital auxiliary module, a latch and an oscillator.

[0042] The first end L1 of the voltage parameter generation module is connected with the first input end L4 of the comparator, the second end L2 of the voltage parameter generation module is connected with the second input end L5 of the comparator, the output end L6 of the comparator is connected with the input end L7 of the digital auxiliary module, the output end L8 of the digital auxiliary module is connected with the input end L9 of the latch, the output end L 10 of the latch is connected with the input end L 11 of the oscillator, and the output end L 12 of the oscillator is connected with the third end L3 of the voltage parameter generation module. The digital auxiliary module and the voltage parameter generation module have a communication link 1 and the comparator has a communication link 2, and the two can communicate.

[0043] Figure 2Another schematic diagram of the oscillator circuit according to an embodiment of the present disclosure is shown.

[0044] As shown in Figure 2 , the voltage parameter generation module includes a current source VDD, a resistor and an equivalent resistor. The resistor and the equivalent resistor can constitute a parallel circuit.

[0045] In an embodiment of the present disclosure, the equivalent resistor is equivalent to two switches and a capacitor.

[0046] In an embodiment of the present disclosure, the oscillator can be a voltage-controlled oscillator.

[0047] It should be understood that Figure 2 The connection relationship of other modules or devices shown in the oscillator circuit can refer to the introduction of the Figure 1 , and will not be described in detail.

[0048] The functions of each module or device in the oscillator circuit provided by the present disclosure and the working principle of the oscillator circuit will be introduced below in combination with Figure 1 and Figure 2 .

[0049] In the present disclosure, the working stage of the oscillator circuit includes three stages, namely the frequency adjustment stage, the frequency stabilization stage and the frequency error correction stage. The three stages will be described in detail below.

[0050] Frequency adjustment stage:

[0051] The first end L1 of the voltage parameter generation module is used to output a reference voltage, and the second end L2 of the voltage parameter generation module is used to output an actual voltage.

[0052] In the present disclosure, the current source VDD provides current for the resistor and the equivalent resistor. The current flows through the resistor to generate a reference voltage, which is output through the first end L1 of the voltage parameter generation module. In addition, the current flows through the equivalent resistor to generate an actual voltage, which is output through the second end L2 of the voltage parameter generation module.

[0053] It should be understood that the actual voltage output by the voltage parameter generation module is the current actual voltage.

[0054] The comparator is used to generate a first digital signal based on the proportional relationship between the actual voltage and the reference voltage, and output the first digital signal through the output end L6 of the comparator.

[0055] In an embodiment of the present disclosure, the comparator is specifically configured to generate a first digital signal for indicating a judgment result of 0 in response to a proportional relationship between the actual voltage and the reference voltage being less than 1, and output the first digital signal through an output terminal L6 of the comparator; or generate a first digital signal for indicating a judgment result of 1 in response to the proportional relationship between the actual voltage and the reference voltage being greater than 1, and output the first digital signal through the output terminal L6 of the comparator.

[0056] In the present disclosure, the first digital signal can represent a size relationship between the actual voltage and the reference voltage. When the comparator judges that the proportional relationship between the actual voltage and the reference voltage is less than 1, it means that the actual voltage is less than the reference voltage, and the generated first digital signal is 0; when the proportional relationship between the actual voltage and the reference voltage is greater than 1, it means that the actual voltage is greater than the reference voltage, and the generated first digital signal is 1.

[0057] The digital auxiliary module is configured to generate a third indication signal based on a first preset algorithm and a current frequency range of the oscillator in response to a plurality of continuous first digital signals before a current time being the same, and a first digital signal at the current time adjacent to the plurality of continuous first digital signals being the same as the plurality of continuous first digital signals, and output the third indication signal through an output terminal L8 of the digital auxiliary module, the third indication signal being used to indicate a first target frequency range of the oscillator.

[0058] In an embodiment of the present disclosure, the digital auxiliary module is specifically configured to generate a third indication signal based on a first preset algorithm and a current frequency range of the oscillator in response to a plurality of continuous first digital signals before a current time all indicating a judgment result of 0, and a first digital signal at the current time adjacent to the plurality of continuous first digital signals indicating a judgment result of 0, and output the third indication signal through an output terminal L8 of the digital auxiliary module, the third indication signal being used to indicate that the oscillator is to be up-regulated from the current frequency range to a first target frequency range.

[0059] Or, generate a third indication signal based on a first preset algorithm and a current frequency range of the oscillator in response to a plurality of continuous first digital signals before a current time all indicating a judgment result of 1, and a first digital signal at the current time adjacent to the plurality of continuous first digital signals indicating a judgment result of 1, and output the third indication signal through an output terminal L8 of the digital auxiliary module, the third indication signal being used to indicate that the oscillator is to be down-regulated from the current frequency range to a first target frequency range.

[0060] In an embodiment of the present disclosure, the first preset algorithm can be a successive approximation algorithm, also known as bisection method.

[0061] In an embodiment of the present disclosure, the continuous multiple first digital signals can be understood as multiple historical digital signals before the current received first digital signal, and the current received historical digital signal is adjacent to the multiple historical digital signals. For example, the digital auxiliary module receives a first digital signal at 00:10 s, and the digital auxiliary module can obtain the first digital signals corresponding to 00:05 s, 00:06 s, 00:07 s, 00:08 s and 00:09 s respectively received before.

[0062] It should be understood that the specific number of the continuous multiple first digital signals can be set by those skilled in the art according to actual needs, and the present application does not limit this, which is within the protection scope of the present disclosure.

[0063] In an embodiment of the present disclosure, the oscillator can have multiple frequency gears, and each frequency gear corresponds to a different frequency. When multiple frequency gears are set, the multiple frequency gears can be set in order from low frequency to high frequency.

[0064] In the present disclosure, when the digital auxiliary module receives a first digital signal of the comparator output, the digital auxiliary module can obtain multiple historical digital signals of the comparator output before the first digital signal from the local, and compare whether these digital signals are the same. If it is judged that the multiple historical digital signals all indicate that the judgment result of the comparator is 0, and the first digital signal also indicates that the judgment result of the comparator is 0, it means that the current actual voltage is still less than the reference voltage, and then the digital auxiliary module needs to instruct the oscillator to increase the frequency gear to the first target frequency gear; if it is judged that the multiple historical digital signals all indicate that the judgment result of the comparator is 1, and the first digital signal also indicates that the judgment result of the comparator is 1, it means that the current actual voltage is still greater than the reference voltage, and then the digital auxiliary module needs to instruct the oscillator to decrease the frequency gear to the first target frequency gear. The digital auxiliary module can determine the first target frequency gear according to the current frequency gear of the oscillator and the successive approximation algorithm when determining the first target frequency gear. After the first target frequency gear is determined, a third indication signal for indicating the first target frequency gear can be generated and outputted.

[0065] For example, assuming that the oscillator is provided with 16 frequency steps, and the lower the frequency step of the oscillator, the lower the frequency of the corresponding oscillator. Assuming that the current frequency step of the oscillator is the 8th step, if the digital auxiliary module determines that the current actual voltage is still less than the reference voltage, the frequency step needs to be raised to increase the frequency of the oscillator, and the digital auxiliary module can use the successive approximation algorithm to select the 12th step as the first target frequency step between the 8th step and the 16th step; if the digital auxiliary module determines that the current actual voltage is still greater than the reference voltage, the frequency step needs to be lowered to reduce the frequency of the oscillator, and the digital auxiliary module can use the successive approximation algorithm to select the 4th step as the first target frequency step between the 8th step and the 1st step.

[0066] In an embodiment of the present disclosure, a judgment module can be provided in the digital auxiliary module to implement the function of judging whether the continuous multiple first digital signals before the current time are the same and whether the currently received first digital signal is the same as the continuous multiple first digital signals.

[0067] In an embodiment of the present disclosure, an algorithm module can be provided in the digital auxiliary module to implement the function of generating the third indication signal based on the first preset algorithm and the current frequency step of the oscillator.

[0068] The latch is used to latch the third indication signal through the output end L 10 The third indication signal is output.

[0069] In an embodiment of the present disclosure, the latch can also be used to latch the third indication signal. It should be understood that latching can be understood as saving.

[0070] The oscillator is used to generate and output a second clock signal to the voltage parameter generation module based on the received third indication signal.

[0071] In an embodiment of the present disclosure, the clock signal of the oscillator can be understood as the oscillation period of the oscillator, which is equal to the inverse of the crystal frequency. In short, the clock signal can reflect the frequency of the oscillator.

[0072] In the present disclosure, if the oscillator receives a third indication signal for indicating up-regulating the frequency from the current frequency notch to the first target frequency notch, the oscillator generates a second clock signal based on the frequency corresponding to the up-regulated first target frequency notch after up-regulating the frequency notch to the first target frequency notch, and outputs the second clock signal to the third end L3 of the voltage parameter generation module to inform the current frequency of the oscillator; if the oscillator receives a third indication signal for indicating down-regulating the frequency from the current frequency notch to the first target frequency notch, the oscillator generates a second clock signal based on the frequency corresponding to the down-regulated first target frequency notch after down-regulating the frequency notch to the first target frequency notch, and outputs the second clock signal to the third end L3 of the voltage parameter generation module to inform the current frequency of the oscillator.

[0073] The voltage parameter generation module is configured to adjust the size of the actual voltage based on the second clock signal.

[0074] In the present disclosure, when the voltage parameter generation module receives the second clock signal output by the oscillator, the resistance value of the equivalent resistance can be adjusted based on the frequency corresponding to the second clock signal, and accordingly, the size of the actual voltage output by the second end L2 of the voltage parameter generation module also changes correspondingly due to the change of the resistance value of the equivalent resistance.

[0075] It should be understood that different frequencies of the oscillator correspond to different resistance values of the equivalent resistance, and the frequency of the oscillator is inversely proportional to the resistance value of the equivalent resistance.

[0076] It can be understood that the voltage parameter generation module continuously outputs the actual voltage and the reference voltage, the comparator continuously outputs the first digital signal for representing the size relationship between the actual voltage and the reference voltage, and the digital auxiliary module continuously instructs the oscillator to adjust the frequency notch, so that the actual voltage gradually approaches the reference voltage by continuously adjusting the frequency notch of the oscillator, until the actual voltage infinitely approaches the reference voltage, i.e., the actual voltage is equal to the reference voltage. Obviously, by setting a closed-loop feedback circuit, the actual voltage can be effectively made to quickly approach the reference voltage.

[0077] Frequency stabilization stage:

[0078] The functions of the voltage parameter generation module and the comparator in this stage are the same as those in the frequency adjustment stage, and reference can be made to the foregoing description, which will not be repeated here.

[0079] The digital auxiliary module is also configured to send a first instruction signal to the voltage parameter generation module and the comparator respectively and output a second instruction signal, and control the digital auxiliary module to be turned off, in response to the fact that the first digital signals before the current time are all the same and the first digital signal of the current time adjacent to the continuous first digital signals is different from the continuous first digital signals.

[0080] In an embodiment of the present disclosure, the digital auxiliary module is also specifically configured to send a first instruction signal to the voltage parameter generation module and the comparator respectively and output a second instruction signal, and control the digital auxiliary module to be turned off, in response to the fact that the first digital signals before the current time are all 0 and the first digital signal of the current time adjacent to the continuous first digital signals is 1, or in response to the fact that the first digital signals before the current time are all 1 and the first digital signal of the current time adjacent to the continuous first digital signals is 0.

[0081] In the present disclosure, when the digital auxiliary module receives a first digital signal output by the comparator, the digital auxiliary module can obtain a plurality of historical digital signals before the first digital signal output by the comparator, and compare whether the plurality of historical digital signals are the same. If it is determined that the plurality of historical digital signals are all 0 and the first digital signal is 1, or it is determined that the plurality of historical digital signals are all 1 and the first digital signal is 0, it is considered that the actual voltage is equal to the reference voltage, and then the digital auxiliary module sends a first instruction signal to the voltage parameter generation module and the comparator respectively through a communication link to instruct the voltage parameter generation module and the comparator to be turned off, and outputs a second instruction signal to the latch to inform the latch to continuously output a signal that does not need to adjust the frequency gear to the oscillator in a period of time. Moreover, the digital auxiliary module is also turned off and no longer works.

[0082] In an embodiment of the present disclosure, the function of the digital auxiliary module in the frequency stabilization stage can be realized by a judgment module in the digital auxiliary module.

[0083] The latch is also configured to save and output the second instruction signal through an output end L 10 The second instruction signal is continuously output.

[0084] In the present disclosure, when the latch receives the second instruction signal output by the digital auxiliary module for indicating the frequency gear, the latch can latch the second instruction signal and continuously output the second instruction signal to the oscillator in a period of time.

[0085] The oscillator is also configured to generate and output a first clock signal based on the received second indication signal.

[0086] In the present disclosure, when the oscillator receives the second indication signal output by the latch, which is used to indicate that the frequency grade is unchanged, it can be known that the current actual voltage has been equal to the reference voltage. Then, the oscillator can output the corresponding first clock signal based on the current frequency grade, and no longer feedback the first clock signal to the voltage parameter generation module. Moreover, in the following period of time, the frequency of the oscillator remains at a stable value, i.e., the frequency stabilization stage is entered, because the latch continues to output the second indication signal used to indicate that the frequency grade is unchanged.

[0087] It can be understood that, when the actual voltage is equal to the reference voltage, the digital auxiliary module turns off the voltage parameter generation module, the comparator and itself, so that they no longer work, and only the latch and the oscillator work. Therefore, the digital auxiliary module no longer needs to output the indication signal to the oscillator in the frequency stabilization stage, which reduces the power consumption of the oscillator circuit.

[0088] Frequency error correction stage:

[0089] The digital auxiliary module is also configured to, in response to a time difference between a time point when the first indication signal, the second indication signal and the control signal for turning off the digital auxiliary module are sent and a current time point being greater than or equal to a preset time threshold, send a fourth indication signal to the voltage parameter generation module and the comparator respectively, and control the digital auxiliary module to be turned on, wherein the fourth indication signal is used to indicate that the voltage parameter generation module and the comparator are turned on.

[0090] In the present disclosure, after entering the frequency stabilization stage, the frequency of the oscillator may drift over time due to the influence of temperature and other factors, which causes the frequency error of the oscillator. Therefore, the digital auxiliary module needs to monitor whether the time difference between the time point when the first indication signal for indicating turning off is sent to the voltage parameter generation module and the comparator, the turning off of the digital auxiliary module and the second indication signal for indicating that the frequency grade of the oscillator is unchanged is output and the current time point is greater than or equal to the preset time threshold. If the digital auxiliary module determines that the time difference is greater than or equal to the preset time threshold, the entire oscillator circuit loop needs to be re-opened, i.e., the digital auxiliary module sends the fourth indication signal to the voltage parameter generation module and the comparator respectively, and the digital auxiliary module is re-opened.

[0091] In an embodiment of the present disclosure, a timing module can be arranged in the digital auxiliary module to realize the function of monitoring whether the time difference is greater than or equal to the preset time threshold. Preferably, the timing module has its own power supply, and the timing module normally works when the digital auxiliary module is turned off.

[0092] It should be understood that the preset time threshold can be set by those skilled in the art according to actual needs, and the disclosure does not limit this, which is within the protection scope.

[0093] The digital auxiliary module is also configured to send a fourth indication signal, and after the digital auxiliary module is turned on, in response to the fact that the first digital signals before the current time are the same in the continuous multiple first digital signals, and the first digital signal of the current time adjacent to the continuous multiple first digital signals is the same as the continuous multiple first digital signals, the fifth indication signal is generated based on the second preset algorithm and the current frequency range of the oscillator, and the fifth indication signal is output through the output end L8 of the digital auxiliary module, and the fifth indication signal is used to indicate the second target frequency range of the oscillator.

[0094] In an embodiment of the disclosure, the second preset algorithm is a gradual algorithm.

[0095] In the disclosure, after the voltage parameter module, the comparator and the digital auxiliary module are turned on again, when the digital auxiliary module receives a first digital signal output by the comparator, if it is judged again that the multiple historical digital signals all indicate that the judgment result of the comparator is 0, and the first digital signal also indicates that the judgment result of the comparator is 0, or the multiple historical digital signals all indicate that the judgment result of the comparator is 1, and the first digital signal also indicates that the judgment result of the comparator is 1, it indicates that the current actual voltage deviates from the reference voltage. At this time, the digital auxiliary module can determine the second target frequency range based on the gradual algorithm and the current frequency range of the oscillator. After the second target frequency range is determined, the fifth indication signal used to indicate the second target frequency range can be generated and output.

[0096] It should be understood that the gradual algorithm is used to adjust the frequency range of the oscillator step by step, that is, only one frequency range is adjusted each time, or one frequency range is lowered.

[0097] Exemplarily, it is also assumed that the oscillator is provided with 16 frequency ranges, and the lower the frequency range of the oscillator is, the lower the frequency of the corresponding oscillator is. It is assumed that the current frequency range of the oscillator is the eighth range, if the digital auxiliary module judges that the current actual voltage deviates from the reference voltage and is less than the reference voltage, the frequency range needs to be adjusted to increase the frequency of the oscillator, then the digital auxiliary module can select the ninth range as the second target frequency range by using the gradual algorithm; if the digital auxiliary module judges that the current actual voltage deviates from the reference voltage and is greater than the reference voltage, the frequency range needs to be adjusted to reduce the frequency of the oscillator, then the digital auxiliary module can select the ninth range as the second target frequency range by using the gradual algorithm.

[0098] In an embodiment of the disclosure, the function of generating the fifth indication signal based on the second preset algorithm and the current frequency range of the oscillator can also be realized by the algorithm module.

[0099] The latch is also used to save the second indication signal received by the latch and continuously output the second indication signal to the oscillator through an output end L of the latch. 10 output a fifth indication signal.

[0100] The oscillator is also used to generate and output a third clock signal to the voltage parameter generation module based on the received fifth indication signal.

[0101] The voltage parameter generation module is also used to adjust the size of the actual voltage based on the third clock signal.

[0102] Similarly to the frequency adjustment stage, the oscillator can correspondingly adjust the current frequency bin to the target frequency bin based on the fifth indication signal output by the latch, and feed back the third clock signal to the voltage parameter generation module to achieve adjustment of the actual voltage, reduce the deviation between the actual voltage and the reference voltage, and until they are the same.

[0103] It can be understood that after the oscillator circuit enters the frequency stabilization stage for a period of time, the closed loop is re-opened, and the frequency bin of the oscillator is fine-tuned again to ensure the accuracy of the clock signal output by the oscillator.

[0104] In the above embodiment, when the digital auxiliary module responds to the fact that the first digital signals before the current time are the same, and the first digital signal at the current time adjacent to the continuous first digital signals is different from the continuous first digital signals, i.e., the actual voltage is equal to the reference voltage, the digital auxiliary module sends a first indication signal to the voltage parameter generation module and the comparator respectively to indicate that the first indication signal is turned off, and outputs a second indication signal to indicate that the frequency bin of the oscillator is unchanged, and controls the digital auxiliary module to be turned off. And the latch also saves and continuously outputs the received second indication signal to the oscillator, so that the oscillator can output the first clock signal of the corresponding frequency based on the received second indication signal. Since the digital auxiliary module is used, when it is determined that the actual voltage is equal to the reference voltage, the voltage parameter generation module, the comparator and the digital auxiliary module are turned off, only the latch and the oscillator are left to work, and the latch can continuously output the second indication signal to the oscillator to indicate that the frequency bin is unchanged. Therefore, under the premise of ensuring the frequency stability of the oscillator, the power consumption of the oscillator circuit is reduced. And after the frequency of the oscillator is stable for a preset time threshold, the digital auxiliary module is turned on again, and the fourth indication signal is sent to indicate that the voltage parameter generation module and the comparator are turned on again, and the frequency of the oscillator is adjusted again to reduce the influence of temperature and other external factors on the frequency of the oscillator, and ensure the accuracy of the clock signal output by the oscillator.

[0105] Figure 3 Another schematic diagram of an oscillator circuit according to an embodiment of the present disclosure is shown.

[0106] As Figure 3As shown, in addition to the modules and devices described above, the oscillator circuit may also include: a frequency divider, the input terminal of which is L 13 With the output terminal L of the oscillator 12 Connect the output terminal L of the frequency divider. 14 The frequency divider is connected to the third terminal L3 of the voltage parameter generation module, and the frequency divider and the digital auxiliary module are connected through communication link 3.

[0107] In one embodiment of this disclosure, the frequency divider is used to generate and output a fourth clock signal based on a preset down-ratio and a second clock signal, or to generate and output a fifth clock signal based on a preset down-ratio and a third clock signal.

[0108] It is understandable that reducing the frequency of the clock signal output by the oscillator using a frequency divider can lower the performance requirements of the oscillator circuit.

[0109] In one embodiment of this disclosure, during the frequency stabilization phase, the digital auxiliary module can also be used to send a first indication signal to the frequency divider to instruct the frequency divider to be turned off. Clearly, turning off the frequency divider when the oscillator frequency is stable can further reduce the power consumption of the oscillator circuit.

[0110] In one embodiment of this disclosure, during the frequency error correction stage, the digital auxiliary module can also be used to send a fourth indication signal to the frequency divider to indicate that the frequency divider is turned on.

[0111] It needs to be explained that, Figure 3 The operating principle of the oscillator circuit shown can be referred to the aforementioned explanation. Figure 1 and Figure 2 The introduction will not be repeated here.

[0112] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A low-power oscillator circuit, characterized in that, The oscillator circuit includes: a voltage parameter generation module, a comparator, a digital auxiliary module, a latch, and an oscillator; wherein, The first terminal of the voltage parameter generation module is connected to the first input terminal of the comparator, and the second terminal of the voltage parameter generation module is connected to the second input terminal of the comparator. The first terminal of the voltage parameter generation module is used to output a reference voltage, and the second terminal of the voltage parameter generation module is used to output the actual voltage. The output terminal of the comparator is connected to the input terminal of the digital auxiliary module. The comparator is used to generate a first digital signal based on the ratio between the actual voltage and the reference voltage, and outputs the first digital signal through the output terminal of the comparator. The output terminal of the digital auxiliary module is connected to the input terminal of the latch. The digital auxiliary module is used to respond to a first digital signal at the current moment that is the same as a series of consecutive first digital signals before the current moment and is different from the series of consecutive first digital signals. The digital auxiliary module sends a first indication signal to the voltage parameter generation module and the comparator respectively, outputs a second indication signal, and controls the digital auxiliary module to turn off. The first indication signal is used to instruct the voltage parameter generation module and the comparator to turn off, and the second indication signal is used to instruct the frequency range of the oscillator to remain unchanged. The output terminal of the latch is connected to the input terminal of the oscillator, and the latch is used to store and continuously output the second indication signal through the output terminal of the latch; The oscillator is used to generate and output a first clock signal based on the received second indication signal.

2. The oscillator circuit according to claim 1, characterized in that, The comparator is specifically used to generate a first digital signal indicating that the judgment result is 0 in response to the ratio of the actual voltage to the reference voltage being less than 1, and output the first digital signal through the output terminal of the comparator; Alternatively, in response to the ratio of the actual voltage to the reference voltage being greater than 1, a first digital signal is generated to indicate that the judgment result is 1, and the first digital signal is output through the output terminal of the comparator.

3. The oscillator circuit according to claim 2, characterized in that, The digital auxiliary module is specifically configured to, in response to a situation where multiple consecutive first digital signals prior to the current time indicate a judgment result of 0, and the first digital signal at the current time adjacent to the multiple consecutive first digital signals indicates a judgment result of 1, or, in response to a situation where multiple consecutive first digital signals prior to the current time indicate a judgment result of 1, and the first digital signal at the current time adjacent to the multiple consecutive first digital signals indicates a judgment result of 0, send the first indication signal to the voltage parameter generation module and the comparator respectively, output the second indication signal, and control the digital auxiliary module to turn off.

4. The oscillator circuit according to any one of claims 1 to 3, characterized in that, The digital auxiliary module is also used to respond to a first digital signal at the current time that is the same as a series of consecutive first digital signals before the current time and is adjacent to the series of consecutive first digital signals. Based on a first preset algorithm and the current frequency range of the oscillator, a third indication signal is generated, and the third indication signal is output through the output terminal of the digital auxiliary module. The third indication signal is used to indicate the first target frequency range of the oscillator.

5. The oscillator circuit according to claim 4, characterized in that, The digital auxiliary module is further specifically used to respond to the fact that multiple consecutive first digital signals before the current time indicate a judgment result of 0, and the first digital signal at the current time adjacent to the multiple consecutive first digital signals indicates a judgment result of 0, generate the third indication signal based on the first preset algorithm and the current frequency range of the oscillator, and output the third indication signal through the output terminal of the digital auxiliary module. The third indication signal is used to instruct the oscillator to adjust from the current frequency range to the first target frequency range. Alternatively, in response to a series of consecutive first digital signals prior to the current moment indicating a judgment result of 1, and a first digital signal at the current moment adjacent to the series of consecutive first digital signals indicating a judgment result of 1, the third indication signal is generated based on the first preset algorithm and the current frequency range of the oscillator, and the third indication signal is output through the output terminal of the digital auxiliary module. The third indication signal is used to instruct the oscillator to downgrade from the current frequency range to the first target frequency range.

6. The oscillator circuit according to claim 4, characterized in that, The latch is also used to output the third indication signal through the output terminal of the latch.

7. The oscillator circuit according to claim 6, characterized in that, The output terminal of the oscillator is connected to the third terminal of the voltage parameter generation module. The oscillator is also used to generate and output a second clock signal to the voltage parameter generation module based on the received third indication signal.

8. The oscillator circuit according to claim 7, characterized in that, The voltage parameter generation module is also used to adjust the magnitude of the actual voltage based on the second clock signal.

9. The oscillator circuit according to claim 1, characterized in that, The digital auxiliary module is further configured to, in response to the time difference between the moment when the first indication signal, the second indication signal, and the moment when the digital auxiliary module is turned off being greater than or equal to a preset time threshold, send a fourth indication signal to the voltage parameter generation module and the comparator respectively, and control the digital auxiliary module to turn on, wherein the fourth indication signal is used to indicate that the voltage parameter generation module and the comparator are turned on.

10. The oscillator circuit according to claim 9, characterized in that, The digital auxiliary module is also used to send the fourth indication signal, and after the digital auxiliary module is turned on, it responds to the first digital signal at the current time that is the same as the first digital signal before the current time and is adjacent to the first digital signal at the current time. Based on the second preset algorithm and the current frequency range of the oscillator, a fifth indication signal is generated, and the fifth indication signal is output through the output terminal of the digital auxiliary module. The fifth indication signal is used to indicate the second target frequency range of the oscillator.

11. The oscillator circuit according to claim 10, characterized in that, The latch is also used to output the fifth indication signal through the output terminal of the latch.

12. The oscillator circuit according to claim 11, characterized in that, The oscillator is also used to generate and output a third clock signal to the voltage parameter generation module based on the received fifth indication signal.

13. The oscillator circuit according to claim 12, characterized in that, The voltage parameter generation module is also used to adjust the magnitude of the actual voltage based on the third clock signal.

14. The oscillator circuit according to any one of claims 7 or 8, characterized in that, The oscillator circuit further includes a frequency divider, the input of which is connected to the output of the oscillator, and the output of which is connected to the third terminal of the voltage parameter generation module. The frequency divider is used to generate and output a fourth clock signal based on a preset down-frequency ratio and the second clock signal.

15. The oscillator circuit according to any one of claims 12 or 13, characterized in that, The oscillator circuit further includes a frequency divider, the input of which is connected to the output of the oscillator, and the output of which is connected to the third terminal of the voltage parameter generation module. The frequency divider is used to generate and output a fifth clock signal based on a preset down-frequency ratio and the third clock signal.

16. The oscillator circuit according to claim 4, characterized in that, The first preset algorithm is a successive approximation algorithm.

17. The oscillator circuit according to any one of claims 10-13, characterized in that, The second preset algorithm is a progressive algorithm.

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