Semiconductor device and power conversion device

Abstract

The main electrodes formed on both sides of the semiconductor element are connected to the corresponding heat sinks. The emitter electrode is connected to the heat sink (50) via the terminal (60). In the terminal (60), the end face (60b) on the heat sink side is rectangular with two sides (61a, 61b) parallel to the X direction and two sides (61c, 61d) parallel to the Y direction. The heat sink (50) is connected to the end face (60b) of the terminal (60) via solder (91). The heat sink (50) has a connection area (51) connected to the terminal (60) and a groove (52) surrounding the connection area (51) and accommodating the remaining solder (91) on the opposite surface (50a) opposite to the terminal (60). The groove (52) is set to overlap with only one or only two of the four sides of the end face (60b) in a plan view.

Description

[0001] Cross-references between related applications

[0002] This application is based on Japanese Patent Application No. 2020-81437 filed on May 1, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The disclosure of this specification relates to a semiconductor device and a power conversion device. Background Art

[0004] Patent Document 1 discloses a semiconductor device with a double-sided heat dissipation structure. The contents of the prior art document are incorporated herein by reference as explanations of the technical elements in this specification.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2007-103909 Summary of the Invention

[0008] As described in Patent Document 1, a semiconductor device includes a block that electrically connects a semiconductor element and a metal plate. A relatively large amount of solder is disposed between the metal body and the block to absorb height variations in the semiconductor device. The metal body has a groove for accommodating excess solder on the surface facing the block. The groove is arranged to match the size of the block in a manner that overlaps the outer peripheral end of the end face of the block over the entire circumference in a plan view. From the above-mentioned viewpoints, or from other viewpoints not mentioned, further improvements are required for the semiconductor device.

[0009] One object of the disclosure is to provide a semiconductor device capable of accommodating excess solder and reducing the number of parts.

[0010] Another object of the disclosure is to reduce the number of parts in a power conversion device including semiconductor devices constituting a plurality of power conversion units.

[0011] The semiconductor device disclosed herein comprises: a semiconductor element having a first main electrode and a second main electrode formed on a surface opposite to the first main electrode in the direction of the plate thickness; a first wiring component connected to the first main electrode; a terminal having a first end face connected to the second main electrode and a second end face opposite to the first end face in the direction of the plate thickness, the second end face being rectangular with two sides parallel to the first direction and two sides parallel to the second direction, the first direction being orthogonal to the plate thickness direction, and the second direction being orthogonal to the plate thickness direction and the first direction; and a second wiring component connected to the second end face of the terminal via solder, having a connection area with the terminal and a groove surrounding the connection area and accommodating remaining solder on a surface opposite to the terminal; the groove is configured to overlap with only one or only two of the four sides of the second end face of the terminal in a planar view viewed from the direction of the plate thickness.

[0012] According to the disclosed semiconductor device, the groove of the second wiring component is arranged so as to overlap with the edge of the second end face of the terminal in a planar view. This allows the remaining solder to flow easily into the groove. The remaining solder can be accommodated in the groove. In addition, the groove is arranged so as to overlap with only one or only two of the four sides of the second end face. Thus, for multiple terminals of different sizes, the remaining solder can be accommodated by the groove having a common structure. As a result, a semiconductor device can be provided that can accommodate the remaining solder while reducing the number of parts.

[0013] The power conversion device disclosed herein comprises: a first semiconductor device constituting a first power conversion section; and a second semiconductor device constituting a second power conversion section; each semiconductor device comprising: a semiconductor element having a first main electrode and a second main electrode formed on a surface opposite to the first main electrode in a plate thickness direction; a first wiring member connected to the first main electrode; and a terminal having a first end surface connected to the second main electrode and a second end surface opposite to the first end surface in the plate thickness direction, the second end surface being rectangular with two sides parallel to the first direction and two sides parallel to the second direction. The first direction is orthogonal to the plate thickness direction, and the second direction is orthogonal to the plate thickness direction and the first direction; and a second wiring component is connected to the second end face of the terminal via solder, and has a connection area with the terminal and a groove surrounding the connection area to accommodate remaining solder on the opposite surface of the terminal; in the first semiconductor device and the second semiconductor device, the sizes of the terminals in the plan view observed from the plate thickness direction are different from each other, and the sizes of the grooves are equal to each other; the grooves of each semiconductor device are set to overlap with only one or only two of the four sides of the second end face of the terminal in the plan view.

[0014] According to the disclosed power conversion device, in the first semiconductor device and the second semiconductor device, the sizes of the grooves are made equal to each other. The structure of the grooves is made common in the first semiconductor device and the second semiconductor device. In addition, the grooves of the common structure overlap with only one or only two of the four sides of the second end face. Thus, even if the structure of the grooves is made common, it is possible to accommodate excess solder. As a result, the second wiring component having the grooves can be made a common part in the first semiconductor device and the second semiconductor device. Thus, the number of parts can be reduced in the power conversion device having semiconductor devices constituting multiple power conversion units.

[0015] The various embodiments disclosed in this specification employ different technical means to achieve their respective objectives. The reference numbers in parentheses in the claims and their sections are provided for illustrative purposes only to indicate their correspondence with the embodiments described below and are not intended to limit the scope of the technology. The objectives, features, and effects disclosed in this specification will become more apparent with reference to the detailed description and accompanying drawings that follow. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a diagram showing a schematic configuration of a drive system of a vehicle to which the power conversion device according to the first embodiment is applied.

[0017] Figure 2 It is a plan view showing a semiconductor module.

[0018] Figure 3 It will Figure 2 Side view as viewed from direction X1.

[0019] Figure 4 It is a plan view showing the semiconductor device according to the first embodiment.

[0020] Figure 5 It is from Figure 4 Plan view from the opposite side.

[0021] Figure 6 It is along Figure 4 A cross-sectional view taken along line VI-VI is shown.

[0022] Figure 7 It is along Figure 4 A cross-sectional view taken along line VII-VII is shown.

[0023] Figure 8 It is along Figure 4 A cross-sectional view taken along line VIII-VIII is shown.

[0024] Figure 9 It is a plan view showing a lead frame.

[0025] Figure 10It is a plan view showing a state where semiconductor elements and terminals are arranged.

[0026] Figure 11 It is a plan view showing a state where a heat sink is arranged on the emitter side.

[0027] Figure 12 It is a partial cross-sectional view showing the molding step of the sealing resin body.

[0028] Figure 13 It is a plan view showing a state after the sealing resin body is molded.

[0029] Figure 14 It is a plan view showing the state after cutting.

[0030] Figure 15 It is a plan view showing the positional relationship between the slot and the end face of the terminal.

[0031] Figure 16 This is a cross-sectional view showing the positional relationship among the slot, terminal, and semiconductor element.

[0032] Figure 17 It is a plan view showing the opposing surface of the heat sink in the semiconductor device according to the second embodiment.

[0033] Figure 18 It is along Figure 17 Cross-sectional view of line XVIII-XVIII.

[0034] Figure 19 It is a diagram showing laser scanning.

[0035] Figure 20 It is a plan view showing a modified example.

[0036] Figure 21 It is a cross-sectional view showing a modified example.

[0037] Figure 22 This is a diagram showing the correction of the signal terminal.

[0038] Figure 23 It is a plan view showing a modified example.

[0039] Figure 24 It is a plan view showing the back surface side of a semiconductor element in the semiconductor device according to the third embodiment.

[0040] Figure 25 This is a graph showing the relationship between the arithmetic mean roughness Ra of the protective film surface and the overall damage rate. DETAILED DESCRIPTION

[0041] Hereinafter, multiple embodiments will be described based on the accompanying drawings. In multiple embodiments, functionally and / or structurally corresponding parts and / or associated parts may be assigned the same reference numerals. For corresponding parts and / or associated parts, reference can be made to the description of other embodiments.

[0042] (First embodiment)

[0043] The power conversion device of this embodiment can be applied to mobile objects driven by rotating electrical machines. Examples of mobile objects include electric vehicles such as electric vehicles (EVs), hybrid electric vehicles (HVs), and fuel cell vehicles (FCVs), flying objects such as drones, ships, construction machinery, and agricultural machinery. Below, a vehicle (hybrid electric vehicle) is used as an example of a mobile object.

[0044] <Vehicle Drive System>

[0045] First, based on Figure 1 The schematic structure of the vehicle drive system 1 to which the power conversion device 5 is applied will be described. Figure 1 As shown, a vehicle drive system 1 includes a DC power supply 2 , motor generators 3 and 4 , and a power converter 5 that converts power between the DC power supply 2 and the motor generators 3 and 4 .

[0046] The DC power supply 2 is a DC voltage source composed of a rechargeable secondary battery. Examples of the secondary battery include a lithium-ion battery and a nickel-metal hydride battery. The motor generators 3 and 4 are three-phase AC rotating electrical machines.

[0047] The motor generator 3 functions as a generator (AC generator) driven by an engine (not shown) to generate electricity, and as a motor (starter) to start the engine. The motor generator 4 functions as an electric motor, serving as the vehicle's driving source. The motor generator 4 functions as a generator during regeneration. The vehicle includes the engine and the motor generator 4 as driving sources. The power converter 5 converts power between the DC power supply 2 and the motor generators 3 and 4.

[0048] <Circuit Structure of Power Converter>

[0049] Then, based on Figure 1 The circuit structure of the power conversion device 5 is described. Figure 1 As shown, the power conversion device 5 includes a filter capacitor C1, a smoothing capacitor C2, a converter 6, inverters 7 and 8, a control circuit unit 9, a drive circuit unit 10, and the like.

[0050] The P line 11, which serves as a high-potential power line, includes a VL line 11L and a VH line 11H. The VL line 11L is connected to the positive terminal of the DC power supply 2. A converter 6 is provided between the VL line 11L and the VH line 11H. The potential of the VH line 11H is set to be higher than that of the VL line 11L. The N line 12 is a low-potential power line connected to the negative terminal of the DC power supply 2. The N line 12 is sometimes referred to as a ground line.

[0051] Filter capacitor C1 is connected between VL line 11L and N line 12. Filter capacitor C1 is connected in parallel with DC power supply 2. Filter capacitor C1 removes power supply noise from DC power supply 2, for example. Because filter capacitor C1 is located on a lower voltage side than smoothing capacitor C2, it is sometimes referred to as a low-voltage side capacitor. A system main relay (SMR), not shown, is provided between DC power supply 2 and filter capacitor C1 on at least one of VL line 11L and N line 12.

[0052] Smoothing capacitor C2 is connected between VH line 11H and N line 12. Smoothing capacitor C2 is provided between converter 6 and inverters 7 and 8, connected in parallel with converter 6 and inverters 7 and 8. Smoothing capacitor C2 smoothes the DC voltage boosted by converter 6, for example, and accumulates the charge of this DC voltage. The voltage across smoothing capacitor C2 becomes the high DC voltage used to drive motor generators 3 and 4. The voltage across smoothing capacitor C2 is set to be greater than the voltage across filter capacitor C1. Because smoothing capacitor C2 is located on the higher voltage side than filter capacitor C1, it is sometimes referred to as a high-voltage side capacitor.

[0053] Converter 6 and inverters 7 and 8, which serve as power conversion units, have upper and lower arm circuits 6HL, 7HL, and 8HL. The upper and lower arm circuits 6HL, 7HL, and 8HL are connected between the VH line 11H and the N line 12. The upper and lower arm circuits 6HL of converter 6 are configured by connecting the upper arm 6H and the lower arm 6L in series, with the upper arm 6H serving as the VH line 11H side. Similarly, the upper and lower arm circuits 7HL of inverter 7 are configured by connecting the upper arm 7H and the lower arm 7L in series. The upper and lower arm circuits 8HL of inverter 8 are configured by connecting the upper arm 8H and the lower arm 8L in series. Below, there are cases where they are simply represented as arms 6H, 6L, 7H, 7L, 8H, and 8L.

[0054] Each arm 6H, 6L includes a switching element Q1 and a freewheeling diode D1 connected in anti-parallel to the switching element Q1. Each arm 7H, 7L includes a switching element Q2 and a freewheeling diode D2 connected in anti-parallel to the switching element Q2. Each arm 8H, 8L includes a switching element Q3 and a freewheeling diode D3 connected in anti-parallel to the switching element Q3. In this embodiment, n-channel IGBTs are used as the switching elements Q1, Q2, and Q3. In addition, the switching elements Q1, Q2, and Q3 are not limited to IGBTs. For example, MOSFETs can also be used. Parasitic diodes can also be used as the diodes D1, D2, and D3.

[0055] Converter 6 is a DC-DC converter. Converter 6 converts a DC voltage into DC voltages of varying values ​​according to switching control by control circuit unit 9. Converter 6 boosts the DC voltage supplied from DC power supply 2. Converter 6 also steps down the DC voltage by charging DC power supply 2 using the charge from smoothing capacitor C2. Converter 6 includes upper and lower arm circuits 6HL and reactor R1.

[0056] In the upper and lower arm circuits 6HL, the collector of the switching element Q1 on the upper arm 6H side is connected to the VH line 11H, and the emitter of the switching element Q1 on the lower arm 6L side is connected to the N line 12. The emitter of the switching element Q1 on the upper arm 6H side and the collector of the switching element Q1 on the lower arm 6L side are connected to each other. One end of the reactor R1 is connected to the VL line 11L, and the other end is connected to the connection point of the upper arm 6H and the lower arm 6L via the boost wiring 13. The converter 6 of this embodiment is configured as a multi-phase converter, specifically a two-phase converter. The converter 6 has two-phase upper and lower arm circuits 6HL and a reactor R1 provided for each of the upper and lower arm circuits 6HL.

[0057] Inverters 7 and 8 are DC-AC conversion units. Inverter 7 is connected to converter 6 via smoothing capacitor C2. Inverter 7 converts DC voltage into three-phase AC voltage according to the switching control of control circuit unit 9 and outputs it to motor generator 3. As a result, motor generator 3 is driven to generate a specified torque. Inverter 7 can also convert the three-phase AC voltage generated by motor generator 3 receiving the output of the engine into DC voltage according to the switching control of control circuit unit 9, and output it to VH line 11H. In this way, inverter 7 performs bidirectional power conversion between converter 6 and motor generator 3. Inverter 7 has three-phase (U phase, V phase, W phase) upper and lower arm circuits 7HL.

[0058] In the upper and lower arm circuits 7HL, the collector of the switching element Q2 on the upper arm 7H side is connected to the VH line 11H, and the emitter of the switching element Q2 on the lower arm 7L side is connected to the N line 12. The emitter of the switching element Q2 on the upper arm 7H side and the collector of the switching element Q2 on the lower arm 7L side are connected to each other. The connection point of the upper and lower arm circuits 7HL of each phase is connected to the stator winding of the corresponding phase via output wiring 14 provided for each phase.

[0059] Similarly, the inverter 8 is also connected to the converter 6 via the smoothing capacitor C2. The inverter 8 converts the DC voltage into a three-phase AC voltage according to the switching control of the control circuit unit 9 and outputs it to the motor generator 4. As a result, the motor generator 4 is driven to generate a specified torque. During regenerative braking of the vehicle, the inverter 8 can also convert the three-phase AC voltage generated by the motor generator 4 due to the rotational force from the drive wheel into a DC voltage according to the switching control of the control circuit unit 9 and output it to the VH line 11H. In this way, the inverter 8 performs bidirectional power conversion between the converter 6 and the motor generator 4. The inverter 8 has a three-phase (U phase, V phase, W phase) upper and lower arm circuit 8HL.

[0060] In the upper and lower arm circuits 8HL, the collector of the switching element Q3 on the upper arm 8H side is connected to the VH line 11H, and the emitter of the switching element Q3 on the lower arm 8L side is connected to the N line 12. The emitter of the switching element Q3 on the upper arm 8H side and the collector of the switching element Q3 on the lower arm 8L side are connected to each other. The connection point of the upper and lower arm circuits 8HL of each phase is connected to the stator winding of the corresponding phase via output wiring 15 provided for each phase.

[0061] The control circuit unit 9 generates drive instructions for operating the switching elements Q1, Q2, and Q3 and outputs them to the drive circuit unit 10. The control circuit unit 9 generates the drive instructions based on a torque request input from a higher-level ECU (not shown), signals detected by various sensors, and the like. The control circuit unit 9 outputs, for example, a PWM signal as a drive instruction. The control circuit unit 9 is configured, for example, with a microcomputer. ECU is the abbreviation for Electronic Control Unit. PWM is the abbreviation for Pulse Width Modulation.

[0062] Various sensors include current sensors, rotation angle sensors, voltage sensors, and temperature sensors. One current sensor detects the phase current flowing through the windings of each phase of motor generators 3 and 4. Another current sensor detects the current flowing through reactor R1. The rotation angle sensor detects the rotation angle of the rotors of motor generators 3 and 4. One voltage sensor detects the voltage across smoothing capacitor C2, that is, the voltage of VH line 11H. Another voltage sensor detects the voltage across filter capacitor C1, that is, the voltage of VL line 11L. The temperature sensor detects the temperature of reactor R1. Power conversion device 5 includes these sensors (not shown).

[0063] The drive circuit unit 10 supplies a drive voltage to the gates of the switching elements Q1, Q2, and Q3 of the corresponding arms 6H, 6L, 7H, 7L, 8H, and 8L based on the drive instructions from the control circuit unit 9. The drive circuit unit 10 drives the corresponding switching elements Q1, Q2, and Q3 by applying the drive voltage, that is, performs on-drive and off-drive. The drive circuit unit 10 is sometimes referred to as a driver. In this embodiment, one drive circuit unit 10 is provided for each arm. The configuration of the drive circuit unit 10 is not limited thereto. For example, a drive circuit unit 10 may be provided for each of the upper and lower arm circuits 6HL, 7HL, and 8HL.

[0064] <Semiconductor Module>

[0065] Then, based on Figure 2 and Figure 3 The structure of the semiconductor module 16 will be described. Figure 3 It will Figure 2 Side view from the X1 direction. Figure 3 , a circuit board 19 is shown together with a semiconductor module 16. Hereinafter, the stacking direction of the semiconductor device 17 and the heat exchange portion 180 is referred to as the Z direction. A direction perpendicular to the Z direction is referred to as the X direction, and a direction perpendicular to both the Z and X directions is referred to as the Y direction.

[0066] like Figure 2 and Figure 3 As shown, the power conversion device 5 includes a semiconductor module 16. Semiconductor module 16 constitutes the upper and lower arm circuits 6HL of inverters 7 and 8 and converter 6. Semiconductor module 16 includes multiple semiconductor devices 17 and a cooler 18 for cooling semiconductor devices 17. Semiconductor module 16 is housed in a housing (not shown) included in the power conversion device 5. The housing also houses the aforementioned filter capacitor C1, smoothing capacitor C2, and reactor R1. The housing also houses a circuit board 19 on which the control circuit unit 9 and the drive circuit unit 10 are formed.

[0067] Semiconductor devices 17 include semiconductor devices 17A that constitute inverter 7, semiconductor devices 17B that constitute inverter 8, and semiconductor devices 17C that constitute upper and lower arm circuits 6HL of converter 6. In this embodiment, one semiconductor device 17 constitutes one of the upper and lower arm circuits. Semiconductor module 16 includes three semiconductor devices 17A that constitute the three-phase upper and lower arm circuits 7HL, three semiconductor devices 17B that constitute the three-phase upper and lower arm circuits 8HL, and two semiconductor devices 17C that constitute the two-phase upper and lower arm circuits 6HL. The outer contours of semiconductor devices 17A, 17B, and 17C are substantially equal.

[0068] The cooler 18 is formed using a metal material with excellent thermal conductivity, such as an aluminum material. The cooler 18 includes a heat exchange portion 180, an inlet pipe 181, and a discharge pipe 182. The heat exchange portion 180 is housed in a box. The heat exchange portion 180 is a flat tubular body as a whole. The heat exchange portion 180 is formed by, for example, stamping at least one of a pair of plates (metal thin plates) into a shape that bulges in the Z direction. Then, the outer peripheral edges of the pair of plates are fixed to each other by caulking or the like, and are joined to each other around the entire circumference by brazing or the like. As a result, a flow path through which the refrigerant can circulate is formed between the pair of plates, which can be used as the heat exchange portion 180.

[0069] The heat exchange sections 180 are stacked alternately with the semiconductor devices 17 in the Z direction. The semiconductor devices 17 and the heat exchange sections 180 are arranged side by side in the Z direction. The semiconductor devices 17 are each sandwiched between the heat exchange sections 180 in the Z direction. In the stack 16a of the semiconductor devices 17 and the heat exchange sections 180, both ends in the Z direction serve as heat exchange sections 180.

[0070] The inlet pipe 181 and the outlet pipe 182 are arranged to extend across the interior and exterior of the housing, respectively. Each of the inlet pipe 181 and the outlet pipe 182 can be formed from a single component or a structure formed by connecting multiple components. The inlet pipe 181 and the outlet pipe 182 are connected to each heat exchange section 180. Refrigerant is supplied to the inlet pipe 181 by a pump (not shown), thereby flowing through the flow path within the stacked heat exchange sections 180. As a result, the semiconductor devices 17 that constitute the stack 16a are cooled by the refrigerant. The refrigerant flowing through each heat exchange section 180 is discharged through the outlet pipe 182.

[0071] As a refrigerant, for example, a refrigerant that undergoes a phase change, such as water or ammonia, or a refrigerant that does not undergo a phase change, such as ethylene glycol, can be used. Semiconductor module 16 may also include an insulating member (not shown) between semiconductor device 17 and heat exchange unit 180. Examples of the insulating member include a ceramic plate, grease, a gel-like heat conductive member, or a combination thereof. The placement of the insulating member can, for example, electrically isolate semiconductor device 17 from heat exchange unit 180.

[0072] As described later, the semiconductor device 17 includes main terminals 80 and signal terminals 85 as external connection terminals. The main terminals 80 and signal terminals 85 extend in opposite directions in the Y direction. The signal terminals 85 are connected to the circuit substrate 19, which is located on one side of the stack 16a in the Y direction. The circuit substrate 19 is arranged so that it overlaps all of the semiconductor devices 17 that constitute the stack 16a in a plan view in the Y direction. The signal terminals 85 of each semiconductor device 17 are inserted and mounted on the circuit substrate 19.

[0073] <Semiconductor Device>

[0074] Then, based on Figures 4 to 11 An example of the semiconductor device 17 will be described. Figure 4 is a plan view of the semiconductor device 17 viewed from the emitter side. Figure 5 This is a plan view viewed from the collector side. Figure 6 、 Figure 7 、 Figure 8 It is along Figure 4 Cross-sectional views along lines VI-VI, VII-VII, and VIII-VIII. Figure 9 1 is a plan view showing the lead frame 95 . Figure 10 It is a plan view showing a state where the semiconductor element 30 and the terminal 60 are arranged on the lead frame 95 . Figure 11 : is a plan view showing a state where the emitter-side heat sink 50 is arranged on the terminal 60. Figures 9 to 11 , the lead frame 95 before cutting is shown for convenience.

[0075] In this embodiment, some elements that constitute semiconductor device 17 are denoted by "H" at the end of their reference numerals to indicate the upper arms 6H, 7H, and 8H, and "L" at the end of their reference numerals to indicate the lower arms 6L, 7L, and 8L. For convenience, other elements are assigned common reference numerals across the upper arms 6H, 7H, and 8H and the lower arms 6L, 7L, and 8L. Unless otherwise specified, the shape observed in plan view from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. Furthermore, the shape observed in plan view from the Z direction is simply referred to as "planar view."

[0076] As described above, the outer contours of the semiconductor devices 17A, 17B, and 17C are substantially equal to each other. The semiconductor devices 17A, 17B, and 17C have a common structure except for the size of the semiconductor element 30 and the size of the terminal 60. Figure 4 、 Figure 5 、 Figure 9 and Figure 11, a structure common to the semiconductor devices 17A, 17B, and 17C is shown.

[0077] like Figures 4 to 11 As shown, semiconductor device 17 includes sealing resin body 20, semiconductor element 30, heat sinks 40, 50, terminal 60, connectors 70, 71, main terminal 80, and signal terminal 85. As described above, semiconductor device 17 constitutes upper and lower arm circuits of one phase.

[0078] The sealing resin body 20 seals a portion of the other elements constituting the semiconductor device 17. The remaining portions of the other elements are exposed outside the sealing resin body 20. The sealing resin body 20 is made of, for example, epoxy resin. The sealing resin body 20 is formed, for example, by transfer molding. Figure 2 and Figure 3 As shown, the sealing resin body 20 has a substantially rectangular planar shape. The sealing resin body 20 has a front surface 20a and a back surface 20b opposite to the front surface 20a in the Z direction. The front surface 20a and the back surface 20b are, for example, flat surfaces.

[0079] Semiconductor element 30 is formed by forming a vertical element on a semiconductor substrate made of silicon (Si) or a wide-bandgap semiconductor with a wider bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The vertical element is configured so that the main current flows in the Z direction, the thickness direction of semiconductor element 30 (semiconductor substrate).

[0080] In semiconductor device 17A, semiconductor element 30 includes a switching element Q1 and a diode D1 as vertical elements. Similarly, in semiconductor device 17B, semiconductor element 30 includes a switching element Q2 and a diode D2. In semiconductor device 17C, semiconductor element 30 includes a switching element Q3 and a diode D3. In this embodiment, IGBTs are used as switching elements Q1, Q2, and Q3, and the vertical elements are RC (Reverse Conducting) IGBTs.

[0081] The semiconductor element 30 has a gate electrode (not shown). The gate electrode has, for example, a trench structure. The semiconductor element 30 has main electrodes on both sides of the element in the thickness direction, i.e., the Z direction. Specifically, as main electrodes, a collector electrode 31C is provided on one side, and an emitter electrode 31E is provided on the opposite side, i.e., the back side. The collector electrode 31C also serves as the cathode electrode of the diode. The emitter electrode 31E also serves as the anode electrode of the diode. The collector electrode 31C corresponds to the first main electrode, and the emitter electrode 31E corresponds to the second main electrode.

[0082] The semiconductor element 30 has a roughly rectangular planar shape. On its back surface, the semiconductor element 30 has a pad 31P formed at a different position from the emitter electrode 31E. The emitter electrode 31E and the pad 31P are each exposed from a protective film (not shown). The collector electrode 31C is formed on substantially the entire surface of one side of the semiconductor element 30. The emitter electrode 31E is formed on a portion of the back surface of the semiconductor element 30. In plan view, the collector electrode 31C has a larger area than the emitter electrode 31E. The emitter electrode 31E has a roughly rectangular planar shape.

[0083] The pad 31P is a signal electrode. The pad 31P is electrically separated from the emitter electrode 31E. The pad 31P is formed at the end on the opposite side of the formation area of ​​the emitter electrode 31E in the Y direction. The pad 31P and the emitter electrode 31E are arranged in the Y direction. The pad 31P includes at least a pad for the gate electrode. The semiconductor element 30 of this embodiment has five pads 31P. Specifically, there are a pad for the gate electrode, a pad for the Kelvin emitter for detecting the potential of the emitter electrode 31E, a pad for current sensing, a pad for the anode potential of the temperature sensor (temperature sensing diode) for detecting the temperature of the semiconductor element 30, and a pad for the cathode potential of the diode. The five pads 31P are concentrated on one end side in the Y direction of the semiconductor element 30, which has a planar shape that is roughly rectangular, and are arranged in the X direction.

[0084] Each semiconductor device 17 includes two semiconductor elements 30. Semiconductor device 17A includes semiconductor element 30H, which constitutes upper arm 6H, and semiconductor element 30L, which constitutes lower arm 6L. In semiconductor device 17A, the two semiconductor elements 30H and 30L have identical structures. Semiconductor elements 30H and 30L are aligned in the X direction. Semiconductor elements 30H and 30L are positioned approximately at the same position in the Z direction.

[0085] Similarly, semiconductor device 17B includes a semiconductor element 30H constituting upper arm 7H and a semiconductor element 30L constituting lower arm 7L. In semiconductor device 17B, the two semiconductor elements 30H and 30L have identical structures. Semiconductor elements 30H and 30L are aligned in the X direction. Semiconductor elements 30H and 30L are positioned approximately at the same position in the Z direction. Semiconductor device 17C includes a semiconductor element 30H constituting upper arm 8H and a semiconductor element 30L constituting lower arm 8L. In semiconductor device 17C, the two semiconductor elements 30H and 30L have identical structures. Semiconductor elements 30H and 30L are aligned in the X direction. Semiconductor elements 30H and 30L are positioned approximately at the same position in the Z direction.

[0086] like Figure 6 、 Figure 8 and Figure 10 As shown, the sizes of semiconductor elements 30 in semiconductor devices 17A, 17B, and 17C differ from one another. Size refers to the size (area) of the planar shape. Semiconductor elements 30H and 30L of semiconductor device 17C constituting converter 6 are larger than semiconductor elements 30H and 30L of semiconductor devices 17A and 17B constituting inverters 7 and 8. Semiconductor elements 30H and 30L of semiconductor device 17A constituting inverter 7 are smaller than semiconductor elements 30H and 30L of semiconductor devices 17B and 17C constituting inverter 7 and converter 6. The sizes of semiconductor elements 30 satisfy the relationship of semiconductor device 17A < semiconductor device 17B < semiconductor device 17C. Furthermore, the size of emitter electrode 31E satisfies the relationship of semiconductor device 17A < semiconductor device 17B < semiconductor device 17C.

[0087] The thickness of the semiconductor element 30 is set according to required characteristics such as withstand voltage, and may be substantially equal to or different from each other in the semiconductor devices 17A, 17B, and 17C.

[0088] The heat sink 40 is positioned on the collector electrode 31C side of the semiconductor element 30 in the Z direction. The heat sink 40 is a wiring component electrically connected to the collector electrode 31C via solder 90. The heat sink 40 corresponds to a first wiring component. The heat sink 40 has an opposing surface 40a facing the semiconductor element 30 and a back surface 40b opposite to the opposing surface 40a. Solder 90 exists between the opposing surface 40a of the heat sink 40 and the collector electrode 31C of the semiconductor element 30, forming a solder joint.

[0089] The heat sink 40 dissipates the heat of the semiconductor element 30 to the outside. As the heat sink 40 (first wiring component), for example, a metal plate made of Cu, Cu alloy, etc., a DBC (Direct Bonded Copper) substrate, etc. can be used. The heat sink 40 can have a plating film of Ni, Au, etc. on the surface. The heat sink 40 of this embodiment is a metal plate made of Cu. The heat sink 40 is formed as a part of the lead frame 95. The heat sink 40 is a thick-walled part in the lead frame 95 of the special-shaped bar. The semiconductor device 17 is provided with two heat sinks 40. The semiconductor device 17 is provided with a heat sink 40H constituting an upper arm and a heat sink 40L constituting a lower arm.

[0090] like Figure 9As shown, the heat sinks 40H and 40L have a generally rectangular planar shape. The heat sinks 40H and 40L are aligned in the X direction. The heat sinks 40H and 40L have approximately the same thickness and are positioned approximately at the same position in the Z direction. Joints formed by solder 90 are formed between the facing surface 40a of the heat sink 40H and the collector electrode 31C of the semiconductor element 30H, and between the facing surface 40a of the heat sink 40L and the collector electrode 31C of the semiconductor element 30L.

[0091] Heat sinks 40H and 40L enclose corresponding semiconductor elements 30 in a plan view viewed from the Z direction. The back surfaces 40b of heat sinks 40H and 40L are exposed from the encapsulating resin body 20. Back surfaces 40b are sometimes referred to as heat dissipation surfaces or exposed surfaces. Back surfaces 40b are substantially coplanar with the back surface 20b of the encapsulating resin body 20. Back surfaces 40b of heat sinks 40H and 40L are aligned in the X direction.

[0092] The heat sink 50 and the terminal 60 are arranged on the back side of the semiconductor element 30 in the Z direction and are wiring components electrically connected to the emitter electrode 31E via solders 91 and 92. The heat sink 50 corresponds to the second wiring component. The heat sink 50 is connected to the emitter electrode 31E via the terminal 60. Solder 91 is interposed between the heat sink 50 and the terminal 60, and solder 92 is interposed between the terminal 60 and the semiconductor element 30.

[0093] The heat sink 50 dissipates the heat of the semiconductor element 30 to the outside. As the heat sink 50 (second wiring component), for example, a metal plate made of Cu, Cu alloy, etc., a DBC (Direct Bonded Copper) substrate, etc. can be used. The heat sink 50 can have a plating film of Ni, Au, etc. on the surface. The heat sink 50 of this embodiment is a metal plate made of Cu. The heat sink 50 has an opposing surface 50a as the surface on the semiconductor element 30 side and a back surface 50b as the surface opposite to the opposing surface 50a. The semiconductor device 17 is provided with two heat sinks 50. The semiconductor device 17 is provided with a heat sink 50H constituting an upper arm and a heat sink 50L constituting a lower arm.

[0094] like Figure 11 As shown, the heat sinks 50H and 50L have a generally rectangular planar shape. They are aligned in the X-direction. They have approximately the same thickness and are positioned approximately at the same position in the Z-direction. When viewed from the Z-direction, the heat sinks 50H and 50L enclose the corresponding semiconductor element 30 and terminal 60. The heat sinks 50H and 50L have a connection region 51 and a groove 52 on their surfaces 50a facing the terminal 60.

[0095] The connection region 51 is an area of ​​the facing surface 50a surrounded by the groove 52. The connection region 51 is an area of ​​a predetermined size (area) set for electrical connection with the terminal 60. The groove 52 defines the connection region 51 within the groove 52. The groove 52 accommodates the remaining solder 91. The groove 52 is formed, for example, in an annular shape.

[0096] The back surfaces 50b of the heat sinks 50H and 50L are exposed from the sealing resin body 20. The back surfaces 50b are sometimes referred to as heat dissipation surfaces or exposed surfaces. The back surfaces 50b are substantially coplanar with the one surface 20a of the sealing resin body 20. The back surfaces 50b of the heat sinks 50H and 50L are aligned in the X direction.

[0097] The terminal 60 is located between the semiconductor element 30 and the heat sink 50 in the Z direction. The terminal 60 is located midway between the electrical and thermal conduction path of the semiconductor element 30 (emitter electrode 31E) and the heat sink 50. The terminal 60 is a columnar body formed using a metal material such as Cu or a Cu alloy. The terminal 60 may have a coating on its surface. The terminal 60 is sometimes referred to as a metal block or a relay component. The terminal 60 has an end face 60a on the semiconductor element 30 side and an end face 60b on the heat sink 50 side. The end face 60a corresponds to the first end face, and the end face 60b corresponds to the second end face.

[0098] Each semiconductor device 17 includes two terminals 60. Each semiconductor device 17 includes a terminal 60H constituting an upper arm and a terminal 60L constituting a lower arm. Joints formed with solder 92 are formed between the end face 60a of the terminal 60H and the emitter electrode 31E of the semiconductor element 30H, and between the end face 60a of the terminal 60L and the emitter electrode 31E of the semiconductor element 30L. Joints formed with solder 91 are formed between the end face 60b of the terminal 60H and the facing surface 50a of the heat sink 50H, and between the end face 60b of the terminal 60L and the facing surface 50a of the heat sink 50L.

[0099] The terminals 60H and 60L of this embodiment are pillars having a substantially rectangular planar shape and having substantially the same size as the emitter electrode 31E in plan view. Figure 6 、 Figure 8 and Figure 10 As shown, the size of the terminal 60 satisfies the relationship of semiconductor device 17A < semiconductor device 17B < semiconductor device 17C. The positional relationship between the terminal 60 and the groove 52 of the heat sink 50 will be described later. The thickness (length in the Z direction) of the terminal 60 is substantially equal in semiconductor devices 17A, 17B, and 17C.

[0100] The connectors 70 and 71 connect the components constituting the upper and lower arm circuits. The connectors connect the components constituting the semiconductor device 17. Figure 6 and Figure 9 As shown, the joint portion 70 is connected to the heat sink 40L. The thickness of the joint portion 70 is thinner than that of the heat sink 40L. The joint portion 70 is connected to the opposing surface (side surface) opposite to the heat sink 40H in a state that is roughly coplanar with the opposing surface 40a of the heat sink 40L. The joint portion 70 has two curved portions so as to be roughly crank-shaped in the ZX plane. The joint portion 70 is covered by the sealing resin body 20. The joint portion 70 can be connected by being provided integrally with respect to the heat sink 40L, or it can be provided as a separate component and connected by connection. The joint portion 70 of this embodiment is provided integrally with the heat sink 40L as part of the lead frame 95.

[0101] like Figure 6 、 Figure 7 and Figure 11 As shown, the joint portion 71 is connected to the corresponding heat sink 50. The joint portion 71 is connected to the heat sinks 50H and 50L, respectively. The thickness of the joint portion 71 is thinner than that of the corresponding heat sink 50. The joint portion 71 is covered by the sealing resin body 20. The joint portion 71 can be connected by being provided integrally with the heat sink 50, or it can be provided as a separate component and connected by connection. The joint portion 71 of this embodiment is provided integrally with the corresponding heat sinks 50H and 50L. The joint portion 71 extends in the X direction from the opposing side surfaces of the two heat sinks 50H and 50L.

[0102] In this embodiment, the heat sink 50H including the joint portion 71 and the heat sink 50L including the joint portion 71 are common components. The heat sink 50H including the joint portion 71 and the heat sink 50L including the joint portion 71 are arranged with bi-symmetry about the Z axis. Solder 93 is present between the opposing surfaces of the joint portion 70 connected to the heat sink 40L and the joint portion 71 connected to the heat sink 50H, forming a solder joint. A groove 72 is formed on the joint surface of the joint portion 71 to surround the solder joint. The groove 72 is, for example, annular in shape. The groove 72 is formed, for example, by stamping.

[0103] Main terminal 80 and signal terminal 85 are external connection terminals. Main terminal 80 is electrically connected to the main electrode of semiconductor element 30. Main terminal 80 includes a positive terminal 80P, a negative terminal 80N, and an output terminal 80S. Positive terminal 80P and negative terminal 80N serve as power supply terminals. Positive terminal 80P is electrically connected to the positive terminal of smoothing capacitor C2. Negative terminal 80N is electrically connected to the negative terminal of smoothing capacitor C2. Positive terminal 80P is sometimes referred to as the P terminal, meaning a high-potential power supply terminal. Negative terminal 80N is sometimes referred to as the N terminal, meaning a low-potential power supply terminal.

[0104] The positive terminal 80P is connected to one end of the heat sink 40H in the Y direction. The thickness of the positive terminal 80P is thinner than that of the heat sink 40H. The positive terminal 80P is connected to the heat sink 40H in a manner that is substantially coplanar with the opposing surface 40a. The positive terminal 80P can be connected by being integrally provided with respect to the heat sink 40H, or it can be provided as a separate component and connected by connection. The positive terminal 80P of this embodiment is integrally provided with the heat sink 40H as part of the lead frame 95. The positive terminal 80P extends from the heat sink 40H in the Y direction and protrudes outward from the side surface 20c of the sealing resin body 20. The positive terminal 80P has a curved portion midway in the portion covered by the sealing resin body 20 and protrudes from near the center in the Z direction of the side surface 20c.

[0105] like Figure 7 As shown, the negative terminal 80N is connected to the tab 71 connected to the heat sink 50L. Solder 94 is present between the opposing surfaces of the negative terminal 80N and the tab 71, forming a solder joint. The negative terminal 80N extends in the Y direction, protruding from the same side surface 20c as the positive terminal 80P toward the outside of the encapsulating resin body 20. The negative terminal 80N has a connection portion 81 connected to the tab 71 near one end in the Y direction. A portion of the negative terminal 80N, including the connection portion 81, is covered by the encapsulating resin body 20, while the remaining portion protrudes from the encapsulating resin body 20. The connection portion 81 is thicker than the portion protruding from the encapsulating resin body 20. The connection portion 81 has a thickness that is approximately the same as the thickness of the heat sink 40, for example. Like the main terminal, the negative terminal 80N also has a curved portion, protruding from near the center of the side surface 20c in the Z direction. The negative terminal 80N in this embodiment is formed as part of the lead frame 95.

[0106] Output terminal 80S is connected to the connection point between the upper arm and the lower arm. Output terminal 80S of semiconductor device 17A is electrically connected to the winding (stator coil) of the corresponding phase of motor generator 3. Output terminal 80S of semiconductor device 17B is electrically connected to the winding (stator coil) of the corresponding phase of motor generator 4. Output terminal 80S of semiconductor device 17C is electrically connected to reactor R1. Output terminal 80S is sometimes referred to as the "O terminal." Output terminals 80S of semiconductor devices 17A and 17B constituting inverters 7 and 8 are sometimes referred to as "AC terminals."

[0107] The output terminal 80S is connected to one end of the heat sink 40L in the Y direction. The output terminal 80S is thinner than the heat sink 40L. The output terminal 80S is connected to the heat sink 40L in a manner substantially coplanar with the opposing surface 40a. The output terminal 80S can be connected to the heat sink 40L by being integrally provided with the heat sink 40L, or it can be provided as a separate component and connected by connection. In this embodiment, the output terminal 80S is integrally provided with the heat sink 40L as part of the lead frame 95.

[0108] The output terminal 80S extends from the heat sink 40L in the Y direction and protrudes from the same side surface 20c as the positive terminal 80P, toward the outside of the sealing resin body 20. Like the positive terminal 80P, the output terminal 80S has a curved portion and protrudes from near the center of the side surface 20c in the Z direction. The three main terminals 80 are arranged in the X direction in the order of the positive terminal 80P, the negative terminal 80N, and the output terminal 80S.

[0109] The signal terminals 85 are electrically connected to the pads 31P of the corresponding semiconductor elements 30. In this embodiment, the electrical connection is via bonding wires 96. The signal terminals 85 extend in the Y direction, protruding outward from the side surface 20d of the encapsulating resin body 20. The side surface 20d is the surface opposite to the side surface 20c in the Y direction. In this embodiment, five signal terminals 85 are provided for each semiconductor element 30.

[0110] In the signal terminal 85, the inner conductor portion disposed inside the sealing resin body 20 is as shown in FIG. Figure 9 and Figure 10 As shown, the bonding wire 96 has a cranked shape. In the signal terminal 85, the connection portion of the bonding wire 96 and the encapsulated end portion on the side surface 20d are offset in the X direction. The connection portion of the bonding wire 96 is closer to the corresponding semiconductor element 30 (pad 31P) in the X direction than the encapsulated end portion on the side surface 20d. This cranked shape shortens the length of the bonding wire 96, which can suppress wire flow during molding of the encapsulating resin body 20.

[0111] in addition, Figure 5 Reference numeral 97 denotes a suspension conductor. The heat sink 40 (40H, 40L), the connector 70, the main terminal 80, and the signal terminal 85 are formed from a common lead frame 95. This lead frame 95 is a shaped strip with varying thicknesses in certain areas. Before cutting, the signal terminal 85 is connected to the suspension conductor 97 via tie bars 98. Unnecessary portions of the lead frame 95, such as the tie bars 98, are cut (removed) after molding the encapsulating resin body 20.

[0112] As described above, in the semiconductor device 17, the plurality of semiconductor elements 30 constituting the upper and lower arm circuits of a single phase are encapsulated by the encapsulating resin body 20. The encapsulating resin body 20 integrally encapsulates the plurality of semiconductor elements 30, a portion of each heat sink 40, a portion of each heat sink 50, the terminal 60, the connector portions 70 and 71, the main terminal 80, and a portion of each signal terminal 85.

[0113] In the Z direction, semiconductor element 30 is positioned between heat sinks 40 and 50. This allows heat from semiconductor element 30 to be dissipated to both sides in the Z direction. Semiconductor device 17 has a double-sided heat dissipation structure. The back surface 40b of heat sink 40 is approximately coplanar with the back surface 20b of encapsulating resin body 20. The back surface 50b of heat sink 50 is approximately coplanar with the first surface 20a of encapsulating resin body 20. Because back surfaces 40b and 50b are exposed, heat dissipation is enhanced.

[0114] As described above, the semiconductor elements 30 (30H, 30L) and the terminals 60 (60H, 60L) differ in size among the semiconductor devices 17A, 17B, and 17C. Other components, specifically the heat sink 40, main terminals 80, signal terminals 85, and connector 70, as well as the heat sink 50 integrated with the connector 71, are common to the semiconductor devices 17A, 17B, and 17C. In other words, they are common parts. The encapsulating resin body 20 also has the same outer contour among the semiconductor devices 17A, 17B, and 17C, and is formed using a common molding die 100, making it a common part.

[0115] <Method for Manufacturing Semiconductor Device>

[0116] Then, based on Figures 9 to 14 An example of a method for manufacturing the above-mentioned semiconductor device 17 will be described. Figure 12 It is a partial cross-sectional view showing the molding process of the sealing resin body 20 . Figure 12 Indicates the mid-stage of resin injection. Figure 12 The figure shows the resin flow around the terminal. Figure 13 It is a plan view showing the sealing resin body 20 after molding. Figure 14 Hereinafter, the solder in the molten state will be referred to as molten solder.

[0117] First, prepare Figure 9 The lead frame 95 shown in FIG. Figure 10 As shown, a stacked body having the semiconductor element 30 and the terminal 60 arranged thereon is formed on the heat sink 40. Specifically, molten solder 90 is applied to the facing surface 40a of the heat sink 40, and the semiconductor element 30 is arranged on the molten solder 90 with the collector electrode 31C facing the facing surface 40a. Next, molten solder 92 is applied to the emitter electrode 31E of the semiconductor element 30, and the terminal 60 is arranged on the molten solder 92. Furthermore, molten solder 91 is applied to the end surface 60b of the terminal 60. Molten solders 93 and 94 are also applied to the joint portion 70 and the connecting portion 81.

[0118] The molten solders 90 to 94 can be applied using, for example, a transfer method. The applied molten solders 90 and 92 solidify (solidify) to form a laminate. The molten solders 90 to 94 can be solidified (solidified) in the order in which they are stacked, or all solidified (solidified) at once. The bonding wire 96 can be connected after the laminate is formed, or before the molten solder 92 is applied to the emitter electrode 31E while the molten solder 90 is solidified.

[0119] As described above, semiconductor device 17 with a double-sided heat dissipation structure is sandwiched between heat exchanger 180 of cooler 18 from both sides in the Z direction. This requires high surface parallelism and high dimensional accuracy between surfaces in the Z direction. Therefore, solder 91 is provided in an amount sufficient to accommodate variations in the height of semiconductor device 17. In other words, more solder 91 is provided than solders 90 and 92. The same applies to solders 93 and 94.

[0120] Then, if Figure 11 As shown, the laminate is connected to the heat sink 50. The heat sink 50 is placed on a pedestal (not shown) with the opposing surface 50a facing upward. Next, the laminate is placed on the heat sink 50 with the end surface 60b of the terminal 60, i.e., the solder 91, facing the opposing surface 50a, and reflow is performed. During reflow, a load is applied in the Z direction from the heat sink 40 side so that the height of the semiconductor device 17 becomes a predetermined height. Specifically, by applying a load, a spacer (not shown) is brought into contact with both the opposing surface 40a of the heat sink 40 and the mounting surface of the pedestal. In this way, the height of the semiconductor device 17 becomes a predetermined height.

[0121] By reflowing, the terminal 60 and the heat sink 50 are connected (joined) via the solder 91. That is, the emitter electrode 31E and the heat sink 50 are electrically connected. The solder 91 absorbs the height deviation caused by the dimensional tolerance and assembly tolerance of the elements constituting the semiconductor device 17. For example, in order to make the height of the semiconductor device 17 a specified height, when the entire amount of solder 91 is required, the entire amount of solder 91 remains in the connection area 51 on the inner side of the groove 52. On the other hand, in order to achieve the specified height, when the solder 91 is excessive, the remaining amount of solder 91 is accommodated in the groove 52. In addition, by reflowing, the joint portion 70 and the joint portion 71 connected to the heat sink 50 are connected via the solder 93. In addition, the joint portion 71 connected to the heat sink 50L and the connection portion 81 of the negative terminal 80N are connected via the solder 94.

[0122] Next, the sealing resin body 20 is molded by transfer molding. For example, the sealing resin body 20 is molded so as to completely cover the heat sinks 40 and 50. Figure 12As shown, resin 21 is injected into cavity 101 of mold 100 through gate 102. Gate 102 is connected to the side surface of cavity 101 on the semiconductor element 30H side. Gate 102 is connected to cavity 101 near the connection between heat sink 40H and suspension conductor 97.

[0123] The molding die 100 includes a flow cavity 103. The flow cavity 103 is connected to the cavity 101 that forms the sealing resin body 20. The flow cavity 103 is connected to the side of the wall forming the cavity 101 opposite to the gate 102. The flow cavity 103 is provided on the signal terminal 85 side in the Y direction.

[0124] The resin 21 flows along the side of the terminal 60 to the area where the semiconductor element 30 and the heat sink 50 face each other. The resin 21 first fills around the terminal 60 (60H) that is closer to the gate 102, and then fills around the terminal 60 (60L) that is farther from the gate 102. Figure 12 As indicated by the hollow arrows, resin 21 flows in the Y direction and in the X direction. Resin 21 also flows into flow chamber 103. This slows the flow of resin in the Y direction. Consequently, the resin 21 flowing in the X direction and the resin 21 flowing in the Y direction merge at the corner of semiconductor element 30L. The corner is located on the Y-direction side of main terminal 80 and on the outside in the X direction.

[0125] Thus, by providing the flow chamber 103, the flow rate of the resin 21 can be adjusted, and the final confluence portion 104 of the resin 21 can be provided at the corner of the semiconductor element 30L. This can reduce the amount of air holes involved. Figure 13 As shown, the protrusions 22 and 23 are connected to the gate 102 and the flow cavity 103. Therefore, after the encapsulation resin body 20 is molded, the protrusions 22 and 23 are removed (cut off).

[0126] Next, the sealing resin body 20 is cut. In this embodiment, the sealing resin body 20 is cut together with a portion of the heat sinks 40 and 50. Figure 14 As shown in FIG. 1 , the back surfaces 40b and 50b of the heat sinks 40 and 50 are exposed from the sealing resin body 20 by cutting. The back surface 40b is substantially flush with the back surface 20b, and the back surface 50b is substantially flush with the one surface 20a.

[0127] Next, unnecessary portions such as the tie bars 98 are removed from the lead frame 95 , thereby obtaining the semiconductor device 17 .

[0128] The method for manufacturing semiconductor device 17 is not limited to the above example. For example, the back surfaces 40b, 50b of heat sinks 40, 50 may be pressed against the wall surface of mold 100, and the encapsulating resin body 20 may be molded in a close contact state. In this case, the back surfaces 40b, 50b are exposed from the encapsulating resin body 20 at the time the encapsulating resin body 20 is molded. This also eliminates the need for a cutting step.

[0129] Furthermore, the method is not limited to solder die bonding. Solder foil, etc., may be used instead of molten solder. Semiconductor device 17 may also be formed through a two-stage reflow process. Specifically, solders 90 and 92 may be reflowed in the first stage to form the aforementioned laminate, and solder 91 may be reflowed in the second stage to connect heat sink 50 to the laminate. In this case, the larger amount of solder 91 can also absorb height variations of semiconductor device 17.

[0130] <Positional Relationship between Terminals and Slots>

[0131] Then, based on Figures 6 to 8 、 Figure 10 and Figure 15 The positional relationship between the terminal 60 and the groove 52 of the heat sink 50 will be described. The dashed lines shown in the figures indicate the relative positions of the semiconductor devices 17A, 17B, and 17C. Figure 15 The positional relationship between the terminal 60 and the groove 52 is shown in each semiconductor device 17A, 17B, and 17C. Figure 15 In order to show the positional relationship, the end surface 60b is shown as the surface on the side facing the heat sink 50. Figure 15 Although the heat sink 50H and the terminal 60H on the upper arm side are illustrated in FIG, the heat sink 50L and the terminal 60L on the lower arm side also have the same structure.

[0132] As described above, the terminal 60 is connected to the emitter electrode 31E of the semiconductor element 30. In semiconductor devices 17A, 17B, and 17C, each having a semiconductor element 30 (emitter electrode 31E) of different sizes, the terminal 60 also has different sizes. In plan view, the size of the terminal 60 satisfies the relationship: semiconductor device 17A < semiconductor device 17B < semiconductor device 17C. The size of the end surface 60b facing the heat sink 50 also satisfies the relationship: semiconductor device 17A < semiconductor device 17B < semiconductor device 17C.

[0133] The planar shape of the end face 60b is roughly rectangular. Figure 15As shown, end face 60b has two sides 61a and 61b roughly parallel to the X direction and two sides 61c and 61d roughly parallel to the Y direction as the outer peripheral end. End face 60b can have rounded corners at the four corners, or it can be made into a structure without rounded corners. In the Y direction, side 61a is set on the signal terminal 85 side, that is, the pad 31P side, and side 61b is set on the main terminal 80 side. In the X direction, side 61c is set on the connector side, and side 61d is set on the outside of side 61c in the X direction. The X direction corresponds to the first direction, and the Y direction corresponds to the second direction. Side 61a corresponds to the first side, and side 61b corresponds to the second side. Side 61c corresponds to the third side, and side 61d corresponds to the fourth side.

[0134] The groove 52 of the heat sink 50 is a common structure in the semiconductor devices 17A, 17B, and 17C. That is, the structure is consistent with each other in a plan view. By making the groove 52 common, the heat sink 50 is a common component in the semiconductor devices 17A, 17B, and 17C. The groove 52 is sized to match the largest terminal 60 in the semiconductor devices 17A, 17B, and 17C that constitute the power conversion unit. In this embodiment, the terminal 60 of the semiconductor device 17C that constitutes the converter 6 is the largest. In a plan view, the size of the groove 52 is set to include the terminal 60 of the semiconductor device 17C. The groove 52 is configured to overlap only one or only two of the four sides 61a, 61b, 61c, and 61d of the end surface 60b in a plan view.

[0135] The planar shape of the groove 52 in this embodiment is roughly a rectangular ring. The groove 52 includes two extended portions 52a and 52b extending roughly parallel to the X direction, and two extended portions 52a and 52b extending roughly parallel to the Y direction. In the Y direction, the extended portion 52a is located on the signal terminal 85 side, i.e., the pad 31P side, while the extended portion 52b is located on the main terminal 80 side. In the X direction, the extended portion 52c is located on the connector side, and the extended portion 52d is located outside the extended portion 52c. The groove 52 may have rounded corners at the four corners of the rectangle, or it may not have rounded corners.

[0136] Groove 52 is offset relative to terminal 60 in the Y direction. Specifically, in the Y direction, the distance between edge 61a on the pad 31P side and extension 52a is shorter than the distance between edge 61b on the opposite side and extension 52b. Thus, groove 52 is positioned so that edge 61a on the pad 31P side is closer to groove 52 than edge 61b on the opposite side. In other words, the center of groove 52 does not coincide with the center of terminal 60, but is offset away from pad 31P. Consequently, terminal 60 is offset in the Y direction toward edge 61a.

[0137] With the above configuration, semiconductor devices 17A, 17B, and 17C include, as part of connection region 51, non-overlapping region 51a between edge 61b of end surface 60b and extended portion 52b of groove 52, where terminal 60 does not overlap. For example, in semiconductor device 17C, distance L1 between edge 61a on the pad 31P side and extended portion 52a is shorter than distance L2 between edge 61b on the opposite side and extended portion 52b. The same applies to other semiconductor devices 17A and 17B.

[0138] In semiconductor devices 17A and 17B, extended portion 52a of groove 52 overlaps side 61a of end surface 60b. Groove 52 does not overlap sides 61b, 61c, and 61d. Sides 61b, 61c, and 61d overlap connection region 51. Thus, in semiconductor devices 17A and 17B constituting inverters 7 and 8, groove 52 of heat sink 50 overlaps side 61a on the pad 31P side of end surface 60b, and does not overlap side 61b on the opposite side. Groove 52 overlaps only side 61a.

[0139] In semiconductor device 17C, extended portion 52c of groove 52 overlaps side 61c, and extended portion 52d overlaps side 61d. Groove 52 does not overlap sides 61a and 61b. Sides 61a and 61b overlap connection region 51. Thus, in semiconductor device 17C constituting inverter 6, groove 52 of heat sink 50 overlaps only with sides 61c and 61d at both ends of end surface 60b in the X direction.

[0140] <Summary of the First Embodiment>

[0141] As described above, in the semiconductor device 17 of this embodiment, the groove 52 of the heat sink 50 is arranged so as to overlap the outer peripheral edge of the end surface 60b of the terminal 60 in a plan view. This facilitates the flow of excess solder 91 into the groove 52. As a result, the excess solder 91 can be contained in the groove 52. For example, the diffusion of solder 91 onto the side surfaces of the terminal 60 can be suppressed.

[0142] Furthermore, rather than designing grooves 52 for each terminal 60, grooves 52 are designed to accommodate multiple types of terminals 60 of varying sizes. Specifically, rather than designing grooves 52 to overlap all four sides 61a, 61b, 61c, and 61d of the end face 60b of the terminal 60, grooves 52 are designed to overlap only one or two of the four sides 61a, 61b, 61c, and 61d. This allows grooves 52, which share a common structure, to accommodate excess solder 91 for multiple terminals 60 of varying sizes. By standardizing grooves 52, the heat sink 50 can be made into a common component.

[0143] As described above, according to the semiconductor device 17 of this embodiment, the excess solder 91 can be accommodated and the number of component types (models) can be reduced. This can reduce costs. In addition, by standardizing the heat sink 50, the mold for forming the groove 52 can also be standardized, thereby reducing manufacturing costs.

[0144] The power conversion device 5 of this embodiment includes multiple types of semiconductor devices 17A, 17B, and 17C that constitute different power conversion units. In the semiconductor devices 17A, 17B, and 17C, the sizes of the semiconductor elements 30 and the terminal 60 are different. On the other hand, the structure of the groove 52 is common. By making the groove 52 common, the heat sink 50 can be made into a common component. In addition, the groove 52 of the common structure is made sized to overlap only one or only two of the four sides 61a, 61b, 61c, and 61d of the end face 60b of the terminal 60 in each semiconductor device 17A, 17B, and 17C. As a result, the remaining solder 91 can be accommodated in the groove 52 in the multiple types of semiconductor devices 17A, 17B, and 17C. As a result, the number of parts in the power conversion device 5 can be reduced.

[0145] Furthermore, power conversion device 5 includes semiconductor device 17A constituting inverter 7, semiconductor device 17B constituting inverter 8, and semiconductor device 17C constituting converter 6. Specifically, it includes three types of semiconductor devices 17 (17A, 17B, and 17C) having semiconductor elements 30 and terminals 60 of different sizes. Any two of the three types of semiconductor devices 17 correspond to the first semiconductor device, and the other corresponds to the second semiconductor device. The power conversion unit formed by the first semiconductor device corresponds to the first power conversion unit, and the power conversion unit formed by the second semiconductor device corresponds to the second power conversion unit. For example, semiconductor device 17A corresponds to the first semiconductor device, and semiconductor device 17C corresponds to the second semiconductor device. Inverter 7 corresponds to the first power conversion unit, and converter 6 corresponds to the second conversion unit.

[0146] Hereinafter, more preferred aspects will be described. Figure 16 1 and 2. This is a cross-sectional view showing the effect of the arrangement of the grooves 52 of the present embodiment, and also showing a reference example. In the reference example, elements identical to or related to those of the present embodiment are denoted by adding r to the end of the reference numerals of the present embodiment.

[0147] In the reference example, the groove 52r does not overlap with the edges 61ar and 61r of the end face 60br of the terminal 60r. The edges 61ar and 61r overlap with the connection region 51r. In this structure, when the laminate is placed on the opposing surface 50ar of the heat sink 50r, the molten solder 91r is pushed from the laminate side and flows around the end face 60br during reflow. The groove 52r is recessed relative to the generally flat connection region 51r. As the solder 91 diffuses from the connection region 51r into the groove 52r, surface tension causes a significant amount of solder 91 to remain at the interface. As a result, the solder 91 bulges around the end face 60br. The solder 91r is closer to the semiconductor element 30r in the Z direction than the end face 60br. Consequently, the bulge of the solder 91r could potentially contact the bonding wire 96r. Furthermore, the solder 91r could potentially contact the side of the terminal 60r.

[0148] In contrast, in the semiconductor devices 17A and 17B of this embodiment, as shown in FIG. Figure 16 As shown, groove 52 is arranged so that it overlaps edge 61a on the pad 31P side of end surface 60b and does not overlap edge 61b on the opposite side. During reflow, even if molten solder 91 is pushed from the laminate side and flows around end surface 60b, it is contained in groove 52 on the pad 31P side. This prevents the formation of a bulge of solder 91 on the pad 31P side. This also prevents solder 91 from contacting bonding wire 96.

[0149] Furthermore, by accommodating a portion of solder 91 within groove 52, less solder 91 flows around end surface 60b and onto connection region 51. This prevents solder 91 from bulging on the side opposite to pad 31P. Even if a bulge occurs, its height is reduced. This prevents solder 91 from contacting the side surfaces of terminal 60.

[0150] In this embodiment, the connection region 51 has a non-overlapping region 51a between the side 61b and the extended portion 52b of the groove 52. Therefore, the solder 91 pressed against the periphery of the end surface 60b wets and spreads in the non-overlapping region 51a. This wetting and spreading prevents swelling of the solder 91.

[0151] In the semiconductor device 17C of this embodiment, the groove 52 is positioned so as to overlap the edges 61c and 61d at both ends of the end face 60b in the X direction. Although the terminal 60 of the semiconductor device 17C is the largest, the solder 91 that is pushed against the periphery of the end face 60b during reflow can be contained within the groove 52 (extended portions 52c and 52d) on both sides in the X direction. This prevents the solder 91 from wetting and spreading to the side surfaces of the terminal 60, for example.

[0152] In particular, in this embodiment, the groove 52 is offset relative to the terminal 60 in the Y direction. Specifically, the distance L1 between the edge 61a on the pad 31P side and the extension 52a is shorter than the distance L2 between the edge 61b on the opposite side and the extension 52b. This makes it easier for solder 91, which is pushed around the end surface 60b during reflow, to be accommodated in the groove 52 on the pad 31P side. This prevents the formation of a protrusion of solder 91 on the pad 31P side, thereby preventing contact between solder 91 and bonding wire 96.

[0153] (Second embodiment)

[0154] This embodiment is a modified example based on the previous embodiment, and the description of the previous embodiment can be cited. In the previous embodiment, the opposing surface 50a of the heat sink 50 is provided with a groove 52 to accommodate the excess solder 91. Furthermore, a structure can be used to prevent the solder from overflowing outside the groove 52.

[0155] Figure 17 In the semiconductor device 17 of this embodiment, the facing surface 50a of the heat sink 50 is shown. Figure 17 In, with Figure 15 Likewise, the end face 60b of the terminal 60 is shown. Figure 17 In FIG, the roughened area 53 is shaded. Figure 17 , the heat sink 50H and the terminal 60H on the upper arm side of the semiconductor device 17B are illustrated. However, the heat sink 50L and the terminal 60L on the lower arm side have the same structure. The semiconductor devices 17A and 17C also have the same structure. Figure 18 It is along Figure 17 Cross-sectional view of line XVIII-XVIII.

[0156] like Figure 17 As shown, semiconductor device 17 has a roughened region 53 on opposing surface 50a of heat sink 50. Roughened region 53 is provided to surround groove 52. Roughened region 53 is a region whose wettability with solder 91 is lower than that of portions of opposing surface 50a excluding roughened region 53, such as connection region 51 and groove 52. Roughened region 53 is provided substantially adjacent to the outer periphery of groove 52. In this embodiment, the entire area of ​​opposing surface 50a outside groove 52 serves as roughened region 53.

[0157] like Figure 18As shown, the heat sink 50 includes a base material 54, a metal film 55 provided on the surface of the base material 54, and an uneven oxide film 56. The base material 54 is the main component of the heat sink 50. The base material 54 is formed using a Cu-based material. The metal film 55 is formed from a material having higher wettability with the solder 91 than the base material 54. The metal film 55 is formed over the entire area of ​​the opposing surface 50a. The uneven oxide film 56 is formed locally on the opposing surface 50a.

[0158] The uneven oxide film 56 is formed locally on the metal film 55 in the opposing surface 50a by irradiating the metal film 55 with a laser. The metal film 55 is provided on the surface of the base material 54, for example, on a surface other than the back surface 50b. The metal film 55 has a base film mainly composed of Ni (nickel) and an upper film mainly composed of Au (gold). In this embodiment, a non-electrolytic Ni plating film containing P (phosphorus) is used as the base film. The upper film (Au) of the portion of the metal film 55 exposed from the uneven oxide film 56 and in contact with the solder 91 diffuses into the solder 91 during reflow. The upper film (Au) of the portion of the metal film 55 that forms the uneven oxide film 56 is removed by irradiation with a laser when the uneven oxide film 56 is formed. The uneven oxide film 56 is a film of an oxide mainly composed of Ni. For example, among the components constituting the uneven oxide film 56, 80% is NI2O3, 10% is NiO, and 10% is Ni.

[0159] The metal film 55 exposed from the uneven oxide film 56 on the facing surface 50a provides a region with high wettability to the solder 91 in the heat sink 50. The metal film 55 is exposed in the connection region 51 and the groove 52. The uneven oxide film 56 is formed in the roughened region 53.

[0160] Figure 18 The reference numeral 57 shown is a concave portion formed on the surface of the metal film 55. The concave portion 57 is formed by irradiation with a pulsed laser. One concave portion 57 is formed for each pulse. By irradiation with the laser, the surface layer of the metal film 55 is partially melted, vaporized, and evaporated, thereby forming a concave-convex oxide film 56. The concave-convex oxide film 56 is an oxide film derived from the metal film 55. The concave-convex oxide film 56 is a film of oxide of the metal (Ni) which is the main component of the metal film 55. The concave-convex oxide film 56 is formed by imitating the concave-convex of the surface of the metal film 55 having the concave portion 57. On the surface of the concave-convex oxide film 56, concave-convex is formed at a pitch finer than the width of the concave portion 57. That is, very fine concave-convex (roughened portion) is formed.

[0161] <Method for Forming Roughened Region>

[0162] Next, the method for forming the roughened region 53 is described. First, a heat sink 50 having a groove 52 is prepared. In this embodiment, a heat sink 50 is integrally connected to a joint portion 71 having a groove 72. The heat sink 50 connected to the joint portion 71 is formed by stamping a metal plate. At this point, the heat sink 50 includes the aforementioned base material 54 and the metal film 55.

[0163] Next, the facing surface 50a is irradiated with pulsed laser light to melt and evaporate the surface of the metal film 55. The pulsed laser light is adjusted so that the energy density is less than 0 J / cm 2 Large and 100J / cm 2 To meet this condition, YAG laser, YVO4 laser, fiber laser, etc. can be used. For example, in the case of YAG laser, the energy density is 1J / cm 2 In the case of electroless Ni plating, for example, even if it is 5J / cm 2 The metal film 55 can also be processed on the left and right sides.

[0164] At this time, the laser light source and heat sink 50 are moved relative to each other, scanning the laser light and sequentially irradiating multiple locations. Laser irradiation melts and vaporizes the surface of metal film 55, forming recesses 57 on the surface of metal film 55. The average thickness of the portion of metal film 55 irradiated with the laser light becomes thinner than the average thickness of the portion not irradiated with the laser light. Furthermore, the multiple recesses 57 formed corresponding to the laser spot are connected, forming a scale-like pattern, for example. A spot is the irradiation range formed by a single pulse.

[0165] For example, the laser beams are scanned so that adjacent laser beam spots in the X direction partially overlap, and adjacent laser beam spots in the Y direction partially overlap. In this case, the laser beam is scanned in the X direction starting from the X-direction reference coordinates to perform the first column of irradiation. Alternatively, after the first column of irradiation is completed, the Y-direction coordinates may be shifted, and the laser beam may be scanned in the X direction starting from the X-direction reference coordinates to perform the second column of irradiation.

[0166] In this embodiment, if Figure 19 As shown, after the first column of irradiation is completed, the laser is scanned in the reverse direction in the X direction to irradiate the second column. This allows for reverse scanning without waiting for return to the reference coordinates. This shortens the laser irradiation time. Furthermore, the light spots 105 in the first column and the light spots 105 in the second column are offset in the X direction. Specifically, the positions of the light spots 105 are offset in the X direction so that the center position between two adjacent light spots 105 in the first column is approximately aligned with the center position of the light spots 105 in the second column.

[0167] Next, the melted metal film 55 is partially solidified. Specifically, the melted and vaporized metal film 55 is vapor-deposited onto the portion irradiated with the laser and its surrounding portion. Thus, by vapor-depositing the melted and vaporized metal film 55, a concave-convex oxide film 56 is formed on the surface of the metal film 55. As described above, the staggered arrangement (staggered arrangement) of the light spots 105 can reduce the variation in the formation of the concave-convex oxide film 56 throughout the roughened region 53. In other words, the thickness of the concave-convex oxide film 56 per unit area can be made substantially uniform throughout the roughened region 53. The heat sink 50 is prepared as described above.

[0168] <Summary of Second Embodiment>

[0169] According to the present embodiment, a roughened area 53 is provided so as to surround the groove 52. In addition, the roughened area 53 is obtained by locally irradiating the metal film 55 having high wettability to the solder 91 with a laser to form a concave-convex oxide film 56. The oxide film (concave-convex oxide film 56) has lower wettability to the solder 91 than the metal film 55. Since the concave-convex oxide film 56 has fine concave and convex portions on its surface, the contact area with the solder 91 becomes smaller, and a portion of the solder 91 becomes spherical due to surface tension. That is, the contact angle becomes larger. As a result, the wettability to the solder 91 is low. Therefore, the concave-convex oxide film 56 can suppress the wetting and diffusion of the solder 91 outside the groove 52.

[0170] In this embodiment, as in the previous embodiment, the groove 52 is provided so as to overlap only one or two of the four sides 61a, 61b, 61c, and 61d of the end face 60b of the terminal 60. For example, in a structure where the groove 52 overlaps only the side 61a, even if the remaining solder 91 cannot be completely accommodated (absorbed) by the extended portion 52a overlapping the side 61a alone, the roughened area 53 (concave-convex oxide film 56) suppresses wetting and diffusion outside the groove 52. As a result, the remaining solder 91 is Figure 17 As indicated by the two-dot chain arrows, the solder 91 infiltrates and diffuses within the groove 52 on the side of the extensions 52c and 52d. Therefore, in a structure where the heat sink 50 is made into a common component by using the common groove 52, it is possible to suppress the solder 91 from overflowing outside the groove 52. This also applies to a structure where the groove 52 overlaps only with the sides 61c and 61d.

[0171] Because a laser is used to form the uneven oxide film 56 as described above, patterning the connection region 51 and grooves 52, which serve as high-wetting areas, and the roughened region 53, which serves as a low-wetting area, is easy. Furthermore, the surface of the uneven oxide film 56 is formed with extremely fine irregularities, which entangle the encapsulating resin body 20, creating an anchoring effect. Furthermore, the contact area with the encapsulating resin body 20 is increased. This ensures close contact between the encapsulating resin body 20 and the roughened region 53, the portion of the heat sink 50 where the uneven oxide film 56 is located.

[0172] <Modification>

[0173] In this embodiment, the entire area outside the groove 52 of the facing surface 50a of the heat sink 50 is provided as the roughened area 53, but the present invention is not limited thereto. Alternatively, the roughened area 53 may be provided only in a portion of the area outside the groove 52 so as to surround the groove 52.

[0174] For example, you can also Figure 20 As shown in the modified example, the area outside the groove 52, excluding the edge area 58, is used as the roughened area 53. Figure 20 In the figure, the roughened area 53 is shaded for clarity. The edge area 58 is the area including the outer periphery of the opposing surface 50a. During laser irradiation, the heat sink 50 is positioned using a positioning jig 106. The positioning jig 106 presses against the side of the heat sink 50. Therefore, if the roughened area 53 is extended to the outer periphery, there is a risk that the laser will cut through the positioning jig 106, reducing positioning accuracy.

[0175] On the opposing surface 50a, a recessed surface caused by stamping is formed within a specified range from the outer peripheral end. The recessed surface is rounded and uneven. During visual inspection using a camera (e.g., binarization), the recessed surface is difficult to inspect and is typically excluded from the inspection area. Therefore, by defining an edge region 58 within the recessed surface, it is possible to minimize the impact on the positioning fixture 106 while maintaining quality.

[0176] Although not shown, a roughened region may be provided on the surface of the connector 71 where the groove 72 is formed. Similar to the roughened region 53, the roughened region is formed by laser irradiation. The roughened region is provided outside the connector 71, surrounding the groove 72. Alternatively, the roughened region of the connector 71 may be provided in contact with the roughened region 53 of the heat sink 50.

[0177] You can also Figure 21 As shown in the modified example, in addition to the roughened area 53 of the heat sink 50, a roughened area 62 is provided on the side of the terminal 60. Figure 21In the figure, a roughened region 62 is provided over substantially the entire area of ​​the side surface. Roughened region 62, like roughened region 53, is formed by laser irradiation. Although not shown in the figure, terminal 60 also comprises a base material, a metal film provided on the base material, and a concave-convex oxide film. The presence of roughened region 62 on the side surface of terminal 60 can suppress the solder 91 from wetting and diffusing onto the side surface. In other words, the solder 91 can be suppressed from flowing through the side surface of terminal 60 into the solder joint of emitter electrode 31E. This can suppress a decrease in the connection reliability of the solder joint of emitter electrode 31E.

[0178] As described above, the signal terminal 85 is inserted and mounted on the circuit board 19. Therefore, for example, Figure 22 The illustrated correction jig 107 corrects the position of the signal terminals 85, particularly the position of the leading ends for insertion. Specifically, the correction jig 107 is pressed against the leading ends of the signal terminals 85, applying a load to the terminals 85 and causing them to deform. The load applied by the correction jig 107 is then released, causing the terminals 85 to rebound. This corrects the leading ends of the plurality of signal terminals 85.

[0179] Thus, in the structure for correcting the position of the signal terminal 85, it is preferable to Figure 23 As shown in the modified example, a roughened area 86 is provided at the base of the outer conductor portion of the signal terminal 85. Figure 23 In the figure, the roughened area 86 is shaded for clarity. The roughened area 86 is formed by laser irradiation, similar to the roughened area 53. Although not shown in the figure, the signal terminal 85 also has a base material, a metal film provided on the base material, and a concave-convex oxide film. In the roughened area 86, the thickness of the metal film (Ni plating) is thinner than that of the non-irradiated area. Therefore, when the signal terminal 85 is corrected, the roughened area 86 becomes the starting point for the plating to rupture. That is, the signal terminal 85 is deformed with the roughened area 86 as the starting point. In this way, since the starting point is stable, the deviation of the front end position after correction can be reduced.

[0180] Furthermore, the roughened region 86 is not limited to the base of the outer conductor. It can also extend from the outer conductor to the inner conductor. In the inner conductor, the roughened region 86 is formed avoiding the connection portion of the bonding wire 96. Providing the roughened region 86 in the inner conductor improves the adhesion of the encapsulating resin body 20.

[0181] (Third embodiment)

[0182] This embodiment is a modified example based on the previous embodiment, and the description of the previous embodiment can be used. In the previous embodiment, no special mention is made of the protective film of the semiconductor element. In contrast, a structure can also be made to prevent the sealing resin from peeling off from the protective film.

[0183] Figure 24 This is a plan view showing the structure of the back side of the semiconductor element 30 in the semiconductor device 17 of this embodiment. The semiconductor element 30 has a protective film 32. Figure 24 In the figure, the protective film 32 is shaded. The structural material of the protective film 32 is, for example, polyimide. The protective film 32 is provided on the back surface of the semiconductor substrate around the emitter electrode 31E and the pad 31P. The emitter electrode 31E and the pad 31P are exposed through an opening in the protective film 32. The protective film 32 is provided on the emitter electrode 31E side and is an insulating film that forms part of the surface of the semiconductor element 30. As described above, the emitter electrode 31E is connected to the solder 92. The pad 31P is connected to the bonding wire 96. The sealing resin body 20 is in close contact with the protective film 32.

[0184] For example, if the sealing resin body 20 peels off from the protective film 32 around the pad 31P, stress acts on the bonding wire 96, possibly breaking the bonding wire 96. Therefore, it is preferable that the protective film 32 has improved adhesion to the sealing resin body 20.

[0185] Figure 25 This is a graph showing the relationship between the arithmetic mean roughness Ra of the surface of the protective film 32 and the bulk fracture rate. Figure 25 Indicates the test results. Figure 25 As shown in Figure 1, if the arithmetic mean roughness Ra is 8 nm or greater, overall failure occurs with a 100% probability. On the other hand, when the roughness is less than 8 nm, interfacial failure and a combination of interfacial failure and overall failure are observed, resulting in an overall failure rate of less than 100%. Based on this understanding, in this embodiment, the surface of the protective film 32 is intentionally roughened to achieve an arithmetic mean roughness Ra of 8 nm or greater.

[0186] For example, the surface of the protective film 32 can be roughened by ashing. Ashing is a process in which high-energy oxygen plasma is irradiated onto the resin surface, causing it to combine with carbon constituting the resin and gasify and decompose as CO 2 (ashing).

[0187] <Summary of the Third Embodiment>

[0188] The semiconductor element 30 of this embodiment includes a protective film 32 having a surface arithmetic mean roughness Ra of 8 nm or greater. This improves the adhesion between the protective film 32 and the encapsulating resin body 20 in the semiconductor device 17. This makes it difficult for the encapsulating resin body 20 to peel from the protective film 32. For example, peeling of the encapsulating resin body 20 can be suppressed around the pad 31P, thereby suppressing breakage of the bonding wire 96.

[0189] Although the example of roughening the surface of the protective film 32 by ashing is shown, the present invention is not limited to this. For example, a plasma species other than oxygen, such as argon or nitrogen, may be used.

[0190] While polyimide is shown as an example of the protective film 32, the present invention is not limited thereto. Insulating films other than polyimide, such as silicon oxide films, silicon nitride films, and PSG (Phospho Silicate Glass) films, may also be used as the protective film 32. By intentionally roughening the surface of these insulating films, peeling of the sealing resin body 20 can be suppressed.

[0191] (Other embodiments)

[0192] The disclosure in this specification and the drawings is not limited to the illustrated embodiments. The present disclosure includes the illustrated embodiments and modified forms made by those skilled in the art based thereon. For example, the present disclosure is not limited to the combination of parts and / or elements shown in the embodiments. The present disclosure can be implemented through a variety of combinations. The present disclosure can have additional parts that are added to the embodiments. The present disclosure includes forms in which parts and / or elements of the embodiments are omitted. The present disclosure includes replacement or combination of parts and / or elements between one embodiment and other embodiments. The disclosed technical scope is not limited to the description of the embodiments. It should be understood that the disclosed several technical scopes are represented by the description of the claims, and also include all changes within the meaning and scope equivalent to the description of the claims.

[0193] The disclosure in the specification, drawings, and other aspects is not limited by the claims. The disclosure in the specification, drawings, and other aspects encompasses the technical concepts described in the claims and, in turn, encompasses technical concepts that are more diverse and extensive than those described in the claims. Therefore, a wide variety of technical concepts can be extracted from the disclosure in the specification, drawings, and other aspects, without being constrained by the claims.

[0194] When referring to an element or layer being "on," "connected," "connected," or "bound to," it may be directly on, connected, connected, or bound to other elements or layers, or there may be sandwiched elements or layers. In contrast, when referring to an element being "directly on," "directly connected," "directly connected," or "directly bound to" other elements or layers, there are no sandwiched elements or layers. Other words used to describe the relationship between elements should be interpreted in the same manner (for example, "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). When used in this specification, the term "and / or" includes any and all combinations of the associated listed one or more items.

[0195] The spatially relative terms "inside", "outside", "back", "bottom", "low", "top", "high", etc. are used here to easily describe the relationship of one element or feature relative to other elements or features as shown in the figures. Spatially relative terms can mean different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the figure is turned over, the element described as "below" or "directly below" other elements or features is oriented "above" other elements or features. Therefore, the term "bottom" can include both upper and lower orientations. The device can also be oriented in other directions (it can also be rotated to 90 degrees or other orientations), and the spatially relative descriptors used in this specification will be interpreted accordingly.

[0196] The control circuit unit 9 and the drive circuit unit 10 are provided by a control system including at least one computer. The control system includes at least one processor (hardware processor) as hardware. The hardware processor can be provided by the following (i), (ii), or (iii).

[0197] (i) A hardware processor may be a hardware logic circuit. In this case, the computer is provided by a digital circuit comprising a large number of programmed logic units (gate circuits). A digital circuit may include a memory storing programs and / or data. A computer may also be provided by an analog circuit. A computer may also be provided by a combination of digital and analog circuits.

[0198] (ii) The hardware processor may be at least one processor core that executes programs stored in at least one memory. In this case, the computer is provided by at least one memory and at least one processor core. A processor core is, for example, referred to as a CPU. Memory is also referred to as a storage medium. Memory is a non-movable, physical storage medium that non-temporarily stores "programs and / or data" that can be read by the processor.

[0199] (iii) The hardware processor may be a combination of (i) and (ii) above. (i) and (ii) may be implemented on different chips or on a common chip.

[0200] That is, the mechanisms and / or functions provided by the control circuit unit 9 and the drive circuit unit 10 can be provided by hardware only, software only, or a combination thereof.

[0201] While the power conversion device 5 is shown as including a control circuit unit 9, the present invention is not limited to this. For example, a configuration without the control circuit unit 9 can be achieved by also assigning the functions of the control circuit unit 9 to a higher-level ECU. While the present invention shows an example in which a drive circuit unit 10 is provided for each arm, the present invention is not limited to this. For example, a single drive circuit unit 10 may be provided for each upper or lower arm circuit.

[0202] The vehicle drive system 1 is not limited to the above-described structure. For example, an example is shown in which two electric generators 3 and 4 are provided, but the present invention is not limited thereto. An example is shown in which the power conversion device 5 includes a converter 6 and inverters 7 and 8 as a power conversion unit, but the present invention is not limited thereto. It is sufficient to have multiple power conversion units. For example, a structure may be provided with only multiple inverters. A structure may also be provided with one inverter and a converter. An example is shown in which the power conversion device 5 includes semiconductor devices 17A, 17B, and 17C, but the present invention is not limited thereto. The number of layers of the semiconductor device 17 in the semiconductor module 16 is also not limited to the above-described example.

[0203] While the semiconductor element 30 is shown as an example of an RC-IGBT element, the present invention is not limited to this. The switching elements Q1, Q2, and Q3 and the diodes D1, D2, and D3 may be implemented as separate chips (separate semiconductor elements). While IGBTs are shown as an example of the switching elements Q1, Q2, and Q3, the present invention is not limited to this. For example, MOSFETs may also be used.

[0204] A plurality of semiconductor elements 30H may be provided and connected in parallel to form one upper arm, and a plurality of semiconductor elements 30L may be provided and connected in parallel to form one lower arm.

[0205] While an example is shown in which the back surfaces 40b and 50b of the heat sinks 40 and 50 are exposed from the encapsulating resin body 20, this is not limiting. Alternatively, at least one of the back surfaces 40b and 50b may be covered by the encapsulating resin body 20. Alternatively, at least one of the back surfaces 40b and 50b may be covered by an insulating member (not shown) that is different from the encapsulating resin body 20. While an example is shown in which the semiconductor device 17 includes the encapsulating resin body 20, this is not limiting. Alternatively, a configuration may be employed in which the encapsulating resin body 20 is not included.

[0206] While the semiconductor device 17 is shown as including multiple semiconductor elements 30 that constitute the upper and lower arm circuits of a single phase, the present invention is not limited to this. Alternatively, the semiconductor device 17 may include only a semiconductor element 30 that constitutes a single arm. For example, the semiconductor device 17 may include only a semiconductor element 30 that constitutes a single arm, a pair of heat sinks 40 and 50 disposed so as to sandwich the semiconductor element 30, and a terminal 60 interposed between the semiconductor element 30 and the heat sink 50. Furthermore, the semiconductor elements that constitute the upper and lower arm circuits of multiple phases may be included as a single package.

[0207] Although the example in which the signal terminal 85 is connected to the pad 31P via the bonding wire 96 is shown, the present invention is not limited thereto. For example, the signal terminal 85 may be connected to the pad 31P via solder.

[0208] Although the example in which the groove 72 is provided in the joint portion 71 is shown, the present invention is not limited thereto and a structure in which the groove 72 is eliminated may be adopted.

Claims

1. A semiconductor device, characterized in that: have: A semiconductor element having a first main electrode and a second main electrode, wherein the second main electrode is formed on a surface opposite to the first main electrode in the thickness direction of the plate; a first wiring member connected to the first main electrode; a terminal having a first end face connected to the second main electrode and a second end face opposite to the first end face in the plate thickness direction, the second end face being rectangular with two sides parallel to a first direction and two sides parallel to a second direction, the first direction being orthogonal to the plate thickness direction, and the second direction being orthogonal to both the plate thickness direction and the first direction; and a second wiring member connected to the second end face of the terminal via solder, and having a connection region connected to the terminal and a groove surrounding the connection region and accommodating excess solder on a surface opposite to the terminal; One of the grooves surrounds only one of the connection areas; In a planar view viewed in the plate thickness direction, the groove is configured to include the terminal and overlap with only one or only two of the four sides of the second end surface of the terminal.

2. The semiconductor device according to claim 1, wherein The semiconductor element includes a pad formed on a surface on the second main electrode side and arranged in alignment with the second main electrode in the second direction; The groove is provided so as to be offset relative to the terminal in the second direction, overlap with a first side on the pad side of the second end surface among the sides, and not overlap with a second side opposite to the first side.

3. The semiconductor device according to claim 2, wherein The connection area is a portion between the second side of the terminal and the groove, including a non-overlapping area that does not overlap with the terminal in the plan view; The solder is also arranged in the non-overlapping region.

4. The semiconductor device according to claim 1, wherein The semiconductor element includes a pad formed on a surface on the second main electrode side and arranged in alignment with the second main electrode in the second direction; The groove overlaps with a third side and a fourth side on both sides of the second end surface in the first direction among the sides.

5. The semiconductor device according to claim 4, wherein The slot is offset relative to the terminal in the second direction; In the second direction, a first side of the second end surface, which is the side on the pad side, is closer to the groove than a second side, which is the side on the opposite side to the first side.

6. The semiconductor device according to any one of claims 1 to 5, wherein The second wiring member comprises a base material, a metal film formed on a surface of the base material, and a concavo-convex oxide film, the concavo-convex oxide film being an oxide of the same metal as the main component of the metal film and having a continuously concavo-convex surface; The uneven oxide film is provided on the opposing surface so as to surround the groove.

7. A power conversion device, characterized in that: have: a first semiconductor device constituting a first power conversion unit; and a second semiconductor device constituting a second power conversion unit; Each semiconductor device has: A semiconductor element having a first main electrode and a second main electrode, wherein the second main electrode is formed on a surface opposite to the first main electrode in the thickness direction of the plate; a first wiring member connected to the first main electrode; a terminal having a first end face connected to the second main electrode and a second end face opposite to the first end face in the plate thickness direction, the second end face being rectangular with two sides parallel to a first direction and two sides parallel to a second direction, the first direction being orthogonal to the plate thickness direction, and the second direction being orthogonal to both the plate thickness direction and the first direction; and a second wiring member connected to the second end face of the terminal via solder, and having a connection region connected to the terminal and a groove surrounding the connection region and accommodating excess solder on a surface opposite to the terminal; In the first semiconductor device and the second semiconductor device, the sizes of the terminals in a plan view viewed in the direction of the plate thickness are different from each other, and the sizes of the grooves are equal to each other; In each semiconductor device, one of the trenches surrounds only one of the connection regions; In the plan view, the groove of each semiconductor device includes the largest terminal among the terminals of each semiconductor device and overlaps with only one or two of the four sides of the second end surface of the terminal.

Images