Semiconductor device

Abstract

The source layer (13) is provided on a first p-type layer (12) composed of a nitride semiconductor, and includes a semiconductor region having electrons as carriers. The drain layer (14) is spaced apart from the source layer (13) on the first p-type layer (12) and faces each other in a first direction, and includes a semiconductor region having electrons as carriers. The channel structure (SR) is provided between the source layer (13) and the drain layer (14) on the first p-type layer (12), and channel regions (CN) and gate regions (GT) are alternately arranged in a second direction orthogonal to the first direction. A channel layer (15) included in the channel structure (SR) constitutes at least a part of the channel region (CN) and is composed of a nitride semiconductor. A gate layer (16) included in the channel structure (SR) constitutes at least a part of the gate region (GT) and electrically connects the gate electrode (19) and the first p-type layer (12).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and particularly to a semiconductor device that can operate in a microwave band. Background Art

[0002] In a conventional transistor using a nitride semiconductor, for example, it is known that a semiconductor device capable of operating with high output at high frequencies such as in a microwave band can be realized by using a high electron mobility transistor (HEMT: High Electron Mobility Transistor) structure or the like (for example, refer to Non-Patent Document 1 below).

[0003] Prior Art Documents

[0004] Non-Patent Documents

[0005] Non-Patent Document 1: G.H. Jessen et al., "Short-Channel Effect Limitations on High-Frequency Operation of AlGaN / GaN HEMTs for T-Gate Devices", IEEE Transactions on Electron Devices, Vol. 54, pp. 2589 - 2597, September 2007 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] In order for the semiconductor device as described above to operate at a higher frequency and with a higher output, it is important to shorten the gate length. However, as described in the above document, if the gate length is shortened, there is a problem that a phenomenon called the short-channel effect occurs and leakage current flows between the drain and the source.

[0008] The present disclosure has been made to solve the above problems, and an object thereof is to provide a semiconductor device that can suppress the short-channel effect even when the gate length is shortened.

[0009] Means for Solving the Problems

[0010] The semiconductor device of the present disclosure can operate in the microwave band and has a first direction and a second direction orthogonal to each other in the in-plane direction perpendicular to the thickness direction. The semiconductor device includes a first p-type layer, a source layer, a source electrode, a drain layer, a drain electrode, a gate electrode, and a channel structure. The first p-type layer is made of a nitride semiconductor. The source layer is provided on the first p-type layer and includes a semiconductor region having electrons as carriers. The source electrode is provided on the source layer. The drain layer is provided on the first p-type layer with a space from the source layer and facing each other in the first direction, and includes a semiconductor region having electrons as carriers. The drain electrode is provided on the drain layer. The gate electrode is separated from the source electrode and the drain electrode and is provided between the source electrode and the drain electrode in the first direction. The channel structure is provided between the source layer and the drain layer on the first p-type layer, and channel regions and gate regions are alternately arranged in the second direction. The channel structure includes a channel layer and a gate layer. The channel layer constitutes at least a part of the channel region and is made of a nitride semiconductor. The gate layer constitutes at least a part of the gate region and electrically connects the gate electrode and the first p-type layer.

[0011] Advantages of the Invention

[0012] According to the present disclosure, since the channel regions and the gate regions are alternately arranged in the second direction, an electric field corresponding to the gate potential can be applied to the channel layer in the channel region from both the one side and the other side in the second direction. Further, since the channel layer is provided on the first p-type layer electrically connected to the gate electrode, an electric field corresponding to the gate potential can also be applied to the channel layer in the channel region from the thickness direction. Based on the above, an electric field corresponding to the gate potential is applied to the channel layer in the channel region from three directions. Thereby, the gate controllability is improved, and thus the intrusion of the power lines from the drain is suppressed. Therefore, the short-channel effect can be suppressed.

[0013] The object, features, aspects, and advantages of the present disclosure become more apparent from the following detailed description and the drawings. Description of the Drawings

[0014] Figure 1 is a cross-sectional perspective view schematically showing the structure of the semiconductor device in Embodiment 1.

[0015] Figure 2 is Figure 1 top view of.

[0016] Figure 3 is along Figure 2 sectional view taken along line III-III of.

[0017] Figure 4 is along Figure 2 sectional view taken along line IV-IV of.

[0018] Figure 5 is a cross-sectional perspective view showing the first step of the manufacturing method of the semiconductor device in Embodiment 1 schematically.

[0019] Figure 6 is a cross-sectional perspective view showing the second step of the manufacturing method of the semiconductor device in Embodiment 1 schematically.

[0020] Figure 7 is a cross-sectional perspective view showing the third step of the manufacturing method of the semiconductor device in Embodiment 1 schematically.

[0021] Figure 8 is a cross-sectional perspective view showing the fourth step of the manufacturing method of the semiconductor device in Embodiment 1 schematically.

[0022] Figure 9 is Figure 8 a top view of.

[0023] Figure 10 is a top view showing the fifth step of the manufacturing method of the semiconductor device in Embodiment 1 schematically.

[0024] Figure 11 is Figure 10 a cross-sectional perspective view of.

[0025] Figure 12 is a cross-sectional perspective view showing the structure of the semiconductor device in a modified example of Embodiment 1 schematically.

[0026] Figure 13 is Figure 12 a top view of.

[0027] Figure 14 is along Figure 13 sectional view taken along line XIV-XIV of.

[0028] Figure 15 is along Figure 13 sectional view taken along line XV-XV of.

[0029] Figure 16 is a cross-sectional perspective view showing the structure of the semiconductor device in Embodiment 2 schematically.

[0030] Figure 17 is Figure 16 a top view of.

[0031] Figure 18 is along Figure 17 sectional view taken along line XVIII-XVIII of.

[0032] Figure 19 is a cross-sectional perspective view showing the structure of the semiconductor device in Embodiment 3 schematically.

[0033] Figure 20 is Figure 19 the top view of

[0034] Figure 21 is the sectional view taken along Figure 20 line XXI-XXI of

[0035] Figure 22 is a cross-sectional perspective view schematically showing the structure of the semiconductor device in Embodiment 4.

[0036] Figure 23 is Figure 22 the top view of

[0037] Figure 24 is the sectional view taken along Figure 23 line XXIV-XXIV of

[0038] Figure 25 is a cross-sectional perspective view schematically showing the structure of the semiconductor device in Embodiment 5.

[0039] Figure 26 is Figure 25 the top view of

[0040] Figure 27 is the sectional view taken along Figure 26 line XXVII-XXVII of

[0041] Figure 28 is the sectional view taken along Figure 26 line XXVIII-XXVIII of

[0042] Figure 29 is a cross-sectional perspective view schematically showing the structure of the semiconductor device in Embodiment 6.

[0043] Figure 30 is Figure 29 the top view of

[0044] Figure 31 is the sectional view taken along Figure 30 line XXXI-XXXI of

[0045] Figure 32 is the sectional view taken along Figure 30 line XXXII-XXXII of

[0046] (Description of Reference Numerals)

[0047] CN: Channel region; GT: Gate region; SR: Channel structure; 10: Substrate; 11: Nucleation layer; 12: p-type layer (first p-type layer); 13, 13V: Source layer; 14, 14V: Drain layer; 15, 15V, 15W: Channel layer; 15a - 15d: Heterojunction layer; 16: Gate layer; 17: Source electrode; 18: Drain electrode; 19: Gate electrode; 20: First source film; 21: Second source film; 22: First drain film; 23: Second drain film; 24: First channel film; 25: Second channel film; 26: Gate layer; 27, 27a - 27d: First channel film; 28, 28a - 28d: Second channel film; 29: p-type layer (second p-type layer); 30: Interlayer film; 40, 41: Mask layer; 100, 100V, 200, 300, 400, 500, 600: Transistor (semiconductor device). Detailed implementation mode

[0048] Hereinafter, the implementation mode will be described based on the drawings. In these drawings, the same or corresponding parts are denoted by the same reference numerals, and their descriptions will not be repeated. In addition, the semiconductor device of the present disclosure can be arranged in any posture with respect to the direction of gravity. Therefore, terms such as "upper part", "lower part", "above", "below", "upper surface" and "lower surface" in this specification, which have the meaning of the relative positional relationship between structural elements, do not necessarily take the direction of gravity as a reference, and any direction can be taken as a reference instead of the weight direction. In addition, in the specification, the "nitride-based semiconductor" is a general term for semiconductors having GaN (gallium nitride), AlN (aluminum nitride), InN (indium nitride), and intermediate components thereof.

[0049] <Embodiment 1>

[0050] Figure 1 and Figure 2 are a cross-sectional perspective view and a top view schematically showing the structure of the transistor 100 (semiconductor device) in the present Embodiment 1, respectively. Figure 3 and Figure 4 are cross-sectional views along Figure 2 the lines III-III and IV-IV, respectively.

[0051] The transistor 100 is a semiconductor device that can operate in the microwave band. The transistor 100 has a first direction ( Figure 1 、 Figure 3 and Figure 4 in the in-plane direction perpendicular to the longitudinal direction in each of the thickness directions ( Figure 2 and Figure 2 ), which are orthogonal to each other, and a second direction ( Figure 1In the perspective view, the first direction is the width direction and the second direction is the depth direction. The transistor 100 includes a p-type layer 12 (first p-type layer), a source layer 13, a source electrode 17, a drain layer 14, a drain electrode 18, a gate electrode 19, and a channel structure SR. Additionally, the transistor 100 may have a substrate 10 and further may have a nucleation layer 11 (buffer layer).

[0052] The p-type layer 12 is made of a nitride-based semiconductor. The p-type layer 12 is preferably composed of Al x Ga 1-x N (1≥x≥0), for example, made of GaN. The thickness of the p-type layer 12 ( Figure 3 and Figure 4 the dimension in the longitudinal direction) is, for example, 2 μm or less.

[0053] The source layer 13 is disposed on the p-type layer 12 and includes a semiconductor region having electrons as carriers. The drain layer 14 is disposed on the p-type layer 12 and includes a semiconductor region having electrons as carriers. Specifically, the source layer 13 and the drain layer 14 have semiconductor regions doped in an n-type manner, and electrons as carriers are generated by this doping. The source layer 13 and the drain layer 14 are, for example, made of GaN. The respective thicknesses of the source layer 13 and the drain layer 14 are, for example, 20 nm or more and 2 μm or less. The drain layer 14 is spaced apart from the source layer 13 on the p-type layer 12 and faces each other in the first direction ( Figure 2 the lateral direction).

[0054] The source electrode 17 and the drain electrode 18 are respectively disposed on the source layer 13 and the drain layer 14. The source electrode 17 and the drain electrode 18 are each preferably made of a metal and, for example, contain at least one of titanium and aluminum. An ohmic contact is preferably provided between the source electrode 17 and the source layer 13 and between the drain electrode 18 and the drain layer 14.

[0055] The gate electrode 19 is separated from the source electrode 17 and the drain electrode 18 and is disposed between the source electrode 17 and the drain electrode 18 in the first direction ( Figure 2 the lateral direction).

[0056] The channel structure SR is disposed between the source layer 13 and the drain layer 14 on the p-type layer 12. In the channel structure SR, the channel regions CN and the gate regions GT are alternately arranged in the second direction ( Figure 1 the longitudinal direction). The channel structure SR includes a channel layer 15 and a gate layer 16.

[0057] The channel layer 15 is composed of a nitride-based semiconductor. The channel layer 15 constitutes at least a part of the channel region CN, and in the present embodiment, it constitutes the whole of the channel region CN. Therefore, in the present embodiment, in the channel region CN, one end face and the other end face of the channel layer 15 are respectively connected to the source layer 13 and the drain layer 14. The channel layer 15 may also constitute a part of the gate region GT. The channel layer 15 is composed of an n-type or undoped single layer. When the channel layer 15 has an n-type, its impurity concentration is preferably equal to or lower than the impurity concentration of the gate layer 16. The dopant for giving an n-type is, for example, Si. The thickness of the channel layer 15 is, for example, 20 nm or more and 2 μm or less.

[0058] The gate layer 16 constitutes at least a part of the gate region GT. In the present embodiment, the gate layer 16 constitutes a part of the gate region GT. Specifically, in the gate region GT, it is disposed separately from each of the source layer 13 and the drain layer 14. In addition, the other part of the gate region GT is composed of the channel layer 15, and through this channel layer 15, the gate layer 16 ( Figure 4 ) is separated from the source layer 13 and the drain layer 14. In addition, as a modified example, in the gate region GT, one end face of the gate layer 16 may be connected to the source layer 13, and instead of or simultaneously with this, the other end face of the gate layer 16 may be connected to the drain layer 14. The gate layer 16 electrically connects the gate electrode 19 and the p-type layer 12. The gate electrode 19 is formed above the gate layer 16 in the gate region GT, and the gate layer 16 is formed above the p-type layer 12 in order to obtain this electrical connection. The gate layer 16 has a p-type and is composed of a nitride-based semiconductor, for example, composed of GaN. The thickness of the gate layer 16 is, for example, 20 nm or more and 2 μm or less. The gate electrode 19 is composed of a metal or a p-type or n-type semiconductor. As the metal, for example, Ni or Pt can be applied. As the p-type semiconductor, for example, polysilicon doped with boron can be applied. As the n-type semiconductor, for example, polysilicon doped with phosphorus can be applied.

[0059] The substrate 10 supports the p-type layer 12. The p-type layer 12 is disposed between each of the source layer 13 and the drain layer 14 and the substrate 10. The p-type layer 12 has a lower surface facing the substrate 10 and an upper surface facing the source layer 13 and the drain layer 14. The material of the substrate 10 is, for example, silicon carbide, silicon, gallium nitride, or sapphire.

[0060] The nucleation layer 11 is provided between the p-type layer 12 and the substrate 10. Specifically, on the substrate 10, the nucleation layer 11 grows epitaxially, and on the nucleation layer 11, the p-type layer 12 grows epitaxially. The nucleation layer 11 has a composition different from that of the substrate 10 and the p-type layer 12, and is, for example, composed of aluminum nitride.

[0061] When operating the transistor 100, while grounding the source electrode 17, a voltage is applied to the gate electrode 19, thereby controlling the potential of the gate layer 16. Thereby, the switching between conduction and cutoff of the channel is performed. In order for the transistor 100 to operate well in the microwave band, the size of the gate layer 16 in the gate region GT in the first direction ( Figure 2 the lateral direction in) is, for example, 0.5 μm or less.

[0062] Next, with further reference to Figures 5 to 11 , an example of the manufacturing method of the transistor 100 will be described below.

[0063] Figure 5 is a cross-sectional perspective view schematically showing the first process. Above the substrate 10, for example, by using Metal Organic Chemical Vapor Deposition (MOCVD), the nucleation layer 11, the p-type layer 12, and the channel layer 15 are epitaxially grown in this order.

[0064] Figure 6 is a cross-sectional perspective view schematically showing the second process. A mask layer 40 is formed on the channel layer 15. For example, SiO 2 is deposited by Chemical Vapor Deposition (CVD). Next, using optical lithography or the like, the mask layer 40 is patterned. Next, using the mask layer 40, the channel layer 15 is etched. The etching is performed, for example, by Inductive Coupling Plasma Reactive Ion Etching (ICP-RIE) using chlorine or the like.

[0065] Figure 7 is a cross-sectional perspective view schematically showing the third process. For example, using the MOCVD method, the source layer 13 and the drain layer 14 are epitaxially grown.

[0066] Figure 8 and Figure 9 are respectively a cross-sectional perspective view and a top view schematically showing the third process. A mask layer 41 is formed on the upper surface formed by the source layer 13, the drain layer 14, and the channel layer 15. For example, SiO 2 is deposited by CVD. Next, using optical lithography or the like, the mask layer 41 is patterned. Next, using the mask layer 41, the channel layer 15 is etched.

[0067] Figure 10 and Figure 11They are a top view and a cross-sectional perspective view schematically showing the fourth process. For example, using the MOCVD method, the gate layer 16 is epitaxially grown.

[0068] Refer to again Figure 1 , for example, using the MOCVD method, the source electrode 17, the drain electrode 18, and the gate electrode are formed. Thus, the transistor 100 is obtained.

[0069] In addition, as a modification, an n-type source layer 13 and a drain layer 14 can also be formed by ion implantation into a semiconductor layer such as the channel layer 15 ( Figure 5 refer to). Regarding the dopant added by ion implantation, for example, Si is implanted. After the ion implantation, a heat treatment for activating the dopant is performed.

[0070] According to the present embodiment, the channel regions CN and the gate regions GT are alternately arranged in the second direction ( Figure 2 the longitudinal direction therein), so that an electric field corresponding to the gate potential can be applied to the channel layer 15 in the channel region CN from both the one side and the other side in the second direction. Further, on the p-type layer 12 ( Figure 4 ) electrically connected to the gate electrode 19 ( Figure 4 ) via the gate layer 16 ( Figure 3 and Figure 4 ), the channel layer 15 ( Figure 3 ) is arranged, so that an electric field corresponding to the gate potential can also be applied to the channel layer 15 in the channel region CN ( Figure 2 ) from the thickness direction. Based on the above, an electric field corresponding to the gate potential is applied to the channel layer 15 in the channel region CN from three directions. In other words, the channel control for switching the conduction and cutoff of the channel by applying the gate potential is performed by applying the electric field from three directions. Therefore, the gate controllability (the channel controllability based on the application of the gate potential) is improved, and thus the intrusion of the power lines from the drain is suppressed. Therefore, the short-channel effect can be suppressed.

[0071] In addition, in the second direction ( Figure 2 the longitudinal direction therein), the channel regions CN and the gate regions GT are alternately arranged as described above, so that the width of each channel region CN ( Figure 2 the dimension in the longitudinal direction therein), that is, each channel width, is smaller than the width of the source layer 13 ( Figure 2 the dimension in the longitudinal direction therein). Thus, the depletion of the carriers contributing to conduction can be suppressed.

[0072] The channel layer 15 ( Figure 3 ) is formed of a single layer, so that the manufacturing method of the transistor 100 can be simplified compared with the case where the channel layer 15 is formed of multiple layers. In addition, in the channel region CN, the entire single layer can be used as the channel.

[0073] The channel layer 15 preferably has an impurity concentration (doping concentration) equal to or lower than that of the gate layer 16. In other words, the impurity concentration of the gate layer 16 is preferably equal to or higher than that of the channel layer 15. Thereby, the gate controllability can be further improved.

[0074] When the nucleation layer 11 is provided between the p-type layer 12 and the substrate 10, the lattice mismatch between the substrate 10 and the p-type layer 12 can be alleviated.

[0075] <Modification Example of Embodiment 1>

[0076] Figure 12 and Figure 13 are a cross-sectional perspective view and a top view schematically showing the structure of the transistor 100V (semiconductor device) in the modification example of the present Embodiment 1, respectively. Figure 14 and Figure 15 are cross-sectional views taken along Figure 13 lines XIV-XIV and XV-XV, respectively.

[0077] Instead of each of the source layer 13 and the drain layer 14 included in the transistor 100 ( Figures 1 to 4 ), the transistor 100V includes a source layer 13V and a drain layer 14V. The source layer 13V and the drain layer 14V are made of a nitride semiconductor. The source layer 13V has a first source film 20 and a second source film 21 provided above the first source film 20 and having a wider bandgap than the first source film 20. The drain layer 14V has a first drain film 22 and a second drain film 23 provided above the first drain film 22 and having a wider bandgap than the first drain film 22. For example, the first source film 20 and the first drain film 22 are GaN, and the second source film 21 and the second drain film 23 are AlGaN. The first source film 20 and the first drain film 22 may be undoped. The second source film 21 and the second drain film 23 may be undoped or may be doped to be n-type.

[0078] According to this modification example, in the source layer 13V, a two-dimensional electron gas (2DEG) caused by polarization is formed between the first source film 20 and the second source film 21. Similarly, 2DEG is formed in the drain layer 14V. Through these 2DEGs, semiconductor regions having electrons as carriers are provided in the source layer 13V and the drain layer 14V. As a result, the mobility between the gate electrode 19 and each of the source electrode 17 and the drain electrode 18 can be improved.

[0079] In addition, by concentrating conduction within the enclosed range of the 2DEG, the parasitic capacitance is reduced. As a result, the operating characteristics of the transistor at 100 V in the microwave band can be made better.

[0080] <Embodiment 2>

[0081] Figure 16 and Figure 17 are a cross-sectional perspective view and a top view schematically showing the structure of the transistor 200 (semiconductor device) in this Embodiment 2, respectively. Figure 18 is a cross-sectional view along Figure 17 the line XVIII-XVIII.

[0082] Instead of the channel layer 15 that the transistor 100 ( Figures 1 to 4 ) has, the transistor 200 has a channel layer 15V. The channel layer 15V is composed of a nitride-based semiconductor. The channel layer 15V is a heterojunction layer composed of a first channel film 24 and a second channel film 25 provided above the first channel film 24 and having a wider bandgap than the first channel film 24. For example, the first channel film 24 is GaN, and the second channel film 25 is AlGaN.

[0083] The second channel film 25 may also have an n-type. The dopant for giving the n-type is, for example, Si.

[0084] In addition, regarding the structure other than the above, it is substantially the same as the structure of the above Embodiment 1, so the same or corresponding elements are given the same reference numerals, and the description thereof is not repeated.

[0085] According to this Embodiment, in the channel layer 15V, a 2DEG caused by polarization is formed between the first channel film 24 and the second channel film 25. As a result, the channel mobility can be improved compared to the channel layer 15 (Embodiment 1). Thus, the operating characteristics of the transistor 200 in the microwave band can be made better.

[0086] When the second channel film 25 has an n-type, the concentration of the 2DEG can be increased. As a result, an improvement in the current driving ability of the transistor 200 can be expected.

[0087] <Embodiment 3>

[0088] Figure 19 and Figure 20 are a cross-sectional perspective view and a top view schematically showing the structure of the transistor 300 (semiconductor device) in this Embodiment 3, respectively. Figure 21 is a cross-sectional view along Figure 20 the line XXI-XXI.

[0089] Instead of the transistor 100 ( Figures 1 to 4) Having a gate layer 16, the transistor 200 has a gate layer 26. The gate layer 26 has a p-type. The gate layer 26 has a polycrystalline structure. The gate layer 26 can be made of a metal compound, and in particular, can be made of a metal oxide. As the material of the gate layer 26, for example, nickel oxide, copper oxide, or molybdenum oxide is preferably used. In addition, as the material of the gate layer 26, p-type polysilicon doped with boron, p-type polycrystalline silicon carbide doped with aluminum, or p-type polycrystalline gallium nitride doped with magnesium can also be applied. The gate layer 26 is formed, for example, by a sputtering method or a CVD method.

[0090] In addition, regarding the structures other than the above, they are substantially the same as those of the above-described Embodiment 1 or 2. Therefore, the same reference numerals are assigned to the same or corresponding elements, and the description thereof will not be repeated.

[0091] According to this embodiment, the gate layer 26 has a polycrystalline structure. Thus, there is no need for an advanced film-forming technique for growing single crystals. Therefore, the manufacturing method of the transistor 300 can be simplified.

[0092] <Embodiment 4>

[0093] Figure 22 It is a cross-sectional perspective view schematically showing the structure of the transistor 400 (semiconductor device) in this Embodiment 4. Figure 23 is Figure 22 the top view of. Figure 24 is along Figure 23 the cross-sectional view taken along line XXIV-XXIV of.

[0094] Instead of the channel layer 15 ([[]] Figures 1 to 4 ) that the transistor 100 has, the transistor 400 has a channel layer 15W. The channel layer 15W is composed of a nitride-based semiconductor. The channel layer 15W has first channel films 27a to 27d (hereinafter, collectively referred to as the first channel film 27) and second channel films 28a to 28d (hereinafter, collectively referred to as the second channel film 28). The first channel film 27 and the second channel film 28 are alternately stacked on the p-type layer 12.

[0095] The channel layer 15W includes a plurality of heterojunction layers 15a to 15d. The plurality of heterojunction layers 15a to 15d are composed of the above-mentioned plurality of first channel films 27 and plurality of second channel films 28 and are stacked on each other. The heterojunction layers 15a to 15d are stacked on the p-type layer 12 in this order.

[0096] Each of the multiple heterojunction layers 15a to 15d is composed of a first channel film 27 and a second channel film 28 provided above the first channel film 27 and having a wider bandgap than the first channel film 27. For example, the first channel film 27 is made of GaN, and the second channel film 28 is made of AlGaN. The second channel film 28 may also be n-type. A dopant for imparting n-type is, for example, Si.

[0097] Specifically, the heterojunction layer 15a is composed of a first channel film 27a and a second channel film 28a provided above the first channel film 27a and having a wider bandgap than the first channel film 27a. Similarly, the heterojunction layer 15b is composed of a first channel film 27b and a second channel film 28b provided above the first channel film 27b and having a wider bandgap than the first channel film 27b. Similarly, the heterojunction layer 15c is composed of a first channel film 27c and a second channel film 28c provided above the first channel film 27c and having a wider bandgap than the first channel film 27c. Similarly, the heterojunction layer 15d is composed of a first channel film 27d and a second channel film 28d provided above the first channel film 27d and having a wider bandgap than the first channel film 27d.

[0098] Since the heterojunction layers 15a to 15d are multiple heterojunction layers, they include a first heterojunction layer and a second heterojunction layer. Here, the first heterojunction layer is defined as being disposed between the second heterojunction layer and the p-type layer 12.

[0099] The average Al composition of the second heterojunction layer in the thickness direction is preferably lower or higher than the average Al composition of the first heterojunction layer in the thickness direction. Thereby, a gradient is set for the 2DEG concentration between the first heterojunction layer and the second heterojunction layer.

[0100] In addition, the heterojunction layers 15a to 15d may also have a composition in which the average Al composition in the thickness direction decreases or increases in this order. Thereby, a gradient is set for the 2DEG concentration in the entire channel layer 15W. For example, the channel layer 15W has GaN / Al 0.4 Ga 0.6 N / GaN / Al 0.35 Ga 0.65 N / GaN / Al 0.3 Ga 0.7 N / GaN / Al 0.25 Ga 0.75 N's stacked structure above the p-type layer 12. The composition of each of the above layers is the average value of each layer in the thickness direction. In this stacked structure, the average Al composition in the thickness direction gradually decreases from 0.4 to 0.25 as it is farther away from the p-type layer 12.

[0101] The average doping concentration of the second heterojunction layer in the thickness direction is preferably lower or higher than the average doping concentration of the first heterojunction layer in the thickness direction. Thus, a gradient is set for the 2DEG concentration between the first heterojunction layer and the second heterojunction layer.

[0102] In addition, the heterojunction layers 15a to 15d may also have doping concentrations that decrease or increase in this order in the thickness direction. Thus, a gradient is set for the 2DEG concentration throughout the channel layer 15W.

[0103] In addition, regarding the structures other than the above, they are substantially the same as the structures of the above-described Embodiments 1 to 3. Therefore, the same or corresponding elements are denoted by the same reference numerals, and the description thereof is not repeated.

[0104] According to this embodiment, a plurality of 2DEG layers are formed in the channel layer 15W instead of a single one. Thus, compared with the case where only a single 2DEG layer is formed, the channel mobility can be further improved. As a result, the operating characteristics of the transistor 400 in the microwave band can be made better. In addition, the current driving ability can be improved.

[0105] When the 2DEG concentration has a gradient that decreases from the p-type layer 12 toward the surface side ( Figure 24 the upper side in

[0106] ), a relatively high-concentration 2DEG is disposed near the p-type layer 12. Therefore, due to the electric field from the p-type layer 12, the channel generated by the high-concentration 2DEG can be more fully controlled. Thus, high driving ability can be achieved without degrading the gate controllability in the transistor 400. Figure 24 When the 2DEG concentration has a gradient that increases from the p-type layer 12 toward the surface side ( Figure 24 the upper side in

[0107] ), a relatively low-concentration 2DEG is disposed near the p-type layer 12. Therefore, the lines of electric force from the p-type layer 12 are more easily reachable toward the surface side (

[0108] Figure 25 and Figure 26 are a cross-sectional perspective view and a top view schematically showing the structure of the transistor 500 (semiconductor device) in this Embodiment 5, respectively. Figure 27 and Figure 28 are cross-sectional views taken along the Figure 26 lines XXVII-XXVII and XXVIII-XXVIII, respectively.

[0109] Except for the transistor 100 ( Figures 1 to 4) structure, the transistor 500 further has a p-type layer 29 (second p-type layer) made of a nitride-based semiconductor. The p-type layer 29 is, for example, GaN or AlGaN, and a p-type dopant such as Mg is used to dope the p-type layer 29. The p-type layer 29 is provided above the channel region CN and the gate region GT. Therefore, the channel layer 15 in the channel region CN is covered by the p-type layer 29. Above the gate region GT, a gate electrode 19 is disposed on the p-type layer 29, whereby the p-type layer 29 is electrically connected to the gate electrode 19.

[0110] In addition, regarding the structure other than the above, it is substantially the same as the structure of the above-described Embodiments 1 to 4. Therefore, the same or corresponding elements are denoted by the same reference numerals, and the description thereof will not be repeated.

[0111] According to the present embodiment, the p-type layer 29 electrically connected to the gate electrode 19 is provided above the channel region CN. Thus, an electric field corresponding to the gate potential is applied to the channel layer 15 in the channel region CN from four directions. In other words, the channel control for switching the conduction and cutoff of the channel by applying the gate potential is performed by applying an electric field from four directions. Therefore, the gate controllability is further improved, and thus the intrusion of the power lines from the drain is further suppressed. Therefore, the short-channel effect can be further suppressed.

[0112] <Embodiment 6>

[0113] Figure 29 and Figure 30 are a cross-sectional perspective view and a top view schematically showing the structure of the transistor 600 (semiconductor device) in the present Embodiment 6, respectively. Figure 31 and Figure 32 are cross-sectional views taken along the Figure 30 lines XXXI-XXXI and XXXII-XXXII, respectively.

[0114] Except for the structure of the transistor 100 ( Figures 1 to 4 ), the transistor 600 further has an interlayer film 30. The interlayer film 30 is provided between each of the source layer 13 and the drain layer 14 and the p-type layer 12. The interlayer film 30 is made of a nitride-based semiconductor having a wider bandgap than the p-type layer 12, and is, for example, made of AlGaN. The thickness of the interlayer film 30 is, for example, 15 nm or more and 100 nm or less.

[0115] In addition, regarding the structure other than the above, it is substantially the same as the structure of the above-described Embodiments 1 to 5. Therefore, the same or corresponding elements are denoted by the same reference numerals, and the description thereof will not be repeated.

[0116] According to the present embodiment, an effect of cutting off the reverse bias current of the pn junction between the source and the gate and between the gate and the drain when a negative voltage is applied to the gate electrode 19 can be expected. In other words, an effect of suppressing the reverse leakage current of the pn junction can be expected.

[0117] In addition, each embodiment can be freely combined, or each embodiment can be appropriately modified or omitted. Although the present disclosure has been described in detail, the above description is illustrative in all forms and is not limited thereto. It should be understood that countless modification examples not illustrated can be conceived from the present disclosure.

Claims

1. A semiconductor device that operates in the microwave band and has a first direction and a second direction orthogonal to each other in a plane direction perpendicular to the thickness direction, the semiconductor device comprising: A first p-type layer made of a nitride semiconductor; A source layer provided above the first p-type layer and including a semiconductor region having electrons as carriers; A source electrode provided above the source layer; A drain layer provided above the first p-type layer at an interval from the source layer and facing each other in the first direction, and including a semiconductor region having electrons as carriers; A drain electrode provided above the drain layer; A gate electrode separated from the source electrode and the drain electrode and provided between the source electrode and the drain electrode in the first direction; And A channel structure provided between the source layer and the drain layer above the first p-type layer, and having a channel region and a gate region alternately arranged in the second direction, The channel structure includes: A channel layer constituting at least a part of the channel region and made of a nitride semiconductor; and A gate layer constituting at least a part of the gate region and electrically connecting the gate electrode and the first p-type layer.

2. The semiconductor device according to claim 1, Characterized in that The gate layer is made of a p-type nitride semiconductor.

3. The semiconductor device according to claim 1, Characterized in that The gate layer has a polycrystalline structure.

4. The semiconductor device according to claim 2, Characterized in that The gate layer has a polycrystalline structure.

5. The semiconductor device according to any one of claims 1 to 4, Characterized in that The channel layer is composed of an n-type or undoped single layer.

6. The semiconductor device according to any one of claims 1 to 4, Characterized in that The channel layer is a heterojunction layer composed of a first channel film and a second channel film provided above the first channel film and having a wider bandgap than the first channel film.

7. The semiconductor device according to any one of claims 1 to 4, Characterized in that The channel layer includes a plurality of heterojunction layers stacked on each other, and each of the plurality of heterojunction layers is composed of a first channel film and a second channel film provided above the first channel film and having a wider bandgap than the first channel film.

8. The semiconductor device according to any one of claims 1 to 4, Characterized in that The source layer has a first source film and a second source film provided above the first source film and having a wider bandgap than the first source film.

9. The semiconductor device according to any one of claims 1 to 4, Characterized in that The drain layer has a first drain film and a second drain film provided above the first drain film and having a wider bandgap than the first drain film.

10. The semiconductor device according to any one of claims 1 to 4, Characterized in that A second p-type layer is further provided above the channel region, and the second p-type layer is electrically connected to the gate electrode and is made of a nitride semiconductor.

11. The semiconductor device according to any one of claims 1 to 4, Characterized in that An interlayer film is further provided between the source layer and the first p-type layer, and the interlayer film is composed of a nitride semiconductor having a wider bandgap than the first p-type layer.

12. The semiconductor device according to any one of claims 1 to 4, characterized in that an interlayer film is further provided between the drain layer and the first p-type layer, and the interlayer film is composed of a nitride semiconductor having a wider bandgap than the first p-type layer.

13. The semiconductor device according to any one of claims 1 to 4, characterized in that the channel layer has an impurity concentration equal to or lower than that of the gate layer.

14. The semiconductor device according to any one of claims 1 to 4, characterized in that the channel layer includes a plurality of heterojunction layers stacked on each other, and each of the plurality of heterojunction layers is composed of a first channel film and a second channel film provided above the first channel film and having a wider bandgap than the first channel film, the plurality of heterojunction layers include a first heterojunction layer and a second heterojunction layer, the first heterojunction layer is disposed between the second heterojunction layer and the first p-type layer, and the average Al composition of the second heterojunction layer in the thickness direction is lower than the average Al composition of the first heterojunction layer in the thickness direction.

15. The semiconductor device according to any one of claims 1 to 4, characterized in that the channel layer includes a plurality of heterojunction layers stacked on each other, and each of the plurality of heterojunction layers is composed of a first channel film and a second channel film provided above the first channel film and having a wider bandgap than the first channel film, the plurality of heterojunction layers include a first heterojunction layer and a second heterojunction layer, the first heterojunction layer is disposed between the second heterojunction layer and the first p-type layer, and the average Al composition of the second heterojunction layer in the thickness direction is higher than the average Al composition of the first heterojunction layer in the thickness direction.

16. The semiconductor device according to any one of claims 1 to 4, characterized in that the channel layer includes a heterojunction layer composed of a first channel film and a second channel film provided above the first channel film and having a wider bandgap than the first channel film, and the second channel film has an n-type.

17. The semiconductor device according to any one of claims 1 to 4, characterized in that the channel layer includes a plurality of heterojunction layers stacked on each other, and each of the plurality of heterojunction layers is composed of a first channel film and a second channel film provided above the first channel film and having a wider bandgap than the first channel film, the plurality of heterojunction layers include a first heterojunction layer and a second heterojunction layer, the first heterojunction layer is disposed between the second heterojunction layer and the first p-type layer, and the average doping concentration of the second heterojunction layer in the thickness direction is lower than the average doping concentration of the first heterojunction layer in the thickness direction.

18. The semiconductor device according to any one of claims 1 to 4, characterized in that The channel layer includes a plurality of heterojunction layers stacked on each other, and each of the plurality of heterojunction layers is composed of a first channel film and a second channel film disposed above the first channel film and having a wider bandgap than the first channel film. The plurality of heterojunction layers include a first heterojunction layer and a second heterojunction layer. The first heterojunction layer is disposed between the second heterojunction layer and the first p-type layer, and the average doping concentration of the second heterojunction layer in the thickness direction is higher than the average doping concentration of the first heterojunction layer in the thickness direction.

19. The semiconductor device according to any one of claims 1 to 4, characterized in that it further includes a substrate that supports the first p-type layer, and the first p-type layer is disposed between the source layer and the drain layer and the substrate respectively.

20. The semiconductor device according to claim 19, characterized in that a nucleation layer is further provided between the first p-type layer and the substrate.

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