In-memory computing circuitry

Abstract

The application discloses a memory computing circuit, comprising a computing component array and an analog-to-digital conversion circuit, the computing component array is used for analog computing operation, the computing component array comprises a memory unit, a first group of computing components and a second group of computing components, the first group of computing components provides capacitance for the analog computing operation in response to an input vector and receives data from a plurality of memory units and the input vector, the second group of computing components provides capacitance for quantization, each computing component of the computing component array is based on a switched capacitor circuit, the analog-to-digital conversion circuit comprises a comparator and a conversion control unit, the comparator has a signal end, a reference end and a comparison output end, wherein the first and second groups of computing components are selectively coupled to the signal end and the reference end. The memory computing circuit of the application can effectively reduce errors and can reduce or avoid inaccuracy caused by process / voltage / temperature (PVT) drift.

Description

Technical Field

[0001] This invention relates to a hardware-based deep learning acceleration technology, and more particularly to a memory computing circuit. Background Technology

[0002] Currently, in the architecture of deep learning accelerators employing memory processing technology, the operating modes of the multiply-accumulate (MAC) operation unit can be divided into current mode and charging mode. As a relevant reference, A. Biswas et al., "Conv-RAM: An Energy Efficient SRAM with Embedded ConvolutionComputation for Low-Power CNN-Based Machine Learning Applications," ISSCC, pp. 488-489, 2018, mention the threshold voltage (V) of the transistor. TH The accuracy of the operation is easily affected by process / voltage / temperature (PVT) drift, which reduces its effectiveness. Furthermore, the results of analog calculations must be converted back to digital signals by an analog-to-digital converter (ADC) before subsequent digital signal processing can be performed in the digital domain. Inconsistencies in the type and generation method of the ADC and the multiplication-accumulation unit will further reduce the accuracy of the calculations.

[0003] Since the input to the multiply-accumulate unit is a finite-bit digital signal, i.e., a quantized signal, the quantizer only needs to quantize a finite quantization level (analog) after the multiply-accumulate unit. The challenge here is that the analog level can be considered a DC level. In typical analog circuits, issues such as DC error and drift are critical to conversion accuracy. This differs from typical communication systems, where signals are mostly transmitted in AC form, and most performance metrics of analog-to-digital converters are defined based on AC response. Summary of the Invention

[0004] The purpose of this invention is to provide an analog multiply-accumulate unit suitable for capacitor mode, which is a combination of a multiply-accumulate unit and a quantizer, and can effectively reduce errors.

[0005] To achieve the above and other objectives, the present invention provides a memory computing circuit, comprising: a computing component array and an analog-to-digital conversion circuit. The computing component array is used for simulating computational operations. The computing component array includes multiple memory cells, a first group of computing components, and a second group of computing components. The first group of computing components provides capacitance for analog computation in response to an input vector, wherein the first group of computing components receives data from the multiple memory cells and the input vector. The second group of computing components provides capacitance for quantization, wherein each computing component in the computing component array is based on a switched capacitor circuit. The analog-to-digital conversion circuit includes a comparator and a conversion control unit. The comparator has a signal terminal, a reference terminal, and a comparison output terminal, wherein the computing components of the first group of computing components are selectively coupled to the signal terminal and the reference terminal according to the input vector. The conversion control unit is coupled to the comparison output terminal and controls a first number of computing components in the second group of computing components to be coupled to the signal terminal and the reference terminal according to the output of the comparison output terminal.

[0006] Optionally, the conversion control unit also controls a second number of computing components to be coupled from the second group of computing components to the signal terminal based on the output of the comparison output terminal.

[0007] Optionally, the conversion control unit determines the final N-bit digital code based on the continuous outputs of the comparison output terminal, where N is an integer greater than 1, and the conversion control unit determines the updated version of the first quantity or the second quantity based on the previous outputs of the continuous outputs of the comparison output terminal.

[0008] Optionally, the computing components of the first set of computing components selectively couple the charging capacitor to the signal terminal and selectively couple the discharging capacitor to the reference terminal based on the data received from multiple memory units and the input vector.

[0009] Optionally, the computing components of the second set of computing components selectively couple the charging capacitor to the reference terminal and the discharging capacitor to the signal terminal according to at least one reference control signal from the conversion control unit.

[0010] Optionally, the conversion control unit determines at least one reference control signal based on the output of the comparison output terminal.

[0011] Optionally, when the signal at the reference terminal is less than the signal at the signal terminal, the conversion control unit generates at least one reference control signal to control the computing components of the second set of computing components to selectively couple the charging capacitor to the reference terminal and the discharging capacitor to the signal terminal.

[0012] Optionally, the computing components of the second set of computing components may further selectively couple an additional charging capacitor to a signal terminal and an additional discharging capacitor to a reference terminal based on at least one reference control signal.

[0013] Optionally, the conversion control unit determines at least one reference control signal based on the output of the comparison output terminal.

[0014] Optionally, when the signal at the reference terminal is greater than the signal at the signal terminal, the conversion control unit generates at least one reference control signal to control the computing components of the second set of computing components to selectively couple the charging capacitor to the reference terminal, couple the discharging capacitor to the signal terminal, couple the additional charging capacitor to the signal terminal, and couple the additional discharging capacitor to the reference terminal.

[0015] Alternatively, the simulation operation is a multiplication-accumulation (MAC) operation.

[0016] Alternatively, the memory computing circuitry can be housed in a single chip.

[0017] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the invention. However, these descriptions and drawings are only for illustrating the present invention and are not intended to limit the scope of the invention in any way. Attached Figure Description

[0018] Figure 1 This is an architectural diagram of the memory computing circuit according to an embodiment of the present invention;

[0019] Figure 2 for Figure 1 A schematic diagram of the computing element array;

[0020] Figure 3A According to Figure 1 A block diagram of the first set of computing components in the architecture;

[0021] Figure 3B According to Figure 1 A block diagram of the second set of computing components in the architecture;

[0022] Figure 4A This is a schematic diagram of a switched capacitor circuit that can be used to construct a computing component according to an embodiment of the present invention.

[0023] Figure 4B This is a schematic diagram of the first set of calculation components based on the switched capacitor circuit according to an embodiment of the present invention;

[0024] Figure 4C This is a schematic diagram of the second set of calculation components based on the switched capacitor circuit according to an embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of the conversion control unit according to an embodiment of the present invention;

[0026] Figure 6 Operation of embodiments of the present invention Figure 1A flowchart of the method for analog-to-digital conversion circuits;

[0027] Figure 7 for Figure 6 Flowchart of step S40;

[0028] Figure 8 This is a schematic diagram illustrating how the conversion control unit controls the signal path that couples multiple computing elements from the first group of computing elements and the second group of computing elements to the signal terminal and the signal path to the reference terminal, according to an embodiment of the present invention.

[0029] Figure 9 This is a schematic diagram of the conversion control unit controlling the signal path from multiple computing elements from the first group of computing elements and the second group of computing elements to the signal terminal and the signal path to the reference terminal, according to an embodiment of the invention.

[0030] Figure 10 This is a schematic diagram illustrating how the conversion control unit controls the signal path that couples multiple computing elements from the first group of computing elements and the second group of computing elements to the signal terminal and the signal path to the reference terminal, according to an embodiment of the present invention.

[0031] Figure 11 This is a schematic diagram illustrating how the conversion control unit controls the signal path that couples multiple computing elements from the first group of computing elements and the second group of computing elements to the signal terminal and the signal path to the reference terminal, according to an embodiment of the present invention.

[0032] Figure 12 This is a schematic diagram of the conversion control unit controlling the signal path from the first group of computing elements and the second group of computing elements to the signal terminal and the signal path to the reference terminal, according to an embodiment of the present invention.

[0033] Figure label:

[0034] 1. Memory computing circuit

[0035] 10 Computing Element Array

[0036] 100 switched capacitor circuit

[0037] 11 First set of computing components

[0038] 110A buffer

[0039] 110B buffer

[0040] 111A switch

[0041] 111B switch

[0042] 113A capacitor

[0043] 113B capacitor

[0044] 115A Selector

[0045] 115B Selector

[0046] 11A First Set of Computing Components

[0047] 12 Second group of computing components

[0048] 12A Second Set of Computing Components

[0049] 20 Analog-to-Digital Converter Circuit

[0050] 21 comparator

[0051] 22 Conversion Control Unit

[0052] 220 controller

[0053] 222 register

[0054] 22A Conversion Control Unit

[0055] BL1 signal path

[0056] BL2 signal path

[0057] I1 Input Value

[0058] I5 Input Value

[0059] I N Input value

[0060] Results of OUT simulation calculation

[0061] Step S10

[0062] S20 Step

[0063] S30 Steps

[0064] Step S35

[0065] S40 Steps

[0066] Step S41

[0067] Step S43

[0068] Step S45

[0069] Step S47

[0070] S50 Steps

[0071] S A Received signal

[0072] S B Received signal

[0073] S CA control signals

[0074] S CB control signals

[0075] S CR Compare output signal

[0076] S CT1 Reference control signal

[0077] S CTB1 Inverted corresponding reference control signal

[0078] S CTBK Inverted corresponding reference control signal

[0079] S CTK Reference control signal

[0080] S CTM Reference control signal

[0081] S TA control signals

[0082] S TB control signals

[0083] VDD power supply voltage

[0084] Vref reference signal

[0085] Vsig input signal

[0086] W1 weight value

[0087] W3 weight value

[0088] W4 weight value

[0089] W5 weighting

[0090] W N weight value Detailed Implementation

[0091] To fully understand the present invention, the following specific embodiments, in conjunction with the accompanying drawings, will provide a detailed description. Those skilled in the art can understand the purpose, features, and effects of the present invention from the content disclosed in this specification. It should be noted that the present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention. Furthermore, the accompanying drawings are for simple illustrative purposes only and are not depictions based on actual dimensions. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the claims of the present invention. The following explanation is provided:

[0092] Reference Figure 1The diagram illustrates the architecture of a memory computing circuit 1, representing various embodiments of the present invention. The memory computing circuit 1 includes a computing element array 10 and an analog-to-digital converter circuit 20. For example, the memory computing circuit 1 is housed in a single chip.

[0093] The computing element array 10 is used to simulate computing operations.

[0094] Reference Figure 1 , Figure 2 , Figure 3A and Figure 3B The computing component array 10 includes multiple memory cells (MCs), a first group of computing components 11 (or the first CE group) and a second group of computing components 12 (or the second CE group).

[0095] like Figure 3A and Figure 3B As shown, each group of first computing components 11 and second computing components 12 includes a corresponding number of computing elements (CE).

[0096] The first set of computational components 11 responds to the input vector (such as...) Figure 1 The “IN” in the text refers to the capacitors provided for analog computation. The first set of computational components 11 receives data from multiple storage units and input vectors. For example, the input vectors can be scalars, arrays, matrices, or multidimensional vectors in digital form, and the first set of computational components 11 can be configured accordingly to the corresponding arrangement of the computational components (CE) for analog computation (e.g., as shown in the image). Figure 2 (The array configuration shown).

[0097] The second set of computing components 12 provides capacitors for quantization, wherein each computing component in the computing component array 10 is based on a switched capacitor circuit.

[0098] The analog-to-digital converter circuit 20 includes a comparator 21 and a conversion control unit 22. The comparator 21 has a signal terminal (e.g., a positive or non-inverting terminal) for receiving an input signal Vsig (e.g., via signal path BL1) for comparison, a reference terminal (e.g., a negative or inverting terminal) for receiving a reference signal Vref (e.g., via signal path BL2), and a comparison output signal S. CR The comparison output terminal. The first set of calculation components 11 is selectively coupled to the signal terminal and the reference terminal according to the input vector. The conversion control unit 22 is coupled to the comparison output terminal and controls the first number of calculation components from the second set of calculation components 12 to be coupled to the signal terminal and the reference terminal according to the output of the comparison output terminal.

[0099] The architecture of the memory computing circuit 1 is based on a circuit combination of computing element array 10 and analog-to-digital converter circuit 20, and operates in charging mode. Therefore, the input signal Vsig used for comparison and the reference signal Vref applied to comparator 21 are obtained through capacitors (selectively charged or discharged) provided by the first set of computing elements 11 and the second set of computing elements 12, respectively. Because each computing element (CE) of the computing element array 10 is based on a switched capacitor circuit, the first set of computing elements 11 and the second set of computing elements 12 can be fabricated with similar types of circuitry on a single chip using the same manufacturing process. Therefore, the architecture of the memory computing circuit 1 helps to effectively reduce relative errors and inaccuracies caused by process / voltage / temperature (PVT) variations in the computing element array 10.

[0100] The following provides an embodiment of the computing element array 10 and the analog-to-digital conversion circuit 20, and their operation in charging mode.

[0101] Reference Figure 3A ,according to Figure 1 The structure illustrates one embodiment of the first set of computational components. For example, the input vector includes multiple input values ​​in digital form (e.g., I1, ..., I...). N (bit value)). Reference Figure 3A Multiple input values ​​(e.g., bit values ​​I1, ..., I2) stored in multiple memory cells (MCs) (e.g., static random access memory (SRAM) cells). N (N>1) and corresponding multiple weight values ​​(e.g., W1, ..., W...). N (Bit values) are respectively applied to the computing components (CE) of the first group of computing components 11. (Refer to...) Figure 3A In an embodiment of the first set of computing components 11, each computing component (CE) provides a corresponding capacitor (charging or discharging) representing the product of the corresponding input value and weight value. For example, the output of the computing component (CE) can be summed to generate a sum of the product of the input value and weight value in voltage or current format, where the sum can be expressed by a formula:

[0102] (Equation 1)

[0103] In some embodiments, the input vector may include multi-bit values; the input vector may be a two-dimensional vector or a multi-dimensional vector; and the first set of computing components 11 can therefore be based on Figure 3A Or, through appropriate modifications, to achieve this.

[0104] Reference Figure 3B ,according to Figure 1 The structure illustrates one embodiment of the second set of computing components. For example... Figure 3BAs shown, the second set of computing components 12 includes multiple computing components (CEs). Each computing component (CE) provides a corresponding capacitor (charging or discharging) for quantization, and according to at least one reference control signal (e.g., S... CT1 ... or S CTM It is selectively controlled.

[0105] As described above, each computing component in the computing component array 10 is based on a switched capacitor circuit. (Refer to...) Figure 4A An embodiment of a switched capacitor circuit is shown, according to which a computing component can be constructed. (Reference) Figure 4A The switched capacitor circuit 100 includes buffers 110A-110B, switches 111A-111B, capacitors 113A-113B, and selectors 115A-115B. Buffer 110A (or 110B) receives signal S. A (or S) B Switch 111A (or 111B) operates according to control signal S. TA (or S) TB The capacitor 113A (or 113B) is controlled. The capacitor 113A (or 113B) is coupled to the output of the switch 111A (or 111B). The selector 115A (or 115B) is coupled to the capacitor 113A (or 113B) and controls the output according to the control signal S. CA (or S) CB It is controlled to produce an output to one of its two ends.

[0106] Capacitor 113A (or 113B) can be adjusted according to signal S A (or S) B Charging or discharging. When signal S A (or S) B The indicator logic is high and the control signal S TA (or S) TB When indicator switch 111A (or 111B) is turned on, capacitor 113A (or 113B) will be charged to a logic high level. When signal S... A (or S) B The indicator logic is low and the control signal S TA (or S) TB When the indicator switch 111A (or 111B) is turned on, capacitor 113A (or 113B) will discharge to a logic high level.

[0107] After capacitor 113A (or 113B) is fully charged or discharged, the control signal S... TA (or S) TB This can be set to indicate that switch 111A (or 111B) is closed. Afterwards, control signal S can be set. CA (or S) CBThis is used to instruct one of the terminals of selector 115A (or 115B) to provide charging or discharging capacitance to one of the terminals of selector 115A (or 115B). In one example, the control signal S CA (or S) CB The selector 115A (or 115B) can be configured to turn off and not provide charging or discharging capacitors. For example, selector 115A or 115B can be implemented using two switches with one or two control signals.

[0108] For the sake of brevity, the following embodiments will not describe in detail the use of control signal S. TA (or S) TB The process of charging or discharging a capacitor can be shown in a simplified form as a diagram of a switched capacitor circuit.

[0109] Reference Figure 4B An embodiment of the first set of computing components is shown based on a switched capacitor circuit. (Refer to...) Figure 4B The first set of computing components 11A is based on Figure 4A Example of a switched capacitor circuit 100 Figure 3A An example of the first set of computing components. Please refer to... Figure 4B Each operational element is implemented using the switched capacitor circuit 100, where signal S A Weight values ​​(e.g., W1, ... or W) N ), signal S B For ground signal (GND), control signal S CA and S CB It is an input value (e.g., I1, ... or I). N ).exist Figure 4B In the diagram, the selector 115A (or 115B) of the switched capacitor circuit 100 is shown as having a switch, wherein the switch may be the result of implementing the selector as two switches, wherein one of the switches is made open.

[0110] For example, in Figure 4B In the calculation component shown, when the weight values ​​(e.g., W1, ... or W...) N When the input value (e.g., I1, ... or I...) is high, the corresponding capacitor is charged, while another capacitor is discharged. N When the indicator switch is open, the charging capacitor is then provided to the signal path of the input signal Vsig, while the discharging capacitor is provided to the signal path of the reference signal Vref. In another example, a weight value (e.g., W1) could indicate a logic low level, and the operation would be similar except that the corresponding capacitor would be discharged.

[0111] Reference Figure 4CAn embodiment of the second set of computing components is shown based on a switched capacitor circuit. (Refer to...) Figure 4C The second set of computing components 12A is based on Figure 4A Example of a switched capacitor circuit 100 Figure 3B Examples of the second set of computing components. See also... Figure 4C Each computing component is implemented based on a switched capacitor circuit 100, wherein signal S A For a logic high-level signal (e.g., power supply voltage VDD), signal S B For ground signal (GND), control signal S CA and S CB Considered as a reference control signal (e.g., S) CT1 ... or S CTK ) and the inverted phase of the corresponding reference control signal (e.g., S) CTB1 ... or S CTBK ).exist Figure 4C In the diagram, the selector 115A (or 115B) of the switched capacitor circuit 100 is shown as having two switches, both of which can be controlled to be either open or one on while the other is open.

[0112] For example, in Figure 4C In the computational component shown, one capacitor is charged while another is discharged. When a reference control signal (e.g., S) is applied... CT1 ... or S CTK When one of the switches (corresponding to the selector) is opened for the signal path of the input signal Vsig, the charging capacitor is then supplied to the signal path of the input signal Vsig, while the discharging capacitor is supplied to the signal path of the reference signal Vref. Conversely, when the reference control signal (e.g., S...) is open... CT1 ... or S CTK When one of the switches (corresponding to the selector) is turned on for the signal path of the reference signal Vref, the charging capacitor is then supplied to the signal path of the reference signal Vref, while the discharging capacitor is supplied to the signal path of the input signal Vsig.

[0113] Reference Figure 5 An embodiment of the conversion control unit is shown. For example... Figure 5 As shown, the conversion control unit 22A includes a controller 220 and a register 222. The controller 220 can be a control logic circuit, a microcontroller-based circuit, or a dedicated hardware circuit to control the analog-to-digital conversion (or quantization) process. The controller 220 responds to the compare output signal S. CR This generates multiple reference control signals (e.g., S). CT1 ... S CTMRegister 222 is used to store data used for conversion, such as approximate digital code and final digital code, which are the results of analog calculations in digital form of in-memory computation (represented by "OUT").

[0114] Reference Figure 6 An operation according to an embodiment is shown. Figure 1 This method uses an analog-to-digital converter circuit. It is a variant of the successive approximation register analog-to-digital converter (SAR-ADC). For illustrative purposes, Figure 1 The analog-to-digital conversion circuit (e.g., 20) in the diagram will be mentioned, but the method is not limited thereto.

[0115] In step S10, initial settings are performed in the analog-to-digital conversion circuit (e.g., 20). For example, an initial version of at least one reference control signal is set. For example, for an N-bit analog-to-digital conversion, the initial version of at least one reference control signal is set to the most significant bit, i.e., the (N-1)th bit, for the first clock phase of the analog-to-digital conversion, which, as with SAR-ADC, requires at least N clock phases (or stages) to complete the analog-to-digital conversion.

[0116] In step S20, the conversion control unit 22 obtains the comparison result of the comparator 21 (e.g., S...). CR ).

[0117] In step S30, the conversion control unit 22 (e.g., controller 220) determines the bits based on the comparison result and the digital code is updated.

[0118] In step S35, the conversion control unit 22 (e.g., controller 220) determines whether to repeat the process for the next bit. If yes, step S40 is executed; otherwise, step S50 is executed. For example, if the conversion of the (N-1)th bit is completed in step S30, the conversion process is repeated for the next bit, i.e., the (N-2)th bit, until the conversion process of the 0th bit is completed.

[0119] In step S40, the conversion control unit 22 (e.g., controller 220) determines an updated version of at least one reference control signal.

[0120] In step S50, the conversion control unit 22 (e.g., controller 220) outputs a digital code as the final digital code, which is the result of the analog calculation of the memory calculation in digital form (represented by "OUT").

[0121] Reference Figure 7 , Figure 6 Step S40 is shown as an example in the form of a flowchart.

[0122] In step S41, the conversion control unit 22 (e.g., controller 220) determines whether the bit determined in step S30 is "1" or "0". If the bit is "1", the method proceeds to step S43. If the bit is "0", the method proceeds to step S45.

[0123] In step S43, the conversion control unit 22 (e.g., controller 220) determines an updated version of at least one reference control signal such that, in addition to the coupling method of the computing components used in the previous phase, at least one additional computing component is coupled to the reference end in this phase.

[0124] In step S45, the conversion control unit 22 (e.g., controller 220) determines an updated version of at least one reference control signal such that, in addition to the coupling method of the computing components used in the previous phase, at least one additional computing component is coupled to the input in this phase.

[0125] In step S47, the conversion control unit 22 (e.g., controller 220) applies an updated version of at least one reference control signal to the second set of computing components.

[0126] In the above embodiments, steps S41-S47 can provide the technical advantage of not requiring capacitor reset, as will be explained later. The conversion control unit (e.g., 22 or 22A) can, according to... Figure 7 The embodiments are designed to reduce the need for capacitor reset during analog-to-digital conversion. Therefore, the following embodiments are provided.

[0127] In some embodiments, the conversion control unit 22 further controls a second number of computing components to be coupled from the second group of computing components 12 to the signal terminal based on the output of the comparison output terminal.

[0128] In some embodiments, the conversion control unit 22 determines the final N-bit digital code based on the continuous outputs of the comparison output terminal, where N is an integer greater than 1, and the conversion control unit 22 determines a first quantity or a second quantity of updated versions based on the previous outputs in the continuous outputs of the comparison output terminal.

[0129] In some embodiments, the computing components of the first set of computing components 11 selectively couple the charging capacitor to the signal terminal and selectively couple the discharging capacitor to the reference terminal based on the data received from multiple memory units and the input vector.

[0130] In some embodiments, the computing components of the second set of computing components 12 selectively couple the charging capacitor to the reference terminal and the discharging capacitor to the signal terminal according to at least one reference control signal from the conversion control unit.

[0131] In some embodiments, the conversion control unit determines at least one reference control signal based on the output of the comparison output terminal.

[0132] In some embodiments, when the signal at the reference end is less than the signal at the signal end, the conversion control unit generates at least one reference control signal to control the computing components of the second set of computing components 12 to selectively couple the charging capacitor to the reference end and the discharging capacitor to the signal end.

[0133] In some embodiments, the computing components of the second set of computing components 12 further selectively couple an additional charging capacitor to a signal terminal and an additional discharging capacitor to a reference terminal according to at least one reference control signal.

[0134] In some embodiments, the conversion control unit determines at least one reference control signal based on the output of the comparison output terminal.

[0135] In some embodiments, when the signal at the reference end is greater than the signal at the signal end, the conversion control unit generates at least one reference control signal to control the computing components of the second set of computing components 12 to selectively couple the charging capacitor to the reference end, couple the discharging capacitor to the signal end, couple the additional charging capacitor to the signal end, and couple the additional discharging capacitor to the reference end.

[0136] See Figure 8-12 Its display is based on Figure 6-7 A schematic diagram of an embodiment of a method for controlling the coupling of signal paths from multiple computing components of a first group of computing components and a second group of computing components to a signal terminal and a reference terminal of a conversion control unit. For illustrative purposes, according to Figure 1 The memory computing circuit was demonstrated, in which, for example... Figure 4B and Figure 4C The first set of computing components 11A and the second set of computing components 12A shown are employed, and the simulated computing operation is a multiply-accumulate (MAC) operation. For simplicity, Figure 8-12 Partially shown is the in-memory computing circuitry, which is based on Figure 1 A comparison is made between the first set of computing components 11A and the second set of computing components 12A, as well as the two signal paths.

[0137] Furthermore, assuming the input vector has five input values ​​(I1, ..., I5), the conversion control unit 22 (e.g., controller 220) performs a 5-bit analog-to-digital conversion. Therefore, the analog-to-digital conversion requires five clock phases. Of course, implementations of the invention are not limited to these embodiments.

[0138] In the first set of computational components 11A, a control signal is formed based on the input vector for simulation purposes. Due to charge sharing, the computational components need to provide equal capacitance for the signal paths of the input signal Vsig and the reference signal Vref, as will be... Figure 8-12 The subsequent phases are explained below.

[0139] refer to Figure 8 If I1 to I5 are logic high (or "H"), W1 to W3 are also "H", and W4 to W5 are "L", meaning the equivalent MAC value is 3. In the circuit, Vsig = 3CV / 5C and Vref = 0CV / 5C, where "C" represents the unit quantity of capacitance.

[0140] Reference Figure 8 In clock phase 1, select 16 (=2) of the second set of computing components 12A. 4 A calculation component is used to provide a 16C charging capacitor to the signal path for the reference signal Vref and a 16C discharging capacitor to the signal path for the input signal Vsig. To make the difference between the input signal Vsig and the reference signal Vref more significant, an additional calculation component from the second set of calculation components 12A is selected to provide a 0.5C charging capacitor to the signal path of the input signal Vsig and a 0.5C discharging capacitor to the signal path of the reference signal Vref. In this case, Vsig = 3CV / (5+16.5)C and Vref = 16CV / (5+16.5)C, where the denominators of the formulas for Vsig and Vref remain the same for both signal paths. Since the reference signal Vref is greater than the input signal Vsig, the bit is set to "0" according to step S30 and the (N-1)th bit (e.g., the fourth bit) of the digital code is set to "0" (represented as D4). According to steps S35, S41 and S45, in the next phase, an additional calculation component (e.g., 8 (=2 3 The computational component will be coupled to the signal path of the input signal Vsig. In other words, at clock phase 2, an additional charging capacitor will be added to the input signal Vsig, and an additional discharging capacitor will be added to the reference signal Vref.

[0141] refer to Figure 9In clock phase 2, Vsig = (3+8)CV / (5+16.5+8)C and Vref = 16CV / (5+16.5+8)C, where the denominators of the formulas for Vsig and Vref remain the same for both signal paths. Because the reference signal Vref is greater than the input signal Vsig, the bit in step S30 is "0" and the (N-2)th bit (i.e., the third bit) of the digital code is set to 0 (denoted as D3). According to steps S35, S41, and S45, in the next phase, additional calculation components (e.g., 4 (=2) 2 The computational components will be coupled to the signal path of the input signal Vsig. In other words, an additional charging capacitor will be added to the input signal Vsig, while an additional discharging capacitor will be added to the reference signal Vref.

[0142] refer to Figure 10 In clock phase 3, Vsig = (3+0.5+8+4)CV / (5+16.5+8+4)C and Vref = 16CV / (5+16.5+8+4)C, where the denominators of the formulas for Vsig and Vref remain the same for both signal paths. Because the reference signal Vref is greater than the input signal Vsig, the bit in step S30 is "0", and the (N-3)th bit of the digital code (e.g., the second bit) is set to "0" (denoted by D2). According to steps S35, S41, and S45, in the next phase, additional calculation components (e.g., 2 (=2 1 The computational component will be coupled to the signal path of the input signal Vsig. In other words, at clock phase 4, an additional charging capacitor will be added to the input signal Vsig, and an additional discharging capacitor will be added to the reference signal Vref.

[0143] refer to Figure 11 In clock phase 4, Vsig = (3+0.5+8+4+2)CV / (5+16.5+8+4+2)C and Vref = 16CV / (5+16.5+8+4+2)C, where the denominators of the formulas for Vsig and Vref remain the same for both signal paths. Because the reference signal Vref is less than the input signal Vsig, the bit in step S30 is "1" and the (N-4)th bit of the digital code (e.g., the first bit) is set to "1" (denoted by D1). According to steps S35, S41, and S43, in the next phase, 1 (=2 0 An additional computational component will be coupled to the signal path of the reference signal Vref. In other words, at clock phase 5, an additional charging capacitor will be added to the reference signal Vref, and an additional discharging capacitor will be added to the input signal Vsig.

[0144] refer to Figure 12At clock phase 5, Vsig = (3+0.5+8+4+2)CV / (5+16.5+8+4+2+1)C and Vref = (16+1)CV / (5+16.5) +8+4+2+1)C, where the denominators of the formulas for Vsig and Vref remain the same for both signal paths. Since the reference signal Vref is less than the input signal Vsig, the bit in step S30 is "1" and the (N-5)th bit (e.g., the zeroth bit) of the digital code is set to 1 (denoted by D0).

[0145] Therefore, the final digital code (D4D3D2D1D0) = (00011)2 = 3.

[0146] It should be noted that in the above embodiment of the analog-to-digital conversion process, when the reference signal Vref is greater than the input signal Vsig at one clock phase, according to... Figure 7 In steps S41 and S45, one or more additional computing components from the second set of computing components 12A are configured to be phase-coupled to the signal path for the input signal Vsig. In this way, resetting the charging capacitor is unnecessary as with conventional SAR-ADCs. The conversion control unit (e.g., 22 or 22A) can, according to... Figure 7 The implementation scheme reduces or eliminates the need for capacitor reset during analog-to-digital conversion. Therefore, analog-to-digital conversion can be performed more efficiently.

[0147] Therefore, various embodiments of memory computing circuits for charging mode have been provided above. The reference voltage and signal voltage are derived from multiple sets of computing elements with the same architecture, effectively reducing relative errors and minimizing or avoiding inaccuracies caused by process / voltage / temperature (PVT) drift. Furthermore, the architecture of the memory computing circuit improves efficiency in the analog-to-digital conversion process, thereby reducing or eliminating the need for capacitor reset.

[0148] The present invention has been disclosed above with reference to preferred embodiments. However, those skilled in the art should understand that the embodiments are for illustrative purposes only and should not be construed as limiting the scope of the invention. It should be noted that all variations and substitutions equivalent to the described embodiments should be included within the scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A memory computing circuit, characterized in that, The memory computing circuit includes: An array of computing components for simulating computational operations, the array of computing components comprising: Multiple storage units; A first set of computing components provides capacitance for analog calculations in response to an input vector, wherein the first set of computing components receives data from the plurality of storage units and the input vector; and The second set of computing components provides capacitance for quantization in analog-to-digital conversion, wherein each computing component in the array of computing components is based on a switched capacitor circuit; and Analog-to-digital converter circuit, the analog-to-digital converter circuit comprising: A comparator having a signal terminal, a reference terminal, and a comparison output terminal, wherein each computing component of the first group of computing components selectively couples a charging capacitor to the signal terminal and selectively couples a discharging capacitor to the reference terminal based on data received from the plurality of memory cells and the input vector; and A conversion control unit, coupled to the comparison output terminal, is configured to control each computing component from a first number of computing components in the second group of computing components to be coupled to the signal terminal and the reference terminal based on the output of the comparison output terminal, wherein each computing component from the first number of computing components in the second group of computing components selectively couples a charging capacitor to the reference terminal and a discharging capacitor to the signal terminal based on at least one reference control signal from the conversion control unit.

2. The memory computing circuit according to claim 1, characterized in that, The conversion control unit also controls a second number of computing components to be coupled from the second group of computing components to the signal terminal based on the output of the comparison output terminal.

3. The memory computing circuit according to claim 2, characterized in that, The conversion control unit determines the final N-bit digital code based on the continuous outputs of the comparison output terminal, where N is an integer greater than 1. The conversion control unit determines the updated version of the first quantity or the second quantity based on the previous outputs of the continuous outputs of the comparison output terminal.

4. The memory computing circuit according to claim 1, characterized in that, The conversion control unit determines at least one of the reference control signals based on the output of the comparison output terminal.

5. The memory computing circuit according to claim 1, characterized in that, When the signal at the reference terminal is less than the signal at the signal terminal, the conversion control unit generates at least one of the reference control signals to control the computing components of the second set of computing components to selectively couple the charging capacitor to the reference terminal and the discharging capacitor to the signal terminal.

6. The memory computing circuit according to claim 1, characterized in that, The second set of computing components, based on the reference control signal, further selectively couples additional charging capacitors other than the charging capacitor to the signal terminal and additional discharging capacitors other than the discharging capacitor to the reference terminal.

7. The memory computing circuit according to claim 6, characterized in that, The conversion control unit determines at least one of the reference control signals based on the output of the comparison output terminal.

8. The memory computing circuit according to claim 6, characterized in that, When the signal at the reference terminal is greater than the signal at the signal terminal, the conversion control unit generates at least one of the reference control signals to control the computing components of the second set of computing components to selectively couple the charging capacitor to the reference terminal, couple the discharging capacitor to the signal terminal, couple the additional charging capacitor to the signal terminal, and couple the additional discharging capacitor to the reference terminal.

9. The memory computing circuit according to claim 1, characterized in that, The simulation operation is a multiplication-accumulation (MAC) operation.

10. The memory computing circuit according to claim 1, characterized in that, The memory computing circuitry is housed in a single chip.

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