Memory device failure test structure and test method

Abstract

The application provides a memory device failure test structure and a test method. The memory device failure test structure comprises: a memory device, containing a plurality of memory cells, each of the memory cells containing a word line and a bit line; a first pad, electrically connected with the word line in all the memory cells; and a second pad, electrically connected with the bit line in all the memory cells. All the memory cells are placed in a '0' state, a negative voltage is applied to the first pad, a first positive voltage is applied to the second pad, stress test is simultaneously performed on all the memory cells, read operation is simultaneously performed on all the memory cells, and whether defects exist in the memory device is judged according to the first leakage current, so that the deterioration tendency of the process can be found in advance in the process, the process abnormality can be improved in time, and the reliability risk of the batch product can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuit manufacturing, and particularly relates to a memory device failure test structure and a test method. BACKGROUND

[0002] With the further development of flash memory, the size of the storage unit is further reduced, and the challenge to the process is also greater. Among them, the further reduction of the width of the word line will cause the electrical performance of the storage unit to be more sensitive to defects on the word line, but the conventional test structure cannot screen out such defects.

[0003] In the conventional test structure, only a single word line and bit line are introduced for detecting the intrinsic characteristics (including threshold voltage Vt and saturation drain current Idsat, etc.) of a single storage unit, but for the abnormality of the line width of the word line being significantly narrowed, it cannot be tested out in advance in the process production process by using this conventional test structure and the corresponding test method, and it is necessary to perform reliability test on the chip to find that the storage unit in which the word line with too narrow line width is located has a decrease in the ability to retain electrons and a threshold voltage drift, so as to determine that there is a defect in the word line in the storage unit, which leads to the inability to find the deterioration tendency of the process in advance, the inability to improve the process anomaly in time, and further leads to the existence of reliability risk of the batch product.

[0004] Therefore, it is necessary to improve the test structure and the test method to solve the above problems. SUMMARY

[0005] The present application aims to provide a memory device failure test structure and a test method, which can find the deterioration tendency of the process in advance in the process, improve the process anomaly in time, and avoid leading to the existence of reliability risk of the batch product.

[0006] To achieve the above-mentioned purpose, the present application provides a memory device failure test structure, comprising:

[0007] a memory device, comprising a plurality of storage units, each of the storage units comprising a word line and a bit line;

[0008] a first pad, electrically connected with the word line in all the storage units;

[0009] a second pad, electrically connected with the bit line in all the storage units.

[0010] Optionally, each of the storage units comprises a source line, and the memory device failure test structure further comprises:

[0011] a third pad, electrically connected with the source line in all the storage units.

[0012] Optionally, the memory device failure test structure further comprises a plurality of conductive plugs and a plurality of metal interconnection lines, the first pad is electrically connected with the word line through the conductive plugs and the metal interconnection lines, and the second pad is electrically connected with the bit line through the conductive plugs and the metal interconnection lines.

[0013] The application further provides a memory device failure test method, comprising:

[0014] The memory device failure test structure is provided.

[0015] All the memory cells are set to a '0' state.

[0016] A negative voltage is applied to the first pad and a first positive voltage is applied to the second pad to simultaneously perform a stress test on all the memory cells.

[0017] A read operation is simultaneously performed on all the memory cells, and whether there is a defect in the memory device is determined according to the first leakage current read.

[0018] Optionally, the step of setting all the memory cells to a '0' state comprises:

[0019] A second positive voltage is applied to the first pad and a third positive voltage is applied to the second pad to simultaneously perform a write operation on all the memory cells, so that all the memory cells are written with all '0's.

[0020] Optionally, the step of setting all the memory cells to a '0' state further comprises:

[0021] A fourth positive voltage is applied to the first pad and a fifth positive voltage is applied to the second pad, and a read operation is simultaneously performed on all the memory cells to read a second leakage current.

[0022] Optionally, the second positive voltage ranges from greater than 9V, the third positive voltage ranges from greater than or equal to 3.5V, the fourth positive voltage ranges from 5V to 9V, and the fifth positive voltage ranges from 0.5V to 1V.

[0023] Optionally, the time range for applying the second positive voltage to the first pad and the third positive voltage to the second pad ranges from 1μs to 10μs.

[0024] Optionally, the negative voltage ranges from less than or equal to -1V, and the first positive voltage ranges from greater than or equal to 3.8V.

[0025] Optionally, the time range for applying the negative voltage to the first pad and the first positive voltage to the second pad ranges from greater than or equal to 1μs.

[0026] Optionally, during the stress test, the electrons in the word line in the storage unit in the '0' state are pulled out into the drain region in the storage unit.

[0027] Optionally, a sixth positive voltage is applied to the first pad and a seventh positive voltage is applied to the second pad to simultaneously perform a read operation on all the storage units.

[0028] Optionally, the sixth positive voltage ranges from 5V to 9V, and the seventh positive voltage ranges from 0.5V to 1V.

[0029] Optionally, if the ratio of the first leakage current and the second leakage current read is less than or equal to 10, the gate structure in the memory device does not have defects; if the ratio of the first leakage current and the second leakage current read is greater than 10, the gate structure in the memory device has defects; wherein the gate structure includes a tunneling oxide layer from bottom to top, a floating gate layer, an inter-gate dielectric layer and the word line.

[0030] Optionally, if the first leakage current and the second leakage current read are both in the nA level, the gate structure in the memory device does not have defects; if the first leakage current is in the μA level and the second leakage current is in the nA level, the gate structure in the memory device has defects.

[0031] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0032] 1、The stress migration test structure of the present application, since all the word lines in the storage units are connected and electrically connected to the same first pad, and all the bit lines in the storage units are connected and electrically connected to the same second pad, it is possible to simultaneously perform a failure test on all the storage units in the memory device through the first pad and the second pad, and thus the memory device can be immediately tested for failure after wafer manufacturing is completed, without waiting until the chip is tested for reliability to find defects, so that the deterioration tendency of the process can be found in advance during the process, the stability of the process can be monitored, and the process abnormalities can be improved in time to avoid causing reliability risks in batch products.

[0033] 2. The stress migration testing method of the present invention provides the memory device failure test structure, and after setting all the memory cells to the '0' state, applies a negative voltage to the first pad and a first positive voltage to the second pad to simultaneously perform stress testing on all the memory cells. This allows the presence of defects in the memory device to be determined based on the first leakage current read after the stress test, thereby enabling the early detection of process deterioration tendencies, monitoring of process stability, and timely improvement of process anomalies, thus avoiding reliability risks to batch products. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a storage device failure test structure according to an embodiment of the present invention;

[0035] Figure 2 This is a schematic diagram of the structure of a storage unit according to an embodiment of the present invention;

[0036] Figure 3 This is a flowchart of a storage device failure testing method according to an embodiment of the present invention.

[0037] Among them, the appendix Figures 1-3 The annotations in the attached figures are explained as follows:

[0038] 11-First pad; 12-Second pad; 13-Third pad; 21-Substrate; 221-Source region; 222-Drain region; 231-Tunneling oxide layer; 232-Floating gate layer; 233-Inter-gate dielectric layer; 234-Control gate layer; 24-Sidewall; 25-Metal silicide layer; 26-Inter-layer dielectric layer; 27-Word line conductive plug; 28-Bit line conductive plug. Detailed Implementation

[0039] To make the objectives, advantages, and features of the present invention clearer, the storage device failure testing structure and testing method proposed in this invention will be further described in detail below. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0040] An embodiment of the present invention provides a memory device failure test structure, comprising: a memory device including a plurality of memory cells, each memory cell including a word line and a bit line; a first pad electrically connected to the word lines of all the memory cells; and a second pad electrically connected to the bit lines of all the memory cells.

[0041] See below. Figures 1-2 The storage device failure test structure provided in this embodiment is described in detail. Among them, Figure 2 It is also a longitudinal cross-sectional diagram of the storage unit.

[0042] The storage device comprises a plurality of storage cells arranged in an array, such as Figure 2 As shown, each memory cell includes a substrate 21 and a gate structure formed on the substrate 21. A well region (not shown) is formed in the substrate 21, and the gate structure is formed on the well region. The gate structure includes, from bottom to top, a tunneling oxide layer 231, a floating gate layer 232, an inter-gate dielectric layer 233, and a control gate layer 234. Sidewalls 24 are formed on the sidewalls of the gate structure, and a metal silicide layer 25 is formed on the top surface of the gate structure. Active regions 2 are formed in the well regions on both sides of the gate structure. The substrate 21 includes a gate structure, a drain region 222, and an interlayer dielectric layer 26. The interlayer dielectric layer 26 buries the gate structure, sidewalls 24, metal silicide layer 25, source region 221, and drain region 222. A word line conductive plug 27 is formed in the interlayer dielectric layer 26 on the metal silicide layer 25, a bit line conductive plug 28 is formed in the interlayer dielectric layer 26 on the drain region 222, and a source line conductive plug (not shown) is formed in the interlayer dielectric layer 26 on the source region 221. Furthermore, the interlayer dielectric layer 26 may also contain several metal interconnects (not shown) for leading the word line conductive plug 27, the bit line conductive plug 28, and the source line conductive plug to the top surface of the interlayer dielectric layer 26, respectively.

[0043] In the memory cell, the control gate layer 234 is called a word line, the drain region 222 is called a bit line, and the source region 221 is called a source line.

[0044] The storage device failure test structure includes a first pad 11, a second pad 12, and a third pad 13, which can be formed on the top surface of the interlayer dielectric layer 26.

[0045] All word lines in the memory cells can be electrically connected to the first pad 11 via the word line conductive plug 27 and the metal interconnect. All bit lines in the memory cells can be electrically connected to the second pad 12 via the bit line conductive plug 28 and the metal interconnect. All source lines in the memory cells can be electrically connected to the third pad 13 via the source line conductive plug and the metal interconnect.

[0046] like Figure 1 As shown, in the memory cell array of the memory device, the first pad 11 is electrically connected to the word lines WL0, WL1 to WLn of all the memory cells, the second pad 12 is electrically connected to the bit lines BL0, BL1, BL2 to BLn of all the memory cells, and the third pad 13 is electrically connected to the source line SL of all the memory cells.

[0047] From the above, the memory device failure test structure provided by the application can simultaneously test all the memory cells in the memory device through the first pad, the second pad and the third pad (i.e. when the gate structure in the memory cell has a defect of too narrow width, the current can be obviously increased), so that the memory device can be tested immediately after the wafer manufacturing is completed, without waiting until the chip is tested for reliability to find defects, so that the deterioration tendency of the process can be found in advance during the process, the stability of the process can be monitored, the process abnormality can be improved in time, and the reliability risk of the batch product can be avoided.

[0048] Based on the same inventive concept, an embodiment of the application provides a memory device failure test method, which is described in detail with reference to Figure 3 Figure 3 As can be seen from the above, the memory device failure test method comprises:

[0049] S1, providing the memory device failure test structure;

[0050] S2, setting all the memory cells to a '0' state;

[0051] S3, applying a negative voltage to the first pad and a first positive voltage to the second pad to simultaneously stress test all the memory cells;

[0052] S4, simultaneously performing a read operation on all the memory cells, and determining whether there is a defect in the memory device according to the first leakage current read.

[0053] The memory device failure test method provided by the embodiment will be described in detail with reference to Figure 1 and Figure 2

[0054] According to S1, the memory device failure test structure is provided, which is described above and will not be described here again.

[0055] According to S2, all the memory cells are set to a '0' state.

[0056] ​​Preferably, the step of setting all the memory cells to the '0' state further comprises applying a fourth positive voltage to the first pad 11 and a fifth positive voltage to the second pad 12, and simultaneously performing a read operation on all the memory cells, to confirm that all the memory cells are set to the '0' state, and thus to confirm that the second leakage current obtained by reading before the stress test is small enough.

[0057] Preferably, the step of setting all the memory cells to the '0' state further comprises applying a fourth positive voltage to the first pad 11 and a fifth positive voltage to the second pad 12, and simultaneously performing a read operation on all the memory cells, to confirm that all the memory cells are set to the '0' state, and thus to confirm that the second leakage current obtained by reading before the stress test is small enough.

[0058] Preferably, the second positive voltage ranges from greater than 9V, the third positive voltage ranges from greater than or equal to 3.5V, the fourth positive voltage ranges from 5V to 9V (including 5V and 9V), and the fifth positive voltage ranges from 0.5V to 1V (including 0.5V and 1V).

[0059] Preferably, the time range for applying the second positive voltage to the first pad 11 and the third positive voltage to the second pad 12 is 1μs to 10μs (including 1μs and 10μs).

[0060] According to step S3, a negative voltage is applied to the first pad 11 and a first positive voltage is applied to the second pad 12, to simultaneously perform a stress test on all the memory cells.

[0061] During the stress test, the electrons in the word lines of the memory cells in the '0' state are pulled out into the drain region. Since the word lines in the gate structure with an excessively narrow width store fewer electrons than the word lines in the gate structure with a normal width, the pulling of the electrons out of the word lines has a greater impact on the word lines with an excessively narrow width than on the word lines with a normal width. The word lines with an excessively narrow width cause the threshold voltage of the memory device after the stress test to decrease and the leakage current to increase. Furthermore, the excessively narrow width of the gate structure causes the channel to also have an excessively narrow width, which causes the electrons in the word lines to be more easily pulled out into the drain region, which further decreases the threshold voltage of the memory device after the stress test and further increases the leakage current.

[0062] Therefore, by applying the voltage to all the memory cells through the first pad 11 and the second pad 12 simultaneously to perform the stress test, whether the gate structure with the width defect exists in the memory device can be determined according to the change of the leakage current before and after the stress test.

[0063] Preferably, the negative voltage is less than or equal to -1V, and the first positive voltage is greater than or equal to 3.8V.

[0064] Preferably, the time range for applying the negative voltage to the first pad 11 and the first positive voltage to the second pad 12 is greater than or equal to 1μs, and the suitable time can be selected according to the defect condition.

[0065] According to step S4, the read operation is performed on all the memory cells simultaneously, and whether the defect exists in the memory device is determined according to the first leakage current read.

[0066] If the ratio of the first leakage current read after the stress test to the second leakage current read before the stress test is less than or equal to 10, the gate structure in the memory device does not have the defect (i.e. the width defect); if the ratio of the first leakage current read after the stress test to the second leakage current read before the stress test is greater than 10, the gate structure in the memory device has the defect.

[0067] For example, if the first leakage current read after the stress test and the second leakage current read before the stress test are both in the order of nA, the gate structure in the memory device does not have the defect; if the first leakage current read after the stress test is in the order of μA and the second leakage current read before the stress test is in the order of nA, the gate structure in the memory device has the defect.

[0068] Preferably, the number of the gate structures with the width defect in the memory device is at least one, and can be Figure 2 The at least one layer structure of the tunneling oxide layer 231, the floating gate layer 232, the inter-gate dielectric layer 233 and the control gate layer 234 in the memory cell shown in FIG. 1 has the width defect.

[0069] And, a read operation can be performed on all the memory cells simultaneously by applying a sixth positive voltage to the first pad 11 and a seventh positive voltage to the second pad 12.

[0070] Preferably, the sixth positive voltage ranges from 5V to 9V (including 5V and 9V), and the seventh positive voltage ranges from 0.5V to 1V (including 0.5V and 1V).

[0071] And, it should be noted that in the above steps S2-S4, the source line SL is grounded through the third pad 13, and the well region is grounded.

[0072] And, the above steps S2-S4 can be performed immediately after the wafer manufacturing is completed, for example, in the process of wafer-level testing, so that defects can be found without waiting until the reliability test of the chip is performed, thereby enabling the deterioration tendency of the process to be found in advance in the process, the stability of the process to be monitored, and the process abnormality to be improved in time, so as to avoid causing the batch products to have reliability risks.

[0073] From the above, it can be seen that the memory device failure test method provided by the present application can simultaneously perform stress tests on all the memory cells by providing the memory device failure test structure and applying a negative voltage to the first pad and a first positive voltage to the second pad after all the memory cells are placed in the '0' state, so that whether there is a defect in the memory device can be determined according to the first leakage current read after the stress test, thereby enabling the deterioration tendency of the process to be found in advance in the process, the stability of the process to be monitored, and the process abnormality to be improved in time, so as to avoid causing the batch products to have reliability risks.

[0074] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any modification or change made by a person of ordinary skill in the art based on the above disclosure is within the protection scope of the claims.

Claims

1. A method for testing the failure of storage devices, characterized in that, include: A storage device failure test structure is provided, the storage device failure test structure includes a storage device, a first pad and a second pad, the storage device includes a plurality of storage cells, each storage cell includes a word line and a bit line, the first pad is electrically connected to the word lines of all the storage cells, and the second pad is electrically connected to the bit lines of all the storage cells; Set all the aforementioned storage units to the '0' state; A negative voltage is applied to the first pad and a first positive voltage is applied to the second pad to simultaneously stress test all of the memory cells; Simultaneously, read operations are performed on all the memory cells, and the presence of defects in the memory device is determined based on the first leakage current read.

2. The storage device failure testing method as described in claim 1, characterized in that, Each of the memory cells includes a source line, and the memory device failure test structure further includes: The third pad is electrically connected to the source line in all of the memory cells.

3. The storage device failure testing method as described in claim 1, characterized in that, The memory device failure test structure also includes several conductive plugs and several metal interconnects. The first pad is electrically connected to the word line through the conductive plugs and the metal interconnects, and the second pad is electrically connected to the bit line through the conductive plugs and the metal interconnects.

4. The storage device failure test method according to any one of claims 1 to 3, characterized in that, The step of setting all the aforementioned storage cells to the '0' state includes: A second positive voltage is applied to the first pad and a third positive voltage is applied to the second pad to simultaneously perform write operations on all the memory cells, such that all the memory cells are written with all '0's.

5. The storage device failure testing method as described in claim 4, characterized in that, The step of setting all the aforementioned storage units to the '0' state further includes: A fourth positive voltage is applied to the first pad and a fifth positive voltage is applied to the second pad, while simultaneously performing read operations on all the memory cells to obtain the second leakage current.

6. The storage device failure testing method as described in claim 5, characterized in that, The second positive voltage is greater than 9V, the third positive voltage is greater than or equal to 3.5V, the fourth positive voltage is 5V to 9V, and the fifth positive voltage is 0.5V to 1V.

7. The storage device failure testing method as described in claim 4, characterized in that, The time range for applying the second positive voltage to the first pad and the third positive voltage to the second pad is 1 μs to 10 μs.

8. The storage device failure test method according to any one of claims 1 to 3, characterized in that, The negative voltage range is less than or equal to -1V, and the first positive voltage range is greater than or equal to 3.8V.

9. The storage device failure test method according to any one of claims 1 to 3, characterized in that, The time range for applying the negative voltage to the first pad and applying the first positive voltage to the second pad is greater than or equal to 1 μs.

10. The storage device failure test method according to any one of claims 1 to 3, characterized in that, During the stress test, electrons in the word lines of the memory cell, which are in the '0' state, are pulled out to the drain region of the memory cell.

11. The storage device failure test method according to any one of claims 1 to 3, characterized in that, A sixth positive voltage is applied to the first pad and a seventh positive voltage is applied to the second pad to simultaneously perform read operations on all of the memory cells.

12. The storage device failure testing method as described in claim 11, characterized in that, The range of the sixth positive voltage is 5V to 9V, and the range of the seventh positive voltage is 0.5V to 1V.

13. The storage device failure testing method as described in claim 5, characterized in that, If the ratio of the first leakage current to the second leakage current read is less than or equal to 10, then there is no defect in the gate structure of the memory device; if the ratio of the first leakage current to the second leakage current read is greater than 10, then there is a defect in the gate structure of the memory device; wherein, the gate structure includes, from bottom to top, a tunneling oxide layer, a floating gate layer, an inter-gate dielectric layer, and the word line.

14. The storage device failure testing method as described in claim 13, characterized in that, If both the first and second leakage currents are in the nA range, then the gate structure in the memory device is free of defects; if the first leakage current is in the μA range and the second leakage current is in the nA range, then the gate structure in the memory device is defective.

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