Trench super junction device and method of fabricating the same
By first fabricating the gate structure and then defining the P-pillar position in the fabrication of the superjunction device, and by utilizing the contact hole self-alignment process, the problems of high cost, poor process stability and thermal budget introduction in the prior art are solved, and a trench-type superjunction device with smaller pitch and lower on-resistance is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ALKAIDSEMI (SHANGHAI) TECHNOLOGIES CORP
- Filing Date
- 2022-04-01
- Publication Date
- 2026-05-29
Smart Images
Figure CN115527857B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and more particularly to power devices, especially to a trench-type superjunction device and its fabrication method. Background Technology
[0002] Compared to conventional VDMOS devices, high-voltage superjunction power devices can combine advantages such as high breakdown voltage and low on-resistance, and are therefore widely used in various power electronic devices.
[0003] Currently, the mainstream fabrication technologies for superjunction devices include multilayer epitaxial growth, multiple ion implantation, and deep trench etching and filling. Among these, multilayer epitaxial growth is simple and easy to control, but it suffers from drawbacks such as high cost and poor process stability. Multiple implantation technology involves high implantation energy, causing significant damage to the wafer surface and is limited to the fabrication of low-voltage devices. In contrast, trench filling offers a simpler process with fewer defects, effectively reducing costs and improving process stability.
[0004] In existing technologies, when fabricating superjunction devices using trench filling technology, the process typically involves deep trench etching, filling, gate fabrication, growth of the interlayer dielectric layer, and then contact hole etching. The first step requires a zero-mark mask, and subsequent photolithography steps (such as P-body) use alignment marks on this layer for alignment. Furthermore, the hard mask layer used in deep trench etching (typically an Oxide-Nitride-Oxide, or ONO structure) needs to be removed after single-crystal silicon epitaxial growth, increasing the fabrication steps and cost. Simultaneously, the large thermal budget introduced during gate fabrication leads to lateral diffusion of the P-pillars, ultimately resulting in charge mismatch, thus affecting device performance and hindering the reduction of the P-pillar pitch. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a trench-type superjunction device and its fabrication method, which solves the problems of existing methods for fabricating superjunction devices, such as high cost, poor process stability, or significant damage to the wafer surface, which can only fabricate low-voltage devices; and the existing trench filling technology first performs deep trench etching, filling, gate fabrication, growth of interlayer dielectric layer and then contact hole etching, which is not only complex, but also introduces a large thermal budget during the fabrication process, leading to lateral diffusion of P pillars, ultimately resulting in charge mismatch, affecting device performance, and also hindering the reduction of pitch between P pillars.
[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a trench-type superjunction device, comprising the following steps:
[0007] A substrate with an epitaxial layer is provided, on which a plurality of spaced gate structures are formed;
[0008] Ion implantation is performed to form a P-type body region and an N-type source region in the epitaxial layer surrounding the gate structure. The N-type source region is located within the P-type body region and is adjacent to the gate structure.
[0009] An interlayer dielectric layer is formed covering the gate structure, the P-type body region and the N-type source region. The interlayer dielectric layer includes, from bottom to top, a silicon nitride layer, a silicon oxide layer and a borosilicate glass layer.
[0010] Photolithographic etching is performed on the interlayer dielectric layer to etch contact holes between adjacent gate structures, the contact holes exposing the P-type body region;
[0011] The interlayer dielectric layer located on the surface of the gate structure is etched as a hard mask layer to form a deep trench below the contact hole that is connected to the contact hole.
[0012] The deep trench is filled to form a P-pillar;
[0013] Etching is performed to expose the contact holes;
[0014] An electrical lead-out layer is formed to cover the interlayer dielectric layer and the contact holes.
[0015] Optionally, the gate structure is a trench gate, and the process of forming the gate structure includes:
[0016] A photoresist layer is formed covering the epitaxial layer, and the photoresist layer is exposed and developed to define the gate region;
[0017] The epitaxial layer is etched according to the photoresist layer to form a plurality of shallow trenches in the epitaxial layer that correspond one-to-one with the gate structure;
[0018] A gate oxide layer is formed on the inner surface of the shallow trench;
[0019] The remaining space inside the shallow trench is filled with a polycrystalline silicon layer.
[0020] Optionally, filling the remaining space inside the shallow trench with a polysilicon layer includes the steps of:
[0021] A polycrystalline silicon layer is formed on the surface of the epitaxial layer within and between the shallow trenches using a chemical vapor deposition process.
[0022] Surface planarization is performed to make the upper surface of the shallow trench flush with the epitaxial layer.
[0023] Optionally, the method for forming the gate oxide layer includes thermal oxidation, wherein the thickness of the gate oxide layer is 15 nm to 150 nm.
[0024] Optionally, the depth of the P-type body region is not greater than the depth of the gate structure.
[0025] Optionally, filling the deep trench to form a P-pillar includes:
[0026] A single-crystal silicon layer filling the deep trenches, contact holes, and covering the gate structure is formed by selective epitaxial growth.
[0027] The single-crystal silicon layer is subjected to surface planarization treatment;
[0028] Etching is performed to expose the side surfaces of the contact holes and the N-type source region.
[0029] Optionally, the electrical lead-out layer includes an adhesion layer and an electrode material layer from bottom to top.
[0030] Alternatively, the adhesion layer may include a titanium layer and / or a titanium nitride layer, and the electrode material layer may include several of a gold layer, a copper layer, and a platinum layer.
[0031] Optionally, the substrate includes a silicon substrate, and the epitaxial layer is deposited on the surface of the substrate by an epitaxial process.
[0032] The present invention also provides a trench-type superjunction device, which is prepared by the preparation method described in any of the above embodiments.
[0033] As described above, the trench-type superjunction device and its fabrication method of the present invention have the following beneficial effects: The improved process design of the present invention defines the P-pillar position in the contact hole region, which can effectively reduce the lateral diffusion of the P-pillar compared with the prior art, which is conducive to reducing the product pitch and reducing the on-resistance of the product; the gate structure is fabricated first, and the subsequent process uses the contact hole self-alignment to define the P-pillar position without the need for additional photomask, which can reduce production costs. Attached Figure Description
[0034] Figure 1 The flowchart shown is a method for fabricating the trench-type superjunction device provided by the present invention.
[0035] Figure 2-11 The diagram shows an exemplary cross-sectional structure of the trench-type superjunction device fabricated using the method provided by this invention, illustrating the various steps involved. Detailed Implementation
[0036] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. For ease of explanation, when detailing the embodiments of the present invention, the cross-sectional views showing the device structure are partially enlarged, not according to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0037] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.
[0038] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0039] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components related to the present invention and are not drawn according to the actual number, shape, and size of the components in the actual implementation. In the actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. To keep the illustrations as concise as possible, not all structures are shown in the figures.
[0040] Please see Figures 1 to 11 .
[0041] like Figure 1 As shown, the present invention provides a method for fabricating a trench-type superjunction device, comprising the following steps:
[0042] S1: A substrate 11 with an epitaxial layer 12 is provided, on which a plurality of spaced gate structures 13 are formed; the substrate 11 can be a single structure, such as a single epitaxial layer, or a composite structure, such as a structure in which the epitaxial layer 12 is deposited on the surface of a semiconductor substrate. The semiconductor substrate used is, for example, any one of silicon, germanium, silicon germanium, silicon-on-insulator, silicon carbide, gallium arsenide, etc. In this example, the substrate 11 is a silicon substrate, and the epitaxial layer 12 is formed into a single crystal on the surface of the substrate 11 through an epitaxial process; the gate structures 13 The gate can be a planar gate or a trench gate; this example will primarily use a trench gate. More specifically, the process of forming a trench gate includes: forming a photoresist layer covering the epitaxial layer 12 using a process including but not limited to spin coating; exposing and developing the photoresist layer to define multiple spaced gate regions, each corresponding to a gate structure 13; etching the epitaxial layer 12 along the photoresist layer to form multiple shallow trenches 14 corresponding to the gate structures 13; and then removing the remaining photoresist layer, resulting in the structure shown below. Figure 2 As shown; a gate oxide layer 131 is formed on the inner surface of the shallow trench 14, for example, by thermal oxidation. The thickness of the gate oxide layer 131 is preferably 15nm-150nm. The formed gate oxide layer 131 will be located on the surface of the shallow trench 14 and the surface of the epitaxial layer 12, resulting in the structure shown. Figure 3 As shown; after forming the gate oxide layer 131, the remaining space inside the shallow trench 14 is filled with a polysilicon layer 132. For example, a polysilicon layer 132 is first formed on the surface of the epitaxial layer 12 inside and between the shallow trenches 14 using a chemical vapor deposition process; then, a surface planarization process is performed, for example, chemical mechanical polishing, to remove the polysilicon layer 132 on the surface of the epitaxial layer 12, but the gate oxide layer 131 on the surface of the epitaxial layer 12 can be retained as a mask for ion implantation in the next step. After the surface planarization process, the upper surface of the shallow trench 14 is flush with the epitaxial layer 12, and the resulting structure is as shown. Figure 4 As shown;
[0043] S2: Next, ion implantation is performed to form a P-type body region 15 and an N-type source region in the epitaxial layer 12 surrounding the gate structure 13. The N-type source region is located within the P-type body region 15 and is adjacent to the gate structure 13. The structure obtained in this step is as follows: Figure 5 As shown; the depth of the P-type body region 15 is usually no greater than the depth of the gate structure 13. Of course, the depth of the gate structure 13 is also less than the thickness of the epitaxial layer 12.
[0044] S3: Form an interlayer dielectric layer 17 covering the gate structure 13, the P-type body region 15, and the N-type source region. The interlayer dielectric layer 17 comprises, from bottom to top, a silicon nitride layer, a silicon oxide layer, and a borosilicate glass layer. Each structural layer of the interlayer dielectric layer 17 is preferably formed using a chemical vapor deposition process, and the silicon nitride layer of the interlayer dielectric layer 17 covers the surface of the gate structure 13, simultaneously serving as the gate dielectric layer. The structure obtained in this step is as follows: Figure 6 As shown;
[0045] S4: Photolithographic etching is performed on the interlayer dielectric layer 17 to etch contact holes 18 between adjacent gate structures 13, the contact holes 18 exposing the P-type body region 15, so that only the interlayer dielectric layer 17 remains on the surface of the gate structure 13; the structure obtained in this step is as follows. Figure 7 As shown;
[0046] S5: The interlayer dielectric layer 17 located on the surface of the gate structure 13 is etched as a hard mask layer to form a deep trench 19 below the contact hole 18 and communicating with the contact hole 18. The depth of the deep trench 19 is usually less than the thickness of the epitaxial layer 12, that is, the deep trench 19 does not penetrate the epitaxial layer 12 and has a gap with the substrate 11. The structure obtained by this step is as follows. Figure 8 As shown; compared with the use of an ONO layer as a hard mask layer in the prior art, this application uses the interlayer dielectric layer 17 located on the surface of the gate structure 13 as a hard mask, which can simplify the fabrication process;
[0047] S6: Fill the deep trench 19 to form a P-pillar 20, for example, fill it with monocrystalline silicon to form a P-pillar 20;
[0048] S7: Etch to expose the contact hole 18; Steps S6 and S7 can be performed by selective epitaxial growth to form a single-crystal silicon layer filling the deep trench 19, the contact hole 18, and covering the gate structure 13, with the single-crystal silicon layer formed in the deep trench 19 serving as a P-pillar 20; the single-crystal silicon layer is then planarized, for example by chemical mechanical polishing, to expose the gate structure 13, resulting in the structure shown below. Figure 9 As shown; then etching is performed to expose the contact hole 18 and the side surface of the N-type source region, and the two are connected, resulting in the structure shown. Figure 10 As shown; it can be seen that several P pillars 20 are spaced apart in the epitaxial layer 12, and the epitaxial layer 12 that separates the P pillars 20 serves as N pillars, thereby forming a super-junction structure. Since the P pillars are defined after the gate structure is fabricated, they will not undergo thermal oxidation similar to the gate structure fabrication process. The thermal processes such as drive-in that are performed when fabricating the P-type body region can effectively reduce the thermal budget, which is beneficial for reducing the pitch and reducing the on-resistance.
[0049] S8: Forming an electrical lead-out layer 21 covering the interlayer dielectric layer 17 and the contact hole 18, resulting in the structure shown below. Figure 11 As shown; specifically, the electrical lead-out layer 21 includes an adhesion layer and an electrode material layer from bottom to top. The adhesion layer includes a titanium layer and / or a titanium nitride layer, and the electrode material layer includes, but is not limited to, several of the following: a gold layer, a copper layer, and a platinum layer.
[0050] The improved process design of this invention defines the P-pillar position in the contact hole region, which can effectively reduce the lateral diffusion of the P-pillar compared with the prior art, which is beneficial to reduce the product pitch and reduce the on-resistance of the product. The gate structure is fabricated first, without the need for a first reference mask (zero mask). Subsequent processes are aligned with the alignment pattern of the gate. The P-pillar position is defined by the self-alignment of the contact hole without the need for an additional photomask, which can reduce production costs.
[0051] This invention also provides a trench-type superjunction device, which is fabricated using the fabrication method described in any of the above embodiments; therefore, the foregoing content can be quoted in its entirety herein. References Figure 11 As shown, the trench-type superjunction device provided by the present invention includes a substrate 11 with an epitaxial layer 12, a P-type body region 15, an N-type source region, an interlayer dielectric layer 17, and an electrical lead-out layer 21. Multiple P-pillars 20 are formed at intervals in the epitaxial layer 12, with the epitaxial layers 12 spaced apart by the P-pillars 20 serving as N-pillars, thereby forming an arrayed superjunction structure. The gate structure 13 is located within or on the upper surface of the epitaxial layers 12 between the P-pillars 20 (depending on whether it is a trench gate or a planar gate). The P-type body region 15 is located within the epitaxial layer 12 outside the gate structure 13 and is connected to the P-pillars 20. The N-type source region is located within the P-type body region 15 and is adjacent to the gate structure 13. The interlayer dielectric layer 17 is located on the surface of the gate structure 13. The electrical lead-out layer 21 covers the P-pillars 20 and the interlayer dielectric layer 17. For further details on the trench-type superjunction device, please refer to the foregoing content; for brevity, further elaboration is omitted. Because it is prepared by the aforementioned method, the trench-type superjunction device provided by the present invention has the advantages of simple preparation process, relatively low preparation cost and better performance.
[0052] In summary, this invention provides a trench-type superjunction device and its fabrication method. The fabrication method includes the following steps: providing a substrate with an epitaxial layer, forming a plurality of spaced gate structures on the epitaxial layer; performing ion implantation to form a P-type body region and an N-type source region in the epitaxial layer surrounding the gate structures, wherein the N-type source region is located within the P-type body region and adjacent to the gate structures; forming an interlayer dielectric layer covering the gate structures, the P-type body region, and the N-type source region, wherein the interlayer dielectric layer comprises, from bottom to top, a silicon nitride layer, a silicon oxide layer, and a borosilicate glass layer; performing photolithography etching on the interlayer dielectric layer to etch contact holes between adjacent gate structures, wherein the contact holes expose the P-type body region; using the interlayer dielectric layer located on the surface of the gate structures as a hard mask layer for etching to form a deep trench below the contact holes and communicating with the contact holes; filling the deep trench to form a P-pillar; etching to expose the contact holes; and forming an electrical lead-out layer covering the interlayer dielectric layer and the contact holes. The improved process design of this invention defines the P-pillar positions in the contact hole region, which, compared to existing technologies, effectively reduces the lateral diffusion of the P-pillars, facilitating smaller product pitch and lower on-resistance. Furthermore, by fabricating the gate structure first, a first-stage reference mask is eliminated. Subsequent processes align with the gate alignment pattern, and the P-pillar positions are defined using contact hole self-alignment, eliminating the need for additional photomasks and reducing production costs. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.
[0053] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a trench-type superjunction device, characterized in that, Including the following steps: A substrate with an epitaxial layer is provided, on which a plurality of spaced gate structures are formed; Ion implantation is performed to form a P-type body region and an N-type source region in the epitaxial layer surrounding the gate structure. The N-type source region is located within the P-type body region and is adjacent to the gate structure. An interlayer dielectric layer is formed covering the gate structure, the P-type body region and the N-type source region. The interlayer dielectric layer includes, from bottom to top, a silicon nitride layer, a silicon oxide layer and a borosilicate glass layer. Photolithographic etching is performed on the interlayer dielectric layer to etch contact holes between adjacent gate structures, the contact holes exposing the P-type body region; The interlayer dielectric layer located on the surface of the gate structure is etched as a hard mask layer to form a deep trench below the contact hole that is connected to the contact hole. The deep trench is filled to form a P-pillar; Etching is performed to expose the sidewalls of the contact holes and the N-type source region; An electrical lead-out layer is formed to cover the interlayer dielectric layer and the contact holes.
2. The preparation method according to claim 1, characterized in that, The gate structure is a trench gate, and the process of forming the gate structure includes: A photoresist layer is formed covering the epitaxial layer, and the photoresist layer is exposed and developed to define the gate region; The epitaxial layer is etched according to the photoresist layer to form a plurality of shallow trenches in the epitaxial layer that correspond one-to-one with the gate structure; A gate oxide layer is formed on the inner surface of the shallow trench; The remaining space inside the shallow trench is filled with a polycrystalline silicon layer.
3. The preparation method according to claim 2, characterized in that, Filling the remaining space inside the shallow trench with a polysilicon layer includes the following steps: A polycrystalline silicon layer is formed on the surface of the epitaxial layer within and between the shallow trenches using a chemical vapor deposition process. Surface planarization is performed to make the upper surface of the shallow trench flush with the epitaxial layer.
4. The preparation method according to claim 2, characterized in that, The method for forming the gate oxide layer includes thermal oxidation, and the thickness of the gate oxide layer is 15 nm-150 nm.
5. The preparation method according to claim 2, characterized in that, The depth of the P-type body region is no greater than the depth of the gate structure.
6. The preparation method according to claim 1, characterized in that, Filling the deep trench to form a P-pillar includes: A single-crystal silicon layer filling the deep trenches, contact holes, and covering the gate structure is formed by selective epitaxial growth. The single-crystal silicon layer is subjected to surface planarization treatment.
7. The preparation method according to claim 1, characterized in that, The electrical lead-out layer comprises, from bottom to top, an adhesion layer and an electrode material layer.
8. The preparation method according to claim 7, characterized in that, The adhesion layer includes a titanium layer and / or a titanium nitride layer, and the electrode material layer includes several of the following: a gold layer, a copper layer, and a platinum layer.
9. The preparation method according to claim 1, characterized in that, The substrate includes a silicon substrate, and the epitaxial layer is deposited on the surface of the substrate by an epitaxial process.
10. A trench-type superjunction device, characterized in that, The trench-type superjunction device is prepared by the preparation method described in any one of claims 1-9.