Thermally enhanced FCBGA package

Abstract

This disclosure relates to a thermally enhanced FCBGA package. The semiconductor device includes: a heat sink having an opening formed through the heat sink; the heat sink being disposed on a substrate, wherein a semiconductor die is disposed in the opening on the substrate; and a thermally conductive material, such as an adhesive or elastomeric plug, being disposed in the opening between the heat sink and the semiconductor die. A conductive layer is formed on the substrate, the heat sink, and the thermally conductive material.

Description

Technical Field

[0001] This invention generally relates to semiconductor manufacturing, and more specifically to methods and semiconductor devices for forming flip-chip ball grid array packages with enhanced thermal properties. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide variety of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and generating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, generate the relationship between voltage and current required to perform the circuit's function.

[0004] Back-end manufacturing refers to the process of dicing or monolithizing a completed wafer into individual semiconductor dies and packaging those dies for structural support, electrical interconnection, and environmental isolation. To monolithize a semiconductor die, the wafer is scribed and broken along non-functional regions of the wafer called scribe lines or kerfs. The wafer is monolithized using a laser cutting tool or saw blade. After monolithization, the individual semiconductor dies are mounted onto a package substrate, which includes pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor die are then connected to contact pads within the package. Electrical connections can be made using conductive layers, bumps, column bumps, conductive paste, bonding wires, or other suitable interconnect structures. Encapsulant or other molding compounds are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, making the functionality of the semiconductor device available for other system components.

[0005] Figure 1aA semiconductor wafer 100 is shown having a substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor materials. A plurality of semiconductor dies or components 104 are formed on the wafer 100, separated by passive, inter-die wafer regions or cleavages 106 as described above. The cleavage 106 provides dicing regions to monolithize the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0006] Figure 1b A cross-sectional view of a portion of semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or passive surface 108 and an active surface 110, the active surface 110 containing analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within or on the die and electrically interconnected, depending on the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as digital signal processors (DSPs), ASICs, MEMS, memory, or other signal processing circuitry. Semiconductor dies 104 may also include integrated passive devices (IPDs) for RF signal processing, such as inductors, capacitors, and resistors. The back surface 108 of semiconductor wafer 100 may undergo optional back-grinding operations, utilizing mechanical grinding or etching processes to remove a portion of the substrate material 102 and reduce the thickness of semiconductor wafer 100 and semiconductor die 104.

[0007] A conductive layer 112 is formed on the active surface 110 using PVD, CVD, electrolytic plating, chemical plating, or other suitable metal deposition processes. The conductive layer 112 may comprise one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as contact pads for circuitry electrically connected to the active surface 110.

[0008] Conductive bump material is deposited on conductive layer 112 using evaporation, electrolytic plating, electroless plating, droplet plating, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, or combinations thereof, with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 112 using suitable adhesion or bonding processes. In one embodiment, the bump material is reflowed by heating it above its melting point to form conductive balls or bumps 114. Conductive bumps 114 are optionally formed on an under-bump metallization (UBM) layer having a wetting layer, a barrier layer, and an adhesive layer. Conductive bumps 114 can also be compression bonded or thermo-pressed bonded to conductive layer 112. Conductive bumps 114 represent a type of interconnect structure that can be formed on conductive layer 112 to electrically connect to a substrate. Interconnect structures can also use bonding wires, conductive paste, cylindrical bumps, microbumps, or other electrical interconnects.

[0009] exist Figure 1c In this process, a saw blade or laser cutting tool 118 is used to monolithize the semiconductor wafer 100 into individual semiconductor dies 104 through cuts 106. Individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies (KGD) after monolithization.

[0010] As more and more components are integrated onto a single semiconductor die 104, the die's thermal budget must be increased. To handle the additional heat generated, a heat sink is added to the semiconductor die during packaging. Figure 2 A semiconductor package 130 with a heat sink 132 is shown. To package the semiconductor die 104, the semiconductor die is picked up and placed onto a substrate 134. Bumps 114 are reflowed onto the substrate 134 for mechanical and electrical coupling.

[0011] A heat sink 132 is disposed on the semiconductor die 104 as a cover. The heat sink 132 is made of steel, copper, or another thermally conductive material. The heat sink 132 is mechanically attached to the substrate 134 using an adhesive. A thermal interface material (TIM) 136 is disposed between the heat sink 132 and the back surface 108 of the die 104.

[0012] The TIM 136 provides a fairly good thermal connection between the back surface 108 and the surface of the heatsink 132. However, heat transfer from the die 104 to the heatsink 132 is limited by the thermal resistance from the die to the TIM 136 and then from the TIM to the heatsink. The use of the TIM 136 also increases manufacturing complexity and material costs. Furthermore, due to the requirement of a thick metal layer on the die 104, the heatsink 132 undesirably increases the height of the package 130.

[0013] Therefore, there is a need for a semiconductor device with improved thermal properties and a method for manufacturing the semiconductor device. Attached Figure Description

[0014] Figures 1a-1c This illustrates a semiconductor wafer having multiple semiconductor dies separated by cleavage.

[0015] Figure 2 A semiconductor package with a heat sink cover is shown;

[0016] Figures 3a-3j This illustrates the formation of a semiconductor package with an open heatsink design.

[0017] Figure 4 This illustrates an open heatsink design with cavities to accommodate underlying components.

[0018] Figure 5 This illustrates a multi-package module formed using an open heatsink design.

[0019] Figure 6 This shows a semi-etched open heatsink design;

[0020] Figure 7 Showing multi-die packaging; and

[0021] Figure 8a and 8b This illustrates the integration of a heat sink package into an electronic device. Detailed Implementation

[0022] In the following description, the invention is described in one or more embodiments with reference to the accompanying drawings, in which the same numerals denote the same or similar elements. While the invention is described according to the best mode for carrying out its objectives, those skilled in the art will understand that the invention is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents supported by the following disclosure and the accompanying drawings. The term “semiconductor die” as used herein refers to both the singular and plural forms of the word, and therefore may refer to both a single semiconductor device and multiple semiconductor devices. The terms “die” and “semiconductor die” are used interchangeably.

[0023] Figures 3a-3j This illustrates a semiconductor package having an open heat sink 200. Figure 3a A cross-sectional view of the radiator 200 is shown, while Figure 3bThis is a plan view. The heat sink 200 is a solid sheet of thermally conductive material having an opening 202 that completely passes through the heat sink between the bottom surface 220 and the top surface 222. The material of the heat sink 200 is copper, steel, carbon fiber, or any other suitable material. The heat sink 200 can be made from a large sheet of material by laser, water, or sawing to form the opening 202 and separate individual heat sinks from the sheet. In other embodiments, the heat sink 200 is processed as part of a large sheet having multiple openings 202 adapted to simultaneously form multiple packages before the heat sink is monolithically packaged as part of a finished package.

[0024] Figure 3c A cross-sectional view is shown of a heat sink 200 disposed around a semiconductor die 104 on a substrate 212. The substrate 212 is provided to be large enough to form a panel of a desired number of packages together. Each individual package may extend a significant distance beyond the footprint of the heat sink 200, but only the portion with the heat sink is shown. The heat sink 200 is provided to absorb heat from the semiconductor die 104, but it is not required that other components of the heat sink be disposed around the substrate 212.

[0025] The substrate 212 includes one or more insulating layers 214 interleaved with one or more conductive layers 216. In one embodiment, the insulating layer 214 is a core insulating plate having conductive layers 216 patterned on a top and bottom surface, such as a copper-clad laminate substrate. The conductive layers 216 also include conductive vias electrically coupled through the insulating layers 214 for vertical interconnection.

[0026] Substrate 212 may include any number of conductive layers 216 and insulating layers 214 interleaved with each other. A solder mask or passivation layer may be formed on either or both sides of substrate 212. Openings are formed in the passivation layer to expose contact pads of the conductive layers 216 for subsequent interconnection. In other embodiments, any suitable type of substrate or leadframe may be used for substrate 212. Typically, packages are formed on substrate 212 as panels or strips large enough to simultaneously form several to hundreds or thousands of packages.

[0027] Any components required for the electrical function are mounted or disposed on substrate 212 and electrically connected to conductive layer 216 using solder, solder paste, bonding wire, or other suitable interconnect structures. Semiconductor die 104 is mounted to substrate 212 by using, for example, pick-and-place processes or machines to place the semiconductor die onto the substrate and then reflowing bumps 114 to physically and electrically connect the bumps to exposed contact pads of conductive layer 216. Optionally, underfill 218 is disposed between semiconductor die 104 and substrate 212. Underfill 218 may be disposed on semiconductor die 104, substrate 212, or both prior to mounting the semiconductor die. Alternatively, after the die is mounted to substrate 212, molded underfill 218 may be dispensed under semiconductor die 104 using capillary action.

[0028] exist Figure 3d The diagram shows a heat sink 200 mounted around a semiconductor die 104. The bottom surface 220 of the heat sink 200 is configured to physically contact the top surface of a substrate 212. An adhesive layer is typically provided between the heat sink 200 and the substrate 212 to bond the heat sink to the substrate. The thickness of the heat sink 200 should be chosen such that the top surface 222 of the heat sink is at approximately the same height on the substrate 212 as the back surface 108 of the semiconductor die 104. The back surface 108 and the top surface 222 should be approximately coplanar. The heights of the semiconductor die 104 and the heat sink 200 may differ, but making their top surfaces coplanar will improve performance and reliability.

[0029] In the plan view, the size of opening 202 is determined to be slightly larger than semiconductor die 104. Semiconductor die 104 is fully fitted within opening 202. Once installed, heat sink 200 extends entirely around semiconductor die 104. The gap 224 between die 104 and heat sink 200 should be just large enough that the heat sink can be placed flat on substrate 200 without interference from underfill 218. There is no minimum or maximum size for gap 224, but a smaller gap will likely improve performance. The total length and width of heat sink 200 can be any suitable value. A larger heat sink 200 will allow greater heat absorption from semiconductor 104.

[0030] The gap 224 is filled with thermally conductive material to provide a pathway for the release of heat energy from the semiconductor die 104 to the heat sink 200. Figure 3e-3g Three different options for filling gap 224 are shown.

[0031] exist Figure 3eIn this process, thermally conductive adhesive 230 is dispensed into gap 224. Adhesive 230 can be a curable epoxy resin or a silicone-based adhesive, such as polydimethylsiloxane. The volume of adhesive 230 is controlled to fill gap 224 such that the top surface 232 of the adhesive is coplanar with the heat sink 200 and the semiconductor die 104. In another embodiment, gap 224 is overfilled with adhesive 230 and then back-ground downwards to ensure coplanarity. The semiconductor die 104 and the heat sink 200 may also be back-ground together with adhesive 230 to ensure that all three surfaces 108, 222, and 232 are coplanar.

[0032] exist Figure 3f In this configuration, a pre-formed elastomeric plug 240 is disposed within the gap 224 as an alternative to adhesive 230. The plug 240 is shaped to be the same as or similar to the gap 224, for example, a hollow square having an inner periphery approximately the same size as the die 104 and an outer periphery approximately the same size as the opening 202. In one embodiment, the plug 240 is slightly larger than the gap 224, such that the plug is slightly compressed and its sides press against the sides of the semiconductor die 104 and the heat sink 200. The plug 240 may have one or more beveled surfaces, making it easier for the bottom of the plug to enter the gap, while the top applies more pressure against the die 104 and the heat sink 200. A narrower bottom may also help the plug 240 accommodate the protrusions of the bottom filler 218 into the gap 224. The plug 240 is pressed into the gap 224 using a plate 242 until the plate contacts the heat sink 200 and the die 104 so that the top surface of the plug is substantially coplanar with the top surfaces of the semiconductor die and the heat sink. In one embodiment, an adhesive similar to adhesive 230 is applied to the gap 224 before the plug 240 is installed to improve the retention of the plug in the gap.

[0033] exist Figure 3g In this process, before the heat sink 200 is disposed onto the substrate 212, adhesive 250 is applied around the semiconductor die 104. Adhesive 250 can be any suitable thermally conductive adhesive, such as those discussed above with respect to adhesive 230. Adhesive 250 is applied to the substrate 212 around the semiconductor die 104, thereby covering the exposed portion of the underfill 218 and also contacting the side surfaces of the semiconductor die.

[0034] The heat sink 200 is positioned downwards around the semiconductor die 104, which displaces some of the adhesive 250 and shapes the adhesive to fit the gap 224. Taking into account that some adhesive is pressed between the bottom surface of the heat sink 200 and the top surface of the substrate 212, the volume of the dispensed adhesive 250 is controlled to substantially fill the gap 224. If necessary, additional adhesive can be dispensed after the heat sink 200 is installed to completely fill the gap 224.

[0035] Figure 3h The gap 224 is shown as fully filled. Although it can be used from... Figure 3e-3g Any method may be used, but adhesive 230 is shown as an example. Using any of the methods described above, the result is that the gap 224 is filled with a thermally conductive material and the substantially flat top surface 260 of the encapsulation includes the semiconductor die 104, the heat sink 200, and the surface of the thermally conductive material disposed in the gap 224. Adhesive 230 or 250 is cured as needed. The plug 240 may be cured if it is only partially cured before insertion into the gap 224 or if additional adhesive used to hold it in the plug requires curing.

[0036] exist Figure 3i In this process, conductive material is sputtered onto surface 260 to form a conductive layer 264. The conductive layer 264 is formed using any suitable metal deposition technique, such as chemical vapor deposition, physical vapor deposition, other sputtering methods, spraying, or electroplating. The sputtering material can be copper, steel, aluminum, gold, combinations thereof, or any other suitable conductive material. In some embodiments, the conductive layer 264 can be formed by sputtering multiple layers of different materials, such as stainless steel-copper-stainless steel or titanium-copper.

[0037] An optional mask 266 is used to prevent conductive material 264 from sputtering onto the substrate 212 surrounding the heat sink 200. In another embodiment, the heat sink 200 is formed and processed as a sheet having a plurality of heat sink units attached to each other. No mask 266 is required because there are no gaps between the units in the heat sink 200. After packaging is complete, the heat sink 200 is monolithized together with the substrate 212, and the heat sink 200 terminates in the same coverage area as the resulting semiconductor package.

[0038] Figure 3j The completed package 270 is shown, wherein bumps 272 are formed on the bottom of substrate 212 in a manner similar to forming bumps 114 on semiconductor die 104. Semiconductor die 104 is electrically coupled to bumps 272 through substrate 212. Conductive layer 264 physically contacts both semiconductor die 104 and heat sink 200. Conductive layer 264 increases heat transfer from semiconductor die 104 to heat sink 200 and presents the resulting package with a uniform, flat upper surface similar to, but thinner than, heat sink 132 in the prior art. Compared to the prior art, the overall package thickness is reduced by having conductive layer 264 formed directly on the back surface 108 of semiconductor die 104 instead of having both a TIM layer and a thicker heat sink on the semiconductor die. Having conductive layer 264 directly sputtered on semiconductor die 104 also contributes to thermal conductivity by eliminating TIM in the thermal path to the heat sink.

[0039] Figure 4 A semiconductor package 280 using an alternative design with heat sink 282 is shown. Heat sink 282 includes one or more cavities 284 to allow components on substrate 212 to protrude into the heat sink. Passive device 286 and subpackage 288 are disposed in two separate cavities 284 within heat sink 282. Any desired electrical component can be mounted on substrate 212 and has a corresponding cavity 284 formed in heat sink 282. Any number of cavities 284 can be formed, and any number of components can be disposed within each individual cavity. Package 280 is further formed in substantially the same manner as described above for package 270.

[0040] Figure 5 A semiconductor package 290 with a heat sink 292 is shown. Package 290 is a multi-chip module (MCM) or multi-package module (MPM). In addition to the semiconductor die 104 being disposed within the opening 202, one or more other sub-packages or bare dies 294 are disposed beneath the heat sink 292. The heat sink 292 is fabricated with a large cavity beneath the heat sink, similar to a conventional cover but with the added opening 202 formed for the semiconductor die 104. Any number and type of electrical components can be disposed beneath the heat sink 292.

[0041] The area beneath heatsink 292 can be just large enough for the components within that area, or the entire heatsink can form a large cavity. A gap 224 is formed between subpackage 294 and semiconductor die 104. Adhesive 230, or one of other thermally conductive filler options, helps transfer heat from subpackage 294 to heatsink 292. Thermally conductive adhesive or thermal interface material (TIM) can be disposed between other surfaces of subpackage 294 and cap 292.

[0042] The heat sink 292 with a cap shape factor can be used without any other semiconductor package or die positioned beneath it. Adhesive 230 is applied in sufficient quantity against the side surface of die 104 to extend to the heat sink 292 without being held in place by sub-package 294. Alternatively, plug 240 or pre-dispensed adhesive 250 can be used.

[0043] Figure 6 A package 295 with a heat sink 296 is shown. The heat sink 296 is etched to approximately half its height around the opening 202. This half-etching creates a gap 298 between the substrate 212 and the heat sink 296 around the die 104. The gap 298 allows more of the adhesive 250 applied before the heat sink 296 is placed onto the substrate 212 to remain below the heat sink and reduces the amount extruded on top of the heat sink.

[0044] Figure 7An embodiment with two dies 104 and a single heatsink 200 is shown. Two openings 202 are formed: one opening for each die 104. The gap 224 between the two openings 202 is filled with adhesive 230 or another thermally conductive material, as described above. The gap 224 can be filled together or one at a time. In another embodiment, the openings 202 are formed large enough to accommodate two dies 104. In this case, the gap 224 extends between the two dies 104, but the heatsink 200 does not extend between the dies. Any number of dies can be disposed within a single heatsink 200. A conductive layer 264 is sputtered onto the back surfaces 108 of the two dies 104 and extends continuously from the back surface 222 of the heatsink 200 to both dies.

[0045] Figure 8a and 8b The above-described package (e.g., package 270 with heat sink 200) is shown to be incorporated into electronic device 300. Figure 8a A partial cross-section of a package 270, mounted as part of an electronic device 300 onto a printed circuit board (PCB) or other substrate 302, is shown. Bumps 272 are routed back onto a conductive layer 304 of the PCB 302 to physically attach and electrically connect the package 270 to the PCB. In other embodiments, thermoforming or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between the package 270 and the PCB 302. A semiconductor die 104 is electrically coupled to the conductive layer 304 via a substrate 212 and bumps 272.

[0046] Figure 8b An electronic device 300 is shown having multiple semiconductor packages (including package 270) mounted on a surface of PCB 302. The electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages, depending on the application. The electronic device 300 may be a standalone system using semiconductor packages to perform one or more electrical functions. Alternatively, the electronic device 300 may be a sub-component of a larger system. For example, the electronic device 300 may be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. The electronic device 300 may also be a graphics card, network interface card, or another signal processing card inserted into a computer. Semiconductor packages may include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, and other semiconductor dies or electrical components.

[0047] exist Figure 8bIn this PCB 302, a general substrate is provided for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed on the surface of PCB 302 or within layers of PCB 302 using evaporation, electroplating, chemical plating, screen printing, or other suitable metal deposition processes. Signal traces 304 provide electrical communication between the semiconductor package, mounted components, and other external systems or components. Trace 304 also provides power and ground connections to the semiconductor package as needed.

[0048] In some embodiments, the semiconductor device has two packaging levels. The first-level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second-level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB 302. In other embodiments, the semiconductor device may have only a first-level package, wherein the die is directly mechanically and electrically mounted to the PCB 302.

[0049] For illustrative purposes, several types of first-level packages are shown on PCB 302, including wire bond package 306 and flip chip 308. Additionally, several types of second-level packages mounted on PCB 302 together with package 270 are shown, including ball grid array (BGA) 310, bump chip carrier (BCC) 312, contact grid array (LGA) 316, multi-chip module (MCM) 318, quad flat no-lead (QFN) package 320, quad flat package 322, and eWLB 324. Conductive traces 304 electrically couple the various packages and components disposed on PCB 302 to package 270, thereby enabling the use of components within package 270 to other components on the PCB.

[0050] Depending on system requirements, any combination of semiconductor packages configured with any combination of first and second level package styles, along with other electronic components, can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less likely to fail and are less expensive to manufacture, resulting in lower costs for consumers.

[0051] While one or more embodiments of the invention have been shown in detail, those skilled in the art will understand that modifications and adaptations to those embodiments may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Provide substrate; A heat sink is provided, the heat sink including an opening formed through the heat sink, a semi-etched portion formed around the opening on a first side of the heat sink, and a top surface opposite the semi-etched portion; A semiconductor die is disposed on the substrate; Multiple solder bumps are reflowed between the top surfaces of the semiconductor die and the substrate to mount the semiconductor die onto the substrate; The heat sink is disposed on the substrate, wherein the semiconductor die is located in the opening, wherein the half-etched portion creates a gap between the heat sink and the substrate around the semiconductor die, wherein the heat sink physically contacts the top surface of the substrate around the gap, and wherein the top surface of the heat sink is coplanar with the back surface of the semiconductor die directly above the half-etched portion. A thermally conductive material is disposed in the opening between the heat sink and the semiconductor die, wherein the thermally conductive material is a pre-formed elastomeric plug, and wherein, before the pre-formed elastomeric plug is disposed in the opening, the bottom of the pre-formed elastomeric plug includes a sloped surface; and The substrate and heat sink are monolithically integrated.

2. The method according to claim 1 further includes forming a conductive layer on the substrate, the heat sink, and the thermally conductive material.

3. The method of claim 1, further comprising configuring the thermally conductive material such that the surface of the thermally conductive material is substantially coplanar with the surface of the semiconductor die and the surface of the heat sink.

4. The method according to claim 1, further comprising: A semiconductor package is disposed on the substrate; as well as The heat sink is mounted on the semiconductor package.

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