A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof. The method comprises: providing a substrate, the substrate comprising a first region and a second region, a plurality of discrete active regions being formed in the substrate at the first region; forming a stack material layer on the substrate, the stack material layer comprising a dielectric layer and a first semiconductor layer distributed from bottom to top; performing an etching process to remove part of the stack material layer and part of the substrate to form at least one recess on the first region, the recess exposing part of the active regions; forming a second semiconductor layer, the second semiconductor layer filling at least part of the recess, and an upper surface of the second semiconductor layer being not lower than a lower surface of the first semiconductor layer; and performing a planarization process to remove the first semiconductor layer and part of the second semiconductor layer at the first region and the second region, so that an upper surface of the remaining second semiconductor layer is flush with an upper surface of the dielectric layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor structure and the semiconductor structure. BACKGROUND

[0002] With the development and progress of technology, semiconductor devices are constantly developing towards miniaturization and high integration. Dynamic random access memory (DRAM) as an important semiconductor device can be used as data storage or program storage for electronic devices during operation to perform data processing. However, in the actual application process of dynamic random access memory, there is often a problem of low reliability. SUMMARY

[0003] Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, comprising:

[0004] providing a substrate, the substrate comprising a first region and a second region, a plurality of discrete active regions being formed in the substrate in the first region; forming a stack material layer on the substrate, the stack material layer comprising a dielectric layer and a first semiconductor layer distributed from bottom to top;

[0005] performing an etching process to remove part of the stack material layer and part of the substrate to form at least one recess on the first region, the recess exposing part of the active region;

[0006] forming a second semiconductor layer, the second semiconductor layer filling at least part of the recess, and an upper surface of the second semiconductor layer being not lower than a lower surface of the first semiconductor layer;

[0007] performing a planarization process to remove the first semiconductor layer and part of the second semiconductor layer in the first region and the second region, so that the upper surface of the remaining second semiconductor layer is flush with the upper surface of the dielectric layer.

[0008] In some embodiments, before performing the etching process, the method further comprises:

[0009] forming a first insulating layer on the stack material layer, the first insulating layer covering the first region and the second region of the substrate;

[0010] performing an etching process, comprising:

[0011] performing an etching process to remove part of the first insulating layer in the first region, part of the stack material layer, and part of the substrate to form the recess.

[0012] In some embodiments, forming the second semiconductor layer comprises:

[0013] forming a semiconductor material layer, the semiconductor material layer filling the recess and covering the first region and the second region of the substrate;

[0014] performing a chemical mechanical polishing process to remove the semiconductor material layer in the second region and to make the upper surface of the semiconductor material layer in the first region flush with the upper surface of the first insulating layer;

[0015] performing an etch-back process on the remaining semiconductor material layer to form the second semiconductor layer, the upper surface of the second semiconductor layer being lower than the upper surface of the first insulating layer while the upper surface of the second semiconductor layer is not lower than the lower surface of the first semiconductor layer.

[0016] In some embodiments, after forming the second semiconductor layer and before performing the planarization process, the method further comprises:

[0017] removing the first insulating layer in the first region and the second region to expose the first semiconductor layer and the second semiconductor layer in the first region and to expose the first semiconductor layer in the second region.

[0018] In some embodiments, after removing the first insulating layer and before performing the planarization process, the method further comprises:

[0019] performing a planarization process to remove the first semiconductor layer in the first region, part of the second semiconductor layer, and the first semiconductor layer in the second region so that the upper surface of the second semiconductor layer is flush with the upper surface of the dielectric layer.

[0020] In some embodiments, forming a stack material layer on the substrate comprises:

[0021] forming a first dielectric layer, the first dielectric layer covering the first region and the second region of the substrate;

[0022] forming a second dielectric layer, the second dielectric layer covering the first dielectric layer;

[0023] forming a first semiconductor layer, the first semiconductor layer covering the second dielectric layer;

[0024] performing the planarization process comprises:

[0025] performing the planarization process to remove the first semiconductor layer in the first region and the second region and part of the second semiconductor layer so that the upper surface of the remaining second semiconductor layer is flush with the upper surface of the second dielectric layer.

[0026] In some embodiments, after performing the planarization process, the preparation method further comprises:

[0027] forming a second insulating layer covering the first region and the second region;

[0028] forming a first mask layer covering the first region;

[0029] removing the second insulating layer and the second dielectric layer in the second region to expose the first dielectric layer in the second region, with the first mask layer as a mask;

[0030] removing the first mask layer.

[0031] In some embodiments, after removing the first mask layer, the preparation method further comprises:

[0032] forming a third semiconductor layer covering the first region and the second region of the substrate;

[0033] forming a second mask layer covering the second region;

[0034] removing the third semiconductor layer and the second insulating layer in the first region to expose the second semiconductor layer in the first region and the second dielectric layer between the second semiconductor layers, with the second mask layer as a mask.

[0035] In some embodiments, after removing the third semiconductor layer and the second insulating layer in the first region to expose the second semiconductor layer in the first region and the second dielectric layer between the second semiconductor layers, the preparation method further comprises:

[0036] removing the second mask layer to expose the third semiconductor layer in the second region.

[0037] In some embodiments, the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are made of the same material.

[0038] In some embodiments, the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are made of polysilicon.

[0039] In some embodiments, after removing the second mask layer, the preparation method further comprises:

[0040] forming a bit line material layer on the second semiconductor layer and covering the first region of the substrate;

[0041] performing an etching process to form one or more bit line structures on the second semiconductor layer.

[0042] In some embodiments, after removing the second mask layer, the preparation method further comprises:

[0043] forming a bit line material layer on the second semiconductor layer and covering the first region and the second region of the substrate;

[0044] performing an etching process on the bit line material layer to form one or more bit line structures on the second semiconductor layer while forming an initial gate structure on the second region;

[0045] performing an etching process on the third semiconductor layer to form a gate structure on the second region.

[0046] In some embodiments, before forming the bit line material layer, the method further comprises:

[0047] performing a doping process on the second semiconductor layer and the third semiconductor layer, the doping process comprising an ion implantation process and an annealing process.

[0048] The embodiments of the present disclosure also provide a semiconductor structure prepared by the method of any of the above embodiments.

[0049] The preparation method of the semiconductor structure provided by the embodiments of the present disclosure comprises the following steps: providing a substrate, wherein the substrate comprises a first region and a second region, and a plurality of discrete active regions are formed in the substrate in the first region; forming a stack material layer on the substrate, wherein the stack material layer comprises a dielectric layer and a first semiconductor layer distributed from bottom to top; performing an etching process to remove part of the stack material layer and part of the substrate, so as to form at least one groove on the first region, and the groove exposes part of the active regions; forming a second semiconductor layer, wherein the second semiconductor layer at least fills part of the groove, and the upper surface of the second semiconductor layer is not lower than the lower surface of the first semiconductor layer; and performing a planarization process to remove the first semiconductor layer and part of the second semiconductor layer in the first region and the second region, so that the upper surface of the remaining second semiconductor layer is flush with the upper surface of the dielectric layer. It can be understood that the remaining second semiconductor layer can be used as a bit line plug of the semiconductor structure in actual use, the bottom of the bit line plug is used for connecting the active region, and the upper part of the bit line plug can be used for connecting a subsequently formed bit line structure. In the embodiments of the present disclosure, at the initial stage of the planarization process, the first semiconductor layer and the second semiconductor layer can form a partition between the process operation interface and the dielectric layer, so as to prevent damage to the dielectric layer during the process. In addition, at the later stage of the planarization process, that is, at the last stage of removing the first semiconductor layer and part of the second semiconductor layer, since the materials of the two semiconductor layers and the dielectric layer are different, the grinding liquid and other materials used during the process are also not easy to damage the dielectric layer located below the first semiconductor layer, so as not to affect the performance of the dielectric layer in actual application, for example, when the subsequently formed bit line structure passes through the vicinity of the active region in which other conductive structures (for example, storage node plugs) are formed, it is not easy to cause a short circuit phenomenon between the bit line structure and the active regions. Therefore, the preparation method provided by the embodiments of the present disclosure can greatly improve the reliability of the finally formed semiconductor structure.

[0050] The details of one or more embodiments of the present disclosure are presented in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without creative labor.

[0052] Figure 1 The flowchart of the preparation method of the semiconductor structure provided by the embodiments of the present disclosure is shown in the figure.

[0053] Figures 2 to 17 A process flow chart of the semiconductor structure provided by the embodiments of the present disclosure in a preparation process is shown. DETAILED DESCRIPTION

[0054] Exemplary embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0055] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily complicate this disclosure. In addition, it is to be understood that the terminology used herein is for the purpose of describing the particular embodiments only and is not intended to be limiting.

[0056] In the drawings, the size of layers, regions, elements, and the relative sizes of the same can be exaggerated for clarity. Like reference numbers and characters in the figures indicate like elements throughout.

[0057] It will be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected" or "directly coupled" to another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

[0058] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0060] In the structure of dynamic random memory (DRAM), a bit line contact structure is an important component, one end of which is connected with an active region in a substrate, and the other end is connected with a bit line structure. However, in the actual preparation process of the bit line contact structure, the dielectric layer between the bit line contact structures is easy to be damaged, and the damaged dielectric layer is easy to expose the active region below. If the setting position of the subsequently formed bit line structure is located near the exposed active region, a short circuit phenomenon is easy to occur between the two, thereby reducing the reliability of the semiconductor structure.

[0061] Based on this, the following technical scheme of the embodiment of the disclosure is proposed:

[0062] The embodiment of the disclosure provides a preparation method of a semiconductor structure, as shown in the figure, the preparation method comprises the following steps: Figure 1 As shown in the figure, the preparation method comprises the following steps:

[0063] Step S101: providing a substrate, the substrate comprising a first region and a second region, a plurality of discrete active regions are formed in the substrate in the first region; a stack material layer is formed on the substrate, the stack material layer comprising a dielectric layer and a first semiconductor layer distributed from bottom to top;

[0064] Step S102: performing an etching process to remove part of the stack material layer and part of the substrate to form at least one recess on the first region, the recess exposing part of the active region;

[0065] Step S103: forming a second semiconductor layer, the second semiconductor layer filling at least part of the recess, and the upper surface of the second semiconductor layer being not lower than the lower surface of the first semiconductor layer;

[0066] Step S104: performing a planarization process to remove the first semiconductor layer and part of the second semiconductor layer on the first region and the second region, so that the upper surface of the remaining second semiconductor layer is flush with the upper surface of the dielectric layer.

[0067] It can be understood that the remaining second semiconductor layer can be used as a bit line plug of the semiconductor structure in actual use, the bottom of which is used to connect the active region, and the upper part of which can be used to connect the subsequently formed bit line structure. In the embodiment of the present disclosure, at the initial stage of performing the planarization process, the first semiconductor layer and the second semiconductor layer can form a partition between the process operation interface and the dielectric layer, preventing damage to the dielectric layer during the process. In addition, at the later stage of performing the planarization process, that is, in the last stage of removing the first semiconductor layer and part of the second semiconductor layer, since the materials of the two semiconductor layers and the dielectric layer are different, the grinding liquid and other materials used during the process are also not easy to damage the dielectric layer located below the first semiconductor layer, so as not to affect the performance of the dielectric layer in actual application, for example, when the subsequently formed bit line structure passes through the vicinity of the active region where other conductive structures (such as storage node plugs) are formed, it is not easy to cause a short circuit phenomenon between the bit line structure and the active region. Therefore, the preparation method provided by the embodiment of the present disclosure can greatly improve the reliability of the finally formed semiconductor structure.

[0068] In order to make the above objectives, characteristics and advantages of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure will be described in detail below with reference to the drawings. In the detailed description of the embodiments of the present disclosure, the schematic diagram will be partially enlarged without the general proportion for the convenience of description, and the schematic diagram is only an example, which should not limit the protection scope of the present disclosure herein.

[0069] Figure 1 The flow chart of the preparation method of the semiconductor structure provided by the embodiment of the present disclosure is shown in the figure;

[0070] Figures 2 to 17 The process flow chart of the semiconductor structure provided by the embodiment of the present disclosure in the preparation process is shown in the figure.

[0071] Firstly, step S101 is performed, for example, Figure 2 and Figure 3As shown, a substrate 10 is provided, the substrate 10 includes a first region 21 and a second region 22, a plurality of discrete active regions 11 are formed in the substrate 10 at the first region 21; a stack material layer is formed on the substrate 10, the stack material layer includes a dielectric layer 12 and a first semiconductor layer 131 distributed from bottom to top.

[0072] It can be understood that, in actual process, the first region 21 can be used as an array region of semiconductor structure, and the second region 22 can be used as a peripheral region of semiconductor structure.

[0073] In some embodiments, the substrate 10 further includes an isolation structure STI, the isolation structure STI isolates the substrate into a plurality of active regions 11.

[0074] Here, the substrate can be a semiconductor substrate; the material of the semiconductor substrate specifically includes elemental semiconductor material (for example, silicon (Si) substrate, germanium (Ge) substrate, etc.), or III-V compound semiconductor material (for example, gallium nitride (GaN) substrate, gallium arsenide (GaAs) substrate, indium phosphide (InP) substrate, etc.), or II-VI compound semiconductor material, or organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon substrate.

[0075] In some embodiments, the material of the isolation structure STI includes but is not limited to at least one of oxide, nitride, and oxynitride, or a combination thereof. In some specific embodiments, the material of the isolation structure STI can be a composite layer composed of silicon oxide, silicon nitride, and silicon oxide. However, it is not limited to this, and in actual process, the isolation structure STI can also be other materials, which can be flexibly selected according to actual situation, and is not particularly limited here.

[0076] In actual process, as shown in FIG. 2, a stack material layer is formed on the substrate, including: Figure 3

[0077] A first dielectric layer L1 is formed, the first dielectric layer L1 covers the first region 21 and the second region 22 of the substrate 10;

[0078] A second dielectric layer L2 is formed, the second dielectric layer L2 covers the first dielectric layer L1;

[0079] A first semiconductor layer 131 is formed, the first semiconductor layer 131 covers the second dielectric layer L2.

[0080] Optionally, the material of the first dielectric layer L1 includes but is not limited to silicon oxide, and the material of the second dielectric layer L2 includes but is not limited to silicon nitride.

[0081] ​Understandably, on the one hand, the dielectric layer 12 can provide electrical isolation between the active region 11 and other structures to be formed subsequently, which can be structures located above but not in direct contact with the active region 11. On the other hand, the second dielectric layer L2 included in the dielectric layer 12 can also be used as a barrier layer for the subsequent planarization process.

[0082] In practice, the dielectric layer can be formed using one or more thin film deposition processes; specifically, the thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof.

[0083] Next, proceed to step S102, as follows: Figure 5 As shown, an etching process is performed to remove part of the stacked material layer and part of the substrate 10 to form at least one groove T on the first region 21, the groove T exposing part of the active region 11.

[0084] In some embodiments, such as Figure 4 and Figure 5 As shown, the preparation method further includes the following steps before performing the etching process:

[0085] A first insulating layer 151 is formed on the stacked material layer, and the first insulating layer 151 covers the first region 21 and the second region 22 of the substrate 10.

[0086] Performing the etching process includes:

[0087] An etching process is performed to remove a portion of the first insulating layer 151, a portion of the stacked material layer, and a portion of the substrate 10 located in the first region 21 to form a groove T.

[0088] Understandably, the first insulating layer formed covers the first semiconductor layer. During the etching process, the presence of the first insulating layer can protect the morphology of the first semiconductor layer from being damaged, creating favorable conditions for the smooth execution of the subsequent planarization process.

[0089] Here, the material of the first insulating layer can be an insulating material, such as silicon oxide. Understandably, the formation process of the first insulating layer can be the same as or different from that of the dielectric layer; no specific limitations are made here.

[0090] Optionally, the etching process for forming the groove T can be one or a combination of dry etching process, wet etching process, or other methods.

[0091] Next, proceed to step S103, as follows: Figures 6 to 8As shown, the second semiconductor layer 132 is formed to fill at least part of the trench T, and the upper surface of the second semiconductor layer 132 is not lower than the lower surface of the first semiconductor layer 131.

[0092] Here, the materials of the first semiconductor layer and the second semiconductor layer can be the same or different. In some specific embodiments, the materials of the first semiconductor layer and the second semiconductor layer can each include polysilicon.

[0093] In some embodiments, the second semiconductor layer 132 is formed by:

[0094] The semiconductor material layer 13a is formed to fill the trench T and cover the first region 21 and the second region 22 of the substrate 10 (as shown in Figure 6 );

[0095] A chemical mechanical polishing process is performed to remove the semiconductor material layer 13a located in the second region 22, and to make the upper surface of the semiconductor material layer 13a located in the first region 21 flush with the upper surface of the first insulating layer 151 (as shown in Figure 7 );

[0096] An etch-back process is performed on the remaining semiconductor material layer 13a to form the second semiconductor layer 132, the upper surface of the second semiconductor layer 132 is lower than the upper surface of the first insulating layer 151, and the upper surface of the second semiconductor layer 132 is not lower than the lower surface of the first semiconductor layer 131 (as shown in Figure 8 ).

[0097] Optionally, as shown, after the second semiconductor layer 132 is formed, before the planarization process (step S104) is performed, the preparation method further includes: Figure 9

[0098] The first insulating layer 151 located in the first region 21 and the second region 22 is removed to expose the first semiconductor layer 131 and the second semiconductor layer 132 located in the first region 21, and to expose the first semiconductor layer 131 located in the second region.

[0099] ​In a conventional operation, the material of the first insulating layer and the first dielectric layer both usually includes silicon oxide. In the step of removing the first insulating layer, since no first semiconductor layer is arranged above the second dielectric layer as a partition, the first dielectric layer below the second dielectric layer is easily removed at the same time when the first insulating layer is removed. It can be understood that the second dielectric layer is attached to the first dielectric layer during the process of stacking the material layers. When the first dielectric layer is removed, the second dielectric layer loses the attachment point and is easily separated from the original position, which easily exposes the active regions between the trenches. These active regions can be used as the connection points of the node contact plugs in the subsequent process. At this time, when the subsequently formed bit line structure passes through these active regions, the conductive material such as titanium nitride in the bit line structure easily penetrates into the vicinity of the exposed active regions, causing a short circuit phenomenon, which seriously reduces the yield and reliability of the semiconductor structure in use.

[0100] It can be understood that in the embodiments of the present disclosure, by arranging the upper surface of the second semiconductor layer 132 to be not lower than the lower surface of the first semiconductor layer 131, the first semiconductor layer 131 and the second semiconductor layer 132 can jointly constitute a partition above the dielectric layer 12 after the process step of removing the first insulating layer 151. The partition can generate a partition between the process operation interface and the dielectric layer 12 at the beginning of the planarization process, avoiding damage to the dielectric layer 12 in this process, to ensure the normal play of the isolation function of the dielectric layer 12, effectively prevent the conductive material such as titanium nitride in the subsequently formed bit line structure from penetrating into the active region 11 directly below the dielectric layer 12, thereby avoiding the occurrence of a short circuit phenomenon.

[0101] In actual operation, in some embodiments, the upper surface of the second semiconductor layer 132 can be flush with the upper surface of the first semiconductor layer 131. At this time, at the beginning of the planarization process, the first semiconductor layer 131 and the second semiconductor layer 132 can have a better partition effect, to a greater extent, to avoid damage to the dielectric layer 12, and after the planarization process, the surface of the second semiconductor layer 132 can have a better flatness.

[0102] In the embodiments of the present disclosure, in the case that the dielectric layer has little or no damage, the subsequently formed bit line structure is not easy to cause a short circuit phenomenon between the bit line structure and the active regions provided with other conductive structures (such as storage node plugs) when passing through the vicinity of the active regions. Therefore, the embodiments of the present disclosure can greatly improve the reliability of the finally formed semiconductor structure.

[0103] Finally, step S104 is performed, like Figure 9 and Figure 10As shown, a planarization process is performed to remove the first semiconductor layer 131 and part of the second semiconductor layer 132 in the first region 21 and the second region 22, so that the upper surface of the remaining second semiconductor layer 132 is flush with the upper surface of the dielectric layer 12.

[0104] In actual operation, the second semiconductor layer 132 formed after the planarization process can be used as a bit line plug of a semiconductor structure, one end of which is connected to an active region and the other end can be connected to a bit line structure to be formed later.

[0105] With reference to Figure 9 and Figure 10 , after the first insulating layer 151 is removed, a planarization process is performed, including:

[0106] The planarization process is performed to remove the first semiconductor layer 131 in the first region 21, part of the second semiconductor layer 132, and the first semiconductor layer 131 in the second region 22, so that the upper surface of the second semiconductor layer 132 is flush with the upper surface of the dielectric layer 12.

[0107] In some embodiments, when the dielectric layer 12 includes two parts of the first dielectric layer L1 and the second dielectric layer L2, the planarization process is performed, including:

[0108] The planarization process is performed to remove the first semiconductor layer 131 and part of the second semiconductor layer 132 in the first region 21 and the second region 22, so that the upper surface of the remaining second semiconductor layer 132 is flush with the upper surface of the second dielectric layer L2.

[0109] In the embodiments of the present disclosure, at the initial stage of the planarization process, the first semiconductor layer and the second semiconductor layer can form a partition between the process operation interface and the dielectric layer, preventing damage to the dielectric layer during the process. In addition, at the later stage of the planarization process, i.e., the last stage of removing the first semiconductor layer and part of the second semiconductor layer, since the materials of the two semiconductor layers and the dielectric layer are different, the grinding liquid and other materials used in the process are also less likely to cause damage to the dielectric layer located below the first semiconductor layer. Therefore, the preparation method provided by the embodiments of the present disclosure can obtain a bit line plug structure while reducing or not damaging the dielectric layer, thereby effectively ensuring the normal functioning of the dielectric layer isolation function.

[0110] In a conventional structure, the stacked material layer only includes a dielectric layer structure, and in the absence of the first semiconductor layer, the formation of the second semiconductor layer is usually accompanied by the removal of the first insulating layer at the same time. In this case, since the similar Figure 8In the process of the etch-back step, dry etching is usually used, which is prone to over-etching or under-etching, and is likely to cause the surface of the second semiconductor layer to be higher or lower than the surface of the second dielectric layer. Therefore, after the process of removing the first insulating layer is completed, the upper surface of the second semiconductor layer can be protruding or lower than the upper surface of the second dielectric layer, which is likely to cause the same material layer in the bit line structure to have a height difference at different positions of the substrate when the bit line structure is subsequently formed on the basis of the structure, and the structure consistency of the bit line structure is poor at different positions, which affects the function in use and can adversely affect the stability and reliability of the device.

[0111] In the embodiments of the present disclosure, the second semiconductor layer as a bit line plug is obtained by performing a planarization process due to the presence of the first semiconductor layer. Since the first semiconductor layer and the second semiconductor layer are of the same material, the removal selectivity of the material is the same when the planarization process is performed, and the process controllability is good. Therefore, after the planarization process is performed, the upper surface of the remaining second semiconductor layer can be flush with the upper surface of the second dielectric layer.

[0112] It can be understood that when the bit line structure is subsequently formed on the basis of the structure, the same material layer in the obtained bit line structure will not have a height difference at different positions of the substrate, and the obtained bit line structure has good consistency at different positions, which effectively improves the stability and reliability of the semiconductor structure.

[0113] In summary, it can be seen that the preparation method provided by the embodiments of the present disclosure not only prevents damage to the dielectric layer to prevent short circuiting, but also provides favorable conditions for obtaining a bit line structure that does not have a height difference at different positions and has high structural consistency. Therefore, the preparation method of the embodiments of the present disclosure can effectively improve the stability and reliability of the semiconductor structure.

[0114] In actual operation, after the planarization process step is performed, other operations can also be performed on the obtained semiconductor structure.

[0115] For example, in some embodiments, as shown in FIGS. 1A and 1B, after the planarization process is performed, the preparation method further includes: Figure 11 and Figure 12 as shown in FIGS. 1A and 1B, after the planarization process is performed, the preparation method further includes:

[0116] forming a second insulating layer 152 covering the first region 21 and the second region 22;

[0117] forming a first mask layer M1 covering the first region 21;

[0118] The second insulating layer 152 and the second dielectric layer L2 in the second region 22 are removed by taking the first mask layer M1 as a mask, so as to expose the first dielectric layer L1 in the second region 22.

[0119] The first mask layer M1 is removed.

[0120] Here, the material of the second insulating layer includes but is not limited to insulating materials such as silicon oxide and the like. Optionally, the forming process of the second insulating layer includes but is not limited to atomic layer deposition process.

[0121] But not limited to this, the forming process of the second insulating layer can also be other thin film deposition processes, which are not specifically limited here.

[0122] Compared with the conventional structure in which the second dielectric layer in the second region is removed first and then the bit line plug in the first region is formed, the embodiment of the present disclosure adopts the way of forming the bit line plug first and then removing the second dielectric layer in the second region. This way of temporarily retaining the second dielectric layer in the second region during the process of forming the bit line plug makes the height difference between the upper surfaces of the first region and the second region almost zero or only a very small size. In this case, no matter whether it is located at the middle position or the edge position of the first region, the surface of the obtained bit line plug and the surface of the dielectric layer between the bit line plugs have better height consistency, so that the subsequent formed bit line structure can have better surface flatness and structural consistency to a great extent.

[0123] In some embodiments, as shown in FIGS. 1A and 1B, after the first mask layer M1 is removed, the preparation method further includes: Figure 13 and Figure 14 As shown in FIGS. 1A and 1B, after the first mask layer M1 is removed, the preparation method further includes:

[0124] The third semiconductor layer 133 is formed, covering the first region 21 and the second region 22 of the substrate 10.

[0125] The second mask layer M2 covering the second region 22 is formed.

[0126] The third semiconductor layer 133 and the second insulating layer 152 in the first region 21 are removed by taking the second mask layer M2 as a mask, so as to expose the second semiconductor layer 132 in the first region 21 and the second dielectric layer L2 between the second semiconductor layers 132.

[0127] It can be understood that in actual processes, the materials of the first semiconductor layer 131, the second semiconductor layer 132 and the third semiconductor layer 133 can be the same.

[0128] In some specific embodiments, the materials of the first semiconductor layer 131, the second semiconductor layer 132 and the third semiconductor layer 133 include polysilicon.

[0129] Here, in Figure 14 the structure shown, the third semiconductor layer 133 located in the second region 22 can be used as part of the gate structure in the transistor structure subsequently formed in the peripheral region.

[0130] Optionally, as Figure 14 shown, after removing the third semiconductor layer 133 and the second insulating layer 152 located in the first region 21 to expose the second semiconductor layer 132 and the second dielectric layer L2 located between the second semiconductor layers 132, the preparation method further comprises:

[0131] removing the second mask layer M2 to expose the third semiconductor layer 133 located in the second region 22.

[0132] In actual operation, after removing the second mask layer, other steps can also be continued to obtain more structures. For example:

[0133] In some embodiments of the present disclosure, as Figure 15 and Figure 16 shown, after removing the second mask layer M2, the preparation method further comprises:

[0134] forming a bit line material layer 14a, the bit line material layer 14a being located on the second semiconductor layer 132 and covering the first region 21 of the substrate 10;

[0135] performing an etching process to form one or more bit line structures 14 on the second semiconductor layer 132.

[0136] Here, the bit line structure 14 can extend along a first direction, the first direction being parallel to the plane of the substrate.

[0137] In actual process, the bit line material 14a can be multi-layered, for example, the bit line material layer can include a transition metal nitride material layer (not labeled in the figure), a metal material layer (not labeled in the figure) and a cap material layer (not labeled in the figure) distributed from bottom to top. Similarly, after performing the etching process, the bit line structure 14 after performing the etching process can also include multi-layers, for example, including a transition metal layer 141, a metal layer 142 and a cap layer 143 distributed from bottom to top.

[0138] Optionally, in some embodiments, the material of the transition metal layer includes but is not limited to titanium nitride and the like, the material of the metal layer includes but is not limited to tungsten and the like, and the material of the cap layer includes but is not limited to silicon nitride and the like. However, this is not limited, and in some other embodiments, each material layer included in the bit line structure can also be composed of other suitable materials, which is not specifically limited here and can be flexibly selected according to actual conditions.

[0139] Continuing to refer toFigure 15 and Figure 16 As shown in FIG. 1 1, in some embodiments of the present disclosure, while forming the bit line structure on the first region, other structures can also be obtained on the second region. For example, after removing the second mask layer M2, the preparation method further comprises:

[0140] forming a bit line material layer 14a on the second semiconductor layer 132 and covering the first region 21 and the second region 22 of the substrate 10;

[0141] performing an etching process on the bit line material layer 14a to form one or more bit line structures 14 on the second semiconductor layer 132 while forming an initial gate structure 161a on the second region;

[0142] performing an etching process on the third semiconductor layer 133 to form the gate structure 161 on the second region 22.

[0143] Here, the bit line structure 14 can extend along a first direction, which is parallel to the plane of the substrate.

[0144] In this embodiment, the material and the layers of the bit line structure 14 can be the same as or different from those in the previous embodiment, which can be flexibly selected according to actual conditions and is not specifically limited here.

[0145] Optionally, after forming the gate structure, a doping process can also be performed on the substrate 10 located on both sides of the gate structure 161 to obtain a first source / drain region 162 and a second source / drain region 163. Here, the gate structure 161 can constitute a transistor structure of the peripheral region together with the first source / drain region 161 and the second source / drain region 162.

[0146] Optionally, in some embodiments, before forming the bit line material layer 14a, the method further comprises:

[0147] performing a doping process on the second semiconductor layer 132 and the third semiconductor layer 133, the doping process comprising an ion implantation process and an annealing process.

[0148] Here, the doping type used when performing the doping process at least includes at least one of N-type doping or P-type doping. When the doping type is N-type doping, the dopant atoms used in the ion implantation process include but are not limited to at least one of phosphorus (P), arsenic (As), antimony (Sb), or other N-type dopants, or a combination thereof. When the doping type is P-type doping, the dopant atoms used in the ion implantation process include but are not limited to at least one of boron, indium, other P-type dopants, or a combination thereof. The conductivity of the material can be significantly improved by performing the doping process, and the power consumption of the finally formed semiconductor structure can be reduced.

[0149] The semiconductor structure is manufactured by the method provided in any of the above embodiments.

[0150] In some embodiments, as shown in Figure 17 The semiconductor structure comprises:

[0151] The substrate 10 comprises a first region 21 and a second region 22, and a plurality of active regions 11 are arranged in the substrate 10 in the first region 21;

[0152] A groove structure (not labeled in the figure) is arranged on the partial active regions 11, and the groove structure is filled with a second semiconductor layer 132;

[0153] A dielectric layer 12 is arranged between the second semiconductor layers 132, and the upper surface of the second semiconductor layer 132 is flush with the upper surface of the dielectric layer 12.

[0154] In some embodiments, the semiconductor structure further comprises a bit line structure 14 arranged on the second semiconductor layer 132, and the bit line structure 14 extends along a first direction, and the first direction is parallel to the plane of the substrate 10.

[0155] In the semiconductor structure of the embodiments of the present disclosure, the dielectric layer has a small damage, which can prevent the phenomenon of short circuit between the active region 11 located directly below the dielectric layer 12 and other structures (such as the bit line structure 14) passing directly above the dielectric layer 12 in the semiconductor structure. In addition, since the upper surface of the second semiconductor layer 132 is flush with the upper surface of the dielectric layer 12, the bit line structure 14 arranged on the base structure can obtain better consistency, effectively improving the stability and reliability of the semiconductor structure.

[0156] In summary, it can be seen that the semiconductor structure provided in the embodiments of the present disclosure has high stability and reliability.

[0157] It should be noted that the semiconductor device manufacturing method provided in the embodiments of the present disclosure can be applied to any semiconductor structure or other semiconductor device comprising the structure, which is not limited herein. The embodiments of the semiconductor device manufacturing method provided by the present disclosure belong to the same concept as the embodiments of the semiconductor device; the technical features in the technical solutions described in each embodiment can be combined arbitrarily without conflict.

[0158] The above is only a preferred embodiment of the present disclosure, and is not intended to limit the protection scope of the present disclosure. Any modification, equivalent replacement and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The preparation method comprises: providing a substrate comprising a first region and a second region, a plurality of discrete active regions being formed in the substrate at the first region; forming a stack material layer on the substrate, the stack material layer comprising a dielectric layer and a first semiconductor layer distributed from bottom to top; performing an etching process to remove part of the stack material layer and part of the substrate to form at least one recess on the first region, the recess exposing part of the active regions; forming a second semiconductor layer, the second semiconductor layer filling at least part of the recess, and an upper surface of the second semiconductor layer being not lower than a lower surface of the first semiconductor layer; 2. The production method according to claim 1, characterized by, performing a planarization process to remove the first semiconductor layer and part of the second semiconductor layer at the first region and the second region, so that an upper surface of the remaining second semiconductor layer is flush with an upper surface of the dielectric layer. Before performing the etching process, the preparation method further comprises: forming a first insulating layer on the stack material layer, the first insulating layer covering the first region and the second region of the substrate; performing an etching process, comprising:

3. The production method according to claim 2, characterized by, performing an etching process to remove part of the first insulating layer at the first region, part of the stack material layer, and part of the substrate to form the recess. forming the second semiconductor layer, comprising: forming a semiconductor material layer, the semiconductor material layer filling the recess and covering the first region and the second region of the substrate; performing a chemical mechanical polishing process to remove the semiconductor material layer at the second region, and to make an upper surface of the semiconductor material layer at the first region flush with an upper surface of the first insulating layer; 4. The production method according to claim 3, characterized by, performing a re-etching process on the remaining semiconductor material layer to form the second semiconductor layer, an upper surface of the second semiconductor layer being lower than an upper surface of the first insulating layer, while the upper surface of the second semiconductor layer being not lower than the lower surface of the first semiconductor layer. After forming the second semiconductor layer and before performing the planarization process, the preparation method further comprises:

5. The production method according to claim 4, characterized by, removing the first insulating layer at the first region and the second region to expose the first semiconductor layer and the second semiconductor layer at the first region, and to expose the first semiconductor layer at the second region. After removing the first insulating layer and performing the planarization process, comprising:

6. The production method according to any one of claims 1 to 5, characterized by, performing a planarization process to remove the first semiconductor layer at the first region, part of the second semiconductor layer, and the first semiconductor layer at the second region, so that an upper surface of the second semiconductor layer is flush with an upper surface of the dielectric layer. forming the stack material layer on the substrate, comprising: forming a first dielectric layer, the first dielectric layer covering the first region and the second region of the substrate; forming a second dielectric layer, the second dielectric layer covering the first dielectric layer; forming a first semiconductor layer, the first semiconductor layer covering the second dielectric layer; performing the planarization process, comprising: performing the planarization process to remove the first semiconductor layer and part of the second semiconductor layer in the first region and the second region, so that an upper surface of the remaining second semiconductor layer is flush with an upper surface of the second dielectric layer.

7. The production method according to claim 6, wherein After performing the planarization process, the preparation method further comprises: forming a second insulating layer covering the first region and the second region; forming a first mask layer covering the first region; removing the second insulating layer and the second dielectric layer in the second region to expose the first dielectric layer in the second region, with the first mask layer as a mask; removing the first mask layer.

8. The preparation method according to claim 7, characterized in that, After removing the first mask layer, the preparation method further comprises: forming a third semiconductor layer covering the first region and the second region of the substrate; forming a second mask layer covering the second region; removing the third semiconductor layer and the second insulating layer in the first region to expose the second semiconductor layer in the first region and the second dielectric layer between the second semiconductor layers, with the second mask layer as a mask.

9. The preparation method according to claim 8, characterized in that, After removing the third semiconductor layer and the second insulating layer in the first region to expose the second semiconductor layer in the first region and the second dielectric layer between the second semiconductor layers, the preparation method further comprises: removing the second mask layer to expose the third semiconductor layer in the second region.

10. The method of claim 9, wherein, The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are made of the same material.

11. The method of claim 10, wherein, The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are made of polysilicon.

12. The method of claim 9, wherein, After removing the second mask layer, the preparation method further comprises: forming a bit line material layer on the second semiconductor layer and covering the first region of the substrate; performing an etching process to form one or more bit line structures on the second semiconductor layer.

13. The preparation method according to claim 9, characterized in that, After removing the second mask layer, the preparation method further comprises: forming a bit line material layer on the second semiconductor layer and covering the first region and the second region of the substrate; performing an etching process on the bit line material layer to form one or more bit line structures on the second semiconductor layer and form an initial gate structure on the second region; performing an etching process on the third semiconductor layer to form a gate structure on the second region.

14. The production method according to claim 12 or 13, characterized by, Before forming the bit line material layer, the method further comprises: performing a doping process on the second semiconductor layer and the third semiconductor layer, the doping process comprising an ion implantation process and an annealing process.

15. A semiconductor structure, characterized by The semiconductor structure is made by the method of any one of claims 1-14.

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