Semiconductor package with integrated and shielded inductor

Abstract

An integrated circuit (IC) package has a ferrite-dielectric shield layer between a planar inductor coil and a semiconductor chip. The shield layer blocks electromagnetic interference (EMI) generated by current in the inductor coil from reaching the semiconductor chip. The shield layer has a ferrite layer surrounded by upper and lower dielectric layers to prevent electrical shorting. A center terminal of the inductor coil is connected to the semiconductor chip through a center post that passes through an opening in the shield layer over the center of the inductor coil air core. The center post can be connected to a chip mount pad on which the semiconductor chip is mounted. Wire bonds connect pads on the semiconductor chip to lead frame pads on lead frame posts whose distal ends are external package connectors. The outer terminals of the inductor coil are connected to lead frame outer posts that also have external package connectors, such as pins or solder balls.

Description

TECHNICAL FIELD

[0001] The present invention relates to semiconductor-inductor packages, and more particularly to a package that shields a semiconductor chip from an integrated inductor. BACKGROUND

[0002] Semiconductor chips are widely used and are typically packaged in a lead-frame plastic package. Bonding wires are placed between bonding pads on the semiconductor chip and bonding pads on the lead-frame. The lead-frame and chip are then encapsulated in plastic, covering and protecting the bonding wires as well as the chip and lead-frame. The ends of the lead-frame protrude from the plastic, forming pins. An electrical path is formed from the pins, through the lead-frame to the lead-frame pads, through the bonding wires to the chip pads.

[0003] While transistors, resistors, and capacitors can be easily integrated into a semiconductor chip using techniques such as complementary metal-oxide semiconductor (CMOS) processes, inductors cannot be integrated because they are too small or too large in area.

[0004] So external inductors are typically used. A metal core inductor is typically formed by wrapping a metal wire around a metal core multiple times. An air core inductor has a lower inductance than a metal core inductor, but is easier to manufacture. An air core inductor can be formed from a small, flat spiral coil. Such planar inductors have low energy losses and are useful for high frequency switching, but for some applications (such as power converters) the inductance is too low.

[0005] Such planar air core inductors can be physically integrated with a semiconductor chip, perhaps in a single package. However, the electromagnetic field generated by the inductor coil can induce currents in nearby metal wires. When the inductor is placed near a semiconductor chip, the electromagnetic field can induce unwanted currents in the metal traces of the semiconductor chip. These unwanted currents can interfere with the desired signals and cause the semiconductor chip to not function properly. For higher inductances and coil currents, and for close proximity to the chip, the induced currents in the chip can even damage the chip. Thus, this electromagnetic interference (EMI) generated by the coil prevents integration with the chip in a semiconductor package.

[0006] The package can be made larger so that the semiconductor chip and inductor are spaced far enough apart that the EMI does not harm the semiconductor chip. However, this spacing can be several times the size of the inductor or chip. The package has to be many times larger than desired.

[0007] Multi-chip modules can have integrated inductors, but these modules are many times larger than single-chip packages. Such large modules are costly and take up too much area on the printed circuit board (PCB) on which they are mounted. Certain applications, such as the Internet-of-Things (IoT), are limited in area and cost and cannot use large packages.

[0008] It would be desirable to have a semiconductor package that contains both a semiconductor chip and an inductor. It would be desirable to shield the semiconductor chip from electromagnetic interference generated by the coil. It would also be desirable to increase the inductance of the coil. It would be desirable to add a structure to the semiconductor package that both protects the chip from EMI and increases the inductance of the inductor. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a simplified cross-sectional view of a shielded inductor semiconductor package.

[0010] Figure 2A 、 2B , 2C is a cross-sectional electromagnetic field intensity plot of the shielded inductor semiconductor package of Figure 1

[0011] Figure 3 is a three-dimensional view of a shielded inductor semiconductor package.

[0012] Figure 4 is a three-dimensional view of the shielded inductor semiconductor package of

[0013] Figure 5 is a top view of the shielded inductor semiconductor package of Figure 3

[0014] Figure 6 is a top view of the shielded inductor semiconductor package of Figure 3

[0015] Figure 7 is a cross-sectional view of the shielded inductor semiconductor package mounted to a PCB using surface mount solder balls.

[0016] Figure 8 is another flip-chip shielded inductor semiconductor package with solder balls.

[0017] Figure 9 is a cross-sectional view of another shielded inductor semiconductor package with two coils.

[0018] Figure 10 is a cross-sectional view of another shielded inductor semiconductor package with two coils.​​​

[0019] Figure 11 is a three-dimensional view of a dual-coil shielded inductor semiconductor package.

[0020] Figure 12 is a three-dimensional view of a dual-coil shielded inductor semiconductor package with the top ferrite-dielectric shield removed to better show the inductor coil.

[0021] Figure 13 is a cross-sectional view of another shielded inductor semiconductor package with two coils. DETAILED DESCRIPTION

[0022] The present invention relates to an improvement in semiconductor-inductor packaging. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein can be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments described and shown, but is to be given the widest scope consistent with the principles and novel features disclosed herein.

[0023] Figure 1 is a simplified cross-sectional view of a shielded inductor semiconductor package. Semiconductor chip 30 and inductor coil 10 are integrated together in a package (not shown). Inductor coil 10 has a hollow core 14 in its center and is spiral-shaped, perpendicular to Figure 1 the plane of the page. Although this cross-section shows inductor coil 10 as broken, inductor coil 10 is actually a continuous coil, perpendicular to Figure 1 the plane of the page.

[0024] When current passes through inductor coil 10, an electromagnetic field is generated, which can cause electromagnetic interference (EMI) in semiconductor chip 30. However, top ferrite-dielectric shield 24 is placed over inductor coil 10, between inductor coil 10 and semiconductor chip 30. Top ferrite-dielectric shield 24 contains ferrite layer 12, which is sandwiched between dielectric layers 20 on its top and bottom.

[0025] Ferrite layer 12 is a ceramic layer containing magnetized iron or ferrite metal particles, such as manganese zinc ferrite (MnZn, molecular formula Mn a Zn (1-a) Fe2O4), or nickel zinc ferrite (NiZn, molecular formula Ni a Zn (1-a)Fe2O4). The dielectric layer 20 can be a plastic laminate or other insulator such as FR4 or PI, which are NEMA grade glass-reinforced epoxy laminate materials. FR-4 is a composite material consisting of woven fiberglass cloth and epoxy resin binder with flame retardancy (self-extinguishing). PI is a polyimide, which is a polymer of imide monomers belonging to the class of high-performance plastics. The classic polyimide is Kapton, which is condensed from pyromellitic dianhydride and 4,4'-oxydianiline. The ferrite-dielectric shield layer 24 can be made as a sheet of ferrite layer 12 covered on its top and bottom by dielectric layers 20, which can be cut to size as needed.

[0026] The second shield is provided by the lower ferrite-dielectric shield layer 26 to prevent the electromagnetic field from escaping from the bottom of the inductor coil 10 and possibly bypassing the edges of the upper ferrite-dielectric shield layer 24 to reach the semiconductor chip 30. Since the inductor coil 10 is sandwiched between the upper ferrite-dielectric shield layer 24 and the lower ferrite-dielectric shield layer 26, the electromagnetic field generated by the inductor coil 10 is confined to a small area between the ferrite layer 12 in the upper ferrite-dielectric shield layer 24 and the ferrite layer 12 in the lower ferrite-dielectric shield layer 26.

[0027] This confinement of the electromagnetic field by the ferrite layer 12 also increases the inductance of the inductor coil 10. Even though the inductor coil 10 is an air-core inductor, the presence of the ferrite layer 12 above and below the plane of the inductor coil 10 also increases its inductance because the center of the inductor coil 10 is the air core 14.

[0028] The upper ferrite-dielectric shield layer 24 can be in contact with the top of the inductor coil 10 because the dielectric layer 20 can prevent an electrical short between the inductor coil 10 and the ferrite layer 12. Thus, the ferrite layer 12 can be placed very close to the inductor coil 10. The thickness of the dielectric layer 20 can be only 0.1 mm, so the electromagnetic field can be very tightly confined. This close spacing and confinement of the electromagnetic field can further enhance the inductance of the inductor coil 10. Although an air-core inductor, the inductor coil 10 surrounded by the ferrite-dielectric shield layers 24, 26 can have an appreciable inductance value close to that of a magnetic-core inductor.

[0029] Figure 2A 、 2B 、2C shows Figure 1 the electromagnetic field intensity plot on the cross-section of the shielded inductor semiconductor package. When an alternating current passes through the inductor coil 10, a time-varying electromagnetic field is generated. When the ferrite layer 12 is not present, as shown in Figure 2A , the intensity of this electromagnetic field is as shown inFigure 2C curve 104.

[0030] Figure 2B The presence of the ferrite 12 causes the electromagnetic field to concentrate within the ferrite layer 12 and to drop off rapidly within the dielectric layer 20 surrounding each ferrite layer 12. Figure 2C Curve 102 shows that the drop off in electromagnetic field strength is so rapid that outside the dielectric layer 20 and ferrite layer 12, each 0.1 mm thick, the electromagnetic field is nearly zero. Near the semiconductor chip 30, the electromagnetic field with the ferrite layer 12 shown by curve 102 is much less than the electromagnetic field without the ferrite layer 12 shown by curve 104.

[0031] Although the electromagnetic field spikes within the ferrite layer 12 are large, as shown by curve 102, these spikes provide a lower electromagnetic field strength outside the dielectric layer 20, such as near the surface of the semiconductor chip 30. Thus, EMI at the semiconductor chip 30 is reduced due to the presence of the ferrite layer 12.

[0032] In the simulation, the surface of the semiconductor chip 30 (distance 0.0) at 10 mm from the center of the empty core 14 (z direction of Fig. 2, i.e., perpendicular to the plane of Fig. 2) and 0.1 mm above the top of the ferrite-dielectric shield layer 24, the electromagnetic field strength is 967 μT when the ferrite layer 12 is not present and only 0.523 μT when the ferrite layer 12 is present.

[0033] Thus, the ferrite layer 12 reduces the electromagnetic field seen by the semiconductor chip 30 by a factor of about 2,000.

[0034] Figure 3 Fig. 1 is a three-dimensional view of a shielded inductor semiconductor package. The semiconductor chip 30 is attached to the die attach pad 34, for example by epoxy or other bonding. The wire bonds 42 run between pads on the semiconductor chip 30 and the lead frame pads 40. Some of the wire bonds run from pads on the semiconductor chip 30 to the die attach pad 34.

[0035] The lead frame pads 40, 41 are at the top of the lead frame posts 46, 45, which are connected to the package pins that protrude from the bottom of the package and can fit into holes in a PCB when the package is soldered to the PCB of a larger system. The lead frame posts 46 can be bent or connected to other parts of the lead frame (not shown) that lead to external package pins, solder balls, or other external connectors (not shown).

[0036] The leadframe posts 45, 46 form a rectangle around the semiconductor chip 30, the chip mount pad 34, and the inductor coil 10, which is mostly hidden by the upper ferrite-dielectric shield 24. The inductor coil 10 is covered at the top by the upper ferrite-dielectric shield 24 and at the bottom by the lower ferrite-dielectric shield 26. The area of the inductor coil 10 can be larger than the area of the chip mount pad 34 and the semiconductor chip 30, depending on the inductance value desired.

[0037] Figure 4 is a three-dimensional view of a shielded inductor semiconductor package with the upper ferrite-dielectric shield removed to show the inductor coil. In Figure 4 , the upper ferrite-dielectric shield 24 has been removed. The inductor coil 10 is a planar coil that is wound outward from a center post 36 in the center, which electrically connects the chip mount pad 34 to the center winding of the inductor coil 10. The outermost windings of the inductor coil 10 are connected to the leadframe outer post 45 by coil extension wires 48.

[0038] Most of the pads on the semiconductor chip 30 are electrically connected by wire bonds 42 and leadframe pads 40 to the package leads at the end of the leadframe posts 46. However, three pads on the semiconductor chip 30 are connected by wire bonds to the top surface of the chip mount pad 34. Electrical connections are then made from the top surface of the chip mount pad 34 to the bottom surface of the chip mount pad 34 and to the center post 36. The chip mount pad 34 can be a conductive or metallic trace, and a hole or via on the chip mount pad 34 can make the electrical connection from the semiconductor chip 30 to the center post 36. Thus, an electrical connection is made from the semiconductor chip 30 to the center winding of the inductor coil 10. The outer windings of the inductor coil 10 are connected to the leadframe outer post 45 by coil extension wires 48, which are connected at the top to the leadframe pads 41 and at the bottom to the external package leads. The leadframe pads 41 do not receive wire bonds 42 from the semiconductor chip 30.

[0039] Thus, the inductor coil 10 provides a series inductance between the three pads on the semiconductor chip 30 and the external package leads. When a varying current flows through the inductor coil 10, the resulting electromagnetic field is shielded by the upper ferrite-dielectric shield 24 Figure 3 ) from causing EMI in the semiconductor chip 30.

[0040] Figure 5 is a top view of the shielded inductor semiconductor package of Figure 3 . The semiconductor chip 30 is connected to the top of the chip mount pad 34 and is electrically connected by wire bonds 42 to the leadframe pads 40. In this top view, the leadframe posts 46 are hidden by the leadframe pads 40.

[0041] Most of the inductor coil 10 is shielded and hidden by an upper ferrite-dielectric shielding layer 24 located between the chip mount pad 34 and the inductor coil 10, providing EMI shielding for the semiconductor chip 30. However, a portion of the outer winding of the inductor coil 10 is visible. The end of the outer winding of the inductor coil 10 is connected to the outer post 45 of the lead frame (not shown) via a coil extension wire 48, and then to the lead frame pad 41. The inner winding of the inductor coil 10 is connected to the underside of the chip mount pad 34, and then to the semiconductor chip 30 via bonding wire 43.

[0042] Figure 6 yes Figure 3 A top view of a shielded inductor semiconductor package, with the upper ferrite-dielectric shield removed to reveal the inductor coil. The inductor coil 10 is wound outwards from its center to its outermost winding, which is concealed by the semiconductor chip 30 and chip mount pads 34. The end of the outermost winding of the inductor coil 10 is connected via a coil extension wire 48 to an outer post 45 of the lead frame (not shown), and then to a lead frame pad 41.

[0043] Figure 7 This is a cross-sectional view showing the shielded inductor semiconductor package mounted onto a PCB using surface mount solder balls. The inductor coil 10 is sandwiched between an upper ferrite-dielectric shielding layer 24 and a lower ferrite-dielectric shielding layer 26, forming a flexible, bendable layer. The coil within the inductor coil 10 can move up or down relative to the plane because the inductor coil 10 is not a continuous metal sheet but a coil forming a metal winding. The upper ferrite-dielectric shielding layer 24 and the lower ferrite-dielectric shielding layer 26 each contain a ferrite layer 12 sandwiched between dielectric layers 20. Dielectric layers 20 prevent short circuits between the ferrite layer 12 and the inductor coil 10. Figure 7 The maximum bending or curvature of the inductor coil 10 is shown.

[0044] A semiconductor chip 30 on chip mounting pad 34 is connected to a lead frame pad 40 on top of a lead frame pillar 46 via bonding wire 42. In this embodiment, the top of the lead frame pillar 46 can be used as the lead frame pad 40. The semiconductor chip 30 is mounted on the chip mounting pad 34, which is located above the upper ferrite-dielectric shielding layer 24. The ferrite layer 12 prevents the magnetic flux generated by the inductor coil 10 from reaching the semiconductor chip 30 and causing EMI.

[0045] The bottom of the lead frame pillar 46 is connected to solder balls 60, which may be solder balls formed during heating to bond with surface mount pads on the PCB 62. A plastic encapsulant (not shown) can encapsulate the semiconductor chip 30 and protect the bonding wires 42.

[0046] Figure 8is another flip-chip shielded inductor semiconductor package with solder balls. Semiconductor chip 30 is a surface mount chip that is flipped over and connected to the top of package substrate 35 by solder balls 62. Patterned metal traces on package substrate 35 connect chip solder balls 62 to larger external solder balls 60 that connect the shielded inductor semiconductor package to a system PCB.

[0047] Also in this variant, there are two inductor coils 10, 11 separated by a dielectric layer 21. An upper ferrite-dielectric shield layer 24 shields the top of inductor coil 10, while a lower ferrite-dielectric shield layer 26 shields the bottom of inductor coil 11. The center air core 14 of inductor coil 10 is aligned with the center air core of inductor coil 11. Coil posts 16 connect the outer windings of upper inductor coil 10 and lower inductor coil 11. Coil posts 16 can extend up to package substrate 35, then to solder balls 60 or semiconductor chip 30. Wire bonds 65 can be added to connect one of the chip solder balls 62 on semiconductor chip 30 to a solder ball 60 that connects to a coil post 16 at the outer end of inductor coil 10.

[0048] Figure 9 is a cross-sectional view of a shielded inductor semiconductor package with two coils. In this variant, there are two inductor coils 10, 11 separated by a dielectric layer 21. An upper ferrite-dielectric shield layer 24 shields the top of inductor coil 10, while a lower ferrite-dielectric shield layer 26 shields the bottom of inductor coil 11. The center air core 14 of inductor coil 10 is aligned with the center air core 15 of inductor coil 11. A semiconductor chip 30 (not shown) can be placed above the upper ferrite-dielectric shield layer 24 or below the lower ferrite-dielectric shield layer 26.

[0049] Figure 10 is a cross-sectional view of another shielded inductor semiconductor package with two coils. In this variant, the two inductor coils 10, 11 are separated by an intermediate ferrite-dielectric shield layer 28 that sandwiches a ferrite layer 13 with a dielectric layer 21. In this variant, inductor coil 10 is shielded from inductor coil 11 by ferrite layer 13. In addition, the inductance of inductor coils 10, 11 can be increased by increasing the thickness of ferrite layer 13.

[0050] Figure 11 is a three-dimensional view of a two-coil shielded inductor semiconductor package. In this embodiment, there are two layers of coils, an upper inductor coil 10 (not shown, hidden by upper ferrite-dielectric shield layer 24) and a lower inductor coil 11. There can be a dielectric layer 21 (not shown) between inductor coils 10, 11, as shown in Figure 9 or an intermediate ferrite-dielectric shield layer 28 (not shown), as shown inFigure 10 The spacing between the inductor coils 10, 11 is exaggerated in Figure 11 and 12 but in reality the spacing between the inductor coils 10, 11 would be much closer, as shown in Figure 9-10 Thus, even with two layers of inductor coils 10, 11, a relatively flat, thin package can be achieved.

[0051] The semiconductor chip 30 is attached to the chip mount pad 34, for example by epoxy or other bonding. Wire bonds 42 are routed between pads on the semiconductor chip 30 and the lead frame pads 40. Some wire bonds are routed from pads on the semiconductor chip 30 to the chip mount pad 34.

[0052] The lead frame pads 40 are at the top of lead frame posts 46, which connect to package leads that protrude from the bottom of the package and can be seated in holes in a PCB when soldered to a larger system's PCB. The lead frame posts 45, 46 can be bent or connected to other parts of the lead frame (not shown) that lead to external package leads, solder balls or other external connectors (not shown).

[0053] The lead frame posts 45, 46 form a rectangle around the semiconductor chip 30, the chip mount pad 34 and the inductor coils 10, most of which are hidden from view by the upper ferrite-dielectric shield 24. The top of the upper inductor coil 10 is covered by the upper ferrite-dielectric shield 24.

[0054] Although the upper inductor coil 10 is mostly covered by the upper ferrite-dielectric shield 24, the lower inductor coil 11 is visible. The lower ferrite-dielectric shield 26 is attached to the bottom of the lower inductor coil 11. Coil posts 16 connect the outer windings of the upper inductor coil 10 and the lower inductor coil 11.

[0055] The bottom of the chip mount pad 34 is connected to a center post 36 that passes through a central opening in the upper ferrite-dielectric shield 24 near the air core 14. This opening in the upper ferrite-dielectric shield 24 allows the center post 36 to connect the chip mount pad 34 to the center winding of the inductor coil 10. When the inductor coils 10, 11 are electrically connected in parallel, the center post 36 can extend downward and connect to the center windings of the upper inductor coil 10 and the lower inductor coil 11.

[0056] Figure 12 is a three-dimensional view of a dual coil layer shielded inductor semiconductor package with the upper ferrite-dielectric shield removed to better show the inductor coils. In Figure 12 the inductor coils 10, 11 are shown in cross-section. Figure 11The upper ferrite-dielectric shield 24 has been removed. The inductor coil 10 is a planar coil wound outward from a center post 36 in the center of the coil. The center post 36 electrically connects the die attach pad 34 to the center winding of the inductor coil 10. The outermost winding of the upper inductor coil 10 is connected to the coil post 16 and to the outermost winding of the lower inductor coil 11. The coil post 16 is shorter than the leadframe post 46.

[0057] Most of the pads on the semiconductor chip 30 are electrically connected by wirebonds 42 and leadframe pads 40 to the package pins at the end of the leadframe post 46. However, three pads of the semiconductor chip 30 are connected by wirebonds to the upper surface of the die attach pad 34. Electrical connections are then made from the upper surface of the die attach pad 34 to the lower surface of the die attach pad 34 and to the center post 36.

[0058] Thus, when the center post 36 is extended downward (not shown), electrical connections are made from the semiconductor chip 30 to the center winding of the upper inductor coil 10 and to the center winding of the lower inductor coil 11. The outer windings of the upper inductor coil 10 and the lower inductor coil 11 are connected by coil extension wires 48 to the outer leadframe post 45, which has leadframe pads 41 at the top and is connected to external package pins at the bottom. The leadframe pads 41 do not receive wirebonds 42 from the semiconductor chip 30, but are connected to the inductor coil 10 by the coil extension wires 48. The leadframe pads 41 have no function other than to preserve the symmetry of the package and can be deleted.

[0059] Thus, the upper inductor coil 10 and the lower inductor coil 11 provide a parallel inductance between the three pads of the semiconductor chip 30 and the external package pins. When varying current flows through the inductor coils 10, 11, the resulting electromagnetic fields are shielded by the upper ferrite-dielectric shield 24 Figure 11 ) from causing EMI in the semiconductor chip 30.

[0060] Figure 13 is another cross-sectional view of a shielded inductor semiconductor package with two coils. In this variant, as in the previous variants, the upper inductor coil 10 is a planar coil wound outward from a center post 36 in the center of the coil. The center post 36 electrically connects the die attach pad 34 to the center winding of the inductor coil 10. The outermost winding of the upper inductor coil 10 is connected to the coil post 16 and to the outermost winding of the lower inductor coil 11. The coil post 16 is shorter than the leadframe post 46. Figure 10As such, the two inductors 10, 11 are separated by an intermediate ferrite-dielectric shield 28, which has a dielectric layer 21 sandwiching a ferrite layer 13. In this variant, the air cores 14 and 15 are connected together by a larger hole that extends through the ferrite layers 12, 13 and the dielectric layers 20, 21. Although there is an opening in the ferrite layer 12 through which magnetic flux can leak and cause EMI in the semiconductor die 30, the opening is relatively small and is in the middle of the coil, so the leakage is small. The larger hole provides more room for the connection between the coils 10, 11. The central opening allows the center post 36 to pass through the ferrite layer 12 and the dielectric layer 20 between the semiconductor die 30 and the inductor 10.

[0061]

[0062] The inventor has added several other embodiments. For example, the semiconductor die can be a silicon die, such as a standard CMOS die, or silicon on another substrate, or another material, such as GaAs. There can be more than one semiconductor die 30 and more than one inductor. Other packaging techniques can be used instead, using a lead frame or similar, or being leadless.

[0063] The semiconductor die 30 is an integrated circuit (IC) or a discrete component, such as a MOSFET, and can be of various types, such as complementary metal-oxide-semiconductor (CMOS) or BiCMOS. A typical IC has thousands of transistors that are formed together in a semiconductor material on a substrate, connected by integrated wiring, such as metal traces. A power IC can have larger but fewer transistors, for example, only 10 transistors. The semiconductor die 30 can have power transistors for a power converter, such as a switch-mode power supply (SMPS).

[0064] Although pins and balls have been described for mounting the shielded inductor semiconductor package to a PCB system board, many variations are possible. The pins can be leads, bent leads or bent pins, flat surface mount pads, and can be mounted into holes in the PCB or onto pads on the surface of the PCB.

[0065] Although external package pins have been described as being placed around the perimeter of the shielded inductor semiconductor package, some or all of these pins, balls or connectors can be in a grid or array, such as in a ball grid array (BGA) package.

[0066] Although a plastic package has been described for the package, the shielded inductor semiconductor package can be a ceramic package or a hybrid package. The PCB can be rigid or flexible, and can be some other type of substrate or larger module or support or frame in the system. ​

[0067] Although in Figure 5 the inductor coil 10 is shown extending beyond the upper ferrite-dielectric shield layer 24, the upper ferrite-dielectric shield layer 24 can also completely cover the inductor coil 10. Both the upper ferrite-dielectric shield layer 24 and the lower ferrite-dielectric shield layer 26 can extend beyond the inductor coil 10 and be squeezed or pinched together, in contact with each other, to seal the perimeter edges of the inductor coil 10.

[0068] Although Figure 11 the parallel connection of the inductor coils 10, 11 has been shown, the upper inductor coil 10 and the lower inductor coil 11 can be connected in series using additional leadframe elements or posts to connect the outer winding of the upper inductor coil 10 to the center winding of the lower inductor coil 11. The coil post 16 can then be removed and the outer winding of the lower inductor coil 11 connected to the leadframe outer post 45 for external connection.

[0069] Instead of using the leadframe outer post 45 for external connection from the inductor coil 10, an internal connection is made within the package from the outer winding of the inductor coil 10 back to one of the leadframe posts 46 that does not have an external connection, through a wire bond 42 to a pad on the semiconductor chip 30. Other internal connections are possible.

[0070] The inductor coil 10 is considered to be an air core inductor because the air core 14 in the center of the planar coil has no ferrite, even though the ferrite layers 12 are above and below the plane of the inductor coil 10, adding inductance to the coil like a ferrite core. The center post 36 can be within the air core in the center of the inductor coil 10. Although the center post 36 is connected to the inductor coil 10, it is not considered to be a metal core of the inductor coil 10.

[0071] The inductor coil 10 is a metal coil, connected to the semiconductor chip 30 through the center post 36 and the chip mounting pad 34, and connected to the external package pin through the leadframe outer post 45 on the other end, so the inductor coil 10 can be considered to be part of the package leadframe, along with the leadframe pads 40 and the leadframe posts 46. Thus, the inductor coil 10 is integrated with the package leadframe.

[0072] By using the ferrite layers 12, the EMI generated by the current flowing through the inductor coil 10 and received by the metal traces or other elements on the semiconductor chip 30 is reduced by at least 90%. The electromagnetic flux is blocked by the ferrite layers 12 placed between the inductor coil 10 and the semiconductor chip 30. The dielectric layer 20 prevents the inductor coil 10 from shorting to the semiconductor chip 30 or other conductors.

[0073] The background section of this invention may include background information about the problem or environment of the invention, rather than a description of prior art. Therefore, the material included in the background section is not an admission of prior art by the applicant.

[0074] Any methods or processes described herein are machine-implemented or computer-implemented and are intended to be performed by machines, computers, or other devices, and not necessarily by humans alone without machine assistance. Tangible results may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio generation devices, and related media devices, and may include hard-copy printouts that are also machine-generated. Computer control of other machines is another tangible result.

[0075] Any advantages and benefits described herein may not necessarily apply to all embodiments of the invention. Generally, one or more words preceding the word "device" are a label intended to facilitate reference to the claim elements, not to express structural limitations. Such device-plus-function claims cover not only the structures described herein for performing that function and their structural equivalents, but also equivalent structures. For example, although nails and screws have different constructions, they are equivalent structures because they both perform a fastening function. Signals are typically electronic signals, but can also be optical signals, for example, transmitted via fiber optic lines.

[0076] The above description of embodiments of the invention is provided for illustrative and descriptive purposes. It is not intended to be exhaustive, nor is it intended to limit the invention to the precise forms disclosed. Many modifications and variations are possible based on the above teaching. The purpose is that the scope of the invention is not limited by this detailed description, but rather by the appended claims.

Claims

1. A semiconductor package with an integrated and shielded leadframe inductor, comprising: a semiconductor die having transistors formed in a semiconductor material and integrated wiring integrated on a die substrate; die pads connected to the integrated wiring and formed on a periphery of the die substrate; an inductor coil that is air cored, the inductor coil being a planar inductor, the planar inductor being substantially located in a plane of the inductor coil, the plane of the inductor coil being parallel to a plane of the semiconductor die; an upper ferrite-dielectric shield layer having a ferrite layer and a dielectric layer located above the ferrite layer and a dielectric layer located below the ferrite layer, the inductor coil being electrically isolated from the ferrite layer by the dielectric layer; wherein the upper ferrite-dielectric shield layer is located in a plane parallel to one of the plane of the inductor coil and the plane of the semiconductor die; a plurality of leadframe pads placed at a periphery of the inductor coil and surrounding the semiconductor die; wire bonds connecting the die pads on the semiconductor die to the plurality of leadframe pads; a plurality of leadframe posts connecting the plurality of leadframe pads to package pins for electrical connection to an external system; a center post connected to an inner end of the inductor coil and electrically connected to the semiconductor die; a leadframe outer post connecting an outer end of the inductor coil to a package pin for electrical connection to the external system.

2. The semiconductor package with an integrated and shielded leadframe inductor of claim 1, wherein, at least 90% of electromagnetic flux generated by current flowing through the inductor coil between the inner end and the outer end of the inductor coil is shielded by the ferrite layer from outside the semiconductor die; whereby the ferrite layer reduces electromagnetic interference (EMI) generated by the inductor coil and received by the semiconductor die by at least 90%.

3. The semiconductor package with an integrated and shielded leadframe inductor of claim 2, wherein, the plurality of leadframe posts pass through the plane of the inductor coil outside a periphery of the inductor coil.

4. The semiconductor package with an integrated and shielded leadframe inductor of claim 3, further comprising: a lower ferrite-dielectric shield layer having a ferrite layer and a dielectric layer located above the ferrite layer and a dielectric layer located below the ferrite layer, the inductor coil being electrically isolated from the ferrite layer by the dielectric layer; wherein the lower ferrite-dielectric shield layer is located in a lower plane parallel to and below one of the plane of the inductor coil and the plane of the semiconductor die.

5. The semiconductor package with an integrated and shielded leadframe inductor of claim 4, further comprising: a die attach pad attached to a bottom of the semiconductor die; wherein the center post is electrically connected to the semiconductor die through the die attach pad.

6. The semiconductor package with an integrated and shielded leadframe inductor of claim 5, further comprising: wire bonds from the die pads to the die attach pad to form an electrical connection from the semiconductor die to the die attach pad and through the center post to a center end of the inductor coil.

7. The semiconductor package with an integrated and shielded leadframe inductor of claim 6, wherein, The package pins include solder balls for soldering to pads on a printed circuit board (PCB).

8. The semiconductor package with integrated and shielded leadframe inductor of claim 7, further comprising: a package agent placed around and between the wire bonds and used to encapsulate the semiconductor chip.

9. The semiconductor package with integrated and shielded leadframe inductor of claim 6, wherein the air core is located at a center of the inductor coil, wherein the center post extends through a hole in an upper ferrite-dielectric shield layer above the air core to connect the semiconductor chip to inner ends of the inductor coil, wherein, the inductor coil is an air core inductor.

10. The semiconductor package with integrated and shielded leadframe inductor of claim 9, further comprising: a second inductor coil having an air core, the second inductor coil being a second planar inductor substantially located in a second plane of the second inductor coil, the second plane of the second inductor coil being parallel to the plane of the semiconductor chip; a second dielectric layer for electrically isolating the inductor coil from the second inductor coil, the second dielectric layer being located between the inductor coil and the second inductor coil; wherein the plurality of leadframe pads are placed at a periphery of the second inductor coil.

11. The semiconductor package with integrated and shielded leadframe inductor of claim 10, further comprising: a second upper ferrite-dielectric shield layer having a second ferrite layer and a second dielectric layer located above the second ferrite layer and a third dielectric layer located below the second ferrite layer, the second inductor coil being electrically isolated from the second ferrite layer by the second dielectric layer; wherein the second upper ferrite-dielectric shield layer is located in a plane parallel to a plane between the second plane of the second inductor coil and the plane of the semiconductor chip.

12. The semiconductor package with an integrated and shielded leadframe inductor of claim 11, wherein, the center post further extends downwardly from the inner ends of the inductor coil to inner ends of the second inductor coil; wherein the leadframe outer post further includes a coil post connected to outer ends of the second inductor coil; wherein the inductor coil and the second inductor coil are connected in parallel between the semiconductor chip and the leadframe outer post.

13. A semiconductor-inductor package that shields electromagnetic interference (EMI), comprising: a semiconductor chip having chip pads connected to semiconductor transistors through an interconnect layer that is all integrated on a chip substrate; a chip mount pad to which the semiconductor chip is mounted; an inductor coil located below the chip mount pad; a first ferrite-dielectric shield layer located between the inductor coil and the chip mount pad for shielding the semiconductor chip from electromagnetic interference generated by the inductor coil; wherein the first ferrite-dielectric shield layer includes a ferrite layer between an upper dielectric layer and a lower dielectric layer, the dielectric layers electrically isolating the ferrite layer from the semiconductor chip; an opening in the first ferrite-dielectric shield layer, the opening being located below a chip mount pad, the opening being located above a center void of the inductor coil, the inductor coil having a metal coil that winds from an inner end at the center void to an outer end; lead frame posts located around the inductor coil and the semiconductor chip, each lead frame post having a top pad for receiving a wire bond from a chip pad on the semiconductor chip, each lead frame post having an external connection end for making an electrical connection to an external system; whereby the ferrite layer protects the semiconductor chip from electromagnetic interference generated by the inductor coil.

14. The EMI shielded semiconductor-inductor package of claim 13, further comprising: a center post passing through the opening in the first ferrite-dielectric shield layer to connect the chip mount pad to the inner end of the inductor coil; wherein the chip mount pad further comprises an electrical connection from the semiconductor chip to the center post, whereby the semiconductor chip is electrically connected to the inner end of the inductor coil through the chip mount pad and the center post.

15. The EMI shielded semiconductor-inductor package of claim 14, further comprising: a lead frame outer post connected to the outer end of the inductor coil, the lead frame outer post having an external connection end for making an electrical connection to an external system, whereby the inductor coil is electrically connected between the semiconductor chip and the external connection end of the lead frame outer post.

16. The EMI shielded semiconductor-inductor package of claim 15, further comprising: a second ferrite-dielectric shield layer located below the inductor coil; wherein the second ferrite-dielectric shield layer comprises a ferrite layer between an upper dielectric layer and a lower dielectric layer, the dielectric layers electrically isolating the ferrite layer.

17. The EMI shielded semiconductor-inductor package of claim 13, wherein, the inductor coil is flexible and can be bent out of the plane of the inductor coil.

18. An integrated circuit (IC) package with an integrated and shielded inductor, comprising: an inductor coil having a center void, the inductor coil being a planar inductor located in a coil plane; an upper ferrite-dielectric shield layer located above the inductor coil; a lower ferrite-dielectric shield layer located below the inductor coil; wherein the upper ferrite-dielectric shield layer and the lower ferrite-dielectric shield layer each comprise a ferrite layer surrounded by an upper dielectric layer and a lower dielectric layer; a package substrate for mounting to a semiconductor chip; an external package connector for soldering the IC package to an external printed circuit board (PCB); whereby the ferrite layer protects the semiconductor chip from electromagnetic interference (EMI) generated by current flowing through the inductor coil.

19. The IC package of claim 18, wherein, the external package connector comprises solder balls located on the package substrate for external connection.

20. The IC package of claim 18, wherein, the semiconductor chip is surface mounted to the package substrate.

Images