Semiconductor structure and its formation method

Abstract

This application provides a semiconductor structure and a method for forming the same. The method includes: providing a substrate, the substrate including an array region and a peripheral region; forming a plurality of first insulating structures on the substrate of the array region and forming a second insulating structure on the substrate of the peripheral region; forming a first opening in an adjacent first insulating structure, the first opening exposing the top of the sidewall of the first insulating structure; depositing a sacrificial layer on the sidewall and bottom of the first opening, and simultaneously depositing a sacrificial layer on the second insulating structure; forming a second opening in the second insulating structure and the sacrificial layer of the peripheral region, wherein the second opening exposes the sidewall of the sacrificial layer; forming a protective layer on at least the surface of the sacrificial layer at the top of the sidewall of the first opening and the surface of the sacrificial layer on the sidewall of the second opening; removing the sacrificial layer at the bottom of the first opening; and removing the protective layers of the array region and the peripheral region to form a first contact hole and a second contact hole in the array region and the peripheral region, respectively.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same. Background Technology

[0002] Semiconductor devices, such as Dynamic Random Access Memory (DRAM), typically include an array region and a peripheral region. When a contact plug is formed in the peripheral region after a first opening is formed in the array region, the formation of the contact plug requires the deposition of a photoresist layer, followed by exposure and development to obtain the contact plug. To prevent the material at the bottom of the first opening from affecting the photoresist exposure process, a sacrificial layer is deposited in both the array region and the peripheral region before the photoresist layer is deposited. After the contact plug is formed, the sacrificial layer at the bottom of the first opening is removed. However, since a sacrificial layer also exists at the top of the contact plug, and the insulating structure on the sidewalls of the contact plug may contain the same material as the sacrificial layer, the process of removing the sacrificial layer at the bottom of the first opening also etches away portions of the peripheral region with the same material as the sacrificial layer. This alters the morphology of the final contact plug, thus affecting its electrical performance. Summary of the Invention

[0003] In view of this, embodiments of this application provide a semiconductor structure and a method for forming the same.

[0004] In a first aspect, embodiments of this application provide a method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate including an array region and a peripheral region; forming a plurality of first insulating structures on the substrate in the array region, and forming a second insulating structure on the substrate in the peripheral region; forming a first opening in adjacent first insulating structures, the first opening exposing the top of a sidewall of the first insulating structure; depositing a sacrificial layer on the sidewall and bottom of the first opening, and simultaneously on the second insulating structure; forming a second opening in the second insulating structure and the sacrificial layer in the peripheral region, wherein the second opening exposes the sidewall of the sacrificial layer; forming a protective layer at least on the surface of the sacrificial layer at the top of the sidewall of the first opening and on the surface of the sacrificial layer on the sidewall of the second opening; removing the sacrificial layer at the bottom of the first opening; and removing the protective layers of the array region and the peripheral region to form a first contact hole and a second contact hole in the array region and the peripheral region, respectively.

[0005] In some embodiments, the protective layer includes a carbon layer, and the formation of the protective layer at least on the surface of the sacrificial layer at the top of the first opening sidewall and the surface of the sacrificial layer on the second opening sidewall includes: dissociating fluoromethane gas by an alternating electric field to form the carbon layer at least on the surface of the sacrificial layer at the top of the first opening sidewall and the surface of the sacrificial layer on the second opening sidewall.

[0006] In some embodiments, the first insulating structure includes a sidewall structure for bit lines. A plurality of first insulating structures are formed on the substrate of the array region, including: forming a plurality of sequentially stacked bit line contacts and bit lines on the substrate of the array region; and forming the sidewall structure on both sides of each of the sequentially stacked bit line contacts and bit lines.

[0007] In some embodiments, a plurality of sequentially stacked bit line contacts and bit lines are formed on the substrate of the array region, including: forming a plurality of bit line contact holes and a bit line contact in each bit line contact hole on the substrate of the array region; and sequentially forming a first conductive layer and an insulating capping layer of the bit line on each bit line contact to form a plurality of sequentially stacked bit line contacts and bit lines on the substrate of the array region.

[0008] In some embodiments, forming a first opening in an adjacent first insulating structure includes depositing a storage node contact between adjacent sidewall structures to form the first opening in the adjacent sidewall structures.

[0009] In some embodiments, forming a second insulating structure on the substrate in the peripheral region includes: depositing a second insulating layer on the substrate in the peripheral region; and depositing a third insulating layer on the second insulating layer to form a second insulating structure having a stacked structure.

[0010] In some embodiments, the material of the sacrificial layer is the same as the material of the sidewall structure; the material of the sacrificial layer is the same as the material of the second insulating layer and / or the third insulating layer.

[0011] In some embodiments, the method further includes: depositing a metal layer within the first contact hole to form a contact pad; wherein the contact pad is used to contact the memory node to jointly connect the source or drain of the transistor in the array region to the memory capacitor of the array region.

[0012] In some embodiments, the substrate of the peripheral region includes an active region, and a second opening is formed in the second insulating structure and the sacrificial layer of the peripheral region, comprising: forming an initial first photoresist layer on the sacrificial layer of the peripheral region; patterning the initial first photoresist layer to form a first photoresist layer having a second opening pattern, wherein the sub-pattern containing the second opening is located above the active region; etching the peripheral region using the second opening pattern as a mask to form the second opening in the second insulating structure and the sacrificial layer of the peripheral region, wherein the second opening extends to the active region.

[0013] In some embodiments, the method further includes: sequentially depositing a buffer layer and a second conductive layer within the second contact hole to form a contact plug in the peripheral region.

[0014] In some embodiments, prior to the sequential deposition of the buffer layer and the second conductive layer, an ohmic contact layer is further formed at the bottom of the second contact hole.

[0015] In some embodiments, the material of the portion of the substrate in the peripheral region that contacts the bottom of the second contact hole includes silicon, and the material of the ohmic contact layer includes cobalt silicide. Forming an ohmic contact layer at the bottom of the second contact hole includes: depositing a cobalt layer in the second contact hole; and subjecting the cobalt layer to high-temperature annealing to form a cobalt silicide layer at the bottom of the second contact hole.

[0016] In some embodiments, after forming a cobalt silicide layer at the bottom of the second contact hole, the method further includes: removing any remaining cobalt layer located within the second contact hole.

[0017] In some embodiments, a dry etching process is used to remove the protective layer of the array region and the peripheral region.

[0018] Secondly, embodiments of this application provide a semiconductor structure, which is prepared according to the above-described semiconductor structure formation method.

[0019] In this embodiment, firstly, a substrate is provided, the substrate including an array region and a peripheral region; secondly, a plurality of first insulating structures are formed on the substrate of the array region, and a second insulating structure is formed on the substrate of the peripheral region; thirdly, a first opening is formed in adjacent first insulating structures, exposing the top of the sidewall of the first insulating structure; a sacrificial layer is deposited on the sidewall and bottom of the first opening, and simultaneously on the second insulating structure; then, a second opening is formed in the second insulating structure and the sacrificial layer of the peripheral region; next, a protective layer is formed at least on the surface of the sacrificial layer at the top of the sidewall of the first opening and on the surface of the sacrificial layer on the sidewall of the second opening; finally, the sacrificial layer at the bottom of the first opening and the protective layer of the array region and the peripheral region are removed to form a first contact hole and a second contact hole in the array region and the peripheral region, respectively.

[0020] Since the protective layer is located at least on the surface of the sacrificial layer at the top of the first opening sidewall and on the surface of the sacrificial layer on the second opening sidewall, and the sacrificial layer covers the top of the first opening sidewall and the second opening sidewall, the protective layer also covers the top of the first opening sidewall and the second opening sidewall. Therefore, during the removal of the sacrificial layer located at the bottom of the first opening, the protective layer located on the top of the first opening sidewall and the second opening sidewall can play a protective role, protecting the top of the first opening sidewall and the second opening sidewall beneath the protective layer from being etched or less frequently, thereby reducing the increase in the size of the second opening and improving the integrity of the first insulation structure. Attached Figure Description

[0021] Figure 1A A schematic diagram of the structure obtained by depositing a sacrificial layer after forming a first opening in the array region in the related technology provided in the embodiments of this application;

[0022] Figure 1B A schematic diagram of the structure obtained after removing the sacrificial layer located at the bottom of the first opening in the related technology provided in the embodiments of this application;

[0023] Figure 1C Provided for the embodiments of this application Figure 1A Enlarged view of region B in the middle;

[0024] Figure 1D Provided for the embodiments of this application Figure 1B Enlarged view of region B in the middle;

[0025] Figure 2A A schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this application;

[0026] Figures 2B to 2L This is a schematic diagram of the semiconductor structure formation method provided in the embodiments of this application;

[0027] Figure 3A schematic diagram of the structure obtained by forming a contact pad in the first contact hole according to an embodiment of this application;

[0028] Figures 4A to 4E This is a schematic diagram illustrating a process of forming a contact plug in a second contact hole, as provided in an embodiment of this application. Detailed Implementation

[0029] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0030] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0031] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0034] Figure 1A This is a schematic diagram of a structure obtained by depositing a sacrificial layer after forming a first opening in the array region (the opening formed after filling the storage node contact 101 within the storage node contact hole, not shown in the figure) in related technologies. Figure 1A As can be seen, the sacrificial layer 102 covers the sidewall structure 104 of the bit line of the array region 10a, the storage node contact 101, and the second insulating structure 302 of the peripheral region 10b. Figure 1B This is a schematic diagram of the structure obtained after removing the sacrificial layer located at the bottom of the first opening in the related technology. Figure 1B It can be seen that after the sacrificial layer at the bottom of the first opening is removed, a portion of the sidewall structure 104 of the bit line and the part of the peripheral area that is the same material as the sacrificial layer will also be etched away, thereby increasing the size of the contact plug hole 304 finally formed in the peripheral area and making the sidewall structure of the bit line incomplete.

[0035] To more clearly illustrate the phenomenon that the contact plug hole 304 ultimately formed in the peripheral area increases after the sacrificial layer located at the bottom of the first opening is removed. Figure 1C and Figure 1D They were displayed respectively Figure 1A and Figure 1B A magnified view of region B in the middle section. (Comparison) Figure 1C and Figure 1D It can be seen that Figure 1D The final size of the contact plug hole 304 formed in the process is significantly larger than that of the contact plug hole 304. Figure 1C The initial contact plug hole 301 in the first opening is sized accordingly. Therefore, after removing the sacrificial layer located at the bottom of the first opening, the final contact plug hole 304 formed in the peripheral region is larger.

[0036] Based on this, embodiments of this application provide a method for forming a semiconductor structure, such as... Figure 2A As shown, the method includes the following steps S101 to S108:

[0037] Step S101: Provide a substrate, which includes an array region and a peripheral region;

[0038] Here, the substrate can be single-layered, such as a silicon (Si) substrate, germanium (Ge) substrate, silicon germanium (SiGe) substrate, gallium arsenide substrate, ceramic substrate, quartz substrate, or glass substrate used for displays; or it can be multi-layered, such as a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate. Shallow trench isolation (STI) can also be formed within the single-layer or multi-layered substrate, isolating several active regions arranged in an array or other distribution type within the substrate. STI is formed by forming trenches within the substrate and then filling the trenches with an isolation material layer. The filling material in STI can include silicon nitride or silicon oxide, with silicon oxide formed by thermal oxidation.

[0039] The array region is the core area of ​​the semiconductor device, used for storing data. The peripheral region is the control area of ​​the memory, used to control the writing and reading of data in the array region. The substrate includes both the array region and the peripheral region; that is, the substrate includes the substrate for the array region and the substrate for the peripheral region.

[0040] Figure 2B The provided schematic diagram shows a substrate 10, which includes spaced-apart isolation regions 1012 and active regions 1011. The active regions 1011 are used to form active devices, and the isolation regions 1012 are used to isolate the active regions 1011 from each other. The substrate 10 includes an array region 10a and a peripheral region 10b.

[0041] Step S102: Form a plurality of first insulating structures on the substrate of the array region and form a second insulating structure on the substrate of the peripheral region;

[0042] Here, the multiple first insulating structures can be arranged at intervals. In some embodiments, the first insulating structure can be a sidewall structure of a bit line, and the sidewall structures are arranged at intervals. This application does not limit the type of first insulating structure.

[0043] The second insulating structure can be a multilayer structure formed on the substrate of the peripheral region, such as a silicon oxide layer and a silicon nitride layer stacked sequentially; or it can be a single-layer structure, such as a silicon nitride layer. The number of layers of the second insulating structure is not limited in the embodiments of this application.

[0044] Figure 2C A schematic diagram of a structure obtained by forming multiple first and second insulating structures on a substrate is shown, wherein the first insulating structure is exemplified by the sidewall structure of a bit line. It can be seen that the sidewall structures 104 of the bit line are arranged at intervals, and the second insulating structure 302 includes a second insulating layer 302b and a third insulating layer 302a stacked sequentially.

[0045] Correspondingly, the implementation of "forming a second insulating structure on the substrate of the peripheral region" in step S102 may include the following steps S1021a and S1022a:

[0046] Step S1021a: Deposit a second insulating layer on the substrate of the peripheral region;

[0047] like Figure 2C As shown, step S1021a can be implemented by depositing a second insulating layer 302b on the substrate 10b in the peripheral region. The deposition process can include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any other suitable deposition process. The deposited material can be silicon oxide.

[0048] In some embodiments, other insulating layers may be deposited before depositing the second insulating layer on the substrate to adjust the height and electrical insulation of the second insulating structure; however, this application does not limit this.

[0049] Step S1022a: A third insulating layer is deposited on the second insulating layer to form a second insulating structure with a stacked structure.

[0050] like Figure 2C As shown, the third insulating layer 302a is an insulating layer deposited on the second insulating layer 302b. The deposition process used for the third insulating layer can be the same as or different from that used for the second insulating layer, and the material of the third insulating layer can be silicon nitride.

[0051] Step S103: Form a first opening in an adjacent first insulating structure, the first opening exposing the top of the sidewall of the first insulating structure;

[0052] Here, since the first insulating structures are arranged at intervals, there is an opening between adjacent first insulating structures, which exposes the entire sidewall of the first insulating structure. Correspondingly, step S103 can be implemented by filling the opening between adjacent first insulating structures with a material, the height of which is at least sufficient to expose the top of the sidewall of the first insulating structure. After filling with the material, the opening formed above the filling material in the adjacent first insulating structure is the first opening. The material of the filling material affects the exposure process of the photoresist layer deposited when forming contact plug holes on the second insulating structure; for example, the material of the filling material can be polysilicon. This application embodiment does not limit the material of the filling material.

[0053] When the first insulation structure includes the sidewall structure of the bit line, the implementation of step S103 may include the following step S1031:

[0054] Step S1031: Deposit storage node contacts between adjacent sidewall structures to form a first opening in the adjacent sidewall structures.

[0055] Here, step S1031 can be implemented by depositing storage node contacts between adjacent sidewall structures using a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any other suitable deposition process. The material of the storage node contacts may include polycrystalline silicon.

[0056] Figure 2D This is a schematic diagram of the structure formed after the deposition storage nodes come into contact, resulting in the first opening. (Example:) Figure 2D As shown, after the memory node contacts 101 are filled between the sidewall structures 104 of adjacent bit lines, the sidewall structures 104 of the bit lines and the memory node contacts 101 together form a first opening 103. The first opening 103 is located above the memory node contacts 101.

[0057] Step S104: Deposit a sacrificial layer on the sidewalls and bottom of the first opening, and simultaneously on the second insulating structure;

[0058] Here, the sacrificial layer is used to isolate the photoresist deposited during the formation of the contact plug hole on the second insulating structure in the peripheral region. Since the photoresist layer is directly deposited on the filler material at the bottom of the first opening, light reflected off the filler material surface can expose areas that do not need exposure. To reduce this problem, a sacrificial layer is deposited on the sidewalls and bottom of the first opening, as well as on the second insulating structure, and then a photoresist layer is deposited on the surface of the sacrificial layer. Since the sacrificial layer can be made of silicon nitride, it can reduce light reflection, thereby reducing the occurrence of exposure of areas that do not need exposure and preventing the filler material from affecting the photoresist exposure process. In some embodiments, the thickness of the sacrificial layer can range from 1 to 3 nanometers (nm) to facilitate process implementation while reducing costs.

[0059] like Figure 1A As shown, the sacrificial layer 102 is located at the first opening (see...). Figure 2D The sacrificial layer is located on the sidewalls and bottom of the bit line, and is also located on the second insulating structure 302. In some embodiments, the sacrificial layer may also be located on top of the sidewall structure 104 of the bit line.

[0060] In some embodiments, the material of the sacrificial layer is the same as that of the first insulating structure (e.g., the sidewall structure); the material of the sacrificial layer is also the same as that of the second and / or third insulating layers. This results in some materials of the first and second insulating structures being etched during the subsequent removal of the sacrificial layer at the bottom of the first opening, leading to incompleteness of the first insulating structure and an enlarged contact plug hole formed in the second insulating structure.

[0061] Step S105: A second opening is formed in the second insulation structure and sacrificial layer of the peripheral region, wherein the second opening exposes the sidewall of the sacrificial layer;

[0062] Here, the second opening is used to form the contact plug in the outer perimeter area, that is... Figure 1A The initial contact plug hole in the middle.

[0063] like Figure 1A As shown, the second opening 301 is located in the second insulating structure 302 and the sacrificial layer 102 of the peripheral region 10b, and the second opening 301 exposes the sidewall of the sacrificial layer 102.

[0064] In some embodiments, the implementation of step S105 may include the following steps S1051 to S1053:

[0065] Step S1051: Form an initial first photoresist layer on the sacrificial layer in the peripheral region;

[0066] Here, photoresists can be divided into positive photoresists and negative photoresists according to their polarity. The difference is that the exposed area of ​​a negative photoresist hardens and is retained after exposure and development, while the unexposed part is dissolved by the developer; after exposure, the colloidal polymer in the exposed area of ​​a positive photoresist will break and soften due to photodissolution and eventually be dissolved by the developer, while the unexposed part is retained. The polarity of the photoresist is not limited in the embodiments of this application.

[0067] Step S1052: Pattern the initial first photoresist layer to form a first photoresist layer with a second opening pattern, wherein the sub-pattern containing the second opening is located above the active region.

[0068] Here, patterning the initial first photoresist layer refers to exposing and developing the initial first photoresist layer, wherein a portion of the initial first photoresist layer is dissolved to form a first photoresist layer with a second opening pattern.

[0069] Step S1053: Etch the peripheral region using the second opening pattern as a mask to form a second opening in the second insulating structure and sacrificial layer of the peripheral region, wherein the second opening extends to the active region.

[0070] Here, since the second opening can be the initial contact plug hole of the peripheral region, the second opening can extend to the active region to realize the connection between the source and drain of the peripheral region transistor and the metal interconnect layer.

[0071] It should be noted that in some embodiments, there can be two second openings, located on both sides of the source and drain of the peripheral region transistor, respectively. In this case, after forming the first second opening, an initial second photoresist layer can be deposited on the second insulating structure and sacrificial layer having the first second opening; then, the initial second photoresist layer can be patterned to form a second photoresist layer with a second second opening pattern; finally, the second insulating structure and sacrificial layer can be etched using the second second opening pattern as a mask to form the second second opening in the second insulating structure and sacrificial layer.

[0072] In this embodiment, an initial first photoresist layer is first formed on the sacrificial layer of the peripheral region; then the initial first photoresist layer is patterned to form a first photoresist layer with a second opening pattern; finally, the peripheral region is etched using the second opening pattern as a mask, thereby realizing the formation of a second opening in the second insulating structure and the sacrificial layer.

[0073] Step S106: A protective layer is formed on the surface of the sacrificial layer at least at the top of the first opening sidewall and on the surface of the sacrificial layer of the second opening sidewall;

[0074] Here, the protective layer is used to protect the sacrificial layers of the first opening sidewall and the second opening sidewall during the subsequent removal of the sacrificial layer at the bottom of the first opening in the array region, so that the sacrificial layers of the first opening sidewall and the second opening sidewall are not etched or are etched less, thereby increasing the size of the second opening and the first opening, and keeping the first insulating structure intact.

[0075] Figure 2E for Figure 1A A schematic diagram of the structure obtained after the protective layer is formed in region A, wherein the protective layer 201 is located at the first opening (see...). Figure 2D The surface of the sacrificial layer 102 at the top of the sidewall. Figure 2F for Figure 1A A schematic diagram of the structure obtained after the protective layer is formed in region B, wherein the protective layer 201 is located on the surface of the sacrificial layer 102 on the sidewall of the second opening 301.

[0076] The protective layer is located at least on the surface of the sacrificial layer at the top of the first opening sidewall and on the surface of the sacrificial layer on the second opening sidewall; that is, the protective layer may also be located at other locations. For example, the protective layer may also be located on the top surface of the first insulating structure, the bottom of the first opening, the entire sidewall of the first opening, the bottom of the second opening, the upper surface of the sacrificial layer, etc. The embodiments of this application do not limit the location of the protective layer.

[0077] In some embodiments, the thickness of the protective layer at the bottom of the first opening may be less than the thickness of the protective layer at the top of the sidewall of the first opening. In this way, during the process of removing the sacrificial layer at the bottom of the first opening, a portion of the protective layer at the top of the sidewall of the first opening will still exist, thereby serving as a sidewall structure to protect the positioning line.

[0078] In some embodiments, if the material in the second insulation structure is the same as the material of the sacrificial layer, and if the protective layer is also located on the sidewall of the second insulation structure, the size of the second opening can be better protected and the increase in the size of the second opening can be reduced during the process of removing the sacrificial layer at the bottom of the first opening.

[0079] Figure 2G and Figure 2H This is a schematic diagram of the protective layer in other locations. For example... Figure 2G As shown, the protective layer 201 is located at the first opening (see...). Figure 2D The surface of the sacrificial layer 102 at the bottom and throughout the sidewalls, and the surface of the sacrificial layer 102 at the top of the sidewall structure 104. (As shown) Figure 2H As shown, the protective layer 201 is located on the sacrificial layer 102, at the bottom of the second opening 301, on the sidewall of the second insulating structure 302, and on the sidewall of the sacrificial layer 102.

[0080] In some embodiments, the protective layer may include a carbon layer. Correspondingly, the implementation of step S106 may include: dissociating the fluoromethane gas by an alternating electric field to form a carbon layer at least on the surface of the sacrificial layer at the top of the first opening sidewall and on the surface of the sacrificial layer of the second opening sidewall. Because under an alternating electric field, the fluoromethane gas dissociates into carbon polymers, hydrogen atoms, and fluorine radicals, and the carbon polymers are deposited at least on the surface of the sacrificial layer at the top of the first opening sidewall and on the surface of the sacrificial layer of the second opening sidewall, thus forming the carbon layer. The dissociation equation for the fluoromethane gas is as follows:

[0081] CH3F→C●+3H+F*

[0082] Wherein, C● represents carbon polymers and F* represents fluorine free radicals.

[0083] Figure 2I A schematic diagram is shown illustrating the formation of a protective layer in the array region by dissociating fluoromethane gas 203 through an alternating electric field. It can be seen that the space at the top of the sidewall structure 104 of the bit line is larger than the first opening (see...). Figure 2D The space of the sidewalls is larger than the space at the bottom of the first opening; therefore, as... Figure 2GAs shown, the thickness of the protective layer deposited on the top of the sidewall structure 104 of the bit line is greater than the thickness of the protective layer deposited on the sidewall of the first opening, and the thickness of the protective layer deposited on the sidewall of the first opening is greater than the thickness of the protective layer deposited at the bottom of the first opening. That is, the protective layer deposited on the top of the sidewall structure 104 of the bit line is the thickest, the protective layer deposited at the bottom of the first opening is the thinnest, and the thickness of the protective layer deposited on the sidewall of the first opening is between the thickness of the protective layer deposited on the top of the sidewall structure 104 of the bit line and the thickness of the protective layer deposited at the bottom of the first opening.

[0084] In this way, during the subsequent process of removing the sacrificial layer at the bottom of the first opening, it is easier to etch away the protective layer located at the bottom of the first opening, thereby removing the sacrificial layer located on the storage node contact; at the same time, the protective layer located at the top of the sidewall structure of the bit line and the sidewall of the first opening can protect the sidewall structure of the bit line during the process of removing the sacrificial layer at the bottom of the first opening, reduce the damage to the sidewall structure, and thus make the sidewall structure of the bit line intact.

[0085] In some embodiments, the process parameters for dissociating fluoromethane gas can be controlled so that there is no protective layer at the bottom of the first opening, thereby further facilitating the removal of the sacrificial layer at the bottom of the first opening.

[0086] Figure 2J A schematic diagram is shown illustrating the formation of a protective layer in the peripheral region by dissociating fluoromethane gas 203 through an alternating electric field. It can also be seen that the space on the sacrificial layer 102 in the peripheral region is larger than the space on the sidewall of the second opening 301, and the space on the sidewall of the second opening 301 is larger than the space at the bottom of the second opening 301. Therefore, as... Figure 2H As shown, after depositing a protective layer on the peripheral region, the thickness of the protective layer 201 on the sacrificial layer 102 is greater than the thickness of the protective layer 201 on the sidewall of the second opening 301, and the thickness of the protective layer 201 on the sidewall of the second opening 301 is greater than the thickness of the protective layer 201 at the bottom of the second opening 301.

[0087] In this way, during the subsequent removal of the sacrificial layer at the bottom of the first opening, the protective layer located on the sidewall of the second opening can protect the sidewall of the second opening, reduce the etching of the sidewall of the second opening, reduce the increase in the critical dimension of the second opening, thereby increasing the process window of the final contact plug hole etching process and improving the electrical performance of the contact plug.

[0088] In this embodiment, a carbon layer is deposited on at least the first and second opening sidewalls by dissociating fluoromethane gas, thereby protecting the first and second opening sidewalls. Because the process of dissociating fluoromethane gas is simple, easy to operate, and allows for convenient control of the thickness of the carbon layer deposited on the first and second opening sidewalls, it can be well applied to openings with a large depth-to-width ratio.

[0089] In some embodiments, the process parameters for the dissociation process may include: a gas flow rate ranging from 25 to 35 standard milliliters per minute (sccm), a gas pressure ranging from 5 to 10 millitors (mTorr), a time ranging from 17 to 23 seconds (s), a continuous wave alternating electric field, and a power greater than 500 watts (W). For example, the process parameters for the dissociation process may be: a gas flow rate of 30 sccm, a gas pressure of 8 mTorr, a time of 20 seconds, a continuous wave alternating electric field, and a power of 600 W. This results in a protective layer of moderate thickness and uniform distribution.

[0090] It should be noted that, in the embodiments of this application, other methods may also be used to form a protective layer at least on the surface of the sacrificial layer at the top of the first opening sidewall and on the surface of the sacrificial layer of the second opening sidewall. The embodiments of this application do not limit the method of forming the protective layer.

[0091] Step S107: Remove the sacrificial layer at the bottom of the first opening;

[0092] Here, step S107 can be implemented by dry etching to remove the sacrificial layer at the bottom of the first opening, thereby exposing the filling material (e.g., memory node contact) beneath the sacrificial layer at the bottom of the first opening. Dry etching processes can include reactive ion etching, plasma etching, etc., and this application embodiment does not limit the type of dry etching process.

[0093] It should be noted that during the removal of the sacrificial layer at the bottom of the first opening, depending on the location and thickness of the protective layer, a portion of the protective layer, a portion of the sidewalls of the first insulation structure, and a portion of the sidewalls of the second insulation structure may also be etched away. However, since the protective layer is present at least on the surface of the sacrificial layer at the top of the sidewall of the first opening and on the surface of the sacrificial layer of the sidewall of the second opening, the reduction in the size of the first opening and the sidewalls of the second opening is smaller compared to the case without a protective layer. This reduces the increase in the size of the second opening, reduces damage to the first insulation structure, and improves the integrity of the first insulation structure.

[0094] Step S108: Remove the protective layer of the array area and the peripheral area to form a first contact hole and a second contact hole in the array area and the peripheral area, respectively.

[0095] In some embodiments, step S108 can be implemented using a dry etching process to remove the remaining protective layer in the array region and peripheral region, allowing the protective layer to be precisely removed. After removing the protective layer, a first contact hole is formed at the location of the first opening, and a second contact hole is formed at the location of the second opening. The first contact hole is used to form contact pads between the memory node contact and the memory capacitor, and the second contact hole is used to form contact plugs in the peripheral region.

[0096] Figure 2KA schematic diagram of the array region obtained after removing the protective layers of the array region and the peripheral region is shown. Specifically, a first contact hole 204 is formed in the array region to... Figure 2K The side wall structure 104 and Figure 1B Compared to the side wall structure 104 in the middle, it can be seen that, Figure 2K The side wall structure 104 is more complete.

[0097] Figure 2L A schematic diagram of the structure of the peripheral region after removing the protective layer from the array region and the peripheral region is shown. A second contact hole 205 is formed in the array region, connecting with... Figure 1D Compared to the contact plug hole 304 in the middle. Figure 2L The size of the second contact hole 205 is significantly reduced.

[0098] In this embodiment, firstly, a substrate is provided, the substrate including an array region and a peripheral region; secondly, a plurality of first insulating structures are formed on the substrate of the array region, and a second insulating structure is formed on the substrate of the peripheral region; thirdly, a first opening is formed in adjacent first insulating structures, exposing the top of the sidewall of the first insulating structure; a sacrificial layer is deposited on the sidewall and bottom of the first opening, and simultaneously on the second insulating structure; then, a second opening is formed in the second insulating structure and the sacrificial layer of the peripheral region; next, a protective layer is formed at least on the surface of the sacrificial layer at the top of the sidewall of the first opening and on the surface of the sacrificial layer on the sidewall of the second opening; finally, the sacrificial layer at the bottom of the first opening and the protective layer of the array region and the peripheral region are removed to form a first contact hole and a second contact hole in the array region and the peripheral region, respectively.

[0099] Since the protective layer is located at least on the surface of the sacrificial layer at the top of the first opening sidewall and on the surface of the sacrificial layer on the second opening sidewall, and the sacrificial layer covers the top of the first opening sidewall and the second opening sidewall, the protective layer also covers the top of the first opening sidewall and the second opening sidewall. Therefore, during the removal of the sacrificial layer located at the bottom of the first opening, the protective layer located on the top of the first opening sidewall and the second opening sidewall can play a protective role, protecting the top of the first opening sidewall and the second opening sidewall beneath the protective layer from being etched or less frequently, thereby reducing the increase in the size of the second opening and improving the integrity of the first insulation structure.

[0100] In some embodiments, the first insulating structure includes a sidewall structure for the bit line, then the implementation of "forming a plurality of first insulating structures on the substrate of the array region" in step S102 may include the following steps S1021b to S1022b:

[0101] Step S1021b: Form a plurality of sequentially stacked bit line contacts and bit lines on the substrate of the array region;

[0102] like Figure 2CAs shown, a plurality of sequentially stacked bit line contacts 107 and bit lines 105 are formed on the substrate 10a of the array region. The materials used for the bit line contacts may include, but are not limited to, conductive materials such as polysilicon, for example, doped or undoped polysilicon. The bit line 105 includes an insulating cap layer 105a and a first conductive layer 105b. In some embodiments, since the insulating cap layer 105a is made of the same material as the sidewall structure 104 of the bit line, therefore... Figure 2C There is no distinction between the insulating cap layer 105a and the side wall structure 104 of the position line.

[0103] In some embodiments, the implementation of step S1021b may include the following steps S11b1 and S11b2:

[0104] Step S11b1: Form multiple bit line contact holes and bit line contacts in each bit line contact hole on the substrate of the array region;

[0105] Here, step S11b1 can be implemented by using a deposition process to deposit a bit line contact inside the bit line contact hole.

[0106] Step S11b2: A first conductive layer and an insulating cap layer are sequentially formed on each bit contact to form a plurality of sequentially stacked bit contacts and bit lines on the substrate of the array region.

[0107] Here, the material of the first conductive layer 105b can be one or more of polycrystalline silicon, metal silicide, conductive metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc.), and metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), etc.). In practical applications, the material of the insulating capping layer 105a can be at least one of oxide, silicon nitride, and silicon oxide nitride, and the insulating capping layer can be formed using a chemical vapor deposition process.

[0108] In other embodiments, bit line 105 may further include a diffusion barrier layer located between the bit line contact and the first conductive layer. The diffusion barrier layer can insulate the first conductive layer from the active region and prevent metal ions in the first conductive layer from entering the active region. The diffusion barrier layer may include a single-layer structure, such as a titanium layer; or it may include a multi-layer structure, such as a titanium layer and a titanium nitride layer.

[0109] In some embodiments, after forming the first conductive layer and insulating capping layer of the bit line on the bit line contact, the bit line contact within the bit line contact hole can be etched using the first conductive layer and insulating capping layer as a mask, so that the bit line contact is the same width as the first conductive layer and insulating capping layer, thereby forming a gap within the bit line contact hole; subsequently, a filling material is deposited within the gap to form a filling material. Figure 2C The insulating layer 106 shown.

[0110] Here, the insulating layer can be made of nitrides, including but not limited to silicon nitride and silicon oxynitride. In some embodiments, to facilitate control of the insulating layer thickness, the insulating layer can be formed using atomic layer deposition (ALD). In other embodiments, other processes can also be used to form the insulating layer, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure CVD, molecular layer deposition (MLD), and plasma-enhanced vapor deposition (PEVDC).

[0111] Step S1022b: Form a sidewall structure on each of the sequentially stacked bitline contacts and the two sidewalls of the bitline.

[0112] like Figure 2C As shown, the sidewall structure 104 may include a silicon nitride-silicon oxide-silicon nitride structure (i.e., NON structure) or a silicon nitride-air interlayer-silicon nitride structure (i.e., NAN structure).

[0113] In this embodiment, a plurality of sequentially stacked bit line contacts and bit lines are first formed on the substrate of the array region, and then sidewall structures are formed on both sides of each sequentially stacked bit line contact and bit line to form a plurality of first insulating structures on the substrate of the array region.

[0114] In some embodiments, after "forming the first contact hole and the second contact hole in the array region and the peripheral region respectively" in step S108, the method further includes the following step S109a:

[0115] Step S109a: Deposit a metal layer in the first contact hole to form a contact pad;

[0116] Among them, the contact pads are used to connect the source or drain of the transistor in the array region to the storage capacitor in the array region together with the contact of the storage node.

[0117] like Figure 2K As shown, a metal layer is deposited within the first contact hole 204 to form as shown. Figure 3 The contact pad 305 is shown. The contact pad 305 and the storage node contact 101 together connect the source or drain of the transistor in the array region to the storage capacitor in the array region.

[0118] In this embodiment, a metal layer is deposited in the first contact hole to form a contact pad, which contacts the storage node to connect the source or drain of the transistor in the array region to the storage capacitor in the array region.

[0119] In some embodiments, after "forming the first contact hole and the second contact hole in the array region and the peripheral region respectively" in step S108, the method further includes the following step S109b:

[0120] Step S109b: In the second contact hole, a buffer layer and a second conductive layer are deposited sequentially to form a contact plug in the peripheral area.

[0121] Here, the buffer layer may be made of titanium to buffer stress between the conductive layer and the substrate and the second insulating structure. The second conductive layer may be made of tungsten, cobalt, copper, aluminum, polycrystalline silicon, doped silicon, silicide, or any combination thereof to achieve electrical connection between the contact plug and the metal interconnect layer.

[0122] For implementation, see Figure 4A A buffer layer 402 is deposited inside the second contact hole, and then a second conductive layer 401 is deposited on the surface of the buffer layer 402. Both the buffer layer 402 and the second conductive layer 401 are deposited as a single layer.

[0123] In some embodiments, after the buffer layer and the second conductive layer are deposited in sequence, a chemical mechanical polishing process can be used to remove the buffer layer 402 and the second conductive layer 401 located on the second insulating structure 302, thereby obtaining the contact plug 403 of the peripheral region.

[0124] In some embodiments, before step S109b "sequentially depositing the buffer layer and the second conductive layer", the following step S110 may also be included:

[0125] Step S110b: Form an ohmic contact layer at the bottom of the second contact hole.

[0126] Here, the ohmic contact layer is used to connect with the second conductive layer of the contact plug, serving to reduce resistance and repair the bottom morphology of the second contact hole. The material of the ohmic contact layer may include titanium silicide (TiSi). x ) or cobalt silicide (CoSi) x ), where x is a constant. In some embodiments, the ohmic contact layer can be formed by depositing a cobalt or titanium layer in the second contact hole; then annealing at high temperature to react the cobalt or titanium layer with the substrate at the bottom of the second contact hole, thereby obtaining cobalt silicide or titanium silicide at the bottom of the second contact hole. The embodiments of this application do not limit the method of forming the ohmic contact layer.

[0127] Figure 4B A schematic diagram of the structure obtained by forming an ohmic contact layer at the bottom of the second contact hole is shown. It can be seen that in this embodiment, before depositing the buffer layer 402 and the second conductive layer 401 in sequence in the second contact hole, an ohmic contact layer 405 is first formed at the bottom of the second contact hole to reduce resistance and repair the morphology of the bottom of the second contact hole.

[0128] In some embodiments, the material of the portion of the substrate in the peripheral region that contacts the bottom of the second contact hole includes silicon, and the material of the ohmic contact layer includes cobalt silicide. Step S110b, "forming an ohmic contact layer at the bottom of the second contact hole," includes the following steps S1101 and S1102:

[0129] Step S1101: Deposit a cobalt layer in the second contact hole;

[0130] Here, step S1101 can be implemented using a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any other suitable deposition process, to deposit a cobalt layer within the second contact hole. For example... Figure 4C As shown, a cobalt layer 404 is deposited in the second contact hole using any of the above deposition processes.

[0131] Step S1102: Perform high-temperature annealing on the cobalt layer to form a cobalt silicide layer at the bottom of the second contact hole.

[0132] Here, the high-temperature annealing temperature range can be from 600 degrees Celsius (°C) to 650 degrees Celsius. At this temperature, the cobalt layer reacts with the silicon in the substrate at the bottom of the second contact hole to form cobalt silicide. If, except for the bottom, the contact areas between the second contact hole and the substrate and the second insulating structure do not contain silicon, the cobalt layer on the surface of the second contact hole, except for the bottom, does not react with the substrate and the second insulating structure and remains the original cobalt material. Figure 4D The diagram shows the structure obtained by high-temperature annealing of the cobalt layer. It can be seen that only the cobalt layer at the bottom of the second contact hole forms a cobalt silicide layer, while the cobalt layer in other parts of the second contact hole remains the original cobalt material.

[0133] In this embodiment, a cobalt layer is deposited in the second contact hole, and then a high-temperature annealing process is used to react the cobalt layer with the silicon in the substrate at the bottom of the second contact hole to generate cobalt silicide, thereby forming a cobalt silicide layer at the bottom of the second contact hole.

[0134] In some embodiments, after "forming a cobalt silicide layer at the bottom of the second contact hole" in step S1102, the method further includes the following step S1103:

[0135] Step S1103: Remove the remaining cobalt layer located in the second contact hole.

[0136] Here, the remaining cobalt layer refers to the portion of the cobalt layer in which cobalt silicide has not formed, i.e. Figure 4D The part referred to in section 406 forms as follows Figure 4E The ohmic contact layer 405 is located in the second contact hole. In some embodiments, step S1103 may be performed by wet etching or dry etching to remove the remaining cobalt layer located in the second contact hole, thereby obtaining the cobalt silicide layer at the bottom of the second contact hole.

[0137] This application also provides a semiconductor structure, which is prepared according to the above-described semiconductor structure formation method.

[0138] The features disclosed in the several method or structural embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0139] The descriptions of the above semiconductor structure embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the semiconductor structure embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding. The above descriptions are merely exemplary embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an array region and a peripheral region; A plurality of first insulating structures are formed on the substrate of the array region, and a second insulating structure is formed on the substrate of the peripheral region; A first opening is formed in an adjacent first insulating structure, the first opening exposing the top of the sidewall of the first insulating structure; A sacrificial layer is deposited on the sidewalls and bottom of the first opening, and simultaneously on the second insulating structure. A second opening is formed in the second insulating structure and the sacrificial layer in the peripheral region, wherein the second opening exposes the sidewall of the sacrificial layer; A protective layer is formed at least on the surface of the sacrificial layer at the top of the first opening sidewall and on the surface of the sacrificial layer of the second opening sidewall; Remove the sacrificial layer at the bottom of the first opening; Remove the protective layer from the array area and the peripheral area to form a first contact hole and a second contact hole in the array area and the peripheral area, respectively.

2. The forming method according to claim 1, characterized in that, The protective layer includes a carbon layer, and the protective layer is formed at least on the surface of the sacrificial layer at the top of the first opening sidewall and on the surface of the sacrificial layer of the second opening sidewall, comprising: The fluoromethane gas is dissociated by an alternating electric field to form the carbon layer at least on the surface of the sacrificial layer at the top of the first opening sidewall and on the surface of the sacrificial layer of the second opening sidewall.

3. The forming method according to claim 1 or 2, characterized in that, The first insulating structure includes a sidewall structure for the bit line, and a plurality of first insulating structures are formed on the substrate of the array region, including: A plurality of sequentially stacked bit line contacts and bit lines are formed on the substrate of the array region; The sidewall structure is formed on each of the sequentially stacked bit line contacts and the two side walls of the bit lines.

4. The forming method according to claim 3, characterized in that, A plurality of sequentially stacked bit line contacts and bit lines are formed on the substrate of the array region, including: A plurality of bit line contact holes and bit line contacts are formed on the substrate of the array region; A first conductive layer and an insulating capping layer are sequentially formed on each of the bit line contacts to form a plurality of sequentially stacked bit line contacts and bit lines on the substrate of the array region.

5. The forming method according to claim 3, characterized in that, The step of forming a first opening in the adjacent first insulating structure includes: Storage node contacts are deposited between adjacent sidewall structures to form the first opening in the adjacent sidewall structures.

6. The forming method according to claim 3, characterized in that, A second insulating structure is formed on the substrate in the peripheral region, comprising: A second insulating layer is deposited on the substrate in the peripheral region; A third insulating layer is deposited on the second insulating layer to form a second insulating structure with a stacked structure.

7. The forming method according to claim 6, characterized in that, The material of the sacrificial layer is the same as the material of the sidewall structure; The material of the sacrificial layer is the same as that of the second insulating layer and / or the third insulating layer.

8. The forming method according to claim 5, characterized in that, The method further includes: A metal layer is deposited within the first contact hole to form a contact pad; The contact pads are used to contact the memory nodes to connect the source or drain of the transistors in the array region to the memory capacitors in the array region.

9. The forming method according to any one of claims 1, 2, 4 to 8, characterized in that, The substrate of the peripheral region includes an active region, and a second opening is formed in the second insulating structure and the sacrificial layer of the peripheral region, including: An initial first photoresist layer is formed on the sacrificial layer in the peripheral region; The initial first photoresist layer is patterned to form a first photoresist layer with a second opening pattern, wherein the sub-pattern containing the second opening is located above the active region. The peripheral region is etched using the second opening pattern as a mask to form the second opening in the second insulating structure and the sacrificial layer of the peripheral region, wherein the second opening extends to the active region.

10. The forming method according to any one of claims 1, 2, 4 to 8, characterized in that, The method further includes: Within the second contact hole, a buffer layer and a second conductive layer are sequentially deposited to form the contact plug of the peripheral area.

11. The forming method according to claim 10, characterized in that, Before the sequential deposition of the buffer layer and the second conductive layer, the following is also included: An ohmic contact layer is formed at the bottom of the second contact hole.

12. The forming method according to claim 11, characterized in that, The material of the portion of the substrate in the peripheral region that contacts the bottom of the second contact hole includes silicon, and the material of the ohmic contact layer includes cobalt silicide. An ohmic contact layer is formed at the bottom of the second contact hole, comprising: A cobalt layer is deposited within the second contact hole; The cobalt layer is subjected to high-temperature annealing to form a cobalt silicide layer at the bottom of the second contact hole.

13. The forming method according to claim 12, characterized in that, After forming a cobalt silicide layer at the bottom of the second contact hole, the method further includes: Remove any remaining cobalt layer located within the second contact hole.

14. The forming method according to any one of claims 1, 2, 4 to 8, 11 to 13, characterized in that, The protective layer of the array region and the peripheral region is removed using a dry etching process.

15. A semiconductor structure, characterized in that, The semiconductor structure is prepared according to any one of claims 1 to 14.

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